Milen Pavlov / XRange_mbed_src

Mbed SDK for XRange SX1272 LoRa module

Dependents:   XRangePingPong XRange-LoRaWAN-lmic-app lora-transceiver

SX1272 LoRa RF module

https://www.netblocks.eu/xrange-sx1272-lora-datasheet/

targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_irq_api.c@339:ac6f3fd999f3, 2016-01-07 (annotated)

Committer:
netblocks
Date:
Thu Jan 07 13:01:25 2016 +0000
Revision:
339:ac6f3fd999f3
Parent:
336:1e18a06a987b 
HSE_VALUE set for XTAL 16Mhz

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 336:1e18a06a987b 1 /* mbed Microcontroller Library
dudmuck 336:1e18a06a987b 2 *******************************************************************************
dudmuck 336:1e18a06a987b 3 * Copyright (c) 2014, STMicroelectronics
dudmuck 336:1e18a06a987b 4 * All rights reserved.
dudmuck 336:1e18a06a987b 5 *
dudmuck 336:1e18a06a987b 6 * Redistribution and use in source and binary forms, with or without
dudmuck 336:1e18a06a987b 7 * modification, are permitted provided that the following conditions are met:
dudmuck 336:1e18a06a987b 8 *
dudmuck 336:1e18a06a987b 9 * 1. Redistributions of source code must retain the above copyright notice,
dudmuck 336:1e18a06a987b 10 * this list of conditions and the following disclaimer.
dudmuck 336:1e18a06a987b 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
dudmuck 336:1e18a06a987b 12 * this list of conditions and the following disclaimer in the documentation
dudmuck 336:1e18a06a987b 13 * and/or other materials provided with the distribution.
dudmuck 336:1e18a06a987b 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
dudmuck 336:1e18a06a987b 15 * may be used to endorse or promote products derived from this software
dudmuck 336:1e18a06a987b 16 * without specific prior written permission.
dudmuck 336:1e18a06a987b 17 *
dudmuck 336:1e18a06a987b 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dudmuck 336:1e18a06a987b 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dudmuck 336:1e18a06a987b 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
dudmuck 336:1e18a06a987b 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
dudmuck 336:1e18a06a987b 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
dudmuck 336:1e18a06a987b 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
dudmuck 336:1e18a06a987b 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
dudmuck 336:1e18a06a987b 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
dudmuck 336:1e18a06a987b 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
dudmuck 336:1e18a06a987b 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
dudmuck 336:1e18a06a987b 28 *******************************************************************************
dudmuck 336:1e18a06a987b 29 */
dudmuck 336:1e18a06a987b 30 #include <stddef.h>
dudmuck 336:1e18a06a987b 31 #include "cmsis.h"
dudmuck 336:1e18a06a987b 32 #include "gpio_irq_api.h"
dudmuck 336:1e18a06a987b 33 #include "pinmap.h"
dudmuck 336:1e18a06a987b 34 #include "mbed_error.h"
dudmuck 336:1e18a06a987b 35
dudmuck 336:1e18a06a987b 36 #define EDGE_NONE (0)
dudmuck 336:1e18a06a987b 37 #define EDGE_RISE (1)
dudmuck 336:1e18a06a987b 38 #define EDGE_FALL (2)
dudmuck 336:1e18a06a987b 39 #define EDGE_BOTH (3)
dudmuck 336:1e18a06a987b 40
dudmuck 336:1e18a06a987b 41 // Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
dudmuck 336:1e18a06a987b 42 #define CHANNEL_NUM (7)
dudmuck 336:1e18a06a987b 43
dudmuck 336:1e18a06a987b 44 // Max pins for one line (max with EXTI10_15)
dudmuck 336:1e18a06a987b 45 #define MAX_PIN_LINE (6)
dudmuck 336:1e18a06a987b 46
dudmuck 336:1e18a06a987b 47 typedef struct gpio_channel {
dudmuck 336:1e18a06a987b 48 uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
dudmuck 336:1e18a06a987b 49 uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
dudmuck 336:1e18a06a987b 50 uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
dudmuck 336:1e18a06a987b 51 uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
dudmuck 336:1e18a06a987b 52 } gpio_channel_t;
dudmuck 336:1e18a06a987b 53
dudmuck 336:1e18a06a987b 54 static gpio_channel_t channels[CHANNEL_NUM] = {
dudmuck 336:1e18a06a987b 55 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 56 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 57 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 58 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 59 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 60 {.pin_mask = 0},
dudmuck 336:1e18a06a987b 61 {.pin_mask = 0}
dudmuck 336:1e18a06a987b 62 };
dudmuck 336:1e18a06a987b 63
dudmuck 336:1e18a06a987b 64 // Used to return the index for channels array.
dudmuck 336:1e18a06a987b 65 static uint32_t pin_base_nr[16] = {
dudmuck 336:1e18a06a987b 66 // EXTI0
dudmuck 336:1e18a06a987b 67 0, // pin 0
dudmuck 336:1e18a06a987b 68 // EXTI1
dudmuck 336:1e18a06a987b 69 0, // pin 1
dudmuck 336:1e18a06a987b 70 // EXTI2
dudmuck 336:1e18a06a987b 71 0, // pin 2
dudmuck 336:1e18a06a987b 72 // EXTI3
dudmuck 336:1e18a06a987b 73 0, // pin 3
dudmuck 336:1e18a06a987b 74 // EXTI4
dudmuck 336:1e18a06a987b 75 0, // pin 4
dudmuck 336:1e18a06a987b 76 // EXTI5_9
dudmuck 336:1e18a06a987b 77 0, // pin 5
dudmuck 336:1e18a06a987b 78 1, // pin 6
dudmuck 336:1e18a06a987b 79 2, // pin 7
dudmuck 336:1e18a06a987b 80 3, // pin 8
dudmuck 336:1e18a06a987b 81 4, // pin 9
dudmuck 336:1e18a06a987b 82 // EXTI10_15
dudmuck 336:1e18a06a987b 83 0, // pin 10
dudmuck 336:1e18a06a987b 84 1, // pin 11
dudmuck 336:1e18a06a987b 85 2, // pin 12
dudmuck 336:1e18a06a987b 86 3, // pin 13
dudmuck 336:1e18a06a987b 87 4, // pin 14
dudmuck 336:1e18a06a987b 88 5 // pin 15
dudmuck 336:1e18a06a987b 89 };
dudmuck 336:1e18a06a987b 90
dudmuck 336:1e18a06a987b 91 static gpio_irq_handler irq_handler;
dudmuck 336:1e18a06a987b 92
dudmuck 336:1e18a06a987b 93 static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
dudmuck 336:1e18a06a987b 94 {
dudmuck 336:1e18a06a987b 95 gpio_channel_t *gpio_channel = &channels[irq_index];
dudmuck 336:1e18a06a987b 96 uint32_t gpio_idx;
dudmuck 336:1e18a06a987b 97
dudmuck 336:1e18a06a987b 98 for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
dudmuck 336:1e18a06a987b 99 uint32_t current_mask = (1 << gpio_idx);
dudmuck 336:1e18a06a987b 100
dudmuck 336:1e18a06a987b 101 if (gpio_channel->pin_mask & current_mask) {
dudmuck 336:1e18a06a987b 102 // Retrieve the gpio and pin that generate the irq
dudmuck 336:1e18a06a987b 103 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
dudmuck 336:1e18a06a987b 104 uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
dudmuck 336:1e18a06a987b 105
dudmuck 336:1e18a06a987b 106 // Clear interrupt flag
dudmuck 336:1e18a06a987b 107 if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
dudmuck 336:1e18a06a987b 108 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
dudmuck 336:1e18a06a987b 109
dudmuck 336:1e18a06a987b 110 if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
dudmuck 336:1e18a06a987b 111
dudmuck 336:1e18a06a987b 112 // Check which edge has generated the irq
dudmuck 336:1e18a06a987b 113 if ((gpio->IDR & pin) == 0) {
dudmuck 336:1e18a06a987b 114 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
dudmuck 336:1e18a06a987b 115 } else {
dudmuck 336:1e18a06a987b 116 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
dudmuck 336:1e18a06a987b 117 }
dudmuck 336:1e18a06a987b 118 }
dudmuck 336:1e18a06a987b 119 }
dudmuck 336:1e18a06a987b 120 }
dudmuck 336:1e18a06a987b 121 }
dudmuck 336:1e18a06a987b 122
dudmuck 336:1e18a06a987b 123 // EXTI line 0
dudmuck 336:1e18a06a987b 124 static void gpio_irq0(void)
dudmuck 336:1e18a06a987b 125 {
dudmuck 336:1e18a06a987b 126 handle_interrupt_in(0, 1);
dudmuck 336:1e18a06a987b 127 }
dudmuck 336:1e18a06a987b 128
dudmuck 336:1e18a06a987b 129 // EXTI line 1
dudmuck 336:1e18a06a987b 130 static void gpio_irq1(void)
dudmuck 336:1e18a06a987b 131 {
dudmuck 336:1e18a06a987b 132 handle_interrupt_in(1, 1);
dudmuck 336:1e18a06a987b 133 }
dudmuck 336:1e18a06a987b 134
dudmuck 336:1e18a06a987b 135 // EXTI line 2
dudmuck 336:1e18a06a987b 136 static void gpio_irq2(void)
dudmuck 336:1e18a06a987b 137 {
dudmuck 336:1e18a06a987b 138 handle_interrupt_in(2, 1);
dudmuck 336:1e18a06a987b 139 }
dudmuck 336:1e18a06a987b 140
dudmuck 336:1e18a06a987b 141 // EXTI line 3
dudmuck 336:1e18a06a987b 142 static void gpio_irq3(void)
dudmuck 336:1e18a06a987b 143 {
dudmuck 336:1e18a06a987b 144 handle_interrupt_in(3, 1);
dudmuck 336:1e18a06a987b 145 }
dudmuck 336:1e18a06a987b 146
dudmuck 336:1e18a06a987b 147 // EXTI line 4
dudmuck 336:1e18a06a987b 148 static void gpio_irq4(void)
dudmuck 336:1e18a06a987b 149 {
dudmuck 336:1e18a06a987b 150 handle_interrupt_in(4, 1);
dudmuck 336:1e18a06a987b 151 }
dudmuck 336:1e18a06a987b 152
dudmuck 336:1e18a06a987b 153 // EXTI lines 5 to 9
dudmuck 336:1e18a06a987b 154 static void gpio_irq5(void)
dudmuck 336:1e18a06a987b 155 {
dudmuck 336:1e18a06a987b 156 handle_interrupt_in(5, 5);
dudmuck 336:1e18a06a987b 157 }
dudmuck 336:1e18a06a987b 158
dudmuck 336:1e18a06a987b 159 // EXTI lines 10 to 15
dudmuck 336:1e18a06a987b 160 static void gpio_irq6(void)
dudmuck 336:1e18a06a987b 161 {
dudmuck 336:1e18a06a987b 162 handle_interrupt_in(6, 6);
dudmuck 336:1e18a06a987b 163 }
dudmuck 336:1e18a06a987b 164
dudmuck 336:1e18a06a987b 165 extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
dudmuck 336:1e18a06a987b 166
dudmuck 336:1e18a06a987b 167 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
dudmuck 336:1e18a06a987b 168 {
dudmuck 336:1e18a06a987b 169 IRQn_Type irq_n = (IRQn_Type)0;
dudmuck 336:1e18a06a987b 170 uint32_t vector = 0;
dudmuck 336:1e18a06a987b 171 uint32_t irq_index;
dudmuck 336:1e18a06a987b 172 gpio_channel_t *gpio_channel;
dudmuck 336:1e18a06a987b 173 uint32_t gpio_idx;
dudmuck 336:1e18a06a987b 174
dudmuck 336:1e18a06a987b 175 if (pin == NC) return -1;
dudmuck 336:1e18a06a987b 176
dudmuck 336:1e18a06a987b 177 uint32_t port_index = STM_PORT(pin);
dudmuck 336:1e18a06a987b 178 uint32_t pin_index = STM_PIN(pin);
dudmuck 336:1e18a06a987b 179
dudmuck 336:1e18a06a987b 180 // Select irq number and interrupt routine
dudmuck 336:1e18a06a987b 181 switch (pin_index) {
dudmuck 336:1e18a06a987b 182 case 0:
dudmuck 336:1e18a06a987b 183 irq_n = EXTI0_IRQn;
dudmuck 336:1e18a06a987b 184 vector = (uint32_t)&gpio_irq0;
dudmuck 336:1e18a06a987b 185 irq_index = 0;
dudmuck 336:1e18a06a987b 186 break;
dudmuck 336:1e18a06a987b 187 case 1:
dudmuck 336:1e18a06a987b 188 irq_n = EXTI1_IRQn;
dudmuck 336:1e18a06a987b 189 vector = (uint32_t)&gpio_irq1;
dudmuck 336:1e18a06a987b 190 irq_index = 1;
dudmuck 336:1e18a06a987b 191 break;
dudmuck 336:1e18a06a987b 192 case 2:
dudmuck 336:1e18a06a987b 193 irq_n = EXTI2_IRQn;
dudmuck 336:1e18a06a987b 194 vector = (uint32_t)&gpio_irq2;
dudmuck 336:1e18a06a987b 195 irq_index = 2;
dudmuck 336:1e18a06a987b 196 break;
dudmuck 336:1e18a06a987b 197 case 3:
dudmuck 336:1e18a06a987b 198 irq_n = EXTI3_IRQn;
dudmuck 336:1e18a06a987b 199 vector = (uint32_t)&gpio_irq3;
dudmuck 336:1e18a06a987b 200 irq_index = 3;
dudmuck 336:1e18a06a987b 201 break;
dudmuck 336:1e18a06a987b 202 case 4:
dudmuck 336:1e18a06a987b 203 irq_n = EXTI4_IRQn;
dudmuck 336:1e18a06a987b 204 vector = (uint32_t)&gpio_irq4;
dudmuck 336:1e18a06a987b 205 irq_index = 4;
dudmuck 336:1e18a06a987b 206 break;
dudmuck 336:1e18a06a987b 207 case 5:
dudmuck 336:1e18a06a987b 208 case 6:
dudmuck 336:1e18a06a987b 209 case 7:
dudmuck 336:1e18a06a987b 210 case 8:
dudmuck 336:1e18a06a987b 211 case 9:
dudmuck 336:1e18a06a987b 212 irq_n = EXTI9_5_IRQn;
dudmuck 336:1e18a06a987b 213 vector = (uint32_t)&gpio_irq5;
dudmuck 336:1e18a06a987b 214 irq_index = 5;
dudmuck 336:1e18a06a987b 215 break;
dudmuck 336:1e18a06a987b 216 case 10:
dudmuck 336:1e18a06a987b 217 case 11:
dudmuck 336:1e18a06a987b 218 case 12:
dudmuck 336:1e18a06a987b 219 case 13:
dudmuck 336:1e18a06a987b 220 case 14:
dudmuck 336:1e18a06a987b 221 case 15:
dudmuck 336:1e18a06a987b 222 irq_n = EXTI15_10_IRQn;
dudmuck 336:1e18a06a987b 223 vector = (uint32_t)&gpio_irq6;
dudmuck 336:1e18a06a987b 224 irq_index = 6;
dudmuck 336:1e18a06a987b 225 break;
dudmuck 336:1e18a06a987b 226 default:
dudmuck 336:1e18a06a987b 227 error("InterruptIn error: pin not supported.\n");
dudmuck 336:1e18a06a987b 228 return -1;
dudmuck 336:1e18a06a987b 229 }
dudmuck 336:1e18a06a987b 230
dudmuck 336:1e18a06a987b 231 // Enable GPIO clock
dudmuck 336:1e18a06a987b 232 uint32_t gpio_add = Set_GPIO_Clock(port_index);
dudmuck 336:1e18a06a987b 233
dudmuck 336:1e18a06a987b 234 // Configure GPIO
dudmuck 336:1e18a06a987b 235 pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
dudmuck 336:1e18a06a987b 236
dudmuck 336:1e18a06a987b 237 // Enable EXTI interrupt
dudmuck 336:1e18a06a987b 238 NVIC_SetVector(irq_n, vector);
dudmuck 336:1e18a06a987b 239 NVIC_EnableIRQ(irq_n);
dudmuck 336:1e18a06a987b 240
dudmuck 336:1e18a06a987b 241 // Save informations for future use
dudmuck 336:1e18a06a987b 242 obj->irq_n = irq_n;
dudmuck 336:1e18a06a987b 243 obj->irq_index = irq_index;
dudmuck 336:1e18a06a987b 244 obj->event = EDGE_NONE;
dudmuck 336:1e18a06a987b 245 obj->pin = pin;
dudmuck 336:1e18a06a987b 246
dudmuck 336:1e18a06a987b 247 gpio_channel = &channels[irq_index];
dudmuck 336:1e18a06a987b 248 gpio_idx = pin_base_nr[pin_index];
dudmuck 336:1e18a06a987b 249 gpio_channel->pin_mask |= (1 << gpio_idx);
dudmuck 336:1e18a06a987b 250 gpio_channel->channel_ids[gpio_idx] = id;
dudmuck 336:1e18a06a987b 251 gpio_channel->channel_gpio[gpio_idx] = gpio_add;
dudmuck 336:1e18a06a987b 252 gpio_channel->channel_pin[gpio_idx] = pin_index;
dudmuck 336:1e18a06a987b 253
dudmuck 336:1e18a06a987b 254 irq_handler = handler;
dudmuck 336:1e18a06a987b 255
dudmuck 336:1e18a06a987b 256 return 0;
dudmuck 336:1e18a06a987b 257 }
dudmuck 336:1e18a06a987b 258
dudmuck 336:1e18a06a987b 259 void gpio_irq_free(gpio_irq_t *obj)
dudmuck 336:1e18a06a987b 260 {
dudmuck 336:1e18a06a987b 261 gpio_channel_t *gpio_channel = &channels[obj->irq_index];
dudmuck 336:1e18a06a987b 262 uint32_t pin_index = STM_PIN(obj->pin);
dudmuck 336:1e18a06a987b 263 uint32_t gpio_idx = pin_base_nr[pin_index];
dudmuck 336:1e18a06a987b 264
dudmuck 336:1e18a06a987b 265 gpio_channel->pin_mask &= ~(1 << gpio_idx);
dudmuck 336:1e18a06a987b 266 gpio_channel->channel_ids[gpio_idx] = 0;
dudmuck 336:1e18a06a987b 267 gpio_channel->channel_gpio[gpio_idx] = 0;
dudmuck 336:1e18a06a987b 268 gpio_channel->channel_pin[gpio_idx] = 0;
dudmuck 336:1e18a06a987b 269
dudmuck 336:1e18a06a987b 270 // Disable EXTI line
dudmuck 336:1e18a06a987b 271 pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
dudmuck 336:1e18a06a987b 272 obj->event = EDGE_NONE;
dudmuck 336:1e18a06a987b 273 }
dudmuck 336:1e18a06a987b 274
dudmuck 336:1e18a06a987b 275 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
dudmuck 336:1e18a06a987b 276 {
dudmuck 336:1e18a06a987b 277 uint32_t mode = STM_MODE_IT_EVT_RESET;
dudmuck 336:1e18a06a987b 278 uint32_t pull = GPIO_NOPULL;
dudmuck 336:1e18a06a987b 279
dudmuck 336:1e18a06a987b 280 if (enable) {
dudmuck 336:1e18a06a987b 281 if (event == IRQ_RISE) {
dudmuck 336:1e18a06a987b 282 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
dudmuck 336:1e18a06a987b 283 mode = STM_MODE_IT_RISING_FALLING;
dudmuck 336:1e18a06a987b 284 obj->event = EDGE_BOTH;
dudmuck 336:1e18a06a987b 285 } else { // NONE or RISE
dudmuck 336:1e18a06a987b 286 mode = STM_MODE_IT_RISING;
dudmuck 336:1e18a06a987b 287 obj->event = EDGE_RISE;
dudmuck 336:1e18a06a987b 288 }
dudmuck 336:1e18a06a987b 289 }
dudmuck 336:1e18a06a987b 290 if (event == IRQ_FALL) {
dudmuck 336:1e18a06a987b 291 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
dudmuck 336:1e18a06a987b 292 mode = STM_MODE_IT_RISING_FALLING;
dudmuck 336:1e18a06a987b 293 obj->event = EDGE_BOTH;
dudmuck 336:1e18a06a987b 294 } else { // NONE or FALL
dudmuck 336:1e18a06a987b 295 mode = STM_MODE_IT_FALLING;
dudmuck 336:1e18a06a987b 296 obj->event = EDGE_FALL;
dudmuck 336:1e18a06a987b 297 }
dudmuck 336:1e18a06a987b 298 }
dudmuck 336:1e18a06a987b 299 } else { // Disable
dudmuck 336:1e18a06a987b 300 if (event == IRQ_RISE) {
dudmuck 336:1e18a06a987b 301 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
dudmuck 336:1e18a06a987b 302 mode = STM_MODE_IT_FALLING;
dudmuck 336:1e18a06a987b 303 obj->event = EDGE_FALL;
dudmuck 336:1e18a06a987b 304 } else { // NONE or RISE
dudmuck 336:1e18a06a987b 305 mode = STM_MODE_IT_EVT_RESET;
dudmuck 336:1e18a06a987b 306 obj->event = EDGE_NONE;
dudmuck 336:1e18a06a987b 307 }
dudmuck 336:1e18a06a987b 308 }
dudmuck 336:1e18a06a987b 309 if (event == IRQ_FALL) {
dudmuck 336:1e18a06a987b 310 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
dudmuck 336:1e18a06a987b 311 mode = STM_MODE_IT_RISING;
dudmuck 336:1e18a06a987b 312 obj->event = EDGE_RISE;
dudmuck 336:1e18a06a987b 313 } else { // NONE or FALL
dudmuck 336:1e18a06a987b 314 mode = STM_MODE_IT_EVT_RESET;
dudmuck 336:1e18a06a987b 315 obj->event = EDGE_NONE;
dudmuck 336:1e18a06a987b 316 }
dudmuck 336:1e18a06a987b 317 }
dudmuck 336:1e18a06a987b 318 }
dudmuck 336:1e18a06a987b 319
dudmuck 336:1e18a06a987b 320 pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
dudmuck 336:1e18a06a987b 321 }
dudmuck 336:1e18a06a987b 322
dudmuck 336:1e18a06a987b 323 void gpio_irq_enable(gpio_irq_t *obj)
dudmuck 336:1e18a06a987b 324 {
dudmuck 336:1e18a06a987b 325 NVIC_EnableIRQ(obj->irq_n);
dudmuck 336:1e18a06a987b 326 }
dudmuck 336:1e18a06a987b 327
dudmuck 336:1e18a06a987b 328 void gpio_irq_disable(gpio_irq_t *obj)
dudmuck 336:1e18a06a987b 329 {
dudmuck 336:1e18a06a987b 330 NVIC_DisableIRQ(obj->irq_n);
dudmuck 336:1e18a06a987b 331 obj->event = EDGE_NONE;
dudmuck 336:1e18a06a987b 332 }