sx1272Regs-LoRa.h

00001 /*
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007     (C)2013 Semtech
00008 
00009 Description: SX1272 LoRa modem registers and bits definitions
00010 
00011 License: Revised BSD License, see LICENSE.TXT file include in the project
00012 
00013 Maintainer: Miguel Luis and Gregory Cristian
00014 */
00015 #ifndef __SX1272_REGS_LORA_H__
00016 #define __SX1272_REGS_LORA_H__
00017 
00018 /*!
00019  * ============================================================================
00020  * SX1272 Internal registers Address
00021  * ============================================================================
00022  */
00023 #define REG_LR_FIFO                                 0x00 
00024 // Common settings
00025 #define REG_LR_OPMODE                               0x01 
00026 #define REG_LR_FRFMSB                               0x06 
00027 #define REG_LR_FRFMID                               0x07
00028 #define REG_LR_FRFLSB                               0x08 
00029 // Tx settings
00030 #define REG_LR_PACONFIG                             0x09 
00031 #define REG_LR_PARAMP                               0x0A 
00032 #define REG_LR_OCP                                  0x0B 
00033 // Rx settings
00034 #define REG_LR_LNA                                  0x0C 
00035 // LoRa registers
00036 #define REG_LR_FIFOADDRPTR                          0x0D 
00037 #define REG_LR_FIFOTXBASEADDR                       0x0E 
00038 #define REG_LR_FIFORXBASEADDR                       0x0F 
00039 #define REG_LR_FIFORXCURRENTADDR                    0x10 
00040 #define REG_LR_IRQFLAGSMASK                         0x11 
00041 #define REG_LR_IRQFLAGS                             0x12 
00042 #define REG_LR_RXNBBYTES                            0x13 
00043 #define REG_LR_RXHEADERCNTVALUEMSB                  0x14 
00044 #define REG_LR_RXHEADERCNTVALUELSB                  0x15 
00045 #define REG_LR_RXPACKETCNTVALUEMSB                  0x16 
00046 #define REG_LR_RXPACKETCNTVALUELSB                  0x17 
00047 #define REG_LR_MODEMSTAT                            0x18 
00048 #define REG_LR_PKTSNRVALUE                          0x19 
00049 #define REG_LR_PKTRSSIVALUE                         0x1A 
00050 #define REG_LR_RSSIVALUE                            0x1B 
00051 #define REG_LR_HOPCHANNEL                           0x1C 
00052 #define REG_LR_MODEMCONFIG1                         0x1D 
00053 #define REG_LR_MODEMCONFIG2                         0x1E 
00054 #define REG_LR_SYMBTIMEOUTLSB                       0x1F 
00055 #define REG_LR_PREAMBLEMSB                          0x20 
00056 #define REG_LR_PREAMBLELSB                          0x21 
00057 #define REG_LR_PAYLOADLENGTH                        0x22 
00058 #define REG_LR_PAYLOADMAXLENGTH                     0x23 
00059 #define REG_LR_HOPPERIOD                            0x24 
00060 #define REG_LR_FIFORXBYTEADDR                       0x25
00061 #define REG_LR_FEIMSB                               0x28
00062 #define REG_LR_FEIMID                               0x29
00063 #define REG_LR_FEILSB                               0x2A
00064 #define REG_LR_RSSIWIDEBAND                         0x2C
00065 #define REG_LR_DETECTOPTIMIZE                       0x31
00066 #define REG_LR_INVERTIQ                             0x33
00067 #define REG_LR_DETECTIONTHRESHOLD                   0x37
00068 #define REG_LR_SYNCWORD                             0x39
00069 
00070 // end of documented register in datasheet
00071 // I/O settings
00072 #define REG_LR_DIOMAPPING1                          0x40
00073 #define REG_LR_DIOMAPPING2                          0x41
00074 // Version
00075 #define REG_LR_VERSION                              0x42
00076 // Additional settings
00077 #define REG_LR_AGCREF                               0x43
00078 #define REG_LR_AGCTHRESH1                           0x44
00079 #define REG_LR_AGCTHRESH2                           0x45
00080 #define REG_LR_AGCTHRESH3                           0x46
00081 #define REG_LR_PLLHOP                               0x4B
00082 #define REG_LR_TCXO                                 0x58
00083 #define REG_LR_PADAC                                0x5A
00084 #define REG_LR_PLL                                  0x5C
00085 #define REG_LR_PLLLOWPN                             0x5E
00086 #define REG_LR_FORMERTEMP                           0x6C
00087 
00088 /*!
00089  * ============================================================================
00090  * SX1272 LoRa bits control definition
00091  * ============================================================================
00092  */
00093 
00094 /*!
00095  * RegFifo
00096  */
00097 
00098 /*!
00099  * RegOpMode
00100  */
00101 #define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F 
00102 #define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
00103 #define RFLR_OPMODE_LONGRANGEMODE_ON                0x80 
00104 
00105 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF 
00106 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40 
00107 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
00108 
00109 #define RFLR_OPMODE_MASK                            0xF8 
00110 #define RFLR_OPMODE_SLEEP                           0x00 
00111 #define RFLR_OPMODE_STANDBY                         0x01 // Default
00112 #define RFLR_OPMODE_SYNTHESIZER_TX                  0x02 
00113 #define RFLR_OPMODE_TRANSMITTER                     0x03 
00114 #define RFLR_OPMODE_SYNTHESIZER_RX                  0x04 
00115 #define RFLR_OPMODE_RECEIVER                        0x05 
00116 // LoRa specific modes
00117 #define RFLR_OPMODE_RECEIVER_SINGLE                 0x06 
00118 #define RFLR_OPMODE_CAD                             0x07 
00119 
00120 /*!
00121  * RegFrf (MHz)
00122  */
00123 #define RFLR_FRFMSB_915_MHZ                         0xE4  // Default
00124 #define RFLR_FRFMID_915_MHZ                         0xC0  // Default
00125 #define RFLR_FRFLSB_915_MHZ                         0x00  // Default
00126 
00127 /*!
00128  * RegPaConfig
00129  */
00130 #define RFLR_PACONFIG_PASELECT_MASK                 0x7F 
00131 #define RFLR_PACONFIG_PASELECT_PABOOST              0x80 
00132 #define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
00133 
00134 #define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0 
00135  
00136 /*!
00137  * RegPaRamp
00138  */
00139 #define RFLR_PARAMP_LOWPNTXPLL_MASK                 0xE0 
00140 #define RFLR_PARAMP_LOWPNTXPLL_OFF                  0x10 // Default
00141 #define RFLR_PARAMP_LOWPNTXPLL_ON                   0x00 
00142 
00143 #define RFLR_PARAMP_MASK                            0xF0 
00144 #define RFLR_PARAMP_3400_US                         0x00 
00145 #define RFLR_PARAMP_2000_US                         0x01 
00146 #define RFLR_PARAMP_1000_US                         0x02
00147 #define RFLR_PARAMP_0500_US                         0x03 
00148 #define RFLR_PARAMP_0250_US                         0x04 
00149 #define RFLR_PARAMP_0125_US                         0x05 
00150 #define RFLR_PARAMP_0100_US                         0x06 
00151 #define RFLR_PARAMP_0062_US                         0x07 
00152 #define RFLR_PARAMP_0050_US                         0x08 
00153 #define RFLR_PARAMP_0040_US                         0x09 // Default
00154 #define RFLR_PARAMP_0031_US                         0x0A 
00155 #define RFLR_PARAMP_0025_US                         0x0B 
00156 #define RFLR_PARAMP_0020_US                         0x0C 
00157 #define RFLR_PARAMP_0015_US                         0x0D 
00158 #define RFLR_PARAMP_0012_US                         0x0E 
00159 #define RFLR_PARAMP_0010_US                         0x0F 
00160 
00161 /*!
00162  * RegOcp
00163  */
00164 #define RFLR_OCP_MASK                               0xDF 
00165 #define RFLR_OCP_ON                                 0x20 // Default
00166 #define RFLR_OCP_OFF                                0x00   
00167 
00168 #define RFLR_OCP_TRIM_MASK                          0xE0
00169 #define RFLR_OCP_TRIM_045_MA                        0x00
00170 #define RFLR_OCP_TRIM_050_MA                        0x01   
00171 #define RFLR_OCP_TRIM_055_MA                        0x02 
00172 #define RFLR_OCP_TRIM_060_MA                        0x03 
00173 #define RFLR_OCP_TRIM_065_MA                        0x04 
00174 #define RFLR_OCP_TRIM_070_MA                        0x05 
00175 #define RFLR_OCP_TRIM_075_MA                        0x06 
00176 #define RFLR_OCP_TRIM_080_MA                        0x07  
00177 #define RFLR_OCP_TRIM_085_MA                        0x08
00178 #define RFLR_OCP_TRIM_090_MA                        0x09 
00179 #define RFLR_OCP_TRIM_095_MA                        0x0A 
00180 #define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
00181 #define RFLR_OCP_TRIM_105_MA                        0x0C 
00182 #define RFLR_OCP_TRIM_110_MA                        0x0D 
00183 #define RFLR_OCP_TRIM_115_MA                        0x0E 
00184 #define RFLR_OCP_TRIM_120_MA                        0x0F 
00185 #define RFLR_OCP_TRIM_130_MA                        0x10
00186 #define RFLR_OCP_TRIM_140_MA                        0x11   
00187 #define RFLR_OCP_TRIM_150_MA                        0x12 
00188 #define RFLR_OCP_TRIM_160_MA                        0x13 
00189 #define RFLR_OCP_TRIM_170_MA                        0x14 
00190 #define RFLR_OCP_TRIM_180_MA                        0x15 
00191 #define RFLR_OCP_TRIM_190_MA                        0x16 
00192 #define RFLR_OCP_TRIM_200_MA                        0x17  
00193 #define RFLR_OCP_TRIM_210_MA                        0x18
00194 #define RFLR_OCP_TRIM_220_MA                        0x19 
00195 #define RFLR_OCP_TRIM_230_MA                        0x1A 
00196 #define RFLR_OCP_TRIM_240_MA                        0x1B
00197 
00198 /*!
00199  * RegLna
00200  */
00201 #define RFLR_LNA_GAIN_MASK                          0x1F 
00202 #define RFLR_LNA_GAIN_G1                            0x20 // Default
00203 #define RFLR_LNA_GAIN_G2                            0x40 
00204 #define RFLR_LNA_GAIN_G3                            0x60 
00205 #define RFLR_LNA_GAIN_G4                            0x80 
00206 #define RFLR_LNA_GAIN_G5                            0xA0 
00207 #define RFLR_LNA_GAIN_G6                            0xC0 
00208 
00209 #define RFLR_LNA_BOOST_MASK                         0xFC 
00210 #define RFLR_LNA_BOOST_OFF                          0x00 // Default
00211 #define RFLR_LNA_BOOST_ON                           0x03 
00212 
00213 /*!
00214  * RegFifoAddrPtr
00215  */
00216 #define RFLR_FIFOADDRPTR                            0x00 // Default
00217 
00218 /*!
00219  * RegFifoTxBaseAddr
00220  */
00221 #define RFLR_FIFOTXBASEADDR                         0x80 // Default
00222 
00223 /*!
00224  * RegFifoTxBaseAddr
00225  */
00226 #define RFLR_FIFORXBASEADDR                         0x00 // Default
00227 
00228 /*!
00229  * RegFifoRxCurrentAddr (Read Only)
00230  */
00231 
00232 /*!
00233  * RegIrqFlagsMask
00234  */
00235 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80 
00236 #define RFLR_IRQFLAGS_RXDONE_MASK                   0x40 
00237 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20 
00238 #define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10 
00239 #define RFLR_IRQFLAGS_TXDONE_MASK                   0x08 
00240 #define RFLR_IRQFLAGS_CADDONE_MASK                  0x04 
00241 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02 
00242 #define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01 
00243 
00244 /*!
00245  * RegIrqFlags
00246  */
00247 #define RFLR_IRQFLAGS_RXTIMEOUT                     0x80 
00248 #define RFLR_IRQFLAGS_RXDONE                        0x40 
00249 #define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20 
00250 #define RFLR_IRQFLAGS_VALIDHEADER                   0x10 
00251 #define RFLR_IRQFLAGS_TXDONE                        0x08 
00252 #define RFLR_IRQFLAGS_CADDONE                       0x04 
00253 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02 
00254 #define RFLR_IRQFLAGS_CADDETECTED                   0x01 
00255 
00256 /*!
00257  * RegFifoRxNbBytes (Read Only)
00258  */
00259 
00260 /*!
00261  * RegRxHeaderCntValueMsb (Read Only)
00262  */
00263 
00264 /*!
00265  * RegRxHeaderCntValueLsb (Read Only)
00266  */
00267 
00268 /*!
00269  * RegRxPacketCntValueMsb (Read Only)
00270  */
00271 
00272 /*!
00273  * RegRxPacketCntValueLsb (Read Only)
00274  */
00275 
00276 /*!
00277  * RegModemStat (Read Only)
00278  */
00279 #define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F 
00280 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0 
00281  
00282 /*!
00283  * RegPktSnrValue (Read Only)
00284  */
00285 
00286 /*!
00287  * RegPktRssiValue (Read Only)
00288  */
00289 
00290 /*!
00291  * RegRssiValue (Read Only)
00292  */
00293 
00294 /*!
00295  * RegHopChannel (Read Only)
00296  */
00297 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F 
00298 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80 
00299 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
00300                                                     
00301 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK           0xBF
00302 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON             0x40
00303 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF            0x00 // Default
00304 
00305 #define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F 
00306 
00307 /*!
00308  * RegModemConfig1
00309  */
00310 #define RFLR_MODEMCONFIG1_BW_MASK                   0x3F 
00311 #define RFLR_MODEMCONFIG1_BW_125_KHZ                0x00 // Default
00312 #define RFLR_MODEMCONFIG1_BW_250_KHZ                0x40 
00313 #define RFLR_MODEMCONFIG1_BW_500_KHZ                0x80 
00314                                                     
00315 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xC7 
00316 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x08
00317 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x10 // Default
00318 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x18 
00319 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x20 
00320                                                     
00321 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFB 
00322 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x04 
00323 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
00324                                                     
00325 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK         0xFD 
00326 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON           0x02 
00327 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF          0x00 // Default
00328                                                     
00329 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK  0xFE 
00330 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON    0x01 
00331 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
00332 
00333 /*!
00334  * RegModemConfig2
00335  */
00336 #define RFLR_MODEMCONFIG2_SF_MASK                   0x0F 
00337 #define RFLR_MODEMCONFIG2_SF_6                      0x60 
00338 #define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
00339 #define RFLR_MODEMCONFIG2_SF_8                      0x80 
00340 #define RFLR_MODEMCONFIG2_SF_9                      0x90 
00341 #define RFLR_MODEMCONFIG2_SF_10                     0xA0 
00342 #define RFLR_MODEMCONFIG2_SF_11                     0xB0 
00343 #define RFLR_MODEMCONFIG2_SF_12                     0xC0 
00344 
00345 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7 
00346 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08 
00347 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00 
00348 
00349 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK              0xFB 
00350 #define RFLR_MODEMCONFIG2_AGCAUTO_ON                0x04 // Default 
00351 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF               0x00 
00352  
00353 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC 
00354 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
00355 
00356 /*!
00357  * RegSymbTimeoutLsb
00358  */
00359 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
00360 
00361 /*!
00362  * RegPreambleLengthMsb
00363  */
00364 #define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
00365 
00366 /*!
00367  * RegPreambleLengthLsb
00368  */
00369 #define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
00370 
00371 /*!
00372  * RegPayloadLength
00373  */
00374 #define RFLR_PAYLOADLENGTH                          0x0E // Default
00375 
00376 /*!
00377  * RegPayloadMaxLength
00378  */
00379 #define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
00380 
00381 /*!
00382  * RegHopPeriod
00383  */
00384 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
00385 
00386 /*!
00387  * RegFifoRxByteAddr (Read Only)
00388  */
00389 
00390 /*!
00391  * RegFeiMsb (Read Only)
00392  */
00393 
00394 /*!
00395  * RegFeiMid (Read Only)
00396  */
00397 
00398 /*!
00399  * RegFeiLsb (Read Only)
00400  */
00401 
00402 /*!
00403  * RegRssiWideband (Read Only)
00404  */
00405 
00406 /*!
00407  * RegDetectOptimize
00408  */
00409 #define RFLR_DETECTIONOPTIMIZE_MASK                 0xF8
00410 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12          0x03 // Default
00411 #define RFLR_DETECTIONOPTIMIZE_SF6                  0x05
00412 
00413 /*!
00414  * RegInvertIQ
00415  */
00416 #define RFLR_INVERTIQ_RX_MASK                       0xBF
00417 #define RFLR_INVERTIQ_RX_OFF                        0x00
00418 #define RFLR_INVERTIQ_RX_ON                         0x40
00419 #define RFLR_INVERTIQ_TX_MASK                       0xFE
00420 #define RFLR_INVERTIQ_TX_OFF                        0x01
00421 #define RFLR_INVERTIQ_TX_ON                         0x00
00422 
00423 /*!
00424  * RegDetectionThreshold
00425  */
00426 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12            0x0A // Default
00427 #define RFLR_DETECTIONTHRESH_SF6                    0x0C
00428 
00429 /*!
00430  * RegDioMapping1
00431  */
00432 #define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
00433 #define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
00434 #define RFLR_DIOMAPPING1_DIO0_01                    0x40
00435 #define RFLR_DIOMAPPING1_DIO0_10                    0x80
00436 #define RFLR_DIOMAPPING1_DIO0_11                    0xC0
00437 
00438 #define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
00439 #define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
00440 #define RFLR_DIOMAPPING1_DIO1_01                    0x10
00441 #define RFLR_DIOMAPPING1_DIO1_10                    0x20
00442 #define RFLR_DIOMAPPING1_DIO1_11                    0x30
00443 
00444 #define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
00445 #define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
00446 #define RFLR_DIOMAPPING1_DIO2_01                    0x04
00447 #define RFLR_DIOMAPPING1_DIO2_10                    0x08
00448 #define RFLR_DIOMAPPING1_DIO2_11                    0x0C
00449 
00450 #define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
00451 #define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
00452 #define RFLR_DIOMAPPING1_DIO3_01                    0x01
00453 #define RFLR_DIOMAPPING1_DIO3_10                    0x02
00454 #define RFLR_DIOMAPPING1_DIO3_11                    0x03
00455 
00456 /*!
00457  * RegDioMapping2
00458  */
00459 #define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
00460 #define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
00461 #define RFLR_DIOMAPPING2_DIO4_01                    0x40
00462 #define RFLR_DIOMAPPING2_DIO4_10                    0x80
00463 #define RFLR_DIOMAPPING2_DIO4_11                    0xC0
00464 
00465 #define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
00466 #define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
00467 #define RFLR_DIOMAPPING2_DIO5_01                    0x10
00468 #define RFLR_DIOMAPPING2_DIO5_10                    0x20
00469 #define RFLR_DIOMAPPING2_DIO5_11                    0x30
00470 
00471 #define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
00472 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
00473 #define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
00474 
00475 /*!
00476  * RegVersion (Read Only)
00477  */
00478 
00479 /*!
00480  * RegAgcRef
00481  */
00482 
00483 /*!
00484  * RegAgcThresh1
00485  */
00486 
00487 /*!
00488  * RegAgcThresh2
00489  */
00490 
00491 /*!
00492  * RegAgcThresh3
00493  */
00494  
00495 /*!
00496  * RegPllHop
00497  */
00498 #define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
00499 #define RFLR_PLLHOP_FASTHOP_ON                      0x80
00500 #define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
00501 
00502 /*!
00503  * RegTcxo
00504  */
00505 #define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
00506 #define RFLR_TCXO_TCXOINPUT_ON                      0x10
00507 #define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
00508 
00509 /*!
00510  * RegPaDac
00511  */
00512 #define RFLR_PADAC_20DBM_MASK                       0xF8
00513 #define RFLR_PADAC_20DBM_ON                         0x07
00514 #define RFLR_PADAC_20DBM_OFF                        0x04  // Default
00515 
00516 /*!
00517  * RegPll
00518  */
00519 #define RFLR_PLL_BANDWIDTH_MASK                     0x3F
00520 #define RFLR_PLL_BANDWIDTH_75                       0x00
00521 #define RFLR_PLL_BANDWIDTH_150                      0x40
00522 #define RFLR_PLL_BANDWIDTH_225                      0x80
00523 #define RFLR_PLL_BANDWIDTH_300                      0xC0  // Default
00524 
00525 /*!
00526  * RegPllLowPn
00527  */
00528 #define RFLR_PLLLOWPN_BANDWIDTH_MASK                0x3F
00529 #define RFLR_PLLLOWPN_BANDWIDTH_75                  0x00
00530 #define RFLR_PLLLOWPN_BANDWIDTH_150                 0x40
00531 #define RFLR_PLLLOWPN_BANDWIDTH_225                 0x80
00532 #define RFLR_PLLLOWPN_BANDWIDTH_300                 0xC0  // Default
00533 
00534 /*!
00535  * RegFormerTemp
00536  */
00537 
00538 #endif // __SX1272_REGS_LORA_H__