Milen Pavlov
XRange SX1272Lib
Dependents: XRangePingPong XRange-LoRaWAN-lmic-app lora-transceiver
SX1272 LoRa RF module https://www.netblocks.eu/xrange-sx1272-lora-datasheet/
Driver for the SX1272 RF Transceiver.
registers/sx1272Regs-LoRa.h@17:a5c9fd1a1ea6, 2015-05-31 (annotated)
- Committer:
- netblocks
- Date:
- Sun May 31 12:52:46 2015 +0000
- Revision:
- 17:a5c9fd1a1ea6
- Parent:
- registers/sx1276Regs-LoRa.h@13:618826a997e2
XRange SX1272Lib
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| GregCr | 0:e6ceb13d2d05 | 1 | /* |
| GregCr | 0:e6ceb13d2d05 | 2 | / _____) _ | | |
| GregCr | 0:e6ceb13d2d05 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
| GregCr | 0:e6ceb13d2d05 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
| GregCr | 0:e6ceb13d2d05 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
| GregCr | 0:e6ceb13d2d05 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
| netblocks | 17:a5c9fd1a1ea6 | 7 | (C)2013 Semtech |
| GregCr | 0:e6ceb13d2d05 | 8 | |
| netblocks | 17:a5c9fd1a1ea6 | 9 | Description: SX1272 LoRa modem registers and bits definitions |
| GregCr | 0:e6ceb13d2d05 | 10 | |
| GregCr | 0:e6ceb13d2d05 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
| GregCr | 0:e6ceb13d2d05 | 12 | |
| GregCr | 0:e6ceb13d2d05 | 13 | Maintainer: Miguel Luis and Gregory Cristian |
| GregCr | 0:e6ceb13d2d05 | 14 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 15 | #ifndef __SX1272_REGS_LORA_H__ |
| netblocks | 17:a5c9fd1a1ea6 | 16 | #define __SX1272_REGS_LORA_H__ |
| GregCr | 0:e6ceb13d2d05 | 17 | |
| GregCr | 0:e6ceb13d2d05 | 18 | /*! |
| GregCr | 0:e6ceb13d2d05 | 19 | * ============================================================================ |
| netblocks | 17:a5c9fd1a1ea6 | 20 | * SX1272 Internal registers Address |
| GregCr | 0:e6ceb13d2d05 | 21 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 22 | */ |
| GregCr | 0:e6ceb13d2d05 | 23 | #define REG_LR_FIFO 0x00 |
| GregCr | 0:e6ceb13d2d05 | 24 | // Common settings |
| GregCr | 0:e6ceb13d2d05 | 25 | #define REG_LR_OPMODE 0x01 |
| GregCr | 0:e6ceb13d2d05 | 26 | #define REG_LR_FRFMSB 0x06 |
| GregCr | 0:e6ceb13d2d05 | 27 | #define REG_LR_FRFMID 0x07 |
| GregCr | 0:e6ceb13d2d05 | 28 | #define REG_LR_FRFLSB 0x08 |
| GregCr | 0:e6ceb13d2d05 | 29 | // Tx settings |
| GregCr | 0:e6ceb13d2d05 | 30 | #define REG_LR_PACONFIG 0x09 |
| GregCr | 0:e6ceb13d2d05 | 31 | #define REG_LR_PARAMP 0x0A |
| GregCr | 0:e6ceb13d2d05 | 32 | #define REG_LR_OCP 0x0B |
| GregCr | 0:e6ceb13d2d05 | 33 | // Rx settings |
| GregCr | 0:e6ceb13d2d05 | 34 | #define REG_LR_LNA 0x0C |
| GregCr | 0:e6ceb13d2d05 | 35 | // LoRa registers |
| GregCr | 0:e6ceb13d2d05 | 36 | #define REG_LR_FIFOADDRPTR 0x0D |
| GregCr | 0:e6ceb13d2d05 | 37 | #define REG_LR_FIFOTXBASEADDR 0x0E |
| GregCr | 0:e6ceb13d2d05 | 38 | #define REG_LR_FIFORXBASEADDR 0x0F |
| GregCr | 0:e6ceb13d2d05 | 39 | #define REG_LR_FIFORXCURRENTADDR 0x10 |
| GregCr | 0:e6ceb13d2d05 | 40 | #define REG_LR_IRQFLAGSMASK 0x11 |
| GregCr | 0:e6ceb13d2d05 | 41 | #define REG_LR_IRQFLAGS 0x12 |
| GregCr | 0:e6ceb13d2d05 | 42 | #define REG_LR_RXNBBYTES 0x13 |
| GregCr | 0:e6ceb13d2d05 | 43 | #define REG_LR_RXHEADERCNTVALUEMSB 0x14 |
| GregCr | 0:e6ceb13d2d05 | 44 | #define REG_LR_RXHEADERCNTVALUELSB 0x15 |
| GregCr | 0:e6ceb13d2d05 | 45 | #define REG_LR_RXPACKETCNTVALUEMSB 0x16 |
| GregCr | 0:e6ceb13d2d05 | 46 | #define REG_LR_RXPACKETCNTVALUELSB 0x17 |
| GregCr | 0:e6ceb13d2d05 | 47 | #define REG_LR_MODEMSTAT 0x18 |
| GregCr | 0:e6ceb13d2d05 | 48 | #define REG_LR_PKTSNRVALUE 0x19 |
| GregCr | 0:e6ceb13d2d05 | 49 | #define REG_LR_PKTRSSIVALUE 0x1A |
| GregCr | 0:e6ceb13d2d05 | 50 | #define REG_LR_RSSIVALUE 0x1B |
| GregCr | 0:e6ceb13d2d05 | 51 | #define REG_LR_HOPCHANNEL 0x1C |
| GregCr | 0:e6ceb13d2d05 | 52 | #define REG_LR_MODEMCONFIG1 0x1D |
| GregCr | 0:e6ceb13d2d05 | 53 | #define REG_LR_MODEMCONFIG2 0x1E |
| GregCr | 0:e6ceb13d2d05 | 54 | #define REG_LR_SYMBTIMEOUTLSB 0x1F |
| GregCr | 0:e6ceb13d2d05 | 55 | #define REG_LR_PREAMBLEMSB 0x20 |
| GregCr | 0:e6ceb13d2d05 | 56 | #define REG_LR_PREAMBLELSB 0x21 |
| GregCr | 0:e6ceb13d2d05 | 57 | #define REG_LR_PAYLOADLENGTH 0x22 |
| GregCr | 0:e6ceb13d2d05 | 58 | #define REG_LR_PAYLOADMAXLENGTH 0x23 |
| GregCr | 0:e6ceb13d2d05 | 59 | #define REG_LR_HOPPERIOD 0x24 |
| GregCr | 0:e6ceb13d2d05 | 60 | #define REG_LR_FIFORXBYTEADDR 0x25 |
| GregCr | 0:e6ceb13d2d05 | 61 | #define REG_LR_FEIMSB 0x28 |
| GregCr | 0:e6ceb13d2d05 | 62 | #define REG_LR_FEIMID 0x29 |
| GregCr | 0:e6ceb13d2d05 | 63 | #define REG_LR_FEILSB 0x2A |
| GregCr | 0:e6ceb13d2d05 | 64 | #define REG_LR_RSSIWIDEBAND 0x2C |
| GregCr | 0:e6ceb13d2d05 | 65 | #define REG_LR_DETECTOPTIMIZE 0x31 |
| GregCr | 0:e6ceb13d2d05 | 66 | #define REG_LR_INVERTIQ 0x33 |
| GregCr | 0:e6ceb13d2d05 | 67 | #define REG_LR_DETECTIONTHRESHOLD 0x37 |
| mluis | 13:618826a997e2 | 68 | #define REG_LR_SYNCWORD 0x39 |
| mluis | 13:618826a997e2 | 69 | |
| GregCr | 0:e6ceb13d2d05 | 70 | // end of documented register in datasheet |
| GregCr | 0:e6ceb13d2d05 | 71 | // I/O settings |
| GregCr | 0:e6ceb13d2d05 | 72 | #define REG_LR_DIOMAPPING1 0x40 |
| GregCr | 0:e6ceb13d2d05 | 73 | #define REG_LR_DIOMAPPING2 0x41 |
| GregCr | 0:e6ceb13d2d05 | 74 | // Version |
| GregCr | 0:e6ceb13d2d05 | 75 | #define REG_LR_VERSION 0x42 |
| GregCr | 0:e6ceb13d2d05 | 76 | // Additional settings |
| netblocks | 17:a5c9fd1a1ea6 | 77 | #define REG_LR_AGCREF 0x43 |
| netblocks | 17:a5c9fd1a1ea6 | 78 | #define REG_LR_AGCTHRESH1 0x44 |
| netblocks | 17:a5c9fd1a1ea6 | 79 | #define REG_LR_AGCTHRESH2 0x45 |
| netblocks | 17:a5c9fd1a1ea6 | 80 | #define REG_LR_AGCTHRESH3 0x46 |
| netblocks | 17:a5c9fd1a1ea6 | 81 | #define REG_LR_PLLHOP 0x4B |
| netblocks | 17:a5c9fd1a1ea6 | 82 | #define REG_LR_TCXO 0x58 |
| netblocks | 17:a5c9fd1a1ea6 | 83 | #define REG_LR_PADAC 0x5A |
| netblocks | 17:a5c9fd1a1ea6 | 84 | #define REG_LR_PLL 0x5C |
| netblocks | 17:a5c9fd1a1ea6 | 85 | #define REG_LR_PLLLOWPN 0x5E |
| netblocks | 17:a5c9fd1a1ea6 | 86 | #define REG_LR_FORMERTEMP 0x6C |
| GregCr | 0:e6ceb13d2d05 | 87 | |
| GregCr | 0:e6ceb13d2d05 | 88 | /*! |
| GregCr | 0:e6ceb13d2d05 | 89 | * ============================================================================ |
| netblocks | 17:a5c9fd1a1ea6 | 90 | * SX1272 LoRa bits control definition |
| GregCr | 0:e6ceb13d2d05 | 91 | * ============================================================================ |
| GregCr | 0:e6ceb13d2d05 | 92 | */ |
| GregCr | 0:e6ceb13d2d05 | 93 | |
| GregCr | 0:e6ceb13d2d05 | 94 | /*! |
| GregCr | 0:e6ceb13d2d05 | 95 | * RegFifo |
| GregCr | 0:e6ceb13d2d05 | 96 | */ |
| GregCr | 0:e6ceb13d2d05 | 97 | |
| GregCr | 0:e6ceb13d2d05 | 98 | /*! |
| GregCr | 0:e6ceb13d2d05 | 99 | * RegOpMode |
| GregCr | 0:e6ceb13d2d05 | 100 | */ |
| GregCr | 0:e6ceb13d2d05 | 101 | #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 102 | #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 103 | #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 |
| GregCr | 0:e6ceb13d2d05 | 104 | |
| GregCr | 0:e6ceb13d2d05 | 105 | #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 106 | #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 |
| GregCr | 0:e6ceb13d2d05 | 107 | #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 108 | |
| GregCr | 0:e6ceb13d2d05 | 109 | #define RFLR_OPMODE_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 110 | #define RFLR_OPMODE_SLEEP 0x00 |
| GregCr | 0:e6ceb13d2d05 | 111 | #define RFLR_OPMODE_STANDBY 0x01 // Default |
| GregCr | 0:e6ceb13d2d05 | 112 | #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 |
| GregCr | 0:e6ceb13d2d05 | 113 | #define RFLR_OPMODE_TRANSMITTER 0x03 |
| GregCr | 0:e6ceb13d2d05 | 114 | #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 |
| GregCr | 0:e6ceb13d2d05 | 115 | #define RFLR_OPMODE_RECEIVER 0x05 |
| GregCr | 0:e6ceb13d2d05 | 116 | // LoRa specific modes |
| GregCr | 0:e6ceb13d2d05 | 117 | #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 |
| GregCr | 0:e6ceb13d2d05 | 118 | #define RFLR_OPMODE_CAD 0x07 |
| GregCr | 0:e6ceb13d2d05 | 119 | |
| GregCr | 0:e6ceb13d2d05 | 120 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 121 | * RegFrf (MHz) |
| GregCr | 0:e6ceb13d2d05 | 122 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 123 | #define RFLR_FRFMSB_915_MHZ 0xE4 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 124 | #define RFLR_FRFMID_915_MHZ 0xC0 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 125 | #define RFLR_FRFLSB_915_MHZ 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 126 | |
| GregCr | 0:e6ceb13d2d05 | 127 | /*! |
| GregCr | 0:e6ceb13d2d05 | 128 | * RegPaConfig |
| GregCr | 0:e6ceb13d2d05 | 129 | */ |
| GregCr | 0:e6ceb13d2d05 | 130 | #define RFLR_PACONFIG_PASELECT_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 131 | #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 |
| GregCr | 0:e6ceb13d2d05 | 132 | #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 133 | |
| GregCr | 0:e6ceb13d2d05 | 134 | #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 |
| GregCr | 0:e6ceb13d2d05 | 135 | |
| GregCr | 0:e6ceb13d2d05 | 136 | /*! |
| GregCr | 0:e6ceb13d2d05 | 137 | * RegPaRamp |
| GregCr | 0:e6ceb13d2d05 | 138 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 139 | #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 |
| netblocks | 17:a5c9fd1a1ea6 | 140 | #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 141 | #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 |
| GregCr | 0:e6ceb13d2d05 | 142 | |
| GregCr | 0:e6ceb13d2d05 | 143 | #define RFLR_PARAMP_MASK 0xF0 |
| GregCr | 0:e6ceb13d2d05 | 144 | #define RFLR_PARAMP_3400_US 0x00 |
| GregCr | 0:e6ceb13d2d05 | 145 | #define RFLR_PARAMP_2000_US 0x01 |
| GregCr | 0:e6ceb13d2d05 | 146 | #define RFLR_PARAMP_1000_US 0x02 |
| GregCr | 0:e6ceb13d2d05 | 147 | #define RFLR_PARAMP_0500_US 0x03 |
| GregCr | 0:e6ceb13d2d05 | 148 | #define RFLR_PARAMP_0250_US 0x04 |
| GregCr | 0:e6ceb13d2d05 | 149 | #define RFLR_PARAMP_0125_US 0x05 |
| GregCr | 0:e6ceb13d2d05 | 150 | #define RFLR_PARAMP_0100_US 0x06 |
| GregCr | 0:e6ceb13d2d05 | 151 | #define RFLR_PARAMP_0062_US 0x07 |
| GregCr | 0:e6ceb13d2d05 | 152 | #define RFLR_PARAMP_0050_US 0x08 |
| GregCr | 0:e6ceb13d2d05 | 153 | #define RFLR_PARAMP_0040_US 0x09 // Default |
| GregCr | 0:e6ceb13d2d05 | 154 | #define RFLR_PARAMP_0031_US 0x0A |
| GregCr | 0:e6ceb13d2d05 | 155 | #define RFLR_PARAMP_0025_US 0x0B |
| GregCr | 0:e6ceb13d2d05 | 156 | #define RFLR_PARAMP_0020_US 0x0C |
| GregCr | 0:e6ceb13d2d05 | 157 | #define RFLR_PARAMP_0015_US 0x0D |
| GregCr | 0:e6ceb13d2d05 | 158 | #define RFLR_PARAMP_0012_US 0x0E |
| GregCr | 0:e6ceb13d2d05 | 159 | #define RFLR_PARAMP_0010_US 0x0F |
| GregCr | 0:e6ceb13d2d05 | 160 | |
| GregCr | 0:e6ceb13d2d05 | 161 | /*! |
| GregCr | 0:e6ceb13d2d05 | 162 | * RegOcp |
| GregCr | 0:e6ceb13d2d05 | 163 | */ |
| GregCr | 0:e6ceb13d2d05 | 164 | #define RFLR_OCP_MASK 0xDF |
| GregCr | 0:e6ceb13d2d05 | 165 | #define RFLR_OCP_ON 0x20 // Default |
| GregCr | 0:e6ceb13d2d05 | 166 | #define RFLR_OCP_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 167 | |
| GregCr | 0:e6ceb13d2d05 | 168 | #define RFLR_OCP_TRIM_MASK 0xE0 |
| GregCr | 0:e6ceb13d2d05 | 169 | #define RFLR_OCP_TRIM_045_MA 0x00 |
| GregCr | 0:e6ceb13d2d05 | 170 | #define RFLR_OCP_TRIM_050_MA 0x01 |
| GregCr | 0:e6ceb13d2d05 | 171 | #define RFLR_OCP_TRIM_055_MA 0x02 |
| GregCr | 0:e6ceb13d2d05 | 172 | #define RFLR_OCP_TRIM_060_MA 0x03 |
| GregCr | 0:e6ceb13d2d05 | 173 | #define RFLR_OCP_TRIM_065_MA 0x04 |
| GregCr | 0:e6ceb13d2d05 | 174 | #define RFLR_OCP_TRIM_070_MA 0x05 |
| GregCr | 0:e6ceb13d2d05 | 175 | #define RFLR_OCP_TRIM_075_MA 0x06 |
| GregCr | 0:e6ceb13d2d05 | 176 | #define RFLR_OCP_TRIM_080_MA 0x07 |
| GregCr | 0:e6ceb13d2d05 | 177 | #define RFLR_OCP_TRIM_085_MA 0x08 |
| GregCr | 0:e6ceb13d2d05 | 178 | #define RFLR_OCP_TRIM_090_MA 0x09 |
| GregCr | 0:e6ceb13d2d05 | 179 | #define RFLR_OCP_TRIM_095_MA 0x0A |
| GregCr | 0:e6ceb13d2d05 | 180 | #define RFLR_OCP_TRIM_100_MA 0x0B // Default |
| GregCr | 0:e6ceb13d2d05 | 181 | #define RFLR_OCP_TRIM_105_MA 0x0C |
| GregCr | 0:e6ceb13d2d05 | 182 | #define RFLR_OCP_TRIM_110_MA 0x0D |
| GregCr | 0:e6ceb13d2d05 | 183 | #define RFLR_OCP_TRIM_115_MA 0x0E |
| GregCr | 0:e6ceb13d2d05 | 184 | #define RFLR_OCP_TRIM_120_MA 0x0F |
| GregCr | 0:e6ceb13d2d05 | 185 | #define RFLR_OCP_TRIM_130_MA 0x10 |
| GregCr | 0:e6ceb13d2d05 | 186 | #define RFLR_OCP_TRIM_140_MA 0x11 |
| GregCr | 0:e6ceb13d2d05 | 187 | #define RFLR_OCP_TRIM_150_MA 0x12 |
| GregCr | 0:e6ceb13d2d05 | 188 | #define RFLR_OCP_TRIM_160_MA 0x13 |
| GregCr | 0:e6ceb13d2d05 | 189 | #define RFLR_OCP_TRIM_170_MA 0x14 |
| GregCr | 0:e6ceb13d2d05 | 190 | #define RFLR_OCP_TRIM_180_MA 0x15 |
| GregCr | 0:e6ceb13d2d05 | 191 | #define RFLR_OCP_TRIM_190_MA 0x16 |
| GregCr | 0:e6ceb13d2d05 | 192 | #define RFLR_OCP_TRIM_200_MA 0x17 |
| GregCr | 0:e6ceb13d2d05 | 193 | #define RFLR_OCP_TRIM_210_MA 0x18 |
| GregCr | 0:e6ceb13d2d05 | 194 | #define RFLR_OCP_TRIM_220_MA 0x19 |
| GregCr | 0:e6ceb13d2d05 | 195 | #define RFLR_OCP_TRIM_230_MA 0x1A |
| GregCr | 0:e6ceb13d2d05 | 196 | #define RFLR_OCP_TRIM_240_MA 0x1B |
| GregCr | 0:e6ceb13d2d05 | 197 | |
| GregCr | 0:e6ceb13d2d05 | 198 | /*! |
| GregCr | 0:e6ceb13d2d05 | 199 | * RegLna |
| GregCr | 0:e6ceb13d2d05 | 200 | */ |
| GregCr | 0:e6ceb13d2d05 | 201 | #define RFLR_LNA_GAIN_MASK 0x1F |
| GregCr | 0:e6ceb13d2d05 | 202 | #define RFLR_LNA_GAIN_G1 0x20 // Default |
| GregCr | 0:e6ceb13d2d05 | 203 | #define RFLR_LNA_GAIN_G2 0x40 |
| GregCr | 0:e6ceb13d2d05 | 204 | #define RFLR_LNA_GAIN_G3 0x60 |
| GregCr | 0:e6ceb13d2d05 | 205 | #define RFLR_LNA_GAIN_G4 0x80 |
| GregCr | 0:e6ceb13d2d05 | 206 | #define RFLR_LNA_GAIN_G5 0xA0 |
| GregCr | 0:e6ceb13d2d05 | 207 | #define RFLR_LNA_GAIN_G6 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 208 | |
| netblocks | 17:a5c9fd1a1ea6 | 209 | #define RFLR_LNA_BOOST_MASK 0xFC |
| netblocks | 17:a5c9fd1a1ea6 | 210 | #define RFLR_LNA_BOOST_OFF 0x00 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 211 | #define RFLR_LNA_BOOST_ON 0x03 |
| GregCr | 0:e6ceb13d2d05 | 212 | |
| GregCr | 0:e6ceb13d2d05 | 213 | /*! |
| GregCr | 0:e6ceb13d2d05 | 214 | * RegFifoAddrPtr |
| GregCr | 0:e6ceb13d2d05 | 215 | */ |
| GregCr | 0:e6ceb13d2d05 | 216 | #define RFLR_FIFOADDRPTR 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 217 | |
| GregCr | 0:e6ceb13d2d05 | 218 | /*! |
| GregCr | 0:e6ceb13d2d05 | 219 | * RegFifoTxBaseAddr |
| GregCr | 0:e6ceb13d2d05 | 220 | */ |
| GregCr | 0:e6ceb13d2d05 | 221 | #define RFLR_FIFOTXBASEADDR 0x80 // Default |
| GregCr | 0:e6ceb13d2d05 | 222 | |
| GregCr | 0:e6ceb13d2d05 | 223 | /*! |
| GregCr | 0:e6ceb13d2d05 | 224 | * RegFifoTxBaseAddr |
| GregCr | 0:e6ceb13d2d05 | 225 | */ |
| GregCr | 0:e6ceb13d2d05 | 226 | #define RFLR_FIFORXBASEADDR 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 227 | |
| GregCr | 0:e6ceb13d2d05 | 228 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 229 | * RegFifoRxCurrentAddr (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 230 | */ |
| GregCr | 0:e6ceb13d2d05 | 231 | |
| GregCr | 0:e6ceb13d2d05 | 232 | /*! |
| GregCr | 0:e6ceb13d2d05 | 233 | * RegIrqFlagsMask |
| GregCr | 0:e6ceb13d2d05 | 234 | */ |
| GregCr | 0:e6ceb13d2d05 | 235 | #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 |
| GregCr | 0:e6ceb13d2d05 | 236 | #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 |
| GregCr | 0:e6ceb13d2d05 | 237 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 |
| GregCr | 0:e6ceb13d2d05 | 238 | #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 |
| GregCr | 0:e6ceb13d2d05 | 239 | #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 |
| GregCr | 0:e6ceb13d2d05 | 240 | #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 |
| GregCr | 0:e6ceb13d2d05 | 241 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 |
| GregCr | 0:e6ceb13d2d05 | 242 | #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 |
| GregCr | 0:e6ceb13d2d05 | 243 | |
| GregCr | 0:e6ceb13d2d05 | 244 | /*! |
| GregCr | 0:e6ceb13d2d05 | 245 | * RegIrqFlags |
| GregCr | 0:e6ceb13d2d05 | 246 | */ |
| GregCr | 0:e6ceb13d2d05 | 247 | #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 |
| GregCr | 0:e6ceb13d2d05 | 248 | #define RFLR_IRQFLAGS_RXDONE 0x40 |
| GregCr | 0:e6ceb13d2d05 | 249 | #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 |
| GregCr | 0:e6ceb13d2d05 | 250 | #define RFLR_IRQFLAGS_VALIDHEADER 0x10 |
| GregCr | 0:e6ceb13d2d05 | 251 | #define RFLR_IRQFLAGS_TXDONE 0x08 |
| GregCr | 0:e6ceb13d2d05 | 252 | #define RFLR_IRQFLAGS_CADDONE 0x04 |
| GregCr | 0:e6ceb13d2d05 | 253 | #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 |
| GregCr | 0:e6ceb13d2d05 | 254 | #define RFLR_IRQFLAGS_CADDETECTED 0x01 |
| GregCr | 0:e6ceb13d2d05 | 255 | |
| GregCr | 0:e6ceb13d2d05 | 256 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 257 | * RegFifoRxNbBytes (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 258 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 259 | |
| GregCr | 0:e6ceb13d2d05 | 260 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 261 | * RegRxHeaderCntValueMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 262 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 263 | |
| GregCr | 0:e6ceb13d2d05 | 264 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 265 | * RegRxHeaderCntValueLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 266 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 267 | |
| GregCr | 0:e6ceb13d2d05 | 268 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 269 | * RegRxPacketCntValueMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 270 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 271 | |
| GregCr | 0:e6ceb13d2d05 | 272 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 273 | * RegRxPacketCntValueLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 274 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 275 | |
| GregCr | 0:e6ceb13d2d05 | 276 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 277 | * RegModemStat (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 278 | */ |
| GregCr | 0:e6ceb13d2d05 | 279 | #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F |
| GregCr | 0:e6ceb13d2d05 | 280 | #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 |
| GregCr | 0:e6ceb13d2d05 | 281 | |
| GregCr | 0:e6ceb13d2d05 | 282 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 283 | * RegPktSnrValue (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 284 | */ |
| GregCr | 0:e6ceb13d2d05 | 285 | |
| GregCr | 0:e6ceb13d2d05 | 286 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 287 | * RegPktRssiValue (Read Only) |
| netblocks | 17:a5c9fd1a1ea6 | 288 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 289 | |
| netblocks | 17:a5c9fd1a1ea6 | 290 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 291 | * RegRssiValue (Read Only) |
| netblocks | 17:a5c9fd1a1ea6 | 292 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 293 | |
| netblocks | 17:a5c9fd1a1ea6 | 294 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 295 | * RegHopChannel (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 296 | */ |
| GregCr | 0:e6ceb13d2d05 | 297 | #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 298 | #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 |
| GregCr | 0:e6ceb13d2d05 | 299 | #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 300 | |
| GregCr | 0:e6ceb13d2d05 | 301 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 302 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 |
| GregCr | 0:e6ceb13d2d05 | 303 | #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 304 | |
| GregCr | 0:e6ceb13d2d05 | 305 | #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F |
| netblocks | 17:a5c9fd1a1ea6 | 306 | |
| GregCr | 0:e6ceb13d2d05 | 307 | /*! |
| GregCr | 0:e6ceb13d2d05 | 308 | * RegModemConfig1 |
| GregCr | 0:e6ceb13d2d05 | 309 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 310 | #define RFLR_MODEMCONFIG1_BW_MASK 0x3F |
| netblocks | 17:a5c9fd1a1ea6 | 311 | #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 312 | #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 |
| netblocks | 17:a5c9fd1a1ea6 | 313 | #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 |
| netblocks | 17:a5c9fd1a1ea6 | 314 | |
| netblocks | 17:a5c9fd1a1ea6 | 315 | #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 |
| netblocks | 17:a5c9fd1a1ea6 | 316 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 |
| netblocks | 17:a5c9fd1a1ea6 | 317 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 318 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 |
| netblocks | 17:a5c9fd1a1ea6 | 319 | #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 |
| GregCr | 0:e6ceb13d2d05 | 320 | |
| netblocks | 17:a5c9fd1a1ea6 | 321 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB |
| netblocks | 17:a5c9fd1a1ea6 | 322 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 |
| netblocks | 17:a5c9fd1a1ea6 | 323 | #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 324 | |
| netblocks | 17:a5c9fd1a1ea6 | 325 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD |
| netblocks | 17:a5c9fd1a1ea6 | 326 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 |
| netblocks | 17:a5c9fd1a1ea6 | 327 | #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 328 | |
| netblocks | 17:a5c9fd1a1ea6 | 329 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE |
| netblocks | 17:a5c9fd1a1ea6 | 330 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 |
| netblocks | 17:a5c9fd1a1ea6 | 331 | #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 332 | |
| GregCr | 0:e6ceb13d2d05 | 333 | /*! |
| GregCr | 0:e6ceb13d2d05 | 334 | * RegModemConfig2 |
| GregCr | 0:e6ceb13d2d05 | 335 | */ |
| GregCr | 0:e6ceb13d2d05 | 336 | #define RFLR_MODEMCONFIG2_SF_MASK 0x0F |
| GregCr | 0:e6ceb13d2d05 | 337 | #define RFLR_MODEMCONFIG2_SF_6 0x60 |
| GregCr | 0:e6ceb13d2d05 | 338 | #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default |
| GregCr | 0:e6ceb13d2d05 | 339 | #define RFLR_MODEMCONFIG2_SF_8 0x80 |
| GregCr | 0:e6ceb13d2d05 | 340 | #define RFLR_MODEMCONFIG2_SF_9 0x90 |
| GregCr | 0:e6ceb13d2d05 | 341 | #define RFLR_MODEMCONFIG2_SF_10 0xA0 |
| GregCr | 0:e6ceb13d2d05 | 342 | #define RFLR_MODEMCONFIG2_SF_11 0xB0 |
| GregCr | 0:e6ceb13d2d05 | 343 | #define RFLR_MODEMCONFIG2_SF_12 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 344 | |
| GregCr | 0:e6ceb13d2d05 | 345 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 |
| GregCr | 0:e6ceb13d2d05 | 346 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 |
| GregCr | 0:e6ceb13d2d05 | 347 | #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 348 | |
| netblocks | 17:a5c9fd1a1ea6 | 349 | #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB |
| netblocks | 17:a5c9fd1a1ea6 | 350 | #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 351 | #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 352 | |
| GregCr | 0:e6ceb13d2d05 | 353 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC |
| netblocks | 17:a5c9fd1a1ea6 | 354 | #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 355 | |
| GregCr | 0:e6ceb13d2d05 | 356 | /*! |
| GregCr | 0:e6ceb13d2d05 | 357 | * RegSymbTimeoutLsb |
| GregCr | 0:e6ceb13d2d05 | 358 | */ |
| GregCr | 0:e6ceb13d2d05 | 359 | #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default |
| GregCr | 0:e6ceb13d2d05 | 360 | |
| GregCr | 0:e6ceb13d2d05 | 361 | /*! |
| GregCr | 0:e6ceb13d2d05 | 362 | * RegPreambleLengthMsb |
| GregCr | 0:e6ceb13d2d05 | 363 | */ |
| GregCr | 0:e6ceb13d2d05 | 364 | #define RFLR_PREAMBLELENGTHMSB 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 365 | |
| GregCr | 0:e6ceb13d2d05 | 366 | /*! |
| GregCr | 0:e6ceb13d2d05 | 367 | * RegPreambleLengthLsb |
| GregCr | 0:e6ceb13d2d05 | 368 | */ |
| GregCr | 0:e6ceb13d2d05 | 369 | #define RFLR_PREAMBLELENGTHLSB 0x08 // Default |
| GregCr | 0:e6ceb13d2d05 | 370 | |
| GregCr | 0:e6ceb13d2d05 | 371 | /*! |
| GregCr | 0:e6ceb13d2d05 | 372 | * RegPayloadLength |
| GregCr | 0:e6ceb13d2d05 | 373 | */ |
| GregCr | 0:e6ceb13d2d05 | 374 | #define RFLR_PAYLOADLENGTH 0x0E // Default |
| GregCr | 0:e6ceb13d2d05 | 375 | |
| GregCr | 0:e6ceb13d2d05 | 376 | /*! |
| GregCr | 0:e6ceb13d2d05 | 377 | * RegPayloadMaxLength |
| GregCr | 0:e6ceb13d2d05 | 378 | */ |
| GregCr | 0:e6ceb13d2d05 | 379 | #define RFLR_PAYLOADMAXLENGTH 0xFF // Default |
| GregCr | 0:e6ceb13d2d05 | 380 | |
| GregCr | 0:e6ceb13d2d05 | 381 | /*! |
| GregCr | 0:e6ceb13d2d05 | 382 | * RegHopPeriod |
| GregCr | 0:e6ceb13d2d05 | 383 | */ |
| GregCr | 0:e6ceb13d2d05 | 384 | #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 385 | |
| GregCr | 0:e6ceb13d2d05 | 386 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 387 | * RegFifoRxByteAddr (Read Only) |
| netblocks | 17:a5c9fd1a1ea6 | 388 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 389 | |
| netblocks | 17:a5c9fd1a1ea6 | 390 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 391 | * RegFeiMsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 392 | */ |
| GregCr | 0:e6ceb13d2d05 | 393 | |
| GregCr | 0:e6ceb13d2d05 | 394 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 395 | * RegFeiMid (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 396 | */ |
| GregCr | 0:e6ceb13d2d05 | 397 | |
| GregCr | 0:e6ceb13d2d05 | 398 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 399 | * RegFeiLsb (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 400 | */ |
| GregCr | 0:e6ceb13d2d05 | 401 | |
| GregCr | 0:e6ceb13d2d05 | 402 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 403 | * RegRssiWideband (Read Only) |
| GregCr | 0:e6ceb13d2d05 | 404 | */ |
| GregCr | 0:e6ceb13d2d05 | 405 | |
| GregCr | 0:e6ceb13d2d05 | 406 | /*! |
| GregCr | 0:e6ceb13d2d05 | 407 | * RegDetectOptimize |
| GregCr | 0:e6ceb13d2d05 | 408 | */ |
| GregCr | 0:e6ceb13d2d05 | 409 | #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 410 | #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default |
| GregCr | 0:e6ceb13d2d05 | 411 | #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 |
| GregCr | 0:e6ceb13d2d05 | 412 | |
| GregCr | 0:e6ceb13d2d05 | 413 | /*! |
| GregCr | 0:e6ceb13d2d05 | 414 | * RegInvertIQ |
| GregCr | 0:e6ceb13d2d05 | 415 | */ |
| GregCr | 0:e6ceb13d2d05 | 416 | #define RFLR_INVERTIQ_RX_MASK 0xBF |
| GregCr | 0:e6ceb13d2d05 | 417 | #define RFLR_INVERTIQ_RX_OFF 0x00 |
| GregCr | 0:e6ceb13d2d05 | 418 | #define RFLR_INVERTIQ_RX_ON 0x40 |
| GregCr | 0:e6ceb13d2d05 | 419 | #define RFLR_INVERTIQ_TX_MASK 0xFE |
| GregCr | 0:e6ceb13d2d05 | 420 | #define RFLR_INVERTIQ_TX_OFF 0x01 |
| GregCr | 0:e6ceb13d2d05 | 421 | #define RFLR_INVERTIQ_TX_ON 0x00 |
| GregCr | 0:e6ceb13d2d05 | 422 | |
| GregCr | 0:e6ceb13d2d05 | 423 | /*! |
| GregCr | 0:e6ceb13d2d05 | 424 | * RegDetectionThreshold |
| GregCr | 0:e6ceb13d2d05 | 425 | */ |
| GregCr | 0:e6ceb13d2d05 | 426 | #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default |
| GregCr | 0:e6ceb13d2d05 | 427 | #define RFLR_DETECTIONTHRESH_SF6 0x0C |
| GregCr | 0:e6ceb13d2d05 | 428 | |
| GregCr | 0:e6ceb13d2d05 | 429 | /*! |
| GregCr | 0:e6ceb13d2d05 | 430 | * RegDioMapping1 |
| GregCr | 0:e6ceb13d2d05 | 431 | */ |
| GregCr | 0:e6ceb13d2d05 | 432 | #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F |
| GregCr | 0:e6ceb13d2d05 | 433 | #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 434 | #define RFLR_DIOMAPPING1_DIO0_01 0x40 |
| GregCr | 0:e6ceb13d2d05 | 435 | #define RFLR_DIOMAPPING1_DIO0_10 0x80 |
| GregCr | 0:e6ceb13d2d05 | 436 | #define RFLR_DIOMAPPING1_DIO0_11 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 437 | |
| GregCr | 0:e6ceb13d2d05 | 438 | #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF |
| GregCr | 0:e6ceb13d2d05 | 439 | #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 440 | #define RFLR_DIOMAPPING1_DIO1_01 0x10 |
| GregCr | 0:e6ceb13d2d05 | 441 | #define RFLR_DIOMAPPING1_DIO1_10 0x20 |
| GregCr | 0:e6ceb13d2d05 | 442 | #define RFLR_DIOMAPPING1_DIO1_11 0x30 |
| GregCr | 0:e6ceb13d2d05 | 443 | |
| GregCr | 0:e6ceb13d2d05 | 444 | #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 |
| GregCr | 0:e6ceb13d2d05 | 445 | #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 446 | #define RFLR_DIOMAPPING1_DIO2_01 0x04 |
| GregCr | 0:e6ceb13d2d05 | 447 | #define RFLR_DIOMAPPING1_DIO2_10 0x08 |
| GregCr | 0:e6ceb13d2d05 | 448 | #define RFLR_DIOMAPPING1_DIO2_11 0x0C |
| GregCr | 0:e6ceb13d2d05 | 449 | |
| GregCr | 0:e6ceb13d2d05 | 450 | #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC |
| GregCr | 0:e6ceb13d2d05 | 451 | #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 452 | #define RFLR_DIOMAPPING1_DIO3_01 0x01 |
| GregCr | 0:e6ceb13d2d05 | 453 | #define RFLR_DIOMAPPING1_DIO3_10 0x02 |
| GregCr | 0:e6ceb13d2d05 | 454 | #define RFLR_DIOMAPPING1_DIO3_11 0x03 |
| GregCr | 0:e6ceb13d2d05 | 455 | |
| GregCr | 0:e6ceb13d2d05 | 456 | /*! |
| GregCr | 0:e6ceb13d2d05 | 457 | * RegDioMapping2 |
| GregCr | 0:e6ceb13d2d05 | 458 | */ |
| GregCr | 0:e6ceb13d2d05 | 459 | #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F |
| GregCr | 0:e6ceb13d2d05 | 460 | #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 461 | #define RFLR_DIOMAPPING2_DIO4_01 0x40 |
| GregCr | 0:e6ceb13d2d05 | 462 | #define RFLR_DIOMAPPING2_DIO4_10 0x80 |
| GregCr | 0:e6ceb13d2d05 | 463 | #define RFLR_DIOMAPPING2_DIO4_11 0xC0 |
| GregCr | 0:e6ceb13d2d05 | 464 | |
| GregCr | 0:e6ceb13d2d05 | 465 | #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF |
| GregCr | 0:e6ceb13d2d05 | 466 | #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 467 | #define RFLR_DIOMAPPING2_DIO5_01 0x10 |
| GregCr | 0:e6ceb13d2d05 | 468 | #define RFLR_DIOMAPPING2_DIO5_10 0x20 |
| GregCr | 0:e6ceb13d2d05 | 469 | #define RFLR_DIOMAPPING2_DIO5_11 0x30 |
| GregCr | 0:e6ceb13d2d05 | 470 | |
| GregCr | 0:e6ceb13d2d05 | 471 | #define RFLR_DIOMAPPING2_MAP_MASK 0xFE |
| GregCr | 0:e6ceb13d2d05 | 472 | #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 |
| GregCr | 0:e6ceb13d2d05 | 473 | #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 474 | |
| GregCr | 0:e6ceb13d2d05 | 475 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 476 | * RegVersion (Read Only) |
| netblocks | 17:a5c9fd1a1ea6 | 477 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 478 | |
| netblocks | 17:a5c9fd1a1ea6 | 479 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 480 | * RegAgcRef |
| GregCr | 0:e6ceb13d2d05 | 481 | */ |
| GregCr | 0:e6ceb13d2d05 | 482 | |
| GregCr | 0:e6ceb13d2d05 | 483 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 484 | * RegAgcThresh1 |
| netblocks | 17:a5c9fd1a1ea6 | 485 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 486 | |
| netblocks | 17:a5c9fd1a1ea6 | 487 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 488 | * RegAgcThresh2 |
| netblocks | 17:a5c9fd1a1ea6 | 489 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 490 | |
| netblocks | 17:a5c9fd1a1ea6 | 491 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 492 | * RegAgcThresh3 |
| netblocks | 17:a5c9fd1a1ea6 | 493 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 494 | |
| netblocks | 17:a5c9fd1a1ea6 | 495 | /*! |
| GregCr | 0:e6ceb13d2d05 | 496 | * RegPllHop |
| GregCr | 0:e6ceb13d2d05 | 497 | */ |
| GregCr | 0:e6ceb13d2d05 | 498 | #define RFLR_PLLHOP_FASTHOP_MASK 0x7F |
| GregCr | 0:e6ceb13d2d05 | 499 | #define RFLR_PLLHOP_FASTHOP_ON 0x80 |
| GregCr | 0:e6ceb13d2d05 | 500 | #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 501 | |
| GregCr | 0:e6ceb13d2d05 | 502 | /*! |
| GregCr | 0:e6ceb13d2d05 | 503 | * RegTcxo |
| GregCr | 0:e6ceb13d2d05 | 504 | */ |
| GregCr | 0:e6ceb13d2d05 | 505 | #define RFLR_TCXO_TCXOINPUT_MASK 0xEF |
| GregCr | 0:e6ceb13d2d05 | 506 | #define RFLR_TCXO_TCXOINPUT_ON 0x10 |
| GregCr | 0:e6ceb13d2d05 | 507 | #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default |
| GregCr | 0:e6ceb13d2d05 | 508 | |
| GregCr | 0:e6ceb13d2d05 | 509 | /*! |
| GregCr | 0:e6ceb13d2d05 | 510 | * RegPaDac |
| GregCr | 0:e6ceb13d2d05 | 511 | */ |
| GregCr | 0:e6ceb13d2d05 | 512 | #define RFLR_PADAC_20DBM_MASK 0xF8 |
| GregCr | 0:e6ceb13d2d05 | 513 | #define RFLR_PADAC_20DBM_ON 0x07 |
| GregCr | 0:e6ceb13d2d05 | 514 | #define RFLR_PADAC_20DBM_OFF 0x04 // Default |
| GregCr | 0:e6ceb13d2d05 | 515 | |
| GregCr | 0:e6ceb13d2d05 | 516 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 517 | * RegPll |
| netblocks | 17:a5c9fd1a1ea6 | 518 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 519 | #define RFLR_PLL_BANDWIDTH_MASK 0x3F |
| netblocks | 17:a5c9fd1a1ea6 | 520 | #define RFLR_PLL_BANDWIDTH_75 0x00 |
| netblocks | 17:a5c9fd1a1ea6 | 521 | #define RFLR_PLL_BANDWIDTH_150 0x40 |
| netblocks | 17:a5c9fd1a1ea6 | 522 | #define RFLR_PLL_BANDWIDTH_225 0x80 |
| netblocks | 17:a5c9fd1a1ea6 | 523 | #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 524 | |
| netblocks | 17:a5c9fd1a1ea6 | 525 | /*! |
| netblocks | 17:a5c9fd1a1ea6 | 526 | * RegPllLowPn |
| netblocks | 17:a5c9fd1a1ea6 | 527 | */ |
| netblocks | 17:a5c9fd1a1ea6 | 528 | #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F |
| netblocks | 17:a5c9fd1a1ea6 | 529 | #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 |
| netblocks | 17:a5c9fd1a1ea6 | 530 | #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 |
| netblocks | 17:a5c9fd1a1ea6 | 531 | #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 |
| netblocks | 17:a5c9fd1a1ea6 | 532 | #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default |
| netblocks | 17:a5c9fd1a1ea6 | 533 | |
| netblocks | 17:a5c9fd1a1ea6 | 534 | /*! |
| GregCr | 0:e6ceb13d2d05 | 535 | * RegFormerTemp |
| GregCr | 0:e6ceb13d2d05 | 536 | */ |
| GregCr | 0:e6ceb13d2d05 | 537 | |
| netblocks | 17:a5c9fd1a1ea6 | 538 | #endif // __SX1272_REGS_LORA_H__ |