[11U68]fix P0_11 to use GPIO
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core_ca9.h
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00001 /**************************************************************************//** 00002 * @file core_ca9.h 00003 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File 00004 * @version 00005 * @date 25 March 2013 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2012 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 #ifndef __CORE_CA9_H_GENERIC 00047 #define __CORE_CA9_H_GENERIC 00048 00049 00050 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00051 CMSIS violates the following MISRA-C:2004 rules: 00052 00053 \li Required Rule 8.5, object/function definition in header file.<br> 00054 Function definitions in header files are used to allow 'inlining'. 00055 00056 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00057 Unions are used for effective representation of core registers. 00058 00059 \li Advisory Rule 19.7, Function-like macro defined.<br> 00060 Function-like macros are used to allow more efficient code. 00061 */ 00062 00063 00064 /******************************************************************************* 00065 * CMSIS definitions 00066 ******************************************************************************/ 00067 /** \ingroup Cortex_A9 00068 @{ 00069 */ 00070 00071 /* CMSIS CA9 definitions */ 00072 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00073 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ 00074 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \ 00075 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00076 00077 #define __CORTEX_A (0x09) /*!< Cortex-A Core */ 00078 00079 00080 #if defined ( __CC_ARM ) 00081 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00082 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00083 #define __STATIC_INLINE static __inline 00084 #define __STATIC_ASM static __asm 00085 00086 #elif defined ( __ICCARM__ ) 00087 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00088 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00089 #define __STATIC_INLINE static inline 00090 #define __STATIC_ASM static __asm 00091 00092 #elif defined ( __TMS470__ ) 00093 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00094 #define __STATIC_INLINE static inline 00095 #define __STATIC_ASM static __asm 00096 00097 #elif defined ( __GNUC__ ) 00098 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00099 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00100 #define __STATIC_INLINE static inline 00101 #define __STATIC_ASM static __asm 00102 00103 #elif defined ( __TASKING__ ) 00104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00106 #define __STATIC_INLINE static inline 00107 #define __STATIC_ASM static __asm 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00112 */ 00113 #if defined ( __CC_ARM ) 00114 #if defined __TARGET_FPU_VFP 00115 #if (__FPU_PRESENT == 1) 00116 #define __FPU_USED 1 00117 #else 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #define __FPU_USED 0 00120 #endif 00121 #else 00122 #define __FPU_USED 0 00123 #endif 00124 00125 #elif defined ( __ICCARM__ ) 00126 #if defined __ARMVFP__ 00127 #if (__FPU_PRESENT == 1) 00128 #define __FPU_USED 1 00129 #else 00130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00131 #define __FPU_USED 0 00132 #endif 00133 #else 00134 #define __FPU_USED 0 00135 #endif 00136 00137 #elif defined ( __TMS470__ ) 00138 #if defined __TI_VFP_SUPPORT__ 00139 #if (__FPU_PRESENT == 1) 00140 #define __FPU_USED 1 00141 #else 00142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00143 #define __FPU_USED 0 00144 #endif 00145 #else 00146 #define __FPU_USED 0 00147 #endif 00148 00149 #elif defined ( __GNUC__ ) 00150 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00151 #if (__FPU_PRESENT == 1) 00152 #define __FPU_USED 1 00153 #else 00154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00155 #define __FPU_USED 0 00156 #endif 00157 #else 00158 #define __FPU_USED 0 00159 #endif 00160 00161 #elif defined ( __TASKING__ ) 00162 #if defined __FPU_VFP__ 00163 #if (__FPU_PRESENT == 1) 00164 #define __FPU_USED 1 00165 #else 00166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00167 #define __FPU_USED 0 00168 #endif 00169 #else 00170 #define __FPU_USED 0 00171 #endif 00172 #endif 00173 00174 #include <stdint.h> /*!< standard types definitions */ 00175 #include "core_caInstr.h" /*!< Core Instruction Access */ 00176 #include "core_caFunc.h" /*!< Core Function Access */ 00177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */ 00178 00179 #endif /* __CORE_CA9_H_GENERIC */ 00180 00181 #ifndef __CMSIS_GENERIC 00182 00183 #ifndef __CORE_CA9_H_DEPENDANT 00184 #define __CORE_CA9_H_DEPENDANT 00185 00186 /* check device defines and use defaults */ 00187 #if defined __CHECK_DEVICE_DEFINES 00188 #ifndef __CA9_REV 00189 #define __CA9_REV 0x0000 00190 #warning "__CA9_REV not defined in device header file; using default!" 00191 #endif 00192 00193 #ifndef __FPU_PRESENT 00194 #define __FPU_PRESENT 1 00195 #warning "__FPU_PRESENT not defined in device header file; using default!" 00196 #endif 00197 00198 #ifndef __Vendor_SysTickConfig 00199 #define __Vendor_SysTickConfig 1 00200 #endif 00201 00202 #if __Vendor_SysTickConfig == 0 00203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9" 00204 #endif 00205 #endif 00206 00207 /* IO definitions (access restrictions to peripheral registers) */ 00208 /** 00209 \defgroup CMSIS_glob_defs CMSIS Global Defines 00210 00211 <strong>IO Type Qualifiers</strong> are used 00212 \li to specify the access to peripheral variables. 00213 \li for automatic generation of peripheral register debug information. 00214 */ 00215 #ifdef __cplusplus 00216 #define __I volatile /*!< Defines 'read only' permissions */ 00217 #else 00218 #define __I volatile const /*!< Defines 'read only' permissions */ 00219 #endif 00220 #define __O volatile /*!< Defines 'write only' permissions */ 00221 #define __IO volatile /*!< Defines 'read / write' permissions */ 00222 00223 /*@} end of group Cortex_A9 */ 00224 00225 00226 /******************************************************************************* 00227 * Register Abstraction 00228 ******************************************************************************/ 00229 /** \defgroup CMSIS_core_register Defines and Type Definitions 00230 \brief Type definitions and defines for Cortex-A processor based devices. 00231 */ 00232 00233 /** \ingroup CMSIS_core_register 00234 \defgroup CMSIS_CORE Status and Control Registers 00235 \brief Core Register type definitions. 00236 @{ 00237 */ 00238 00239 /** \brief Union type to access the Application Program Status Register (APSR). 00240 */ 00241 typedef union 00242 { 00243 struct 00244 { 00245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */ 00248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00253 } b; /*!< Structure used for bit access */ 00254 uint32_t w ; /*!< Type used for word access */ 00255 } APSR_Type; 00256 00257 00258 /*@} end of group CMSIS_CORE */ 00259 00260 /*@} end of CMSIS_Core_FPUFunctions */ 00261 00262 00263 #endif /* __CORE_CA9_H_GENERIC */ 00264 00265 #endif /* __CMSIS_GENERIC */ 00266 00267 #ifdef __cplusplus 00268 } 00269 00270 00271 #endif
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