en 129 / mbed-src

[11U68]fix P0_11 to use GPIO

Fork of mbed-src by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Child:
482:d9a48e768ce0
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file system_MBRZA1H.c
mbed_official 390:35c2c1cf29cd 3 * @brief CMSIS Device System Source File for
mbed_official 390:35c2c1cf29cd 4 * ARMCA9 Device Series
mbed_official 390:35c2c1cf29cd 5 * @version V1.00
mbed_official 390:35c2c1cf29cd 6 * @date 19 Sept 2013
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * @note
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 11 /* Copyright (c) 2011 - 2013 ARM LIMITED
mbed_official 390:35c2c1cf29cd 12
mbed_official 390:35c2c1cf29cd 13 All rights reserved.
mbed_official 390:35c2c1cf29cd 14 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 15 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 16 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 17 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 18 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 19 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 20 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 21 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 22 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 23 specific prior written permission.
mbed_official 390:35c2c1cf29cd 24 *
mbed_official 390:35c2c1cf29cd 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 35 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 36 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38
mbed_official 390:35c2c1cf29cd 39 #include <stdint.h>
mbed_official 390:35c2c1cf29cd 40 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 41 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 42
mbed_official 390:35c2c1cf29cd 43
mbed_official 390:35c2c1cf29cd 44 extern void $Super$$main(void);
mbed_official 390:35c2c1cf29cd 45 __asm void FPUEnable(void);
mbed_official 390:35c2c1cf29cd 46
mbed_official 390:35c2c1cf29cd 47 uint32_t IRQNestLevel;
mbed_official 390:35c2c1cf29cd 48
mbed_official 390:35c2c1cf29cd 49
mbed_official 390:35c2c1cf29cd 50 /**
mbed_official 390:35c2c1cf29cd 51 * Initialize the cache.
mbed_official 390:35c2c1cf29cd 52 *
mbed_official 390:35c2c1cf29cd 53 * @param none
mbed_official 390:35c2c1cf29cd 54 * @return none
mbed_official 390:35c2c1cf29cd 55 *
mbed_official 390:35c2c1cf29cd 56 * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
mbed_official 390:35c2c1cf29cd 57 */
mbed_official 390:35c2c1cf29cd 58 #pragma push
mbed_official 390:35c2c1cf29cd 59 #pragma arm
mbed_official 390:35c2c1cf29cd 60
mbed_official 390:35c2c1cf29cd 61 void InitMemorySubsystem(void) {
mbed_official 390:35c2c1cf29cd 62
mbed_official 390:35c2c1cf29cd 63 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
mbed_official 390:35c2c1cf29cd 64 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
mbed_official 390:35c2c1cf29cd 65 * You are not required to invalidate the main TLB, even though it is recommended for safety
mbed_official 390:35c2c1cf29cd 66 * reasons. This ensures compatibility with future revisions of the processor. */
mbed_official 390:35c2c1cf29cd 67
mbed_official 390:35c2c1cf29cd 68 unsigned int l2_id;
mbed_official 390:35c2c1cf29cd 69
mbed_official 390:35c2c1cf29cd 70 /* Invalidate undefined data */
mbed_official 390:35c2c1cf29cd 71 __ca9u_inv_tlb_all();
mbed_official 390:35c2c1cf29cd 72 __v7_inv_icache_all();
mbed_official 390:35c2c1cf29cd 73 __v7_inv_dcache_all();
mbed_official 390:35c2c1cf29cd 74 __v7_inv_btac();
mbed_official 390:35c2c1cf29cd 75
mbed_official 390:35c2c1cf29cd 76 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
mbed_official 390:35c2c1cf29cd 77 * invalidate in order to flush the valid data to the next level cache.
mbed_official 390:35c2c1cf29cd 78 */
mbed_official 390:35c2c1cf29cd 79 __enable_mmu();
mbed_official 390:35c2c1cf29cd 80
mbed_official 390:35c2c1cf29cd 81 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
mbed_official 390:35c2c1cf29cd 82 __enable_caches();
mbed_official 390:35c2c1cf29cd 83 __enable_btac();
mbed_official 390:35c2c1cf29cd 84
mbed_official 390:35c2c1cf29cd 85 /* If present, you may also need to Invalidate and Enable L2 cache here */
mbed_official 390:35c2c1cf29cd 86 l2_id = PL310_GetID();
mbed_official 390:35c2c1cf29cd 87 if (l2_id)
mbed_official 390:35c2c1cf29cd 88 {
mbed_official 390:35c2c1cf29cd 89 PL310_InvAllByWay();
mbed_official 390:35c2c1cf29cd 90 PL310_Enable();
mbed_official 390:35c2c1cf29cd 91 }
mbed_official 390:35c2c1cf29cd 92 }
mbed_official 390:35c2c1cf29cd 93 #pragma pop
mbed_official 390:35c2c1cf29cd 94
mbed_official 390:35c2c1cf29cd 95 IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
mbed_official 390:35c2c1cf29cd 96
mbed_official 390:35c2c1cf29cd 97 uint32_t IRQCount = sizeof IRQTable / 4;
mbed_official 390:35c2c1cf29cd 98
mbed_official 390:35c2c1cf29cd 99 uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
mbed_official 390:35c2c1cf29cd 100 {
mbed_official 390:35c2c1cf29cd 101 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 102 IRQTable[irq] = handler;
mbed_official 390:35c2c1cf29cd 103 return 0;
mbed_official 390:35c2c1cf29cd 104 }
mbed_official 390:35c2c1cf29cd 105 else {
mbed_official 390:35c2c1cf29cd 106 return 1;
mbed_official 390:35c2c1cf29cd 107 }
mbed_official 390:35c2c1cf29cd 108 }
mbed_official 390:35c2c1cf29cd 109
mbed_official 390:35c2c1cf29cd 110 uint32_t InterruptHandlerUnregister (IRQn_Type irq)
mbed_official 390:35c2c1cf29cd 111 {
mbed_official 390:35c2c1cf29cd 112 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 113 IRQTable[irq] = 0;
mbed_official 390:35c2c1cf29cd 114 return 0;
mbed_official 390:35c2c1cf29cd 115 }
mbed_official 390:35c2c1cf29cd 116 else {
mbed_official 390:35c2c1cf29cd 117 return 1;
mbed_official 390:35c2c1cf29cd 118 }
mbed_official 390:35c2c1cf29cd 119 }
mbed_official 390:35c2c1cf29cd 120
mbed_official 390:35c2c1cf29cd 121 /**
mbed_official 390:35c2c1cf29cd 122 * Initialize the system
mbed_official 390:35c2c1cf29cd 123 *
mbed_official 390:35c2c1cf29cd 124 * @param none
mbed_official 390:35c2c1cf29cd 125 * @return none
mbed_official 390:35c2c1cf29cd 126 *
mbed_official 390:35c2c1cf29cd 127 * @brief Setup the microcontroller system.
mbed_official 390:35c2c1cf29cd 128 * Initialize the System.
mbed_official 390:35c2c1cf29cd 129 */
mbed_official 390:35c2c1cf29cd 130 void SystemInit (void)
mbed_official 390:35c2c1cf29cd 131 {
mbed_official 390:35c2c1cf29cd 132 IRQNestLevel = 0;
mbed_official 390:35c2c1cf29cd 133 /* do not use global variables because this function is called before
mbed_official 390:35c2c1cf29cd 134 reaching pre-main. RW section maybe overwritten afterwards. */
mbed_official 390:35c2c1cf29cd 135 RZ_A1_InitClock();
mbed_official 390:35c2c1cf29cd 136 RZ_A1_InitBus();
mbed_official 390:35c2c1cf29cd 137
mbed_official 390:35c2c1cf29cd 138 //Configure GIC ICDICFR GIC_SetICDICFR()
mbed_official 390:35c2c1cf29cd 139 GIC_Enable();
mbed_official 390:35c2c1cf29cd 140 __enable_irq();
mbed_official 390:35c2c1cf29cd 141
mbed_official 390:35c2c1cf29cd 142 }
mbed_official 390:35c2c1cf29cd 143
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 //Fault Status Register (IFSR/DFSR) definitions
mbed_official 390:35c2c1cf29cd 146 #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
mbed_official 390:35c2c1cf29cd 147 #define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 148 #define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
mbed_official 390:35c2c1cf29cd 149 #define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
mbed_official 390:35c2c1cf29cd 150 #define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
mbed_official 390:35c2c1cf29cd 151 #define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
mbed_official 390:35c2c1cf29cd 152 #define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 153 #define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 154 #define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 155 #define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 156 #define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 157 #define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 158 #define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 159 #define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 160 #define FSR_DEBUG_EVENT 0x02 //internal
mbed_official 390:35c2c1cf29cd 161 #define FSR_SYNC_EXT_ABORT 0x08 //sync/external
mbed_official 390:35c2c1cf29cd 162 #define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
mbed_official 390:35c2c1cf29cd 163 #define FSR_LOCKDOWN 0x14 //internal
mbed_official 390:35c2c1cf29cd 164 #define FSR_COPROCESSOR_ABORT 0x1a //internal
mbed_official 390:35c2c1cf29cd 165 #define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
mbed_official 390:35c2c1cf29cd 166 #define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 167 #define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 168
mbed_official 390:35c2c1cf29cd 169 void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 170 uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 171
mbed_official 390:35c2c1cf29cd 172 switch(FS) {
mbed_official 390:35c2c1cf29cd 173 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 174 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 175 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 176 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 177 return;
mbed_official 390:35c2c1cf29cd 178
mbed_official 390:35c2c1cf29cd 179 //Your code here. Value in DFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 180 case FSR_ALIGNMENT_FAULT:
mbed_official 390:35c2c1cf29cd 181 case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
mbed_official 390:35c2c1cf29cd 182 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 183 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 184 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 185 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 186 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 187 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 188 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 189 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 190 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 191 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 192 case FSR_DEBUG_EVENT:
mbed_official 390:35c2c1cf29cd 193 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 194 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 195 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 196 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 197 case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
mbed_official 390:35c2c1cf29cd 198 case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
mbed_official 390:35c2c1cf29cd 199 default:
mbed_official 390:35c2c1cf29cd 200 while(1);
mbed_official 390:35c2c1cf29cd 201 }
mbed_official 390:35c2c1cf29cd 202 }
mbed_official 390:35c2c1cf29cd 203
mbed_official 390:35c2c1cf29cd 204 void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 205 uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 206
mbed_official 390:35c2c1cf29cd 207 switch(FS) {
mbed_official 390:35c2c1cf29cd 208 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 209 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 210 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 211 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 212 return;
mbed_official 390:35c2c1cf29cd 213
mbed_official 390:35c2c1cf29cd 214 //Your code here. Value in IFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 215 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 216 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 217 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 218 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 219 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 220 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 221 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 222 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 223 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 224 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 225 case FSR_DEBUG_EVENT: //IFAR invalid
mbed_official 390:35c2c1cf29cd 226 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 227 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 228 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 229 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 230 default:
mbed_official 390:35c2c1cf29cd 231 while(1);
mbed_official 390:35c2c1cf29cd 232 }
mbed_official 390:35c2c1cf29cd 233 }
mbed_official 390:35c2c1cf29cd 234
mbed_official 390:35c2c1cf29cd 235 //returns amount to decrement lr by
mbed_official 390:35c2c1cf29cd 236 //this will be 0 when we have emulated the instruction and simply want to execute the next instruction
mbed_official 390:35c2c1cf29cd 237 //this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
mbed_official 390:35c2c1cf29cd 238 //this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
mbed_official 390:35c2c1cf29cd 239 uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 240 const int THUMB = 2;
mbed_official 390:35c2c1cf29cd 241 const int ARM = 4;
mbed_official 390:35c2c1cf29cd 242 //Lazy VFP/NEON initialisation and switching
mbed_official 390:35c2c1cf29cd 243 if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
mbed_official 390:35c2c1cf29cd 244 (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
mbed_official 390:35c2c1cf29cd 245 if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
mbed_official 390:35c2c1cf29cd 246 FPUEnable();
mbed_official 390:35c2c1cf29cd 247 return state;
mbed_official 390:35c2c1cf29cd 248 }
mbed_official 390:35c2c1cf29cd 249 }
mbed_official 390:35c2c1cf29cd 250
mbed_official 390:35c2c1cf29cd 251 //Add code here for other Undef cases
mbed_official 390:35c2c1cf29cd 252 while(1);
mbed_official 390:35c2c1cf29cd 253 }
mbed_official 390:35c2c1cf29cd 254
mbed_official 390:35c2c1cf29cd 255 #pragma push
mbed_official 390:35c2c1cf29cd 256 #pragma arm
mbed_official 390:35c2c1cf29cd 257 //Critical section, called from undef handler, so systick is disabled
mbed_official 390:35c2c1cf29cd 258 __asm void FPUEnable(void) {
mbed_official 390:35c2c1cf29cd 259 ARM
mbed_official 390:35c2c1cf29cd 260
mbed_official 390:35c2c1cf29cd 261 //Permit access to VFP registers by modifying CPACR
mbed_official 390:35c2c1cf29cd 262 MRC p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 263 ORR R1,R1,#0x00F00000
mbed_official 390:35c2c1cf29cd 264 MCR p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 265
mbed_official 390:35c2c1cf29cd 266 //Enable VFP
mbed_official 390:35c2c1cf29cd 267 VMRS R1,FPEXC
mbed_official 390:35c2c1cf29cd 268 ORR R1,R1,#0x40000000
mbed_official 390:35c2c1cf29cd 269 VMSR FPEXC,R1
mbed_official 390:35c2c1cf29cd 270
mbed_official 390:35c2c1cf29cd 271 //Initialise VFP registers to 0
mbed_official 390:35c2c1cf29cd 272 MOV R2,#0
mbed_official 390:35c2c1cf29cd 273 VMOV D0, R2,R2
mbed_official 390:35c2c1cf29cd 274 VMOV D1, R2,R2
mbed_official 390:35c2c1cf29cd 275 VMOV D2, R2,R2
mbed_official 390:35c2c1cf29cd 276 VMOV D3, R2,R2
mbed_official 390:35c2c1cf29cd 277 VMOV D4, R2,R2
mbed_official 390:35c2c1cf29cd 278 VMOV D5, R2,R2
mbed_official 390:35c2c1cf29cd 279 VMOV D6, R2,R2
mbed_official 390:35c2c1cf29cd 280 VMOV D7, R2,R2
mbed_official 390:35c2c1cf29cd 281 VMOV D8, R2,R2
mbed_official 390:35c2c1cf29cd 282 VMOV D9, R2,R2
mbed_official 390:35c2c1cf29cd 283 VMOV D10,R2,R2
mbed_official 390:35c2c1cf29cd 284 VMOV D11,R2,R2
mbed_official 390:35c2c1cf29cd 285 VMOV D12,R2,R2
mbed_official 390:35c2c1cf29cd 286 VMOV D13,R2,R2
mbed_official 390:35c2c1cf29cd 287 VMOV D14,R2,R2
mbed_official 390:35c2c1cf29cd 288 VMOV D15,R2,R2
mbed_official 390:35c2c1cf29cd 289
mbed_official 390:35c2c1cf29cd 290 //Initialise FPSCR to a known state
mbed_official 390:35c2c1cf29cd 291 VMRS R2,FPSCR
mbed_official 390:35c2c1cf29cd 292 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
mbed_official 390:35c2c1cf29cd 293 AND R2,R2,R3
mbed_official 390:35c2c1cf29cd 294 VMSR FPSCR,R2
mbed_official 390:35c2c1cf29cd 295
mbed_official 390:35c2c1cf29cd 296 BX LR
mbed_official 390:35c2c1cf29cd 297 }
mbed_official 390:35c2c1cf29cd 298 #pragma pop