Ibrahim Abd Elkader
/
nrflash
Program Nordic nRF24LU1+ chips using SPI.
nrflash.cpp@0:f9a5ac1b59f7, 2011-03-13 (annotated)
- Committer:
- mux
- Date:
- Sun Mar 13 11:30:09 2011 +0000
- Revision:
- 0:f9a5ac1b59f7
1.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mux | 0:f9a5ac1b59f7 | 1 | #include <nrflash.h> |
mux | 0:f9a5ac1b59f7 | 2 | #define WREN (0x06) /*Set flash write enable,FSR.WEN*/ |
mux | 0:f9a5ac1b59f7 | 3 | #define WRDIS (0x04) /*Reset flash write enable, FSR.WEN*/ |
mux | 0:f9a5ac1b59f7 | 4 | #define RDSR (0x05) /*1 (or more) Read Flash Status Register (FSR)*/ |
mux | 0:f9a5ac1b59f7 | 5 | #define WRSR (0x01) /*1 Write Flash Status Register (FSR).*/ |
mux | 0:f9a5ac1b59f7 | 6 | #define READ (0x03) /*Read data from flash*/ |
mux | 0:f9a5ac1b59f7 | 7 | #define PROGRAM (0x02) /*Write data to flash*/ |
mux | 0:f9a5ac1b59f7 | 8 | #define ERASE_PAGE (0x52) /*Erase addressed flash page*/ |
mux | 0:f9a5ac1b59f7 | 9 | #define ERASE_ALL (0x62) /* Erase all pages of flash MainBlock*/ |
mux | 0:f9a5ac1b59f7 | 10 | #define RDFPCR (0x89) /*Read Flash Protect Configuration Register (FPCR)*/ |
mux | 0:f9a5ac1b59f7 | 11 | #define RDISIP (0x84) /*Set flash InfoPage read-back disable*/ |
mux | 0:f9a5ac1b59f7 | 12 | #define RDISMB (0x85) /*Set flash MainBlock read-back disable*/ |
mux | 0:f9a5ac1b59f7 | 13 | #define ENDEBUG (0x86) /*Write 0x00 to InfoPage byte 0x24*/ |
mux | 0:f9a5ac1b59f7 | 14 | #define RDYN (1<<4) |
mux | 0:f9a5ac1b59f7 | 15 | #define FLASH_LEN (32768) |
mux | 0:f9a5ac1b59f7 | 16 | NRFlash::NRFlash(PinName mosi, PinName miso, PinName sclk, PinName ssel_, PinName prog_, PinName rst_): |
mux | 0:f9a5ac1b59f7 | 17 | spi(mosi, miso, sclk), |
mux | 0:f9a5ac1b59f7 | 18 | ssel(ssel_), |
mux | 0:f9a5ac1b59f7 | 19 | prog(prog_), |
mux | 0:f9a5ac1b59f7 | 20 | rst(rst_) |
mux | 0:f9a5ac1b59f7 | 21 | { |
mux | 0:f9a5ac1b59f7 | 22 | spi.frequency(12500000); |
mux | 0:f9a5ac1b59f7 | 23 | spi.format(8, 0); |
mux | 0:f9a5ac1b59f7 | 24 | rst = 1; |
mux | 0:f9a5ac1b59f7 | 25 | } |
mux | 0:f9a5ac1b59f7 | 26 | |
mux | 0:f9a5ac1b59f7 | 27 | void NRFlash::reset() |
mux | 0:f9a5ac1b59f7 | 28 | { |
mux | 0:f9a5ac1b59f7 | 29 | rst = 0; |
mux | 0:f9a5ac1b59f7 | 30 | wait_ms(2); |
mux | 0:f9a5ac1b59f7 | 31 | rst = 1; |
mux | 0:f9a5ac1b59f7 | 32 | } |
mux | 0:f9a5ac1b59f7 | 33 | |
mux | 0:f9a5ac1b59f7 | 34 | void NRFlash::enable_programming() |
mux | 0:f9a5ac1b59f7 | 35 | { |
mux | 0:f9a5ac1b59f7 | 36 | prog = 1; |
mux | 0:f9a5ac1b59f7 | 37 | wait_ms(2); |
mux | 0:f9a5ac1b59f7 | 38 | } |
mux | 0:f9a5ac1b59f7 | 39 | |
mux | 0:f9a5ac1b59f7 | 40 | void NRFlash::disable_programming() |
mux | 0:f9a5ac1b59f7 | 41 | { |
mux | 0:f9a5ac1b59f7 | 42 | prog = 0; |
mux | 0:f9a5ac1b59f7 | 43 | } |
mux | 0:f9a5ac1b59f7 | 44 | |
mux | 0:f9a5ac1b59f7 | 45 | void NRFlash::write_enable() |
mux | 0:f9a5ac1b59f7 | 46 | { |
mux | 0:f9a5ac1b59f7 | 47 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 48 | spi.write(WREN); |
mux | 0:f9a5ac1b59f7 | 49 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 50 | } |
mux | 0:f9a5ac1b59f7 | 51 | |
mux | 0:f9a5ac1b59f7 | 52 | int NRFlash::read_fsr() |
mux | 0:f9a5ac1b59f7 | 53 | { |
mux | 0:f9a5ac1b59f7 | 54 | int fsr; |
mux | 0:f9a5ac1b59f7 | 55 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 56 | spi.write(RDSR); |
mux | 0:f9a5ac1b59f7 | 57 | fsr = spi.write(0); |
mux | 0:f9a5ac1b59f7 | 58 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 59 | return fsr; |
mux | 0:f9a5ac1b59f7 | 60 | } |
mux | 0:f9a5ac1b59f7 | 61 | |
mux | 0:f9a5ac1b59f7 | 62 | void NRFlash::write_fsr(int fsr) |
mux | 0:f9a5ac1b59f7 | 63 | { |
mux | 0:f9a5ac1b59f7 | 64 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 65 | spi.write(WRSR); |
mux | 0:f9a5ac1b59f7 | 66 | spi.write(fsr); |
mux | 0:f9a5ac1b59f7 | 67 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 68 | } |
mux | 0:f9a5ac1b59f7 | 69 | |
mux | 0:f9a5ac1b59f7 | 70 | void NRFlash::erase_flash() |
mux | 0:f9a5ac1b59f7 | 71 | { |
mux | 0:f9a5ac1b59f7 | 72 | write_enable(); |
mux | 0:f9a5ac1b59f7 | 73 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 74 | spi.write(ERASE_ALL); |
mux | 0:f9a5ac1b59f7 | 75 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 76 | while (read_fsr() & RDYN); /*wait for flash to be erased*/ |
mux | 0:f9a5ac1b59f7 | 77 | } |
mux | 0:f9a5ac1b59f7 | 78 | |
mux | 0:f9a5ac1b59f7 | 79 | int NRFlash::read_flash(const char *path) |
mux | 0:f9a5ac1b59f7 | 80 | { |
mux | 0:f9a5ac1b59f7 | 81 | int bytes = 0; |
mux | 0:f9a5ac1b59f7 | 82 | int count = 0; |
mux | 0:f9a5ac1b59f7 | 83 | char buf[1024]; |
mux | 0:f9a5ac1b59f7 | 84 | |
mux | 0:f9a5ac1b59f7 | 85 | FILE *fp = fopen(path, "wb"); |
mux | 0:f9a5ac1b59f7 | 86 | if (fp == NULL) { |
mux | 0:f9a5ac1b59f7 | 87 | printf("file not found\n"); |
mux | 0:f9a5ac1b59f7 | 88 | return -1; |
mux | 0:f9a5ac1b59f7 | 89 | } |
mux | 0:f9a5ac1b59f7 | 90 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 91 | spi.write(READ); |
mux | 0:f9a5ac1b59f7 | 92 | spi.write(0); |
mux | 0:f9a5ac1b59f7 | 93 | spi.write(0); |
mux | 0:f9a5ac1b59f7 | 94 | while (bytes++ < FLASH_LEN) { |
mux | 0:f9a5ac1b59f7 | 95 | buf[count++] = spi.write(0); |
mux | 0:f9a5ac1b59f7 | 96 | if (count == sizeof(buf)) { |
mux | 0:f9a5ac1b59f7 | 97 | count = 0; |
mux | 0:f9a5ac1b59f7 | 98 | fwrite(buf, 1, sizeof(buf), fp); |
mux | 0:f9a5ac1b59f7 | 99 | } |
mux | 0:f9a5ac1b59f7 | 100 | } |
mux | 0:f9a5ac1b59f7 | 101 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 102 | fclose(fp); |
mux | 0:f9a5ac1b59f7 | 103 | return 0; |
mux | 0:f9a5ac1b59f7 | 104 | } |
mux | 0:f9a5ac1b59f7 | 105 | |
mux | 0:f9a5ac1b59f7 | 106 | int NRFlash::write_flash(const char *path) |
mux | 0:f9a5ac1b59f7 | 107 | { |
mux | 0:f9a5ac1b59f7 | 108 | int len; |
mux | 0:f9a5ac1b59f7 | 109 | uint16_t addr = 0; |
mux | 0:f9a5ac1b59f7 | 110 | char buf[256]; |
mux | 0:f9a5ac1b59f7 | 111 | |
mux | 0:f9a5ac1b59f7 | 112 | FILE *fp = fopen(path, "rb"); |
mux | 0:f9a5ac1b59f7 | 113 | if (fp == NULL) { |
mux | 0:f9a5ac1b59f7 | 114 | printf("file not found\n"); |
mux | 0:f9a5ac1b59f7 | 115 | return -1; |
mux | 0:f9a5ac1b59f7 | 116 | } |
mux | 0:f9a5ac1b59f7 | 117 | |
mux | 0:f9a5ac1b59f7 | 118 | while ((len = fread(buf, 1, sizeof(buf), fp)) > 0) { |
mux | 0:f9a5ac1b59f7 | 119 | write_enable(); |
mux | 0:f9a5ac1b59f7 | 120 | ssel = 0; |
mux | 0:f9a5ac1b59f7 | 121 | spi.write(PROGRAM); /*PROGRAM command*/ |
mux | 0:f9a5ac1b59f7 | 122 | spi.write(addr>>8); /*write address MSB*/ |
mux | 0:f9a5ac1b59f7 | 123 | spi.write(addr&0x0F); /*write address LSB*/ |
mux | 0:f9a5ac1b59f7 | 124 | addr += len; |
mux | 0:f9a5ac1b59f7 | 125 | for (int i=0; i<len; i++) { |
mux | 0:f9a5ac1b59f7 | 126 | spi.write(buf[i]); |
mux | 0:f9a5ac1b59f7 | 127 | } |
mux | 0:f9a5ac1b59f7 | 128 | ssel = 1; |
mux | 0:f9a5ac1b59f7 | 129 | while (read_fsr() & RDYN); /*wait for flash to be ready*/ |
mux | 0:f9a5ac1b59f7 | 130 | } |
mux | 0:f9a5ac1b59f7 | 131 | fclose(fp); |
mux | 0:f9a5ac1b59f7 | 132 | return 0; |
mux | 0:f9a5ac1b59f7 | 133 | } |