Murilo Pontes
/
cc1101
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cc1101_regs.h
00001 /* 00002 * CC1101_REGS.h 00003 * 00004 * Created on: 07/02/2014 00005 * Author: mpontes <murilopontes@gmail.com> 00006 */ 00007 00008 #ifndef CC1101_BOARD_REGS_H_ 00009 #define CC1101_BOARD_REGS_H_ 00010 00011 #define CC1101_DUMMY_BYTE 0xDB 00012 00013 #define CC1101_WRITE_BYTE 0x00 00014 #define CC1101_WRITE_BURST 0x40 00015 #define CC1101_READ_BYTE 0x80 00016 #define CC1101_READ_BURST 0xC0 00017 00018 00019 /* configuration registers */ 00020 #define CC1101_IOCFG2 0x00 /* IOCFG2 - GDO2 output pin configuration */ 00021 #define CC1101_IOCFG1 0x01 /* IOCFG1 - GDO1 output pin configuration */ 00022 #define CC1101_IOCFG0 0x02 /* IOCFG1 - GDO0 output pin configuration */ 00023 #define CC1101_FIFOTHR 0x03 /* FIFOTHR - RX FIFO and TX FIFO thresholds */ 00024 #define CC1101_SYNC1 0x04 /* SYNC1 - Sync word, high byte */ 00025 #define CC1101_SYNC0 0x05 /* SYNC0 - Sync word, low byte */ 00026 #define CC1101_PKTLEN 0x06 /* PKTLEN - Packet length */ 00027 #define CC1101_PKTCTRL1 0x07 /* PKTCTRL1 - Packet automation control */ 00028 #define CC1101_PKTCTRL0 0x08 /* PKTCTRL0 - Packet automation control */ 00029 #define CC1101_ADDR 0x09 /* ADDR - Device address */ 00030 #define CC1101_CHANNR 0x0A /* CHANNR - Channel number */ 00031 #define CC1101_FSCTRL1 0x0B /* FSCTRL1 - Frequency synthesizer control */ 00032 #define CC1101_FSCTRL0 0x0C /* FSCTRL0 - Frequency synthesizer control */ 00033 #define CC1101_FREQ2 0x0D /* FREQ2 - Frequency control word, high byte */ 00034 #define CC1101_FREQ1 0x0E /* FREQ1 - Frequency control word, middle byte */ 00035 #define CC1101_FREQ0 0x0F /* FREQ0 - Frequency control word, low byte */ 00036 #define CC1101_MDMCFG4 0x10 /* MDMCFG4 - Modem configuration */ 00037 #define CC1101_MDMCFG3 0x11 /* MDMCFG3 - Modem configuration */ 00038 #define CC1101_MDMCFG2 0x12 /* MDMCFG2 - Modem configuration */ 00039 #define CC1101_MDMCFG1 0x13 /* MDMCFG1 - Modem configuration */ 00040 #define CC1101_MDMCFG0 0x14 /* MDMCFG0 - Modem configuration */ 00041 #define CC1101_DEVIATN 0x15 /* DEVIATN - Modem deviation setting */ 00042 #define CC1101_MCSM2 0x16 /* MCSM2 - Main Radio Control State Machine configuration */ 00043 #define CC1101_MCSM1 0x17 /* MCSM1 - Main Radio Control State Machine configuration */ 00044 #define CC1101_MCSM0 0x18 /* MCSM0 - Main Radio Control State Machine configuration */ 00045 #define CC1101_FOCCFG 0x19 /* FOCCFG - Frequency Offset Compensation configuration */ 00046 #define CC1101_BSCFG 0x1A /* BSCFG - Bit Synchronization configuration */ 00047 #define CC1101_AGCCTRL2 0x1B /* AGCCTRL2 - AGC control */ 00048 #define CC1101_AGCCTRL1 0x1C /* AGCCTRL1 - AGC control */ 00049 #define CC1101_AGCCTRL0 0x1D /* AGCCTRL0 - AGC control */ 00050 #define CC1101_WOREVT1 0x1E /* WOREVT1 - High byte Event0 timeout */ 00051 #define CC1101_WOREVT0 0x1F /* WOREVT0 - Low byte Event0 timeout */ 00052 #define CC1101_WORCTRL 0x20 /* WORCTRL - Wake On Radio control */ 00053 #define CC1101_FREND1 0x21 /* FREND1 - Front end RX configuration */ 00054 #define CC1101_FREND0 0x22 /* FREDN0 - Front end TX configuration */ 00055 #define CC1101_FSCAL3 0x23 /* FSCAL3 - Frequency synthesizer calibration */ 00056 #define CC1101_FSCAL2 0x24 /* FSCAL2 - Frequency synthesizer calibration */ 00057 #define CC1101_FSCAL1 0x25 /* FSCAL1 - Frequency synthesizer calibration */ 00058 #define CC1101_FSCAL0 0x26 /* FSCAL0 - Frequency synthesizer calibration */ 00059 #define CC1101_RCCTRL1 0x27 /* RCCTRL1 - RC oscillator configuration */ 00060 #define CC1101_RCCTRL0 0x28 /* RCCTRL0 - RC oscillator configuration */ 00061 #define CC1101_FSTEST 0x29 /* FSTEST - Frequency synthesizer calibration control */ 00062 #define CC1101_PTEST 0x2A /* PTEST - Production test */ 00063 #define CC1101_AGCTEST 0x2B /* AGCTEST - AGC test */ 00064 #define CC1101_TEST2 0x2C /* TEST2 - Various test settings */ 00065 #define CC1101_TEST1 0x2D /* TEST1 - Various test settings */ 00066 #define CC1101_TEST0 0x2E /* TEST0 - Various test settings */ 00067 00068 /* command strobe registers */ 00069 #define CC1101_SRES 0x30 /* SRES - Reset chip. */ 00070 #define CC1101_SFSTXON 0x31 /* SFSTXON - Enable and calibrate frequency synthesizer. */ 00071 #define CC1101_SXOFF 0x32 /* SXOFF - Turn off crystal oscillator. */ 00072 #define CC1101_SCAL 0x33 /* SCAL - Calibrate frequency synthesizer and turn it off. */ 00073 #define CC1101_SRX 0x34 /* SRX - Enable RX. Perform calibration if enabled. */ 00074 #define CC1101_STX 0x35 /* STX - Enable TX. If in RX state, only enable TX if CCA passes. */ 00075 #define CC1101_SIDLE 0x36 /* SIDLE - Exit RX / TX, turn off frequency synthesizer. */ 00076 #define CC1101_SRSVD 0x37 /* SRVSD - Reserved. Do not use. */ 00077 #define CC1101_SWOR 0x38 /* SWOR - Start automatic RX polling sequence (Wake-on-Radio) */ 00078 #define CC1101_SPWD 0x39 /* SPWD - Enter power down mode when CSn goes high. */ 00079 #define CC1101_SFRX 0x3A /* SFRX - Flush the RX FIFO buffer. */ 00080 #define CC1101_SFTX 0x3B /* SFTX - Flush the TX FIFO buffer. */ 00081 #define CC1101_SWORRST 0x3C /* SWORRST - Reset real time clock. */ 00082 #define CC1101_SNOP 0x3D /* SNOP - No operation. Returns status byte. */ 00083 00084 /* status registers */ 00085 #define CC1101_PARTNUM 0x30 /* PARTNUM - Chip ID */ 00086 #define CC1101_VERSION 0x31 /* VERSION - Chip ID */ 00087 #define CC1101_FREQEST 0x32 /* FREQEST – Frequency Offset Estimate from demodulator */ 00088 #define CC1101_LQI 0x33 /* LQI – Demodulator estimate for Link Quality */ 00089 #define CC1101_RSSI 0x34 /* RSSI – Received signal strength indication */ 00090 #define CC1101_MARCSTATE 0x35 /* MARCSTATE – Main Radio Control State Machine state */ 00091 #define CC1101_WORTIME1 0x36 /* WORTIME1 – High byte of WOR time */ 00092 #define CC1101_WORTIME0 0x37 /* WORTIME0 – Low byte of WOR time */ 00093 #define CC1101_PKTSTATUS 0x38 /* PKTSTATUS – Current GDOx status and packet status */ 00094 #define CC1101_VCO_VC_DAC 0x39 /* VCO_VC_DAC – Current setting from PLL calibration module */ 00095 #define CC1101_TXBYTES 0x3a /* TXBYTES – Underflow and number of bytes */ 00096 #define CC1101_RXBYTES 0x3b /* RXBYTES – Overflow and number of bytes */ 00097 #define CC1101_RCCTRL1_STATUS 0x3c /* RCCTRL1_STATUS – Last RC Oscillator Calibration Result */ 00098 #define CC1101_RCCTRL0_STATUS 0x3d /* RCCTRL0_STATUS – Last RC Oscillator Calibration Result */ 00099 00100 00101 /* burst write registers */ 00102 #define CC1101_PA_TABLE0 0x3E /* PA_TABLE0 - PA control settings table */ 00103 #define CC1101_TXFIFO 0x3F /* TXFIFO - Transmit FIFO */ 00104 #define CC1101_RXFIFO 0x3F /* RXFIFO - Receive FIFO */ 00105 00106 00107 00108 00109 00110 00111 00112 //----------------------------------------------------------------------------- 00113 // CC1101 STATE MACHINE 00114 //------------------------------------------------------------------------------ 00115 #define CC1101_MARCSTATE_SLEEP 0x00 00116 #define CC1101_MARCSTATE_IDLE 0x01 00117 #define CC1101_MARCSTATE_XOFF 0x02 00118 #define CC1101_MARCSTATE_VCOON_MC 0x03 00119 #define CC1101_MARCSTATE_REGON_MC 0x04 00120 #define CC1101_MARCSTATE_MANCAL 0x05 00121 #define CC1101_MARCSTATE_VCOON 0x06 00122 #define CC1101_MARCSTATE_REGON 0x07 00123 #define CC1101_MARCSTATE_STARTCAL 0x08 00124 #define CC1101_MARCSTATE_BWBOOST 0x09 00125 #define CC1101_MARCSTATE_FS_LOCK 0x0a 00126 #define CC1101_MARCSTATE_IFADCON 0x0b 00127 #define CC1101_MARCSTATE_ENDCAL 0x0c 00128 #define CC1101_MARCSTATE_RX 0x0d 00129 #define CC1101_MARCSTATE_RX_END 0x0e 00130 #define CC1101_MARCSTATE_RX_RST 0x0f 00131 #define CC1101_MARCSTATE_TXRX_SWITCH 0x10 00132 #define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11 00133 #define CC1101_MARCSTATE_FSTXON 0x12 00134 #define CC1101_MARCSTATE_TX 0x13 00135 #define CC1101_MARCSTATE_TX_END 0x14 00136 #define CC1101_MARCSTATE_RXTX_SWITCH 0x15 00137 #define CC1101_MARCSTATE_TXFIFO_UNDERFLOW 0x16 00138 00139 //-------------------------------------------- 00140 // CC1101 GDO config 00141 //-------------------------------------------- 00142 00143 00144 #define CC1101_GDO_RX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD 0x00 00145 #define CC1101_GDO_RX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD_OR_END_PACKET 0x01 00146 #define CC1101_GDO_TX_ASSERT_WHEN_FILLED_OR_ABOVE_THRESHOLD 0x02 00147 #define CC1101_GDO_TX_ASSERT_WHEN_FULL 0x03 00148 #define CC1101_GDO_RX_ASSERT_ON_OVERFLOW 0x04 00149 #define CC1101_GDO_TX_ASSERT_ON_UNDERFLOW 0x05 00150 #define CC1101_GDO_ASSERT_ON_SYNC_WORD 0x06 00151 #define CC1101_GDO_ASSERT_ON_CRC_OK 0x07 00152 #define CC1101_GDO_ASSERT_ON_PQI_ABOVE_PQT 0x08 00153 #define CC1101_GDO_CCA_ASSERT_WHEN_RSSI_ABOVE_THRESHOLD 0x09 00154 #define CC1101_GDO_LOCK_DETECTOR_OUTPUT 0x0a 00155 #define CC1101_GDO_SERIAL_CLOCK 0x0b 00156 #define CC1101_GDO_SERIAL_SYNCHRONOUS_DATA_OUTPUT 0x0c 00157 #define CC1101_GDO_SERIA_DATA_OUTPUT 0x0d 00158 #define CC1101_GDO_CARRIER_SENSE_HIGH_IF_RSSI_ABOVE_THRESHOLD 0x0e 00159 #define CC1101_GDO_CRC_OK 0x0f 00160 #define CC1101_GDO_RX_HARD_DATA_1 0x16 00161 #define CC1101_GDO_RX_HARD_DATA_0 0x17 00162 #define CC1101_GDO_PA_PD 0x1b 00163 #define CC1101_GDO_LNA_PD 0x1c 00164 #define CC1101_GDO_RX_SYMBOL_TICK 0x1d 00165 #define CC1101_GDO_WOR_1 0x24 00166 #define CC1101_GDO_WOR_0 0x25 00167 #define CC1101_GDO_CLK_32K 0x27 00168 #define CC1101_GDO_CHIP_RDYN 0x29 00169 #define CC1101_GDO_XOSC_STABLE 0x2b 00170 #define CC1101_GDO_GDO0_Z_EN_N 0x2d 00171 #define CC1101_GDO_HIGH_IMPEDANCE 0x2e 00172 #define CC1101_GDO_HW_0 0x2f 00173 #define CC1101_GDO_CLK_XOSC1 0x30 00174 #define CC1101_GDO_CLK_XOSC15 0x31 00175 #define CC1101_GDO_CLK_XOSC2 0x32 00176 #define CC1101_GDO_CLK_XOSC3 0x33 00177 #define CC1101_GDO_CLK_XOSC4 0x34 00178 #define CC1101_GDO_CLK_XOSC6 0x35 00179 #define CC1101_GDO_CLK_XOSC8 0x36 00180 #define CC1101_GDO_CLK_XOSC12 0x37 00181 #define CC1101_GDO_CLK_XOSC16 0x38 00182 #define CC1101_GDO_CLK_XOSC24 0x39 00183 #define CC1101_GDO_CLK_XOSC32 0x3a 00184 #define CC1101_GDO_CLK_XOSC48 0x3b 00185 #define CC1101_GDO_CLK_XOSC64 0x3c 00186 #define CC1101_GDO_CLK_XOSC96 0x3d 00187 #define CC1101_GDO_CLK_XOSC128 0x3e 00188 #define CC1101_GDO_CLK_XOSC192 0x3f 00189 00190 00191 00192 00193 #endif /* CC1101_BOARD_REGS_H_ */
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