RawNAND.h

00001 #ifndef RAWNAND_H
00002 #define RAWNAND_H
00003 
00004 #include "mbed.h"
00005 
00006 // KIOXIA 1Gbit SLC NAND, 3.3V, x8, 24nm, TSOP
00007 // TC58NVG0S3HTA00 datasheet 2019-10-01C 
00008 
00009 //
00010 // Timing parameter
00011 //
00012 // CLE Setup Time
00013 #define tCLS_US  0.012
00014 
00015 // CLE Hold Time
00016 #define tCLH_US   0.005
00017 
00018 // CEB Setup Time
00019 #define tCS_US    0.020
00020 
00021 // CEB Hold Time
00022 #define tCH_US    0.005
00023 
00024 // Write Pulse Width
00025 #define tWP_US    0.012
00026 
00027 // ALE Setup Time
00028 #define tALS_US   0.012
00029 
00030 // ALE Hold Time
00031 #define tALH_US   0.005
00032 
00033 // DATA Setup Time
00034 #define tDS_US    0.012
00035 
00036 // DATA Hold Time
00037 #define tDH_US    0.005
00038 
00039 // Write Cycle Time
00040 #define tWC_US    0.025
00041 
00042 // WEB High Hold Time
00043 #define tWH_US    0.010
00044 
00045 // WPB High to WEB Low
00046 #define tWW_US    0.100
00047 
00048 // Ready to REB Falling Edge
00049 #define tRR_US    0.020
00050 
00051 // Ready to WEB Falling Edge
00052 #define tRW_US    0.020
00053 
00054 // Read Pulse Width
00055 #define tRP_US    0.012
00056 
00057 // Read Cycle Time
00058 #define tRC_US    0.025
00059 
00060 // REB Access Time
00061 #define tREA_US   0.020
00062 
00063 // CEB Access Time
00064 #define tCEA_US   0.025
00065 
00066 // CLE Low to REB Low
00067 #define tCLR_US   0.010
00068 
00069 // ALE Low to REB Low
00070 #define tAR_US    0.010
00071 
00072 // REB High to Output Hold Time
00073 #define tRHOH_US  0.025
00074 
00075 // REB Low to Output Hold Time
00076 #define tRLOH_US  0.005
00077 
00078 // REB High to Output High Impedance
00079 #define tRHZ_US   0.060
00080 
00081 // CEB High to Output High Impedance
00082 #define tCHZ_US   0.020
00083 
00084 // CEB High to ALE or CLE Don't care
00085 #define tCSD_US   0.000
00086 
00087 // REB High Hold Time
00088 #define tREH_US   0.010
00089 
00090 // Output-High-Impedance-to-REB Falling Edge
00091 #define tIR_US    0.000
00092 
00093 // REB High to WEB Low
00094 #define tRHW_US   0.030
00095 
00096 // WEB High to CEB Low
00097 #define tWHC_US   0.030
00098 
00099 // WEB High to REB Low
00100 #define tWHR_US   0.060
00101 
00102 // WEB High to Busy
00103 #define tWB_US    0.100
00104 
00105 // Device Reset Time(Ready)
00106 #define tRST_RDY_US       5.0
00107 
00108 // Device Reset Time(Read)
00109 #define tRST_READ_US      5.0
00110 
00111 // Device Reset Time(Program)
00112 #define tRST_PROGRAM_US  10.0
00113 
00114 // Devise Reset Time(Erase)
00115 #define tRST_ERASE_US   500.0
00116 
00117 // Programming Time
00118 #define tPROG_US        700.0
00119 
00120 // Data Cache Busy Time in Write Cache( following 15h ) 
00121 #define tDCBAYW2_US     700.0
00122 
00123 // Number of Partial Program Cycles in the same page
00124 #define NCYCLES_SAME_PAGE 4
00125 
00126 // Block Erasing Time
00127 #define tBERASE_US     5000.0
00128 
00129 // Memory Cell Array to Staring Address ( tR )
00130 #define MC2SA_US         25.0
00131 
00132 // Data Cache Busy in Read Cache ( following 31h and 3Fh )
00133 #define tDCBSYR1_US      25.0
00134 
00135 // Data Cache Busy in Page Copy ( following 3Ah )
00136 #define tDCBSYR2_US      30.0
00137 
00138 
00139 
00140 class RawNAND
00141 {
00142     public:
00143         RawNAND(PinName ceb0, PinName ceb1,
00144                 PinName cle , PinName ale ,
00145                 PinName web , PinName reb ,
00146                 PinName wpb , PinName rbb , 
00147                 PinName io1 , PinName io2 ,
00148                 PinName io3 , PinName io4 ,
00149                 PinName io5 , PinName io6 ,
00150                 PinName io7 , PinName io8 );
00151         void reset(uint8_t cs);
00152         void idRead(uint8_t cs, uint8_t * readData);
00153         uint8_t statusRead(uint8_t cs);
00154         void setWriteProtect(uint8_t writeProtect);
00155         void pageRead(uint8_t cs, uint8_t * readData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats);
00156         // return status
00157         uint8_t pageProgram(uint8_t cs, const uint8_t * writeData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats);
00158         // return status
00159         uint8_t erase(uint8_t cs, uint16_t blockAddress);
00160         
00161 
00162     private:
00163         DigitalOut _ceb0;
00164         DigitalOut _ceb1;
00165         DigitalOut _cle;
00166         DigitalOut _ale;
00167         DigitalOut _web;
00168         DigitalOut _reb;
00169         DigitalOut _wpb;
00170         DigitalIn  _rbb;
00171         BusInOut   _io;
00172 
00173 };
00174 
00175 #endif