RawNAND.cpp

00001 #include "RawNAND.h"
00002 
00003 // TODO: Replace wait_us(int) to wait_ns 
00004 
00005 RawNAND::RawNAND(PinName ceb0,PinName ceb1, PinName cle,
00006                  PinName ale, PinName web,
00007                  PinName reb, PinName wpb,
00008                  PinName rbb, 
00009                  PinName io1, PinName io2,
00010                  PinName io3, PinName io4,
00011                  PinName io5, PinName io6,
00012                  PinName io7, PinName io8)
00013         : _ceb0(ceb0,1),_ceb1(ceb1,1),_cle(cle,1),
00014           _ale(ale,1),_web(web,1),
00015           _reb(reb,1),_wpb(wpb,1),
00016           _rbb(rbb,PullUp),
00017           _io(io1,io2,io3,io4,io5,io6,io7,io8) {
00018           _io.mode(PullNone);
00019           _io.input();
00020               
00021 }
00022 void RawNAND::reset(uint8_t cs) {
00023     // wait ready
00024     while(_rbb==0){
00025         __NOP();    
00026     }
00027     // RESET COMMAND (0xff)
00028     if(cs==0) {
00029         _ceb0 = 0;
00030     } else if (cs==1) {
00031         _ceb1 = 1;
00032     }
00033     _cle = 1;
00034     _ale = 0;
00035     _web = 0;
00036     _io=0xff;
00037     _io.output();
00038     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00039     wait_us(tCS_US);
00040     _web = 1;
00041     // wait hold time : max(tCLH,tALH,tDH,tWH,tWB,tCH)
00042     wait_us(tWB_US);
00043     // check tRBB;
00044     while (_rbb==0){
00045         __NOP();
00046     }
00047     if(cs==0) {
00048         _ceb0 = 1;
00049     } else if (cs==1) {
00050         _ceb1 = 1;
00051     }
00052 }
00053 void RawNAND::idRead(uint8_t cs, uint8_t * readData) {
00054     // ID READ COMMAND (0x90)
00055     if(cs==0) {
00056         _ceb0 = 0;
00057     } else if (cs==1) {
00058         _ceb1 = 0;
00059     }
00060     _cle = 1;
00061     _ale = 0;
00062     _web = 0;
00063     _io=0x90;
00064     _io.output();
00065     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00066     wait_us(tCS_US);
00067     _web = 1;
00068     // wait hold time : max(tCLH,tALH,tDH,tWH)
00069     wait_us(tWH_US);
00070     
00071     // IO READ ADDRESS  (0x00)
00072     _cle=0;
00073     _ale=1;
00074     _web=0;
00075     _io=0x00;
00076     // wait setup time : max(tCLS,tALS,tDS,tWP)
00077     wait_us(tCLS_US);
00078     _web=1;
00079     // wait hold time : max(tCLH,tALH,tDH,tWH)
00080     wait_us(tWH_US);
00081 
00082     // ALE low and IO input
00083     _ale=0;
00084     _io.input();
00085     // ALE low to tREB low : tAR
00086     wait_us(tAR_US);
00087 
00088     // IO READ read data
00089     for (int l=0;l<5;l++) {
00090         _reb = 0;
00091         // wait max(tREA,tRP)
00092         wait_us(tREA_US);
00093         *(readData+l)=_io;
00094         _reb = 1;
00095         // wait tREH
00096         wait_us(tREH_US);
00097     }
00098     // wait io hiz
00099     if(cs==0) {
00100         _ceb0 = 1;
00101     } else if (cs==1) {
00102         _ceb1 = 1;
00103     }
00104     wait_us(tCHZ_US);
00105 }
00106 uint8_t RawNAND::statusRead(uint8_t cs) {
00107     uint8_t status;
00108     // wait ready
00109     while(_rbb==0){
00110         __NOP();    
00111     }
00112 
00113     // STATUS READ COMMAND (0x70)
00114     if(cs==0) {
00115         _ceb0 = 0;
00116     } else if (cs==1) {
00117         _ceb1 = 0;
00118     }
00119     _cle = 1;
00120     _ale = 0;
00121     _web = 0;
00122     _io=0x70;
00123     _io.output();
00124     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00125     wait_us(tCS_US);
00126     _web = 1;
00127     // wait hold time : max(tCLH,tDH,tWH)
00128     wait_us(tWH_US);
00129     _cle = 0;
00130     _io.input();
00131     // wait max(tWHR-tWH,tCLR-tWH)
00132     wait_us(tWHR_US-tWH_US);
00133     _reb = 0;
00134     // wait max(tREA,tRP)
00135     wait_us(tREA_US);
00136     status = _io;
00137     _reb = 1;
00138     // wait tREH
00139     wait_us(tREH_US);
00140     if(cs==0) {
00141         _ceb0 = 1;
00142     } else if (cs==1) {
00143         _ceb1 = 1;
00144     }
00145     wait_us(tCHZ_US);
00146     // wait io hiz
00147     return status;
00148 }
00149 
00150 void RawNAND::setWriteProtect(uint8_t writeProtect){
00151     _wpb = writeProtect;
00152     // wait tWW
00153     wait_us(tWW_US);
00154 }
00155 
00156 void RawNAND::pageRead(uint8_t cs, uint8_t * readData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){
00157     // wait ready
00158     while(_rbb==0){
00159         __NOP();    
00160     }
00161 
00162     // 1ST READ COMMAND (0x00)
00163     if(cs==0) {
00164         _ceb0 = 0;
00165     } else if (cs==1) {
00166         _ceb1 = 0;
00167     }
00168     _cle = 1;
00169     _ale = 0;
00170     _web = 0;
00171     _io=0x00;
00172     _io.output();
00173     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00174     wait_us(tCS_US);
00175 
00176     _web = 1;
00177     // wait hold time : max(tCLH,tDH,tWH)
00178     wait_us(tWH_US);
00179 
00180     // 1st address column [7:0]
00181     _cle = 0;
00182     _ale = 1;
00183     _web = 0;
00184     _io  = columnAddress & 0xff;
00185     // wait setup time : max(tALS,tCLS,tDS,tWP)
00186     wait_us(tWP_US);
00187 
00188     _web = 1;
00189     // wait hold time : max(tCLH,tDH,tWH)
00190     wait_us(tWH_US);   
00191 
00192     // 2nd address column [11:8]
00193     _web = 0;
00194     _io  = (columnAddress>>8) & 0x0f;            
00195     // wait setup time : max(tALS,tCLS,tDS,tWP)
00196     wait_us(tWP_US);
00197 
00198     _web = 1;
00199     // wait hold time : max(tCLH,tDH,tWH)
00200     wait_us(tWH_US);
00201     
00202     // 3rd address  {blockAddress[1:0],pageAddress[5:0]}
00203     _web = 0;
00204     _io  = ((blockAddress<<6) | pageAddress) ;            
00205     // wait setup time : max(tALS,tDS,tWP)
00206     wait_us(tWP_US);
00207 
00208     _web = 1;
00209     // wait hold time : max(tALH,tDH,tWH)
00210     wait_us(tWH_US);
00211     
00212     // 4th address  blockAddress[9:2]
00213     _web = 0;
00214     _io  = (blockAddress>>2) ;   
00215     // wait setup time : max(tALS,tDS,tWP)
00216     wait_us(tWP_US);
00217 
00218     _web = 1;
00219     // wait hold time : max(tALH,tDH,tWH)
00220     wait_us(tWH_US);
00221 
00222     // 2ND READ COMMAND (0x30)
00223     _cle = 1;
00224     _ale = 0;
00225     _web = 0;
00226     _io  = 0x30;
00227     // wait setup time : max(tALS,tCLS,tDS,tWP)
00228     wait_us(tWP_US);
00229 
00230     _web = 1;
00231     // wait hold time : max(tALH,tDH,tWH,tWB)
00232     wait_us(tWB_US);
00233 
00234     _cle = 0;
00235     _io.input();
00236 
00237     // wait ready
00238     while(_rbb==0){
00239         __NOP();    
00240     }
00241 
00242     // wait tRR  ( RBB to REB Low )
00243     wait_us(tRR_US);
00244 
00245     // read sequence
00246     for (int b=0;b<beats;b++){
00247         _reb = 0;
00248         // wait max(tREA,tRP)
00249         wait_us(tREA_US);
00250          *(readData + b)= _io;
00251         _reb = 1;
00252         // wait tREH
00253         wait_us(tREH_US);
00254     }
00255 
00256     if(cs==0) {
00257         _ceb0 = 1;
00258     } else if (cs==1) {
00259         _ceb1 = 1;
00260     }
00261     // wait io hiz
00262     wait_us(tCHZ_US);
00263 
00264 }
00265 
00266 
00267 uint8_t RawNAND::erase(uint8_t cs, uint16_t blockAddress){
00268     // wait ready
00269     while(_rbb==0){
00270         __NOP();    
00271     }
00272 
00273     // 1ST ERASE COMMAND (0x60)
00274     if(cs==0) {
00275         _ceb0 = 0;
00276     } else if (cs==1) {
00277         _ceb1 = 0;
00278     }
00279     _cle = 1;
00280     _ale = 0;
00281     _web = 0;
00282     _io=0x60;
00283     _io.output();
00284     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00285     wait_us(tCS_US);
00286 
00287     _web = 1;
00288     // wait hold time : max(tCLH,tDH,tWH)
00289     wait_us(tWH_US);
00290 
00291 
00292     // 1st page address  {blockAddress[1:0],pageAddress[5:0]}
00293     _cle = 0;
00294     _ale = 1;
00295     _web = 0;
00296     _io  = (blockAddress<<6) ;            
00297     // wait setup time : max(tALS,tDS,tWP)
00298     wait_us(tWP_US);
00299 
00300     _web = 1;
00301     // wait hold time : max(tALH,tDH,tWH)
00302     wait_us(tWH_US);
00303     
00304     // 2nd page address  blockAddress[9:2]
00305     _web = 0;
00306     _io  = (blockAddress>>2) ;   
00307     // wait setup time : max(tALS,tDS,tWP)
00308     wait_us(tWP_US);
00309 
00310     _web = 1;
00311     // wait hold time : max(tALH,tDH,tWH)
00312     wait_us(tWH_US);
00313 
00314     // 2ND ERASE COMMAND (0xD0)
00315     _cle = 1;
00316     _ale = 0;
00317     _web = 0;
00318     _io  = 0xD0;
00319     // wait setup time : max(tALS,tCLS,tDS,tWP)
00320     wait_us(tWP_US);
00321 
00322     _web = 1;
00323     // wait hold time : max(tALH,tDH,tWH,tWB)
00324     wait_us(tWB_US);
00325 
00326     _cle = 0;
00327     _io.input();
00328 
00329     // wait ready
00330     while(_rbb==0){
00331         __NOP();    
00332     }
00333 
00334     return statusRead(cs);
00335 }
00336 
00337 uint8_t RawNAND::pageProgram(uint8_t cs, const uint8_t * writeData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats){
00338     // wait ready
00339     while(_rbb==0){
00340         __NOP();    
00341     }
00342 
00343     // 1ST PROGRAM COMMAND (0x80)
00344     if(cs==0) {
00345         _ceb0 = 0;
00346     } else if (cs==1) {
00347         _ceb1 = 0;
00348     }
00349     _cle = 1;
00350     _ale = 0;
00351     _web = 0;
00352     _io  = 0x80;
00353     _io.output();
00354     // wait setup time : max(tCS,tCLS,tALS,tDS,tWP)
00355     wait_us(tCS_US);
00356 
00357     _web = 1;
00358     // wait hold time : max(tCLH,tDH,tWH)
00359     wait_us(tWH_US);
00360 
00361     // 1st address column [7:0]
00362     _cle = 0;
00363     _ale = 1;
00364     _web = 0;
00365     _io  = columnAddress & 0xff;
00366     // wait setup time : max(tALS,tCLS,tDS,tWP)
00367     wait_us(tWP_US);
00368 
00369     _web = 1;
00370     // wait hold time : max(tCLH,tDH,tWH)
00371     wait_us(tWH_US);   
00372 
00373     // 2nd address column [11:8]
00374     _web = 0;
00375     _io  = (columnAddress>>8) & 0x0f;            
00376     // wait setup time : max(tALS,tCLS,tDS,tWP)
00377     wait_us(tWP_US);
00378 
00379     _web = 1;
00380     // wait hold time : max(tCLH,tDH,tWH)
00381     wait_us(tWH_US);
00382     
00383     // 3rd address  {blockAddress[1:0],pageAddress[5:0]}
00384     _web = 0;
00385     _io  = ((blockAddress<<6) | pageAddress) ;            
00386     // wait setup time : max(tALS,tDS,tWP)
00387     wait_us(tWP_US);
00388 
00389     _web = 1;
00390     // wait hold time : max(tALH,tDH,tWH)
00391     wait_us(tWH_US);
00392     
00393     // 4th address  blockAddress[9:2]
00394     _web = 0;
00395     _io  = (blockAddress>>2) ;   
00396     // wait setup time : max(tALS,tDS,tWP)
00397     wait_us(tWP_US);
00398 
00399     _web = 1;
00400     // wait hold time : max(tALH,tDH,tWH)
00401     wait_us(tWH_US);
00402 
00403     // datain
00404     _ale = 0;
00405     for (int b=0;b<beats;b++) {
00406         _io = *(writeData+b);
00407         _web = 0;
00408         // setup
00409         // wait setup time : max(tALS,tCLS,tDS,tWP)
00410         wait_us(tWP_US);
00411         
00412         _web = 1;
00413         // hold
00414         // wait hold time : max(tALH,tDH,tWH)
00415         wait_us(tWH_US);        
00416     }
00417 
00418     // 2ND PROGRAM COMMAND (0x10)
00419     _cle = 1;
00420     _ale = 0;
00421     _io  = 0x10;
00422     _web = 0;
00423     // wait setup time : max(tALS,tCLS,tDS,tWP)
00424     wait_us(tWP_US);
00425 
00426     _web = 1;
00427     // wait hold time : max(tCLH,tDH,tWH,tWB)
00428     wait_us(tWB_US);
00429     
00430     _cle = 0;
00431     _io.input();
00432     
00433     // wait ready
00434     while(_rbb==0){
00435         __NOP();    
00436     }
00437     
00438     return statusRead(cs);
00439 }