Takanobu Muraguchi / USBDevice

USB device stack

Dependents:   USBMSD_step1 USBMSD_step1_5 picossd_step1_2cs

targets/TARGET_STM/USBRegs_STM32.h@71:53949e6131f6, 2017-07-27 (annotated)

Committer:
Kojto
Date:
Thu Jul 27 12:14:04 2017 +0100
Revision:
71:53949e6131f6
Update libraries



Fixes the previous commmit, as some devices were not copied. USBDevice contains

now targets directory with all targets implementations

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 71:53949e6131f6 1 /**
Kojto 71:53949e6131f6 2 ******************************************************************************
Kojto 71:53949e6131f6 3 * @file usb_regs.h
Kojto 71:53949e6131f6 4 * @author MCD Application Team
Kojto 71:53949e6131f6 5 * @version V2.1.0
Kojto 71:53949e6131f6 6 * @date 19-March-2012
Kojto 71:53949e6131f6 7 * @brief hardware registers
Kojto 71:53949e6131f6 8 ******************************************************************************
Kojto 71:53949e6131f6 9 * @attention
Kojto 71:53949e6131f6 10 *
Kojto 71:53949e6131f6 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
Kojto 71:53949e6131f6 12 *
Kojto 71:53949e6131f6 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
Kojto 71:53949e6131f6 14 * You may not use this file except in compliance with the License.
Kojto 71:53949e6131f6 15 * You may obtain a copy of the License at:
Kojto 71:53949e6131f6 16 *
Kojto 71:53949e6131f6 17 * http://www.st.com/software_license_agreement_liberty_v2
Kojto 71:53949e6131f6 18 *
Kojto 71:53949e6131f6 19 * Unless required by applicable law or agreed to in writing, software
Kojto 71:53949e6131f6 20 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 71:53949e6131f6 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 71:53949e6131f6 22 * See the License for the specific language governing permissions and
Kojto 71:53949e6131f6 23 * limitations under the License.
Kojto 71:53949e6131f6 24 *
Kojto 71:53949e6131f6 25 ******************************************************************************
Kojto 71:53949e6131f6 26 */
Kojto 71:53949e6131f6 27
Kojto 71:53949e6131f6 28 #ifndef __USB_OTG_REGS_H__
Kojto 71:53949e6131f6 29 #define __USB_OTG_REGS_H__
Kojto 71:53949e6131f6 30
Kojto 71:53949e6131f6 31 typedef struct //000h
Kojto 71:53949e6131f6 32 {
Kojto 71:53949e6131f6 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
Kojto 71:53949e6131f6 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
Kojto 71:53949e6131f6 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
Kojto 71:53949e6131f6 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
Kojto 71:53949e6131f6 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
Kojto 71:53949e6131f6 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
Kojto 71:53949e6131f6 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
Kojto 71:53949e6131f6 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
Kojto 71:53949e6131f6 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
Kojto 71:53949e6131f6 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
Kojto 71:53949e6131f6 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
Kojto 71:53949e6131f6 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
Kojto 71:53949e6131f6 45 uint32_t Reserved30[2]; /* Reserved 030h*/
Kojto 71:53949e6131f6 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
Kojto 71:53949e6131f6 47 __IO uint32_t CID; /* User ID Register 03Ch*/
Kojto 71:53949e6131f6 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
Kojto 71:53949e6131f6 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
Kojto 71:53949e6131f6 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
Kojto 71:53949e6131f6 51 }
Kojto 71:53949e6131f6 52 USB_OTG_GREGS;
Kojto 71:53949e6131f6 53
Kojto 71:53949e6131f6 54 typedef struct // 800h
Kojto 71:53949e6131f6 55 {
Kojto 71:53949e6131f6 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
Kojto 71:53949e6131f6 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
Kojto 71:53949e6131f6 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
Kojto 71:53949e6131f6 59 uint32_t Reserved0C; /* Reserved 80Ch*/
Kojto 71:53949e6131f6 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
Kojto 71:53949e6131f6 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
Kojto 71:53949e6131f6 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
Kojto 71:53949e6131f6 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
Kojto 71:53949e6131f6 64 uint32_t Reserved20; /* Reserved 820h*/
Kojto 71:53949e6131f6 65 uint32_t Reserved9; /* Reserved 824h*/
Kojto 71:53949e6131f6 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
Kojto 71:53949e6131f6 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
Kojto 71:53949e6131f6 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
Kojto 71:53949e6131f6 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
Kojto 71:53949e6131f6 70 }
Kojto 71:53949e6131f6 71 USB_OTG_DREGS;
Kojto 71:53949e6131f6 72
Kojto 71:53949e6131f6 73 typedef struct
Kojto 71:53949e6131f6 74 {
Kojto 71:53949e6131f6 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
Kojto 71:53949e6131f6 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
Kojto 71:53949e6131f6 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
Kojto 71:53949e6131f6 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
Kojto 71:53949e6131f6 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
Kojto 71:53949e6131f6 80 uint32_t Reserved14;
Kojto 71:53949e6131f6 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
Kojto 71:53949e6131f6 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
Kojto 71:53949e6131f6 83 }
Kojto 71:53949e6131f6 84 USB_OTG_INEPREGS;
Kojto 71:53949e6131f6 85
Kojto 71:53949e6131f6 86 typedef struct
Kojto 71:53949e6131f6 87 {
Kojto 71:53949e6131f6 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Kojto 71:53949e6131f6 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Kojto 71:53949e6131f6 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Kojto 71:53949e6131f6 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Kojto 71:53949e6131f6 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Kojto 71:53949e6131f6 93 uint32_t Reserved14[3];
Kojto 71:53949e6131f6 94 }
Kojto 71:53949e6131f6 95 USB_OTG_OUTEPREGS;
Kojto 71:53949e6131f6 96
Kojto 71:53949e6131f6 97 typedef struct
Kojto 71:53949e6131f6 98 {
Kojto 71:53949e6131f6 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Kojto 71:53949e6131f6 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Kojto 71:53949e6131f6 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Kojto 71:53949e6131f6 102 uint32_t Reserved40C; /* Reserved 40Ch*/
Kojto 71:53949e6131f6 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Kojto 71:53949e6131f6 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Kojto 71:53949e6131f6 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Kojto 71:53949e6131f6 106 }
Kojto 71:53949e6131f6 107 USB_OTG_HREGS;
Kojto 71:53949e6131f6 108
Kojto 71:53949e6131f6 109 typedef struct
Kojto 71:53949e6131f6 110 {
Kojto 71:53949e6131f6 111 __IO uint32_t HCCHAR;
Kojto 71:53949e6131f6 112 __IO uint32_t HCSPLT;
Kojto 71:53949e6131f6 113 __IO uint32_t HCINT;
Kojto 71:53949e6131f6 114 __IO uint32_t HCINTMSK;
Kojto 71:53949e6131f6 115 __IO uint32_t HCTSIZ;
Kojto 71:53949e6131f6 116 uint32_t Reserved[3];
Kojto 71:53949e6131f6 117 }
Kojto 71:53949e6131f6 118 USB_OTG_HC_REGS;
Kojto 71:53949e6131f6 119
Kojto 71:53949e6131f6 120 typedef struct
Kojto 71:53949e6131f6 121 {
Kojto 71:53949e6131f6 122 USB_OTG_GREGS GREGS;
Kojto 71:53949e6131f6 123 uint32_t RESERVED0[188];
Kojto 71:53949e6131f6 124 USB_OTG_HREGS HREGS;
Kojto 71:53949e6131f6 125 uint32_t RESERVED1[9];
Kojto 71:53949e6131f6 126 __IO uint32_t HPRT;
Kojto 71:53949e6131f6 127 uint32_t RESERVED2[47];
Kojto 71:53949e6131f6 128 USB_OTG_HC_REGS HC_REGS[8];
Kojto 71:53949e6131f6 129 uint32_t RESERVED3[128];
Kojto 71:53949e6131f6 130 USB_OTG_DREGS DREGS;
Kojto 71:53949e6131f6 131 uint32_t RESERVED4[50];
Kojto 71:53949e6131f6 132 USB_OTG_INEPREGS INEP_REGS[4];
Kojto 71:53949e6131f6 133 uint32_t RESERVED5[96];
Kojto 71:53949e6131f6 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
Kojto 71:53949e6131f6 135 uint32_t RESERVED6[160];
Kojto 71:53949e6131f6 136 __IO uint32_t PCGCCTL;
Kojto 71:53949e6131f6 137 uint32_t RESERVED7[127];
Kojto 71:53949e6131f6 138 __IO uint32_t FIFO[4][1024];
Kojto 71:53949e6131f6 139 }
Kojto 71:53949e6131f6 140 USB_OTG_CORE_REGS;
Kojto 71:53949e6131f6 141
Kojto 71:53949e6131f6 142
Kojto 71:53949e6131f6 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
Kojto 71:53949e6131f6 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
Kojto 71:53949e6131f6 145
Kojto 71:53949e6131f6 146 #endif //__USB_OTG_REGS_H__
Kojto 71:53949e6131f6 147
Kojto 71:53949e6131f6 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 71:53949e6131f6 149