Camille Muller / ST_L152_32MHZ

Fixed with HAL.

Fork of ST_L152_32MHZ by Peter Drescher

Not finish yet. External crystal doesn't work.

Files at this revision

API Documentation at this revision

Revision 4:13f94218b838, committed 2015-04-21

Comitter:
mullercamille
Date:
Tue Apr 21 20:55:37 2015 +0000
Parent:
3:1e82f1f333ad
Commit message:
Add somes fix.

Changed in this revision

ST_L152_32MHZ.cpp Show annotated file Show diff for this revision Revisions of this file 
diff -r 1e82f1f333ad -r 13f94218b838 ST_L152_32MHZ.cpp
--- a/ST_L152_32MHZ.cpp	Tue Apr 08 17:17:56 2014 +0000
+++ b/ST_L152_32MHZ.cpp	Tue Apr 21 20:55:37 2015 +0000
@@ -15,8 +15,7 @@
  */
  
 #include "stm32l1xx.h"
-#include "stm32l1xx_flash.h"
-#include "stm32l1xx_rcc.h"
+#include "stm32l1xx_hal_rcc.h"
 #include "ST_L152_32MHZ.h"
 
 // only the constructor  
@@ -28,9 +27,15 @@
 
 ClockStatus L152_init32::setup_clock_32MHZ(int external)
 {
+   
+   
+   
+   
+   
+   
     uint32_t PLLStartUpCounter = 0,PLLStatus = 0,error;
 
-    RCC_DeInit();  // we have to reset the clock settings !
+    HAL_RCC_DeInit();  // we have to reset the clock settings !
 /* Enable 64-bit access */
     FLASH->ACR |= FLASH_ACR_ACC64;
 
@@ -67,12 +72,15 @@
         RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL6 | RCC_CFGR_PLLDIV3);
         }
     else{
-        RCC_HSEConfig(RCC_HSE_ON);                // start external crystal osc.
-        error = RCC_WaitForHSEStartUp();
-        if(error == ERROR ) { // no external crystal
-            return(EXT_ERR);
-            }    
-        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);    
+       
+       /** Need to be update with HAL_RCC_OscConfig
+                                                         **/
+       // __HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
+        //error = RCC_WaitForHSEStartUp();
+       // if(error == ERROR ) { // no external crystal
+         //   return(EXT_ERR);
+          //  }    
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);    
         }    
 
     /* Enable PLL */