Richard Blimmel / Mbed 2 deprecated CIG_HTTPClient

HTTPClient using static IP

Dependencies:   mbed

NetServices/drv/usb/UsbInc.h@0:d8f2f7d5f31b, 2011-05-30 (annotated)

Committer:
mr_q
Date:
Mon May 30 11:53:37 2011 +0000
Revision:
0:d8f2f7d5f31b
v0.01 Draft

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mr_q 0:d8f2f7d5f31b 1
mr_q 0:d8f2f7d5f31b 2 /*
mr_q 0:d8f2f7d5f31b 3 Copyright (c) 2010 Donatien Garnier (donatiengar [at] gmail [dot] com)
mr_q 0:d8f2f7d5f31b 4
mr_q 0:d8f2f7d5f31b 5 Permission is hereby granted, free of charge, to any person obtaining a copy
mr_q 0:d8f2f7d5f31b 6 of this software and associated documentation files (the "Software"), to deal
mr_q 0:d8f2f7d5f31b 7 in the Software without restriction, including without limitation the rights
mr_q 0:d8f2f7d5f31b 8 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
mr_q 0:d8f2f7d5f31b 9 copies of the Software, and to permit persons to whom the Software is
mr_q 0:d8f2f7d5f31b 10 furnished to do so, subject to the following conditions:
mr_q 0:d8f2f7d5f31b 11
mr_q 0:d8f2f7d5f31b 12 The above copyright notice and this permission notice shall be included in
mr_q 0:d8f2f7d5f31b 13 all copies or substantial portions of the Software.
mr_q 0:d8f2f7d5f31b 14
mr_q 0:d8f2f7d5f31b 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
mr_q 0:d8f2f7d5f31b 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
mr_q 0:d8f2f7d5f31b 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
mr_q 0:d8f2f7d5f31b 18 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
mr_q 0:d8f2f7d5f31b 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mr_q 0:d8f2f7d5f31b 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
mr_q 0:d8f2f7d5f31b 21 THE SOFTWARE.
mr_q 0:d8f2f7d5f31b 22 */
mr_q 0:d8f2f7d5f31b 23
mr_q 0:d8f2f7d5f31b 24 #ifndef USB_INC_H
mr_q 0:d8f2f7d5f31b 25 #define USB_INC_H
mr_q 0:d8f2f7d5f31b 26
mr_q 0:d8f2f7d5f31b 27 #include "mbed.h"
mr_q 0:d8f2f7d5f31b 28
mr_q 0:d8f2f7d5f31b 29 #define MIN(a,b) ((a)<(b)?(a):(b))
mr_q 0:d8f2f7d5f31b 30 #define MAX(a,b) ((a)>(b)?(a):(b))
mr_q 0:d8f2f7d5f31b 31
mr_q 0:d8f2f7d5f31b 32 //typedef int32_t RC;
mr_q 0:d8f2f7d5f31b 33
mr_q 0:d8f2f7d5f31b 34 typedef uint8_t byte;
mr_q 0:d8f2f7d5f31b 35 typedef uint16_t word;
mr_q 0:d8f2f7d5f31b 36
mr_q 0:d8f2f7d5f31b 37 enum UsbErr
mr_q 0:d8f2f7d5f31b 38 {
mr_q 0:d8f2f7d5f31b 39 __USBERR_MIN = -0xFFFF,
mr_q 0:d8f2f7d5f31b 40 USBERR_DISCONNECTED,
mr_q 0:d8f2f7d5f31b 41 USBERR_NOTFOUND,
mr_q 0:d8f2f7d5f31b 42 USBERR_BADCONFIG,
mr_q 0:d8f2f7d5f31b 43 USBERR_PROCESSING,
mr_q 0:d8f2f7d5f31b 44 USBERR_HALTED, //Transfer on an ep is stalled
mr_q 0:d8f2f7d5f31b 45 USBERR_BUSY,
mr_q 0:d8f2f7d5f31b 46 USBERR_TDFAIL,
mr_q 0:d8f2f7d5f31b 47 USBERR_ERROR,
mr_q 0:d8f2f7d5f31b 48 USBERR_OK = 0
mr_q 0:d8f2f7d5f31b 49 };
mr_q 0:d8f2f7d5f31b 50
mr_q 0:d8f2f7d5f31b 51
mr_q 0:d8f2f7d5f31b 52 /* From NXP's USBHostLite stack's usbhost_lpc17xx.h */
mr_q 0:d8f2f7d5f31b 53 /* Only the types names have been changed to avoid unecessary typedefs */
mr_q 0:d8f2f7d5f31b 54
mr_q 0:d8f2f7d5f31b 55
mr_q 0:d8f2f7d5f31b 56 /*
mr_q 0:d8f2f7d5f31b 57 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 58 * NXP USB Host Stack
mr_q 0:d8f2f7d5f31b 59 *
mr_q 0:d8f2f7d5f31b 60 * (c) Copyright 2008, NXP SemiConductors
mr_q 0:d8f2f7d5f31b 61 * (c) Copyright 2008, OnChip Technologies LLC
mr_q 0:d8f2f7d5f31b 62 * All Rights Reserved
mr_q 0:d8f2f7d5f31b 63 *
mr_q 0:d8f2f7d5f31b 64 * www.nxp.com
mr_q 0:d8f2f7d5f31b 65 * www.onchiptech.com
mr_q 0:d8f2f7d5f31b 66 *
mr_q 0:d8f2f7d5f31b 67 * File : usbhost_lpc17xx.h
mr_q 0:d8f2f7d5f31b 68 * Programmer(s) : Ravikanth.P
mr_q 0:d8f2f7d5f31b 69 * Version :
mr_q 0:d8f2f7d5f31b 70 *
mr_q 0:d8f2f7d5f31b 71 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 72 */
mr_q 0:d8f2f7d5f31b 73
mr_q 0:d8f2f7d5f31b 74
mr_q 0:d8f2f7d5f31b 75
mr_q 0:d8f2f7d5f31b 76 /*
mr_q 0:d8f2f7d5f31b 77 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 78 * OHCI OPERATIONAL REGISTER FIELD DEFINITIONS
mr_q 0:d8f2f7d5f31b 79 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 80 */
mr_q 0:d8f2f7d5f31b 81
mr_q 0:d8f2f7d5f31b 82 /* ------------------ HcControl Register --------------------- */
mr_q 0:d8f2f7d5f31b 83 #define OR_CONTROL_CLE 0x00000010
mr_q 0:d8f2f7d5f31b 84 #define OR_CONTROL_BLE 0x00000020
mr_q 0:d8f2f7d5f31b 85 #define OR_CONTROL_HCFS 0x000000C0
mr_q 0:d8f2f7d5f31b 86 #define OR_CONTROL_HC_OPER 0x00000080
mr_q 0:d8f2f7d5f31b 87 /* ----------------- HcCommandStatus Register ----------------- */
mr_q 0:d8f2f7d5f31b 88 #define OR_CMD_STATUS_HCR 0x00000001
mr_q 0:d8f2f7d5f31b 89 #define OR_CMD_STATUS_CLF 0x00000002
mr_q 0:d8f2f7d5f31b 90 #define OR_CMD_STATUS_BLF 0x00000004
mr_q 0:d8f2f7d5f31b 91 /* --------------- HcInterruptStatus Register ----------------- */
mr_q 0:d8f2f7d5f31b 92 #define OR_INTR_STATUS_WDH 0x00000002
mr_q 0:d8f2f7d5f31b 93 #define OR_INTR_STATUS_RHSC 0x00000040
mr_q 0:d8f2f7d5f31b 94 #define OR_INTR_STATUS_UE 0x00000010
mr_q 0:d8f2f7d5f31b 95 /* --------------- HcInterruptEnable Register ----------------- */
mr_q 0:d8f2f7d5f31b 96 #define OR_INTR_ENABLE_WDH 0x00000002
mr_q 0:d8f2f7d5f31b 97 #define OR_INTR_ENABLE_RHSC 0x00000040
mr_q 0:d8f2f7d5f31b 98 #define OR_INTR_ENABLE_MIE 0x80000000
mr_q 0:d8f2f7d5f31b 99 /* ---------------- HcRhDescriptorA Register ------------------ */
mr_q 0:d8f2f7d5f31b 100 #define OR_RH_STATUS_LPSC 0x00010000
mr_q 0:d8f2f7d5f31b 101 #define OR_RH_STATUS_DRWE 0x00008000
mr_q 0:d8f2f7d5f31b 102 /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
mr_q 0:d8f2f7d5f31b 103 #define OR_RH_PORT_CCS 0x00000001
mr_q 0:d8f2f7d5f31b 104 #define OR_RH_PORT_PRS 0x00000010
mr_q 0:d8f2f7d5f31b 105 #define OR_RH_PORT_CSC 0x00010000
mr_q 0:d8f2f7d5f31b 106 #define OR_RH_PORT_PRSC 0x00100000
mr_q 0:d8f2f7d5f31b 107
mr_q 0:d8f2f7d5f31b 108
mr_q 0:d8f2f7d5f31b 109 /*
mr_q 0:d8f2f7d5f31b 110 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 111 * FRAME INTERVAL
mr_q 0:d8f2f7d5f31b 112 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 113 */
mr_q 0:d8f2f7d5f31b 114
mr_q 0:d8f2f7d5f31b 115 #define FI 0x2EDF /* 12000 bits per frame (-1) */
mr_q 0:d8f2f7d5f31b 116 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
mr_q 0:d8f2f7d5f31b 117
mr_q 0:d8f2f7d5f31b 118 /*
mr_q 0:d8f2f7d5f31b 119 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 120 * ENDPOINT DESCRIPTOR CONTROL FIELDS
mr_q 0:d8f2f7d5f31b 121 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 122 */
mr_q 0:d8f2f7d5f31b 123
mr_q 0:d8f2f7d5f31b 124 #define ED_SKIP (uint32_t) (0x00001000) /* Skip this ep in queue */
mr_q 0:d8f2f7d5f31b 125
mr_q 0:d8f2f7d5f31b 126 /*
mr_q 0:d8f2f7d5f31b 127 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 128 * TRANSFER DESCRIPTOR CONTROL FIELDS
mr_q 0:d8f2f7d5f31b 129 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 130 */
mr_q 0:d8f2f7d5f31b 131
mr_q 0:d8f2f7d5f31b 132 #define TD_ROUNDING (uint32_t) (0x00040000) /* Buffer Rounding */
mr_q 0:d8f2f7d5f31b 133 #define TD_SETUP (uint32_t)(0) /* Direction of Setup Packet */
mr_q 0:d8f2f7d5f31b 134 #define TD_IN (uint32_t)(0x00100000) /* Direction In */
mr_q 0:d8f2f7d5f31b 135 #define TD_OUT (uint32_t)(0x00080000) /* Direction Out */
mr_q 0:d8f2f7d5f31b 136 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) /* Delay Interrupt */
mr_q 0:d8f2f7d5f31b 137 #define TD_TOGGLE_0 (uint32_t)(0x02000000) /* Toggle 0 */
mr_q 0:d8f2f7d5f31b 138 #define TD_TOGGLE_1 (uint32_t)(0x03000000) /* Toggle 1 */
mr_q 0:d8f2f7d5f31b 139 #define TD_CC (uint32_t)(0xF0000000) /* Completion Code */
mr_q 0:d8f2f7d5f31b 140
mr_q 0:d8f2f7d5f31b 141 /*
mr_q 0:d8f2f7d5f31b 142 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 143 * USB STANDARD REQUEST DEFINITIONS
mr_q 0:d8f2f7d5f31b 144 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 145 */
mr_q 0:d8f2f7d5f31b 146
mr_q 0:d8f2f7d5f31b 147 #define USB_DESCRIPTOR_TYPE_DEVICE 1
mr_q 0:d8f2f7d5f31b 148 #define USB_DESCRIPTOR_TYPE_CONFIGURATION 2
mr_q 0:d8f2f7d5f31b 149 #define USB_DESCRIPTOR_TYPE_INTERFACE 4
mr_q 0:d8f2f7d5f31b 150 #define USB_DESCRIPTOR_TYPE_ENDPOINT 5
mr_q 0:d8f2f7d5f31b 151 /* ----------- Control RequestType Fields ----------- */
mr_q 0:d8f2f7d5f31b 152 #define USB_DEVICE_TO_HOST 0x80
mr_q 0:d8f2f7d5f31b 153 #define USB_HOST_TO_DEVICE 0x00
mr_q 0:d8f2f7d5f31b 154 #define USB_REQUEST_TYPE_CLASS 0x20
mr_q 0:d8f2f7d5f31b 155 #define USB_RECIPIENT_DEVICE 0x00
mr_q 0:d8f2f7d5f31b 156 #define USB_RECIPIENT_INTERFACE 0x01
mr_q 0:d8f2f7d5f31b 157 /* -------------- USB Standard Requests -------------- */
mr_q 0:d8f2f7d5f31b 158 #define SET_ADDRESS 5
mr_q 0:d8f2f7d5f31b 159 #define GET_DESCRIPTOR 6
mr_q 0:d8f2f7d5f31b 160 #define SET_CONFIGURATION 9
mr_q 0:d8f2f7d5f31b 161 #define SET_INTERFACE 11
mr_q 0:d8f2f7d5f31b 162
mr_q 0:d8f2f7d5f31b 163 /*
mr_q 0:d8f2f7d5f31b 164 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 165 * TYPE DEFINITIONS
mr_q 0:d8f2f7d5f31b 166 **************************************************************************************************************
mr_q 0:d8f2f7d5f31b 167 */
mr_q 0:d8f2f7d5f31b 168
mr_q 0:d8f2f7d5f31b 169 typedef struct hcEd { /* ----------- HostController EndPoint Descriptor ------------- */
mr_q 0:d8f2f7d5f31b 170 volatile uint32_t Control; /* Endpoint descriptor control */
mr_q 0:d8f2f7d5f31b 171 volatile uint32_t TailTd; /* Physical address of tail in Transfer descriptor list */
mr_q 0:d8f2f7d5f31b 172 volatile uint32_t HeadTd; /* Physcial address of head in Transfer descriptor list */
mr_q 0:d8f2f7d5f31b 173 volatile uint32_t Next; /* Physical address of next Endpoint descriptor */
mr_q 0:d8f2f7d5f31b 174 } HCED;
mr_q 0:d8f2f7d5f31b 175
mr_q 0:d8f2f7d5f31b 176 typedef struct hcTd { /* ------------ HostController Transfer Descriptor ------------ */
mr_q 0:d8f2f7d5f31b 177 volatile uint32_t Control; /* Transfer descriptor control */
mr_q 0:d8f2f7d5f31b 178 volatile uint32_t CurrBufPtr; /* Physical address of current buffer pointer */
mr_q 0:d8f2f7d5f31b 179 volatile uint32_t Next; /* Physical pointer to next Transfer Descriptor */
mr_q 0:d8f2f7d5f31b 180 volatile uint32_t BufEnd; /* Physical address of end of buffer */
mr_q 0:d8f2f7d5f31b 181 } HCTD;
mr_q 0:d8f2f7d5f31b 182
mr_q 0:d8f2f7d5f31b 183 typedef struct hcca { /* ----------- Host Controller Communication Area ------------ */
mr_q 0:d8f2f7d5f31b 184 volatile uint32_t IntTable[32]; /* Interrupt Table */
mr_q 0:d8f2f7d5f31b 185 volatile uint32_t FrameNumber; /* Frame Number */
mr_q 0:d8f2f7d5f31b 186 volatile uint32_t DoneHead; /* Done Head */
mr_q 0:d8f2f7d5f31b 187 volatile uint8_t Reserved[116]; /* Reserved for future use */
mr_q 0:d8f2f7d5f31b 188 volatile uint8_t Unknown[4]; /* Unused */
mr_q 0:d8f2f7d5f31b 189 } HCCA;
mr_q 0:d8f2f7d5f31b 190
mr_q 0:d8f2f7d5f31b 191
mr_q 0:d8f2f7d5f31b 192
mr_q 0:d8f2f7d5f31b 193 #endif