Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

mbed-src/targets/hal/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /* mbed Microcontroller Library
sam_grove 5:3f93dd1d4cb3 2 * Copyright (c) 2006-2013 ARM Limited
sam_grove 5:3f93dd1d4cb3 3 *
sam_grove 5:3f93dd1d4cb3 4 * Licensed under the Apache License, Version 2.0 (the "License");
sam_grove 5:3f93dd1d4cb3 5 * you may not use this file except in compliance with the License.
sam_grove 5:3f93dd1d4cb3 6 * You may obtain a copy of the License at
sam_grove 5:3f93dd1d4cb3 7 *
sam_grove 5:3f93dd1d4cb3 8 * http://www.apache.org/licenses/LICENSE-2.0
sam_grove 5:3f93dd1d4cb3 9 *
sam_grove 5:3f93dd1d4cb3 10 * Unless required by applicable law or agreed to in writing, software
sam_grove 5:3f93dd1d4cb3 11 * distributed under the License is distributed on an "AS IS" BASIS,
sam_grove 5:3f93dd1d4cb3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
sam_grove 5:3f93dd1d4cb3 13 * See the License for the specific language governing permissions and
sam_grove 5:3f93dd1d4cb3 14 * limitations under the License.
sam_grove 5:3f93dd1d4cb3 15 */
sam_grove 5:3f93dd1d4cb3 16 #include <stddef.h>
sam_grove 5:3f93dd1d4cb3 17
sam_grove 5:3f93dd1d4cb3 18 #include "gpio_irq_api.h"
sam_grove 5:3f93dd1d4cb3 19 #include "error.h"
sam_grove 5:3f93dd1d4cb3 20 #include "cmsis.h"
sam_grove 5:3f93dd1d4cb3 21
sam_grove 5:3f93dd1d4cb3 22 #define CHANNEL_NUM 48
sam_grove 5:3f93dd1d4cb3 23
sam_grove 5:3f93dd1d4cb3 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
sam_grove 5:3f93dd1d4cb3 25 static gpio_irq_handler irq_handler;
sam_grove 5:3f93dd1d4cb3 26
sam_grove 5:3f93dd1d4cb3 27 static void handle_interrupt_in(void) {
sam_grove 5:3f93dd1d4cb3 28 // Read in all current interrupt registers. We do this once as the
sam_grove 5:3f93dd1d4cb3 29 // GPIO interrupt registers are on the APB bus, and this is slow.
sam_grove 5:3f93dd1d4cb3 30 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
sam_grove 5:3f93dd1d4cb3 31 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
sam_grove 5:3f93dd1d4cb3 32 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
sam_grove 5:3f93dd1d4cb3 33 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
sam_grove 5:3f93dd1d4cb3 34 uint8_t bitloc;
sam_grove 5:3f93dd1d4cb3 35
sam_grove 5:3f93dd1d4cb3 36 while(rise0 > 0) { //Continue as long as there are interrupts pending
sam_grove 5:3f93dd1d4cb3 37 bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sam_grove 5:3f93dd1d4cb3 38 if (channel_ids[bitloc] != 0)
sam_grove 5:3f93dd1d4cb3 39 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
sam_grove 5:3f93dd1d4cb3 40
sam_grove 5:3f93dd1d4cb3 41 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sam_grove 5:3f93dd1d4cb3 42 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sam_grove 5:3f93dd1d4cb3 43 rise0 -= 1<<bitloc;
sam_grove 5:3f93dd1d4cb3 44 }
sam_grove 5:3f93dd1d4cb3 45
sam_grove 5:3f93dd1d4cb3 46 while(fall0 > 0) { //Continue as long as there are interrupts pending
sam_grove 5:3f93dd1d4cb3 47 bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sam_grove 5:3f93dd1d4cb3 48 if (channel_ids[bitloc] != 0)
sam_grove 5:3f93dd1d4cb3 49 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
sam_grove 5:3f93dd1d4cb3 50
sam_grove 5:3f93dd1d4cb3 51 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sam_grove 5:3f93dd1d4cb3 52 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
sam_grove 5:3f93dd1d4cb3 53 fall0 -= 1<<bitloc;
sam_grove 5:3f93dd1d4cb3 54 }
sam_grove 5:3f93dd1d4cb3 55
sam_grove 5:3f93dd1d4cb3 56 //Same for port 2, only we need to watch the channel_index
sam_grove 5:3f93dd1d4cb3 57 while(rise2 > 0) { //Continue as long as there are interrupts pending
sam_grove 5:3f93dd1d4cb3 58 bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sam_grove 5:3f93dd1d4cb3 59
sam_grove 5:3f93dd1d4cb3 60 if (bitloc < 16) //Not sure if this is actually needed
sam_grove 5:3f93dd1d4cb3 61 if (channel_ids[bitloc+32] != 0)
sam_grove 5:3f93dd1d4cb3 62 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
sam_grove 5:3f93dd1d4cb3 63
sam_grove 5:3f93dd1d4cb3 64 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sam_grove 5:3f93dd1d4cb3 65 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sam_grove 5:3f93dd1d4cb3 66 rise2 -= 1<<bitloc;
sam_grove 5:3f93dd1d4cb3 67 }
sam_grove 5:3f93dd1d4cb3 68
sam_grove 5:3f93dd1d4cb3 69 while(fall2 > 0) { //Continue as long as there are interrupts pending
sam_grove 5:3f93dd1d4cb3 70 bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
sam_grove 5:3f93dd1d4cb3 71
sam_grove 5:3f93dd1d4cb3 72 if (bitloc < 16) //Not sure if this is actually needed
sam_grove 5:3f93dd1d4cb3 73 if (channel_ids[bitloc+32] != 0)
sam_grove 5:3f93dd1d4cb3 74 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
sam_grove 5:3f93dd1d4cb3 75
sam_grove 5:3f93dd1d4cb3 76 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
sam_grove 5:3f93dd1d4cb3 77 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
sam_grove 5:3f93dd1d4cb3 78 fall2 -= 1<<bitloc;
sam_grove 5:3f93dd1d4cb3 79 }
sam_grove 5:3f93dd1d4cb3 80 }
sam_grove 5:3f93dd1d4cb3 81
sam_grove 5:3f93dd1d4cb3 82 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
sam_grove 5:3f93dd1d4cb3 83 if (pin == NC) return -1;
sam_grove 5:3f93dd1d4cb3 84
sam_grove 5:3f93dd1d4cb3 85 irq_handler = handler;
sam_grove 5:3f93dd1d4cb3 86
sam_grove 5:3f93dd1d4cb3 87 obj->port = (int)pin & ~0x1F;
sam_grove 5:3f93dd1d4cb3 88 obj->pin = (int)pin & 0x1F;
sam_grove 5:3f93dd1d4cb3 89
sam_grove 5:3f93dd1d4cb3 90 // Interrupts available only on GPIO0 and GPIO2
sam_grove 5:3f93dd1d4cb3 91 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
sam_grove 5:3f93dd1d4cb3 92 error("pins on this port cannot generate interrupts\n");
sam_grove 5:3f93dd1d4cb3 93 }
sam_grove 5:3f93dd1d4cb3 94
sam_grove 5:3f93dd1d4cb3 95 // put us in the interrupt table
sam_grove 5:3f93dd1d4cb3 96 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
sam_grove 5:3f93dd1d4cb3 97 channel_ids[index] = id;
sam_grove 5:3f93dd1d4cb3 98 obj->ch = index;
sam_grove 5:3f93dd1d4cb3 99
sam_grove 5:3f93dd1d4cb3 100 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
sam_grove 5:3f93dd1d4cb3 101 NVIC_EnableIRQ(EINT3_IRQn);
sam_grove 5:3f93dd1d4cb3 102 return 0;
sam_grove 5:3f93dd1d4cb3 103 }
sam_grove 5:3f93dd1d4cb3 104
sam_grove 5:3f93dd1d4cb3 105 void gpio_irq_free(gpio_irq_t *obj) {
sam_grove 5:3f93dd1d4cb3 106 channel_ids[obj->ch] = 0;
sam_grove 5:3f93dd1d4cb3 107 }
sam_grove 5:3f93dd1d4cb3 108
sam_grove 5:3f93dd1d4cb3 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
sam_grove 5:3f93dd1d4cb3 110 // ensure nothing is pending
sam_grove 5:3f93dd1d4cb3 111 switch (obj->port) {
sam_grove 5:3f93dd1d4cb3 112 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
sam_grove 5:3f93dd1d4cb3 113 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
sam_grove 5:3f93dd1d4cb3 114 }
sam_grove 5:3f93dd1d4cb3 115
sam_grove 5:3f93dd1d4cb3 116 // enable the pin interrupt
sam_grove 5:3f93dd1d4cb3 117 if (event == IRQ_RISE) {
sam_grove 5:3f93dd1d4cb3 118 switch (obj->port) {
sam_grove 5:3f93dd1d4cb3 119 case LPC_GPIO0_BASE:
sam_grove 5:3f93dd1d4cb3 120 if (enable) {
sam_grove 5:3f93dd1d4cb3 121 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
sam_grove 5:3f93dd1d4cb3 122 } else {
sam_grove 5:3f93dd1d4cb3 123 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
sam_grove 5:3f93dd1d4cb3 124 }
sam_grove 5:3f93dd1d4cb3 125 break;
sam_grove 5:3f93dd1d4cb3 126 case LPC_GPIO2_BASE:
sam_grove 5:3f93dd1d4cb3 127 if (enable) {
sam_grove 5:3f93dd1d4cb3 128 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
sam_grove 5:3f93dd1d4cb3 129 } else {
sam_grove 5:3f93dd1d4cb3 130 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
sam_grove 5:3f93dd1d4cb3 131 }
sam_grove 5:3f93dd1d4cb3 132 break;
sam_grove 5:3f93dd1d4cb3 133 }
sam_grove 5:3f93dd1d4cb3 134 } else {
sam_grove 5:3f93dd1d4cb3 135 switch (obj->port) {
sam_grove 5:3f93dd1d4cb3 136 case LPC_GPIO0_BASE:
sam_grove 5:3f93dd1d4cb3 137 if (enable) {
sam_grove 5:3f93dd1d4cb3 138 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
sam_grove 5:3f93dd1d4cb3 139 } else {
sam_grove 5:3f93dd1d4cb3 140 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
sam_grove 5:3f93dd1d4cb3 141 }
sam_grove 5:3f93dd1d4cb3 142 break;
sam_grove 5:3f93dd1d4cb3 143 case LPC_GPIO2_BASE:
sam_grove 5:3f93dd1d4cb3 144 if (enable) {
sam_grove 5:3f93dd1d4cb3 145 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
sam_grove 5:3f93dd1d4cb3 146 } else {
sam_grove 5:3f93dd1d4cb3 147 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
sam_grove 5:3f93dd1d4cb3 148 }
sam_grove 5:3f93dd1d4cb3 149 break;
sam_grove 5:3f93dd1d4cb3 150 }
sam_grove 5:3f93dd1d4cb3 151 }
sam_grove 5:3f93dd1d4cb3 152 }