Mike Pulice / ublox_C200Test

Integrating the ublox LISA C200 modem

Fork of SprintUSBModemHTTPClientTest by Donatien Garnier

SprintUSBModem/USBHostWANDongleSprint/USBHost/USBHostTypes.h@5:3f93dd1d4cb3, 2013-09-26 (annotated)

Committer:
sam_grove
Date:
Thu Sep 26 00:44:20 2013 -0500
Revision:
5:3f93dd1d4cb3
Exported program and replaced contents of the repo with the source

to build and debug using keil mdk. Libs NOT upto date are lwip, lwip-sys

and socket. these have newer versions under mbed_official but were starting

from a know working point

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sam_grove 5:3f93dd1d4cb3 1 /* Copyright (c) 2010-2012 mbed.org, MIT License
sam_grove 5:3f93dd1d4cb3 2 *
sam_grove 5:3f93dd1d4cb3 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
sam_grove 5:3f93dd1d4cb3 4 * and associated documentation files (the "Software"), to deal in the Software without
sam_grove 5:3f93dd1d4cb3 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
sam_grove 5:3f93dd1d4cb3 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
sam_grove 5:3f93dd1d4cb3 7 * Software is furnished to do so, subject to the following conditions:
sam_grove 5:3f93dd1d4cb3 8 *
sam_grove 5:3f93dd1d4cb3 9 * The above copyright notice and this permission notice shall be included in all copies or
sam_grove 5:3f93dd1d4cb3 10 * substantial portions of the Software.
sam_grove 5:3f93dd1d4cb3 11 *
sam_grove 5:3f93dd1d4cb3 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
sam_grove 5:3f93dd1d4cb3 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
sam_grove 5:3f93dd1d4cb3 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
sam_grove 5:3f93dd1d4cb3 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
sam_grove 5:3f93dd1d4cb3 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
sam_grove 5:3f93dd1d4cb3 17 */
sam_grove 5:3f93dd1d4cb3 18
sam_grove 5:3f93dd1d4cb3 19 #ifndef USB_INC_H
sam_grove 5:3f93dd1d4cb3 20 #define USB_INC_H
sam_grove 5:3f93dd1d4cb3 21
sam_grove 5:3f93dd1d4cb3 22 #include "mbed.h"
sam_grove 5:3f93dd1d4cb3 23
sam_grove 5:3f93dd1d4cb3 24 enum USB_TYPE {
sam_grove 5:3f93dd1d4cb3 25 USB_TYPE_DISCONNECTED = -10,
sam_grove 5:3f93dd1d4cb3 26 USB_TYPE_NOTFOUND = -9,
sam_grove 5:3f93dd1d4cb3 27 USB_TYPE_BADCONFIG = -8,
sam_grove 5:3f93dd1d4cb3 28 USB_TYPE_FREE = -7,
sam_grove 5:3f93dd1d4cb3 29 USB_TYPE_IDLE = -6,
sam_grove 5:3f93dd1d4cb3 30 USB_TYPE_PROCESSING = -5,
sam_grove 5:3f93dd1d4cb3 31 USB_TYPE_HALTED = -4, //Transfer on an ep is stalled
sam_grove 5:3f93dd1d4cb3 32 USB_TYPE_BUSY = -3,
sam_grove 5:3f93dd1d4cb3 33 USB_TYPE_TDFAIL = -2,
sam_grove 5:3f93dd1d4cb3 34 USB_TYPE_ERROR = -1,
sam_grove 5:3f93dd1d4cb3 35 USB_TYPE_OK = 0
sam_grove 5:3f93dd1d4cb3 36 };
sam_grove 5:3f93dd1d4cb3 37
sam_grove 5:3f93dd1d4cb3 38 #define AUDIO_CLASS 0x01
sam_grove 5:3f93dd1d4cb3 39 #define CDC_CLASS 0x02
sam_grove 5:3f93dd1d4cb3 40 #define MSD_CLASS 0x08
sam_grove 5:3f93dd1d4cb3 41 #define HID_CLASS 0x03
sam_grove 5:3f93dd1d4cb3 42
sam_grove 5:3f93dd1d4cb3 43
sam_grove 5:3f93dd1d4cb3 44 // From NXP's USBHostLite stack's usbhost_lpc17xx.h
sam_grove 5:3f93dd1d4cb3 45 // Only the types names have been changed to avoid unecessary typedefs
sam_grove 5:3f93dd1d4cb3 46
sam_grove 5:3f93dd1d4cb3 47
sam_grove 5:3f93dd1d4cb3 48 /*
sam_grove 5:3f93dd1d4cb3 49 **************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 50 * NXP USB Host Stack
sam_grove 5:3f93dd1d4cb3 51 *
sam_grove 5:3f93dd1d4cb3 52 * (c) Copyright 2008, NXP SemiConductors
sam_grove 5:3f93dd1d4cb3 53 * (c) Copyright 2008, OnChip Technologies LLC
sam_grove 5:3f93dd1d4cb3 54 * All Rights Reserved
sam_grove 5:3f93dd1d4cb3 55 *
sam_grove 5:3f93dd1d4cb3 56 * www.nxp.com
sam_grove 5:3f93dd1d4cb3 57 * www.onchiptech.com
sam_grove 5:3f93dd1d4cb3 58 *
sam_grove 5:3f93dd1d4cb3 59 * File : usbhost_lpc17xx.h
sam_grove 5:3f93dd1d4cb3 60 * Programmer(s) : Ravikanth.P
sam_grove 5:3f93dd1d4cb3 61 * Version :
sam_grove 5:3f93dd1d4cb3 62 *
sam_grove 5:3f93dd1d4cb3 63 **************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 64 */
sam_grove 5:3f93dd1d4cb3 65
sam_grove 5:3f93dd1d4cb3 66
sam_grove 5:3f93dd1d4cb3 67 // ------------------ HcControl Register ---------------------
sam_grove 5:3f93dd1d4cb3 68 #define OR_CONTROL_PLE 0x00000004
sam_grove 5:3f93dd1d4cb3 69 #define OR_CONTROL_CLE 0x00000010
sam_grove 5:3f93dd1d4cb3 70 #define OR_CONTROL_BLE 0x00000020
sam_grove 5:3f93dd1d4cb3 71 #define OR_CONTROL_HCFS 0x000000C0
sam_grove 5:3f93dd1d4cb3 72 #define OR_CONTROL_HC_OPER 0x00000080
sam_grove 5:3f93dd1d4cb3 73 // ----------------- HcCommandStatus Register -----------------
sam_grove 5:3f93dd1d4cb3 74 #define OR_CMD_STATUS_HCR 0x00000001
sam_grove 5:3f93dd1d4cb3 75 #define OR_CMD_STATUS_CLF 0x00000002
sam_grove 5:3f93dd1d4cb3 76 #define OR_CMD_STATUS_BLF 0x00000004
sam_grove 5:3f93dd1d4cb3 77 // --------------- HcInterruptStatus Register -----------------
sam_grove 5:3f93dd1d4cb3 78 #define OR_INTR_STATUS_WDH 0x00000002
sam_grove 5:3f93dd1d4cb3 79 #define OR_INTR_STATUS_RHSC 0x00000040
sam_grove 5:3f93dd1d4cb3 80 #define OR_INTR_STATUS_UE 0x00000010
sam_grove 5:3f93dd1d4cb3 81 // --------------- HcInterruptEnable Register -----------------
sam_grove 5:3f93dd1d4cb3 82 #define OR_INTR_ENABLE_WDH 0x00000002
sam_grove 5:3f93dd1d4cb3 83 #define OR_INTR_ENABLE_RHSC 0x00000040
sam_grove 5:3f93dd1d4cb3 84 #define OR_INTR_ENABLE_MIE 0x80000000
sam_grove 5:3f93dd1d4cb3 85 // ---------------- HcRhDescriptorA Register ------------------
sam_grove 5:3f93dd1d4cb3 86 #define OR_RH_STATUS_LPSC 0x00010000
sam_grove 5:3f93dd1d4cb3 87 #define OR_RH_STATUS_DRWE 0x00008000
sam_grove 5:3f93dd1d4cb3 88 // -------------- HcRhPortStatus[1:NDP] Register --------------
sam_grove 5:3f93dd1d4cb3 89 #define OR_RH_PORT_CCS 0x00000001
sam_grove 5:3f93dd1d4cb3 90 #define OR_RH_PORT_PRS 0x00000010
sam_grove 5:3f93dd1d4cb3 91 #define OR_RH_PORT_CSC 0x00010000
sam_grove 5:3f93dd1d4cb3 92 #define OR_RH_PORT_PRSC 0x00100000
sam_grove 5:3f93dd1d4cb3 93 #define OR_RH_PORT_LSDA 0x00000200
sam_grove 5:3f93dd1d4cb3 94
sam_grove 5:3f93dd1d4cb3 95
sam_grove 5:3f93dd1d4cb3 96 //
sam_grove 5:3f93dd1d4cb3 97 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 98 //* FRAME INTERVAL
sam_grove 5:3f93dd1d4cb3 99 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 100 //
sam_grove 5:3f93dd1d4cb3 101
sam_grove 5:3f93dd1d4cb3 102 #define FI 0x2EDF // 12000 bits per frame (-1)
sam_grove 5:3f93dd1d4cb3 103 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
sam_grove 5:3f93dd1d4cb3 104
sam_grove 5:3f93dd1d4cb3 105 //
sam_grove 5:3f93dd1d4cb3 106 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 107 //* ENDPOINT DESCRIPTOR CONTROL FIELDS
sam_grove 5:3f93dd1d4cb3 108 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 109 //
sam_grove 5:3f93dd1d4cb3 110
sam_grove 5:3f93dd1d4cb3 111 #define ED_SKIP (uint32_t) (0x00001000) // Skip this ep in queue
sam_grove 5:3f93dd1d4cb3 112
sam_grove 5:3f93dd1d4cb3 113 //
sam_grove 5:3f93dd1d4cb3 114 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 115 //* TRANSFER DESCRIPTOR CONTROL FIELDS
sam_grove 5:3f93dd1d4cb3 116 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 117 //
sam_grove 5:3f93dd1d4cb3 118
sam_grove 5:3f93dd1d4cb3 119 #define TD_ROUNDING (uint32_t) (0x00040000) // Buffer Rounding
sam_grove 5:3f93dd1d4cb3 120 #define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
sam_grove 5:3f93dd1d4cb3 121 #define TD_IN (uint32_t)(0x00100000) // Direction In
sam_grove 5:3f93dd1d4cb3 122 #define TD_OUT (uint32_t)(0x00080000) // Direction Out
sam_grove 5:3f93dd1d4cb3 123 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) // Delay Interrupt
sam_grove 5:3f93dd1d4cb3 124 #define TD_TOGGLE_0 (uint32_t)(0x02000000) // Toggle 0
sam_grove 5:3f93dd1d4cb3 125 #define TD_TOGGLE_1 (uint32_t)(0x03000000) // Toggle 1
sam_grove 5:3f93dd1d4cb3 126 #define TD_CC (uint32_t)(0xF0000000) // Completion Code
sam_grove 5:3f93dd1d4cb3 127
sam_grove 5:3f93dd1d4cb3 128 //
sam_grove 5:3f93dd1d4cb3 129 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 130 //* USB STANDARD REQUEST DEFINITIONS
sam_grove 5:3f93dd1d4cb3 131 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 132 //
sam_grove 5:3f93dd1d4cb3 133
sam_grove 5:3f93dd1d4cb3 134 #define DEVICE_DESCRIPTOR (1)
sam_grove 5:3f93dd1d4cb3 135 #define CONFIGURATION_DESCRIPTOR (2)
sam_grove 5:3f93dd1d4cb3 136 #define INTERFACE_DESCRIPTOR (4)
sam_grove 5:3f93dd1d4cb3 137 #define ENDPOINT_DESCRIPTOR (5)
sam_grove 5:3f93dd1d4cb3 138 #define HID_DESCRIPTOR (33)
sam_grove 5:3f93dd1d4cb3 139
sam_grove 5:3f93dd1d4cb3 140 // ----------- Control RequestType Fields -----------
sam_grove 5:3f93dd1d4cb3 141 #define USB_DEVICE_TO_HOST 0x80
sam_grove 5:3f93dd1d4cb3 142 #define USB_HOST_TO_DEVICE 0x00
sam_grove 5:3f93dd1d4cb3 143 #define USB_REQUEST_TYPE_CLASS 0x20
sam_grove 5:3f93dd1d4cb3 144 #define USB_RECIPIENT_DEVICE 0x00
sam_grove 5:3f93dd1d4cb3 145 #define USB_RECIPIENT_INTERFACE 0x01
sam_grove 5:3f93dd1d4cb3 146
sam_grove 5:3f93dd1d4cb3 147 // -------------- USB Standard Requests --------------
sam_grove 5:3f93dd1d4cb3 148 #define SET_ADDRESS 5
sam_grove 5:3f93dd1d4cb3 149 #define GET_DESCRIPTOR 6
sam_grove 5:3f93dd1d4cb3 150 #define SET_CONFIGURATION 9
sam_grove 5:3f93dd1d4cb3 151 #define SET_INTERFACE 11
sam_grove 5:3f93dd1d4cb3 152
sam_grove 5:3f93dd1d4cb3 153 // -------------- USB Descriptor Length --------------
sam_grove 5:3f93dd1d4cb3 154 #define DEVICE_DESCRIPTOR_LENGTH 0x12
sam_grove 5:3f93dd1d4cb3 155 #define CONFIGURATION_DESCRIPTOR_LENGTH 0x09
sam_grove 5:3f93dd1d4cb3 156
sam_grove 5:3f93dd1d4cb3 157
sam_grove 5:3f93dd1d4cb3 158 //
sam_grove 5:3f93dd1d4cb3 159 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 160 //* TYPE DEFINITIONS
sam_grove 5:3f93dd1d4cb3 161 //**************************************************************************************************************
sam_grove 5:3f93dd1d4cb3 162 //
sam_grove 5:3f93dd1d4cb3 163
sam_grove 5:3f93dd1d4cb3 164 // ----------- HostController EndPoint Descriptor -------------
sam_grove 5:3f93dd1d4cb3 165 typedef struct hcEd {
sam_grove 5:3f93dd1d4cb3 166 volatile uint32_t control; // Endpoint descriptor control
sam_grove 5:3f93dd1d4cb3 167 volatile uint32_t tailTD; // Physical address of tail in Transfer descriptor list
sam_grove 5:3f93dd1d4cb3 168 volatile uint32_t headTD; // Physcial address of head in Transfer descriptor list
sam_grove 5:3f93dd1d4cb3 169 volatile uint32_t nextED; // Physical address of next Endpoint descriptor
sam_grove 5:3f93dd1d4cb3 170 } HCED;
sam_grove 5:3f93dd1d4cb3 171
sam_grove 5:3f93dd1d4cb3 172 // ------------ HostController Transfer Descriptor ------------
sam_grove 5:3f93dd1d4cb3 173 typedef struct hcTd {
sam_grove 5:3f93dd1d4cb3 174 volatile uint32_t control; // Transfer descriptor control
sam_grove 5:3f93dd1d4cb3 175 volatile uint32_t currBufPtr; // Physical address of current buffer pointer
sam_grove 5:3f93dd1d4cb3 176 volatile uint32_t nextTD; // Physical pointer to next Transfer Descriptor
sam_grove 5:3f93dd1d4cb3 177 volatile uint32_t bufEnd; // Physical address of end of buffer
sam_grove 5:3f93dd1d4cb3 178 } HCTD;
sam_grove 5:3f93dd1d4cb3 179
sam_grove 5:3f93dd1d4cb3 180 // ----------- Host Controller Communication Area ------------
sam_grove 5:3f93dd1d4cb3 181 typedef struct hcca {
sam_grove 5:3f93dd1d4cb3 182 volatile uint32_t IntTable[32]; // Interrupt Table
sam_grove 5:3f93dd1d4cb3 183 volatile uint32_t FrameNumber; // Frame Number
sam_grove 5:3f93dd1d4cb3 184 volatile uint32_t DoneHead; // Done Head
sam_grove 5:3f93dd1d4cb3 185 volatile uint8_t Reserved[116]; // Reserved for future use
sam_grove 5:3f93dd1d4cb3 186 volatile uint8_t Unknown[4]; // Unused
sam_grove 5:3f93dd1d4cb3 187 } HCCA;
sam_grove 5:3f93dd1d4cb3 188
sam_grove 5:3f93dd1d4cb3 189
sam_grove 5:3f93dd1d4cb3 190
sam_grove 5:3f93dd1d4cb3 191 #endif