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targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c@445:9a3ffe6cfa19, 2015-01-14 (annotated)
- Committer:
- moirans2
- Date:
- Wed Jan 14 20:53:08 2015 +0000
- Revision:
- 445:9a3ffe6cfa19
- Parent:
- 441:d2c15dda23c1
internal clock stm32L051
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 441:d2c15dda23c1 | 1 | /** |
mbed_official | 441:d2c15dda23c1 | 2 | ****************************************************************************** |
mbed_official | 441:d2c15dda23c1 | 3 | * @file system_stm32f0xx.c |
mbed_official | 441:d2c15dda23c1 | 4 | * @author MCD Application Team |
mbed_official | 441:d2c15dda23c1 | 5 | * @version V2.2.0 |
mbed_official | 441:d2c15dda23c1 | 6 | * @date 05-December-2014 |
mbed_official | 441:d2c15dda23c1 | 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. |
mbed_official | 441:d2c15dda23c1 | 8 | * |
mbed_official | 441:d2c15dda23c1 | 9 | * 1. This file provides two functions and one global variable to be called from |
mbed_official | 441:d2c15dda23c1 | 10 | * user application: |
mbed_official | 441:d2c15dda23c1 | 11 | * - SystemInit(): This function is called at startup just after reset and |
mbed_official | 441:d2c15dda23c1 | 12 | * before branch to main program. This call is made inside |
mbed_official | 441:d2c15dda23c1 | 13 | * the "startup_stm32f0xx.s" file. |
mbed_official | 441:d2c15dda23c1 | 14 | * |
mbed_official | 441:d2c15dda23c1 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 441:d2c15dda23c1 | 16 | * by the user application to setup the SysTick |
mbed_official | 441:d2c15dda23c1 | 17 | * timer or configure other parameters. |
mbed_official | 441:d2c15dda23c1 | 18 | * |
mbed_official | 441:d2c15dda23c1 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 441:d2c15dda23c1 | 20 | * be called whenever the core clock is changed |
mbed_official | 441:d2c15dda23c1 | 21 | * during program execution. |
mbed_official | 441:d2c15dda23c1 | 22 | * |
mbed_official | 441:d2c15dda23c1 | 23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
mbed_official | 441:d2c15dda23c1 | 24 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to |
mbed_official | 441:d2c15dda23c1 | 25 | * configure the system clock before to branch to main program. |
mbed_official | 441:d2c15dda23c1 | 26 | * |
mbed_official | 441:d2c15dda23c1 | 27 | * 3. This file configures the system clock as follows: |
mbed_official | 441:d2c15dda23c1 | 28 | *============================================================================= |
mbed_official | 441:d2c15dda23c1 | 29 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 441:d2c15dda23c1 | 30 | * | (external 8 MHz clock) | (internal 48 MHz) |
mbed_official | 441:d2c15dda23c1 | 31 | * | 2- PLL_HSE_XTAL | |
mbed_official | 441:d2c15dda23c1 | 32 | * | (external 8 MHz xtal) | |
mbed_official | 441:d2c15dda23c1 | 33 | *----------------------------------------------------------------------------- |
mbed_official | 441:d2c15dda23c1 | 34 | * SYSCLK(MHz) | 48 | 48 |
mbed_official | 441:d2c15dda23c1 | 35 | *----------------------------------------------------------------------------- |
mbed_official | 441:d2c15dda23c1 | 36 | * AHBCLK (MHz) | 48 | 48 |
mbed_official | 441:d2c15dda23c1 | 37 | *----------------------------------------------------------------------------- |
mbed_official | 441:d2c15dda23c1 | 38 | * APB1CLK (MHz) | 48 | 48 |
mbed_official | 441:d2c15dda23c1 | 39 | *----------------------------------------------------------------------------- |
mbed_official | 441:d2c15dda23c1 | 40 | * USB capable (48 MHz precise clock) | YES | YES |
mbed_official | 441:d2c15dda23c1 | 41 | *============================================================================= |
mbed_official | 441:d2c15dda23c1 | 42 | ****************************************************************************** |
mbed_official | 441:d2c15dda23c1 | 43 | * @attention |
mbed_official | 441:d2c15dda23c1 | 44 | * |
mbed_official | 441:d2c15dda23c1 | 45 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 441:d2c15dda23c1 | 46 | * |
mbed_official | 441:d2c15dda23c1 | 47 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 441:d2c15dda23c1 | 48 | * are permitted provided that the following conditions are met: |
mbed_official | 441:d2c15dda23c1 | 49 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 441:d2c15dda23c1 | 50 | * this list of conditions and the following disclaimer. |
mbed_official | 441:d2c15dda23c1 | 51 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 441:d2c15dda23c1 | 52 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 441:d2c15dda23c1 | 53 | * and/or other materials provided with the distribution. |
mbed_official | 441:d2c15dda23c1 | 54 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 441:d2c15dda23c1 | 55 | * may be used to endorse or promote products derived from this software |
mbed_official | 441:d2c15dda23c1 | 56 | * without specific prior written permission. |
mbed_official | 441:d2c15dda23c1 | 57 | * |
mbed_official | 441:d2c15dda23c1 | 58 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 441:d2c15dda23c1 | 59 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 441:d2c15dda23c1 | 60 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 441:d2c15dda23c1 | 61 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 441:d2c15dda23c1 | 62 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 441:d2c15dda23c1 | 63 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 441:d2c15dda23c1 | 64 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 441:d2c15dda23c1 | 65 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 441:d2c15dda23c1 | 66 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 441:d2c15dda23c1 | 67 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 441:d2c15dda23c1 | 68 | * |
mbed_official | 441:d2c15dda23c1 | 69 | ****************************************************************************** |
mbed_official | 441:d2c15dda23c1 | 70 | */ |
mbed_official | 441:d2c15dda23c1 | 71 | |
mbed_official | 441:d2c15dda23c1 | 72 | /** @addtogroup CMSIS |
mbed_official | 441:d2c15dda23c1 | 73 | * @{ |
mbed_official | 441:d2c15dda23c1 | 74 | */ |
mbed_official | 441:d2c15dda23c1 | 75 | |
mbed_official | 441:d2c15dda23c1 | 76 | /** @addtogroup stm32f0xx_system |
mbed_official | 441:d2c15dda23c1 | 77 | * @{ |
mbed_official | 441:d2c15dda23c1 | 78 | */ |
mbed_official | 441:d2c15dda23c1 | 79 | |
mbed_official | 441:d2c15dda23c1 | 80 | /** @addtogroup STM32F0xx_System_Private_Includes |
mbed_official | 441:d2c15dda23c1 | 81 | * @{ |
mbed_official | 441:d2c15dda23c1 | 82 | */ |
mbed_official | 441:d2c15dda23c1 | 83 | |
mbed_official | 441:d2c15dda23c1 | 84 | #include "stm32f0xx.h" |
mbed_official | 441:d2c15dda23c1 | 85 | #include "hal_tick.h" |
mbed_official | 441:d2c15dda23c1 | 86 | |
mbed_official | 441:d2c15dda23c1 | 87 | /** |
mbed_official | 441:d2c15dda23c1 | 88 | * @} |
mbed_official | 441:d2c15dda23c1 | 89 | */ |
mbed_official | 441:d2c15dda23c1 | 90 | |
mbed_official | 441:d2c15dda23c1 | 91 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions |
mbed_official | 441:d2c15dda23c1 | 92 | * @{ |
mbed_official | 441:d2c15dda23c1 | 93 | */ |
mbed_official | 441:d2c15dda23c1 | 94 | |
mbed_official | 441:d2c15dda23c1 | 95 | /** |
mbed_official | 441:d2c15dda23c1 | 96 | * @} |
mbed_official | 441:d2c15dda23c1 | 97 | */ |
mbed_official | 441:d2c15dda23c1 | 98 | |
mbed_official | 441:d2c15dda23c1 | 99 | /** @addtogroup STM32F0xx_System_Private_Defines |
mbed_official | 441:d2c15dda23c1 | 100 | * @{ |
mbed_official | 441:d2c15dda23c1 | 101 | */ |
mbed_official | 441:d2c15dda23c1 | 102 | #if !defined (HSE_VALUE) |
mbed_official | 441:d2c15dda23c1 | 103 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
mbed_official | 441:d2c15dda23c1 | 104 | This value can be provided and adapted by the user application. */ |
mbed_official | 441:d2c15dda23c1 | 105 | #endif /* HSE_VALUE */ |
mbed_official | 441:d2c15dda23c1 | 106 | |
mbed_official | 441:d2c15dda23c1 | 107 | #if !defined (HSI_VALUE) |
mbed_official | 441:d2c15dda23c1 | 108 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
mbed_official | 441:d2c15dda23c1 | 109 | This value can be provided and adapted by the user application. */ |
mbed_official | 441:d2c15dda23c1 | 110 | #endif /* HSI_VALUE */ |
mbed_official | 441:d2c15dda23c1 | 111 | /** |
mbed_official | 441:d2c15dda23c1 | 112 | * @} |
mbed_official | 441:d2c15dda23c1 | 113 | */ |
mbed_official | 441:d2c15dda23c1 | 114 | |
mbed_official | 441:d2c15dda23c1 | 115 | /** @addtogroup STM32F0xx_System_Private_Macros |
mbed_official | 441:d2c15dda23c1 | 116 | * @{ |
mbed_official | 441:d2c15dda23c1 | 117 | */ |
mbed_official | 441:d2c15dda23c1 | 118 | |
mbed_official | 441:d2c15dda23c1 | 119 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
mbed_official | 441:d2c15dda23c1 | 120 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
mbed_official | 441:d2c15dda23c1 | 121 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
mbed_official | 441:d2c15dda23c1 | 122 | |
mbed_official | 441:d2c15dda23c1 | 123 | /** |
mbed_official | 441:d2c15dda23c1 | 124 | * @} |
mbed_official | 441:d2c15dda23c1 | 125 | */ |
mbed_official | 441:d2c15dda23c1 | 126 | |
mbed_official | 441:d2c15dda23c1 | 127 | /** @addtogroup STM32F0xx_System_Private_Variables |
mbed_official | 441:d2c15dda23c1 | 128 | * @{ |
mbed_official | 441:d2c15dda23c1 | 129 | */ |
mbed_official | 441:d2c15dda23c1 | 130 | /* This variable is updated in three ways: |
mbed_official | 441:d2c15dda23c1 | 131 | 1) by calling CMSIS function SystemCoreClockUpdate() |
mbed_official | 441:d2c15dda23c1 | 132 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
mbed_official | 441:d2c15dda23c1 | 133 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
mbed_official | 441:d2c15dda23c1 | 134 | Note: If you use this function to configure the system clock there is no need to |
mbed_official | 441:d2c15dda23c1 | 135 | call the 2 first functions listed above, since SystemCoreClock variable is |
mbed_official | 441:d2c15dda23c1 | 136 | updated automatically. |
mbed_official | 441:d2c15dda23c1 | 137 | */ |
mbed_official | 441:d2c15dda23c1 | 138 | uint32_t SystemCoreClock = 48000000; |
mbed_official | 441:d2c15dda23c1 | 139 | |
mbed_official | 441:d2c15dda23c1 | 140 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 441:d2c15dda23c1 | 141 | |
mbed_official | 441:d2c15dda23c1 | 142 | /** |
mbed_official | 441:d2c15dda23c1 | 143 | * @} |
mbed_official | 441:d2c15dda23c1 | 144 | */ |
mbed_official | 441:d2c15dda23c1 | 145 | |
mbed_official | 441:d2c15dda23c1 | 146 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes |
mbed_official | 441:d2c15dda23c1 | 147 | * @{ |
mbed_official | 441:d2c15dda23c1 | 148 | */ |
mbed_official | 441:d2c15dda23c1 | 149 | |
mbed_official | 441:d2c15dda23c1 | 150 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 441:d2c15dda23c1 | 151 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 441:d2c15dda23c1 | 152 | #endif |
mbed_official | 441:d2c15dda23c1 | 153 | |
mbed_official | 441:d2c15dda23c1 | 154 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 441:d2c15dda23c1 | 155 | |
mbed_official | 441:d2c15dda23c1 | 156 | /** |
mbed_official | 441:d2c15dda23c1 | 157 | * @} |
mbed_official | 441:d2c15dda23c1 | 158 | */ |
mbed_official | 441:d2c15dda23c1 | 159 | |
mbed_official | 441:d2c15dda23c1 | 160 | /** @addtogroup STM32F0xx_System_Private_Functions |
mbed_official | 441:d2c15dda23c1 | 161 | * @{ |
mbed_official | 441:d2c15dda23c1 | 162 | */ |
mbed_official | 441:d2c15dda23c1 | 163 | |
mbed_official | 441:d2c15dda23c1 | 164 | extern int NVIC_vtor_remap; |
mbed_official | 441:d2c15dda23c1 | 165 | |
mbed_official | 441:d2c15dda23c1 | 166 | /** |
mbed_official | 441:d2c15dda23c1 | 167 | * @brief Setup the microcontroller system. |
mbed_official | 441:d2c15dda23c1 | 168 | * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. |
mbed_official | 441:d2c15dda23c1 | 169 | * @param None |
mbed_official | 441:d2c15dda23c1 | 170 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 171 | */ |
mbed_official | 441:d2c15dda23c1 | 172 | void SystemInit(void) |
mbed_official | 441:d2c15dda23c1 | 173 | { |
mbed_official | 441:d2c15dda23c1 | 174 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
mbed_official | 441:d2c15dda23c1 | 175 | /* Set HSION bit */ |
mbed_official | 441:d2c15dda23c1 | 176 | RCC->CR |= (uint32_t)0x00000001; |
mbed_official | 441:d2c15dda23c1 | 177 | |
mbed_official | 441:d2c15dda23c1 | 178 | #if defined (STM32F051x8) || defined (STM32F058x8) |
mbed_official | 441:d2c15dda23c1 | 179 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
mbed_official | 441:d2c15dda23c1 | 180 | RCC->CFGR &= (uint32_t)0xF8FFB80C; |
mbed_official | 441:d2c15dda23c1 | 181 | #else |
mbed_official | 441:d2c15dda23c1 | 182 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ |
mbed_official | 441:d2c15dda23c1 | 183 | RCC->CFGR &= (uint32_t)0x08FFB80C; |
mbed_official | 441:d2c15dda23c1 | 184 | #endif /* STM32F051x8 or STM32F058x8 */ |
mbed_official | 441:d2c15dda23c1 | 185 | |
mbed_official | 441:d2c15dda23c1 | 186 | /* Reset HSEON, CSSON and PLLON bits */ |
mbed_official | 441:d2c15dda23c1 | 187 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
mbed_official | 441:d2c15dda23c1 | 188 | |
mbed_official | 441:d2c15dda23c1 | 189 | /* Reset HSEBYP bit */ |
mbed_official | 441:d2c15dda23c1 | 190 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 441:d2c15dda23c1 | 191 | |
mbed_official | 441:d2c15dda23c1 | 192 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
mbed_official | 441:d2c15dda23c1 | 193 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; |
mbed_official | 441:d2c15dda23c1 | 194 | |
mbed_official | 441:d2c15dda23c1 | 195 | /* Reset PREDIV[3:0] bits */ |
mbed_official | 441:d2c15dda23c1 | 196 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
mbed_official | 441:d2c15dda23c1 | 197 | |
mbed_official | 441:d2c15dda23c1 | 198 | #if defined (STM32F072xB) || defined (STM32F078xB) |
mbed_official | 441:d2c15dda23c1 | 199 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 200 | RCC->CFGR3 &= (uint32_t)0xFFFCFE2C; |
mbed_official | 441:d2c15dda23c1 | 201 | #elif defined (STM32F071xB) |
mbed_official | 441:d2c15dda23c1 | 202 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 203 | RCC->CFGR3 &= (uint32_t)0xFFFFCEAC; |
mbed_official | 441:d2c15dda23c1 | 204 | #elif defined (STM32F091xC) || defined (STM32F098xx) |
mbed_official | 441:d2c15dda23c1 | 205 | /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 206 | RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; |
mbed_official | 441:d2c15dda23c1 | 207 | #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) |
mbed_official | 441:d2c15dda23c1 | 208 | /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 209 | RCC->CFGR3 &= (uint32_t)0xFFFFFEEC; |
mbed_official | 441:d2c15dda23c1 | 210 | #elif defined (STM32F051x8) || defined (STM32F058xx) |
mbed_official | 441:d2c15dda23c1 | 211 | /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 212 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; |
mbed_official | 441:d2c15dda23c1 | 213 | #elif defined (STM32F042x6) || defined (STM32F048xx) |
mbed_official | 441:d2c15dda23c1 | 214 | /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 215 | RCC->CFGR3 &= (uint32_t)0xFFFFFE2C; |
mbed_official | 441:d2c15dda23c1 | 216 | #elif defined (STM32F070x6) || defined (STM32F070xB) |
mbed_official | 441:d2c15dda23c1 | 217 | /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ |
mbed_official | 441:d2c15dda23c1 | 218 | RCC->CFGR3 &= (uint32_t)0xFFFFFE6C; |
mbed_official | 441:d2c15dda23c1 | 219 | /* Set default USB clock to PLLCLK, since there is no HSI48 */ |
mbed_official | 441:d2c15dda23c1 | 220 | RCC->CFGR3 |= (uint32_t)0x00000080; |
mbed_official | 441:d2c15dda23c1 | 221 | #else |
mbed_official | 441:d2c15dda23c1 | 222 | #warning "No target selected" |
mbed_official | 441:d2c15dda23c1 | 223 | #endif |
mbed_official | 441:d2c15dda23c1 | 224 | |
mbed_official | 441:d2c15dda23c1 | 225 | /* Reset HSI14 bit */ |
mbed_official | 441:d2c15dda23c1 | 226 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; |
mbed_official | 441:d2c15dda23c1 | 227 | |
mbed_official | 441:d2c15dda23c1 | 228 | /* Disable all interrupts */ |
mbed_official | 441:d2c15dda23c1 | 229 | RCC->CIR = 0x00000000; |
mbed_official | 441:d2c15dda23c1 | 230 | |
mbed_official | 441:d2c15dda23c1 | 231 | /* Configure the Cube driver */ |
mbed_official | 441:d2c15dda23c1 | 232 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
mbed_official | 441:d2c15dda23c1 | 233 | NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector() |
mbed_official | 441:d2c15dda23c1 | 234 | HAL_Init(); |
mbed_official | 441:d2c15dda23c1 | 235 | |
mbed_official | 441:d2c15dda23c1 | 236 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 441:d2c15dda23c1 | 237 | AHB/APBx prescalers and Flash settings */ |
mbed_official | 441:d2c15dda23c1 | 238 | SetSysClock(); |
mbed_official | 441:d2c15dda23c1 | 239 | |
mbed_official | 441:d2c15dda23c1 | 240 | /* Reset the timer to avoid issues after the RAM initialization */ |
mbed_official | 441:d2c15dda23c1 | 241 | TIM_MST_RESET_ON; |
mbed_official | 441:d2c15dda23c1 | 242 | TIM_MST_RESET_OFF; |
mbed_official | 441:d2c15dda23c1 | 243 | } |
mbed_official | 441:d2c15dda23c1 | 244 | |
mbed_official | 441:d2c15dda23c1 | 245 | /** |
mbed_official | 441:d2c15dda23c1 | 246 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
mbed_official | 441:d2c15dda23c1 | 247 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 441:d2c15dda23c1 | 248 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 441:d2c15dda23c1 | 249 | * other parameters. |
mbed_official | 441:d2c15dda23c1 | 250 | * |
mbed_official | 441:d2c15dda23c1 | 251 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 441:d2c15dda23c1 | 252 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 441:d2c15dda23c1 | 253 | * based on this variable will be incorrect. |
mbed_official | 441:d2c15dda23c1 | 254 | * |
mbed_official | 441:d2c15dda23c1 | 255 | * @note - The system frequency computed by this function is not the real |
mbed_official | 441:d2c15dda23c1 | 256 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 441:d2c15dda23c1 | 257 | * constant and the selected clock source: |
mbed_official | 441:d2c15dda23c1 | 258 | * |
mbed_official | 441:d2c15dda23c1 | 259 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 441:d2c15dda23c1 | 260 | * |
mbed_official | 441:d2c15dda23c1 | 261 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 441:d2c15dda23c1 | 262 | * |
mbed_official | 441:d2c15dda23c1 | 263 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 441:d2c15dda23c1 | 264 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 441:d2c15dda23c1 | 265 | * |
mbed_official | 441:d2c15dda23c1 | 266 | * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
mbed_official | 441:d2c15dda23c1 | 267 | * 8 MHz) but the real value may vary depending on the variations |
mbed_official | 441:d2c15dda23c1 | 268 | * in voltage and temperature. |
mbed_official | 441:d2c15dda23c1 | 269 | * |
mbed_official | 441:d2c15dda23c1 | 270 | * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
mbed_official | 441:d2c15dda23c1 | 271 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 441:d2c15dda23c1 | 272 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 441:d2c15dda23c1 | 273 | * have wrong result. |
mbed_official | 441:d2c15dda23c1 | 274 | * |
mbed_official | 441:d2c15dda23c1 | 275 | * - The result of this function could be not correct when using fractional |
mbed_official | 441:d2c15dda23c1 | 276 | * value for HSE crystal. |
mbed_official | 441:d2c15dda23c1 | 277 | * |
mbed_official | 441:d2c15dda23c1 | 278 | * @param None |
mbed_official | 441:d2c15dda23c1 | 279 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 280 | */ |
mbed_official | 441:d2c15dda23c1 | 281 | void SystemCoreClockUpdate (void) |
mbed_official | 441:d2c15dda23c1 | 282 | { |
mbed_official | 441:d2c15dda23c1 | 283 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; |
mbed_official | 441:d2c15dda23c1 | 284 | |
mbed_official | 441:d2c15dda23c1 | 285 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 441:d2c15dda23c1 | 286 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 441:d2c15dda23c1 | 287 | |
mbed_official | 441:d2c15dda23c1 | 288 | switch (tmp) |
mbed_official | 441:d2c15dda23c1 | 289 | { |
mbed_official | 441:d2c15dda23c1 | 290 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
mbed_official | 441:d2c15dda23c1 | 291 | SystemCoreClock = HSI_VALUE; |
mbed_official | 441:d2c15dda23c1 | 292 | break; |
mbed_official | 441:d2c15dda23c1 | 293 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
mbed_official | 441:d2c15dda23c1 | 294 | SystemCoreClock = HSE_VALUE; |
mbed_official | 441:d2c15dda23c1 | 295 | break; |
mbed_official | 441:d2c15dda23c1 | 296 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
mbed_official | 441:d2c15dda23c1 | 297 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 441:d2c15dda23c1 | 298 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
mbed_official | 441:d2c15dda23c1 | 299 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 441:d2c15dda23c1 | 300 | pllmull = ( pllmull >> 18) + 2; |
mbed_official | 441:d2c15dda23c1 | 301 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
mbed_official | 441:d2c15dda23c1 | 302 | |
mbed_official | 441:d2c15dda23c1 | 303 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
mbed_official | 441:d2c15dda23c1 | 304 | { |
mbed_official | 441:d2c15dda23c1 | 305 | /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ |
mbed_official | 441:d2c15dda23c1 | 306 | SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; |
mbed_official | 441:d2c15dda23c1 | 307 | } |
mbed_official | 441:d2c15dda23c1 | 308 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 441:d2c15dda23c1 | 309 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) |
mbed_official | 441:d2c15dda23c1 | 310 | { |
mbed_official | 441:d2c15dda23c1 | 311 | /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ |
mbed_official | 441:d2c15dda23c1 | 312 | SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; |
mbed_official | 441:d2c15dda23c1 | 313 | } |
mbed_official | 441:d2c15dda23c1 | 314 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ |
mbed_official | 441:d2c15dda23c1 | 315 | else |
mbed_official | 441:d2c15dda23c1 | 316 | { |
mbed_official | 441:d2c15dda23c1 | 317 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \ |
mbed_official | 441:d2c15dda23c1 | 318 | defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \ |
mbed_official | 441:d2c15dda23c1 | 319 | defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
mbed_official | 441:d2c15dda23c1 | 320 | /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ |
mbed_official | 441:d2c15dda23c1 | 321 | SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; |
mbed_official | 441:d2c15dda23c1 | 322 | #else |
mbed_official | 441:d2c15dda23c1 | 323 | /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ |
mbed_official | 441:d2c15dda23c1 | 324 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
mbed_official | 441:d2c15dda23c1 | 325 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || |
mbed_official | 441:d2c15dda23c1 | 326 | STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || |
mbed_official | 441:d2c15dda23c1 | 327 | STM32F091xC || STM32F098xx || STM32F030xC */ |
mbed_official | 441:d2c15dda23c1 | 328 | } |
mbed_official | 441:d2c15dda23c1 | 329 | break; |
mbed_official | 441:d2c15dda23c1 | 330 | default: /* HSI used as system clock */ |
mbed_official | 441:d2c15dda23c1 | 331 | SystemCoreClock = HSI_VALUE; |
mbed_official | 441:d2c15dda23c1 | 332 | break; |
mbed_official | 441:d2c15dda23c1 | 333 | } |
mbed_official | 441:d2c15dda23c1 | 334 | /* Compute HCLK clock frequency ----------------*/ |
mbed_official | 441:d2c15dda23c1 | 335 | /* Get HCLK prescaler */ |
mbed_official | 441:d2c15dda23c1 | 336 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 441:d2c15dda23c1 | 337 | /* HCLK clock frequency */ |
mbed_official | 441:d2c15dda23c1 | 338 | SystemCoreClock >>= tmp; |
mbed_official | 441:d2c15dda23c1 | 339 | } |
mbed_official | 441:d2c15dda23c1 | 340 | |
mbed_official | 441:d2c15dda23c1 | 341 | /** |
mbed_official | 441:d2c15dda23c1 | 342 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 441:d2c15dda23c1 | 343 | * AHB/APBx prescalers and Flash settings |
mbed_official | 441:d2c15dda23c1 | 344 | * @note This function should be called only once the RCC clock configuration |
mbed_official | 441:d2c15dda23c1 | 345 | * is reset to the default reset state (done in SystemInit() function). |
mbed_official | 441:d2c15dda23c1 | 346 | * @param None |
mbed_official | 441:d2c15dda23c1 | 347 | * @retval None |
mbed_official | 441:d2c15dda23c1 | 348 | */ |
mbed_official | 441:d2c15dda23c1 | 349 | void SetSysClock(void) |
mbed_official | 441:d2c15dda23c1 | 350 | { |
mbed_official | 441:d2c15dda23c1 | 351 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 441:d2c15dda23c1 | 352 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 441:d2c15dda23c1 | 353 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 441:d2c15dda23c1 | 354 | #endif |
mbed_official | 441:d2c15dda23c1 | 355 | { |
mbed_official | 441:d2c15dda23c1 | 356 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 441:d2c15dda23c1 | 357 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 441:d2c15dda23c1 | 358 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 441:d2c15dda23c1 | 359 | #endif |
mbed_official | 441:d2c15dda23c1 | 360 | { |
mbed_official | 441:d2c15dda23c1 | 361 | /* 3- If fail start with HSI clock */ |
mbed_official | 441:d2c15dda23c1 | 362 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 441:d2c15dda23c1 | 363 | { |
mbed_official | 441:d2c15dda23c1 | 364 | while(1) |
mbed_official | 441:d2c15dda23c1 | 365 | { |
mbed_official | 441:d2c15dda23c1 | 366 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 441:d2c15dda23c1 | 367 | } |
mbed_official | 441:d2c15dda23c1 | 368 | } |
mbed_official | 441:d2c15dda23c1 | 369 | } |
mbed_official | 441:d2c15dda23c1 | 370 | } |
mbed_official | 441:d2c15dda23c1 | 371 | |
mbed_official | 441:d2c15dda23c1 | 372 | // Output clock on MCO pin(PA8) for debugging purpose |
mbed_official | 441:d2c15dda23c1 | 373 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 374 | } |
mbed_official | 441:d2c15dda23c1 | 375 | |
mbed_official | 441:d2c15dda23c1 | 376 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 441:d2c15dda23c1 | 377 | /******************************************************************************/ |
mbed_official | 441:d2c15dda23c1 | 378 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 441:d2c15dda23c1 | 379 | /******************************************************************************/ |
mbed_official | 441:d2c15dda23c1 | 380 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 441:d2c15dda23c1 | 381 | { |
mbed_official | 441:d2c15dda23c1 | 382 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 441:d2c15dda23c1 | 383 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 441:d2c15dda23c1 | 384 | |
mbed_official | 441:d2c15dda23c1 | 385 | // Select HSE oscillator as PLL source |
mbed_official | 441:d2c15dda23c1 | 386 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; |
mbed_official | 441:d2c15dda23c1 | 387 | if (bypass == 0) { |
mbed_official | 441:d2c15dda23c1 | 388 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
mbed_official | 441:d2c15dda23c1 | 389 | } else { |
mbed_official | 441:d2c15dda23c1 | 390 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only |
mbed_official | 441:d2c15dda23c1 | 391 | } |
mbed_official | 441:d2c15dda23c1 | 392 | RCC_OscInitStruct.HSI48State = 0; // not used |
mbed_official | 441:d2c15dda23c1 | 393 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 441:d2c15dda23c1 | 394 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
mbed_official | 441:d2c15dda23c1 | 395 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; |
mbed_official | 441:d2c15dda23c1 | 396 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
mbed_official | 441:d2c15dda23c1 | 397 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
mbed_official | 441:d2c15dda23c1 | 398 | return 0; // FAIL |
mbed_official | 441:d2c15dda23c1 | 399 | } |
mbed_official | 441:d2c15dda23c1 | 400 | |
mbed_official | 441:d2c15dda23c1 | 401 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
mbed_official | 441:d2c15dda23c1 | 402 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
mbed_official | 441:d2c15dda23c1 | 403 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 404 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 405 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 406 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
mbed_official | 441:d2c15dda23c1 | 407 | return 0; // FAIL |
mbed_official | 441:d2c15dda23c1 | 408 | } |
mbed_official | 441:d2c15dda23c1 | 409 | |
mbed_official | 441:d2c15dda23c1 | 410 | // Output clock on MCO pin(PA8) for debugging purpose |
mbed_official | 441:d2c15dda23c1 | 411 | //if (bypass == 0) |
mbed_official | 441:d2c15dda23c1 | 412 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal |
mbed_official | 441:d2c15dda23c1 | 413 | //else |
mbed_official | 441:d2c15dda23c1 | 414 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO |
mbed_official | 441:d2c15dda23c1 | 415 | |
mbed_official | 441:d2c15dda23c1 | 416 | return 1; // OK |
mbed_official | 441:d2c15dda23c1 | 417 | } |
mbed_official | 441:d2c15dda23c1 | 418 | #endif |
mbed_official | 441:d2c15dda23c1 | 419 | |
mbed_official | 441:d2c15dda23c1 | 420 | /******************************************************************************/ |
mbed_official | 441:d2c15dda23c1 | 421 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 441:d2c15dda23c1 | 422 | /******************************************************************************/ |
mbed_official | 441:d2c15dda23c1 | 423 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 441:d2c15dda23c1 | 424 | { |
mbed_official | 441:d2c15dda23c1 | 425 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 441:d2c15dda23c1 | 426 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 441:d2c15dda23c1 | 427 | |
mbed_official | 441:d2c15dda23c1 | 428 | // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) |
mbed_official | 441:d2c15dda23c1 | 429 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
mbed_official | 441:d2c15dda23c1 | 430 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
mbed_official | 441:d2c15dda23c1 | 431 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 441:d2c15dda23c1 | 432 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 |
mbed_official | 441:d2c15dda23c1 | 433 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
mbed_official | 441:d2c15dda23c1 | 434 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
mbed_official | 441:d2c15dda23c1 | 435 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
mbed_official | 441:d2c15dda23c1 | 436 | return 0; // FAIL |
mbed_official | 441:d2c15dda23c1 | 437 | } |
mbed_official | 441:d2c15dda23c1 | 438 | |
mbed_official | 441:d2c15dda23c1 | 439 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
mbed_official | 441:d2c15dda23c1 | 440 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
mbed_official | 441:d2c15dda23c1 | 441 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 442 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 443 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 444 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
mbed_official | 441:d2c15dda23c1 | 445 | return 0; // FAIL |
mbed_official | 441:d2c15dda23c1 | 446 | } |
mbed_official | 441:d2c15dda23c1 | 447 | |
mbed_official | 441:d2c15dda23c1 | 448 | // Output clock on MCO1 pin(PA8) for debugging purpose |
mbed_official | 441:d2c15dda23c1 | 449 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz |
mbed_official | 441:d2c15dda23c1 | 450 | |
mbed_official | 441:d2c15dda23c1 | 451 | return 1; // OK |
mbed_official | 441:d2c15dda23c1 | 452 | } |
mbed_official | 441:d2c15dda23c1 | 453 | |
mbed_official | 441:d2c15dda23c1 | 454 | /** |
mbed_official | 441:d2c15dda23c1 | 455 | * @} |
mbed_official | 441:d2c15dda23c1 | 456 | */ |
mbed_official | 441:d2c15dda23c1 | 457 | |
mbed_official | 441:d2c15dda23c1 | 458 | /** |
mbed_official | 441:d2c15dda23c1 | 459 | * @} |
mbed_official | 441:d2c15dda23c1 | 460 | */ |
mbed_official | 441:d2c15dda23c1 | 461 | |
mbed_official | 441:d2c15dda23c1 | 462 | /** |
mbed_official | 441:d2c15dda23c1 | 463 | * @} |
mbed_official | 441:d2c15dda23c1 | 464 | */ |
mbed_official | 441:d2c15dda23c1 | 465 | |
mbed_official | 441:d2c15dda23c1 | 466 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
mbed_official | 441:d2c15dda23c1 | 467 |