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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc_ex.c@340:28d1f895c6fe, 2014-10-09 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Oct 09 08:15:07 2014 +0100
- Revision:
- 340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602
Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/
HAL: nrf51822 - Few fixes for PWM and Serial
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 340:28d1f895c6fe | 1 | /** |
mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_rcc_ex.c |
mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
mbed_official | 340:28d1f895c6fe | 5 | * @version V1.1.0 |
mbed_official | 340:28d1f895c6fe | 6 | * @date 03-Oct-2014 |
mbed_official | 340:28d1f895c6fe | 7 | * @brief Extended RCC HAL module driver |
mbed_official | 340:28d1f895c6fe | 8 | * This file provides firmware functions to manage the following |
mbed_official | 340:28d1f895c6fe | 9 | * functionalities RCC extension peripheral: |
mbed_official | 340:28d1f895c6fe | 10 | * + Extended Clock Source configuration functions |
mbed_official | 340:28d1f895c6fe | 11 | * |
mbed_official | 340:28d1f895c6fe | 12 | @verbatim |
mbed_official | 340:28d1f895c6fe | 13 | ============================================================================== |
mbed_official | 340:28d1f895c6fe | 14 | ##### How to use this driver ##### |
mbed_official | 340:28d1f895c6fe | 15 | ============================================================================== |
mbed_official | 340:28d1f895c6fe | 16 | |
mbed_official | 340:28d1f895c6fe | 17 | For CRS, RCC Extention HAL driver can be used as follows: |
mbed_official | 340:28d1f895c6fe | 18 | |
mbed_official | 340:28d1f895c6fe | 19 | (#) In System clock config, HSI48 need to be enabled |
mbed_official | 340:28d1f895c6fe | 20 | |
mbed_official | 340:28d1f895c6fe | 21 | (#] Enable CRS clock in IP MSP init which will use CRS functions |
mbed_official | 340:28d1f895c6fe | 22 | |
mbed_official | 340:28d1f895c6fe | 23 | (#) Call CRS functions like this |
mbed_official | 340:28d1f895c6fe | 24 | (##) Prepare synchronization configuration necessary for HSI48 calibration |
mbed_official | 340:28d1f895c6fe | 25 | (+++) Default values can be set for frequency Error Measurement (reload and error limit) |
mbed_official | 340:28d1f895c6fe | 26 | and also HSI48 oscillator smooth trimming. |
mbed_official | 340:28d1f895c6fe | 27 | (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate |
mbed_official | 340:28d1f895c6fe | 28 | directly reload value with target and sychronization frequencies values |
mbed_official | 340:28d1f895c6fe | 29 | (##) Call function HAL_RCCEx_CRSConfig which |
mbed_official | 340:28d1f895c6fe | 30 | (+++) Reset CRS registers to their default values. |
mbed_official | 340:28d1f895c6fe | 31 | (+++) Configure CRS registers with synchronization configuration |
mbed_official | 340:28d1f895c6fe | 32 | (+++) Enable automatic calibration and frequency error counter feature |
mbed_official | 340:28d1f895c6fe | 33 | |
mbed_official | 340:28d1f895c6fe | 34 | (##) A polling function is provided to wait for complete Synchronization |
mbed_official | 340:28d1f895c6fe | 35 | (+++) Call function HAL_RCCEx_CRSWaitSynchronization() |
mbed_official | 340:28d1f895c6fe | 36 | (+++) According to CRS status, user can decide to adjust again the calibration or continue |
mbed_official | 340:28d1f895c6fe | 37 | application if synchronization is OK |
mbed_official | 340:28d1f895c6fe | 38 | |
mbed_official | 340:28d1f895c6fe | 39 | (#) User can retrieve information related to synchronization in calling function |
mbed_official | 340:28d1f895c6fe | 40 | HAL_RCCEx_CRSGetSynchronizationInfo() |
mbed_official | 340:28d1f895c6fe | 41 | |
mbed_official | 340:28d1f895c6fe | 42 | (#) Regarding synchronization status and synchronization information, user can try a new calibration |
mbed_official | 340:28d1f895c6fe | 43 | in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. |
mbed_official | 340:28d1f895c6fe | 44 | Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), |
mbed_official | 340:28d1f895c6fe | 45 | it means that the actual frequency is lower than the target (and so, that the TRIM value should be |
mbed_official | 340:28d1f895c6fe | 46 | incremented), while when it is detected during the upcounting phase it means that the actual frequency |
mbed_official | 340:28d1f895c6fe | 47 | is higher (and that the TRIM value should be decremented). |
mbed_official | 340:28d1f895c6fe | 48 | |
mbed_official | 340:28d1f895c6fe | 49 | (#) To use IT mode, user needs to handle it in calling different macros available to do it |
mbed_official | 340:28d1f895c6fe | 50 | (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler) |
mbed_official | 340:28d1f895c6fe | 51 | (++) Call function HAL_RCCEx_CRSConfig() |
mbed_official | 340:28d1f895c6fe | 52 | (++) Enable RCC_IRQn (thnaks to NVIC functions) |
mbed_official | 340:28d1f895c6fe | 53 | (++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT) |
mbed_official | 340:28d1f895c6fe | 54 | (++) Implement CRS status management in RCC_CRS_IRQHandler |
mbed_official | 340:28d1f895c6fe | 55 | |
mbed_official | 340:28d1f895c6fe | 56 | (#) To force a SYNC EVENT, user can use function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be |
mbed_official | 340:28d1f895c6fe | 57 | called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) |
mbed_official | 340:28d1f895c6fe | 58 | |
mbed_official | 340:28d1f895c6fe | 59 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 60 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 61 | * @attention |
mbed_official | 340:28d1f895c6fe | 62 | * |
mbed_official | 340:28d1f895c6fe | 63 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 340:28d1f895c6fe | 64 | * |
mbed_official | 340:28d1f895c6fe | 65 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 340:28d1f895c6fe | 66 | * are permitted provided that the following conditions are met: |
mbed_official | 340:28d1f895c6fe | 67 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 68 | * this list of conditions and the following disclaimer. |
mbed_official | 340:28d1f895c6fe | 69 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 70 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 340:28d1f895c6fe | 71 | * and/or other materials provided with the distribution. |
mbed_official | 340:28d1f895c6fe | 72 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 340:28d1f895c6fe | 73 | * may be used to endorse or promote products derived from this software |
mbed_official | 340:28d1f895c6fe | 74 | * without specific prior written permission. |
mbed_official | 340:28d1f895c6fe | 75 | * |
mbed_official | 340:28d1f895c6fe | 76 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 340:28d1f895c6fe | 77 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 340:28d1f895c6fe | 78 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 340:28d1f895c6fe | 79 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 340:28d1f895c6fe | 80 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 340:28d1f895c6fe | 81 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 340:28d1f895c6fe | 82 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 340:28d1f895c6fe | 83 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 340:28d1f895c6fe | 84 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 340:28d1f895c6fe | 85 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 340:28d1f895c6fe | 86 | * |
mbed_official | 340:28d1f895c6fe | 87 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 88 | */ |
mbed_official | 340:28d1f895c6fe | 89 | |
mbed_official | 340:28d1f895c6fe | 90 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 91 | #include "stm32f0xx_hal.h" |
mbed_official | 340:28d1f895c6fe | 92 | |
mbed_official | 340:28d1f895c6fe | 93 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 340:28d1f895c6fe | 94 | * @{ |
mbed_official | 340:28d1f895c6fe | 95 | */ |
mbed_official | 340:28d1f895c6fe | 96 | |
mbed_official | 340:28d1f895c6fe | 97 | /** @defgroup RCCEx RCCEx Extended HAL module driver |
mbed_official | 340:28d1f895c6fe | 98 | * @brief RCC Extension HAL module driver. |
mbed_official | 340:28d1f895c6fe | 99 | * @{ |
mbed_official | 340:28d1f895c6fe | 100 | */ |
mbed_official | 340:28d1f895c6fe | 101 | |
mbed_official | 340:28d1f895c6fe | 102 | #ifdef HAL_RCC_MODULE_ENABLED |
mbed_official | 340:28d1f895c6fe | 103 | |
mbed_official | 340:28d1f895c6fe | 104 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 105 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 106 | /** @defgroup RCCEx_Private_Define RCCEx Private Define |
mbed_official | 340:28d1f895c6fe | 107 | * @{ |
mbed_official | 340:28d1f895c6fe | 108 | */ |
mbed_official | 340:28d1f895c6fe | 109 | #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 340:28d1f895c6fe | 110 | |
mbed_official | 340:28d1f895c6fe | 111 | /* Bit position in register */ |
mbed_official | 340:28d1f895c6fe | 112 | #define CRS_CFGR_FELIM_BITNUMBER 16 |
mbed_official | 340:28d1f895c6fe | 113 | #define CRS_CR_TRIM_BITNUMBER 8 |
mbed_official | 340:28d1f895c6fe | 114 | #define CRS_ISR_FECAP_BITNUMBER 16 |
mbed_official | 340:28d1f895c6fe | 115 | /** |
mbed_official | 340:28d1f895c6fe | 116 | * @} |
mbed_official | 340:28d1f895c6fe | 117 | */ |
mbed_official | 340:28d1f895c6fe | 118 | |
mbed_official | 340:28d1f895c6fe | 119 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 120 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 121 | /** @defgroup RCCEx_Private_Variables RCCEx Private Variables |
mbed_official | 340:28d1f895c6fe | 122 | * @{ |
mbed_official | 340:28d1f895c6fe | 123 | */ |
mbed_official | 340:28d1f895c6fe | 124 | const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, |
mbed_official | 340:28d1f895c6fe | 125 | 10, 11, 12, 13, 14, 15, 16, 16}; |
mbed_official | 340:28d1f895c6fe | 126 | const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, |
mbed_official | 340:28d1f895c6fe | 127 | 9,10, 11, 12, 13, 14, 15, 16}; |
mbed_official | 340:28d1f895c6fe | 128 | /** |
mbed_official | 340:28d1f895c6fe | 129 | * @} |
mbed_official | 340:28d1f895c6fe | 130 | */ |
mbed_official | 340:28d1f895c6fe | 131 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 132 | /* Exported functions ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 133 | |
mbed_official | 340:28d1f895c6fe | 134 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
mbed_official | 340:28d1f895c6fe | 135 | * @{ |
mbed_official | 340:28d1f895c6fe | 136 | */ |
mbed_official | 340:28d1f895c6fe | 137 | |
mbed_official | 340:28d1f895c6fe | 138 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
mbed_official | 340:28d1f895c6fe | 139 | * @brief Extended RCC clocks control functions |
mbed_official | 340:28d1f895c6fe | 140 | * |
mbed_official | 340:28d1f895c6fe | 141 | @verbatim |
mbed_official | 340:28d1f895c6fe | 142 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 143 | ##### Extended Peripheral Control functions ##### |
mbed_official | 340:28d1f895c6fe | 144 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 145 | [..] |
mbed_official | 340:28d1f895c6fe | 146 | This subsection provides a set of functions allowing to control the RCC Clocks |
mbed_official | 340:28d1f895c6fe | 147 | frequencies. |
mbed_official | 340:28d1f895c6fe | 148 | [..] |
mbed_official | 340:28d1f895c6fe | 149 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
mbed_official | 340:28d1f895c6fe | 150 | select the RTC clock source; in this case the Backup domain will be reset in |
mbed_official | 340:28d1f895c6fe | 151 | order to modify the RTC Clock source, as consequence RTC registers (including |
mbed_official | 340:28d1f895c6fe | 152 | the backup registers) and RCC_BDCR register are set to their reset values. |
mbed_official | 340:28d1f895c6fe | 153 | |
mbed_official | 340:28d1f895c6fe | 154 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 155 | * @{ |
mbed_official | 340:28d1f895c6fe | 156 | */ |
mbed_official | 340:28d1f895c6fe | 157 | |
mbed_official | 340:28d1f895c6fe | 158 | /** |
mbed_official | 340:28d1f895c6fe | 159 | * @brief Initializes the RCC Oscillators according to the specified parameters in the |
mbed_official | 340:28d1f895c6fe | 160 | * RCC_OscInitTypeDef. |
mbed_official | 340:28d1f895c6fe | 161 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 340:28d1f895c6fe | 162 | * contains the configuration information for the RCC Oscillators. |
mbed_official | 340:28d1f895c6fe | 163 | * @note The PLL is not disabled when used as system clock. |
mbed_official | 340:28d1f895c6fe | 164 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 165 | */ |
mbed_official | 340:28d1f895c6fe | 166 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
mbed_official | 340:28d1f895c6fe | 167 | { |
mbed_official | 340:28d1f895c6fe | 168 | uint32_t tickstart = 0; |
mbed_official | 340:28d1f895c6fe | 169 | |
mbed_official | 340:28d1f895c6fe | 170 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 171 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); |
mbed_official | 340:28d1f895c6fe | 172 | /*------------------------------- HSE Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 173 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) |
mbed_official | 340:28d1f895c6fe | 174 | { |
mbed_official | 340:28d1f895c6fe | 175 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 176 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); |
mbed_official | 340:28d1f895c6fe | 177 | /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ |
mbed_official | 340:28d1f895c6fe | 178 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || |
mbed_official | 340:28d1f895c6fe | 179 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) |
mbed_official | 340:28d1f895c6fe | 180 | { |
mbed_official | 340:28d1f895c6fe | 181 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) |
mbed_official | 340:28d1f895c6fe | 182 | { |
mbed_official | 340:28d1f895c6fe | 183 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 184 | } |
mbed_official | 340:28d1f895c6fe | 185 | } |
mbed_official | 340:28d1f895c6fe | 186 | else |
mbed_official | 340:28d1f895c6fe | 187 | { |
mbed_official | 340:28d1f895c6fe | 188 | /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/ |
mbed_official | 340:28d1f895c6fe | 189 | __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF); |
mbed_official | 340:28d1f895c6fe | 190 | |
mbed_official | 340:28d1f895c6fe | 191 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 192 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 193 | |
mbed_official | 340:28d1f895c6fe | 194 | /* Wait till HSE is ready */ |
mbed_official | 340:28d1f895c6fe | 195 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 196 | { |
mbed_official | 340:28d1f895c6fe | 197 | if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 198 | { |
mbed_official | 340:28d1f895c6fe | 199 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 200 | } |
mbed_official | 340:28d1f895c6fe | 201 | } |
mbed_official | 340:28d1f895c6fe | 202 | |
mbed_official | 340:28d1f895c6fe | 203 | /* Set the new HSE configuration ---------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 204 | __HAL_RCC_HSE_CONFIG((uint8_t)RCC_OscInitStruct->HSEState); |
mbed_official | 340:28d1f895c6fe | 205 | |
mbed_official | 340:28d1f895c6fe | 206 | /* Check the HSE State */ |
mbed_official | 340:28d1f895c6fe | 207 | if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) |
mbed_official | 340:28d1f895c6fe | 208 | { |
mbed_official | 340:28d1f895c6fe | 209 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 210 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 211 | |
mbed_official | 340:28d1f895c6fe | 212 | /* Wait till HSE is ready */ |
mbed_official | 340:28d1f895c6fe | 213 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 214 | { |
mbed_official | 340:28d1f895c6fe | 215 | if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 216 | { |
mbed_official | 340:28d1f895c6fe | 217 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 218 | } |
mbed_official | 340:28d1f895c6fe | 219 | } |
mbed_official | 340:28d1f895c6fe | 220 | } |
mbed_official | 340:28d1f895c6fe | 221 | else |
mbed_official | 340:28d1f895c6fe | 222 | { |
mbed_official | 340:28d1f895c6fe | 223 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 224 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 225 | |
mbed_official | 340:28d1f895c6fe | 226 | /* Wait till HSE is ready */ |
mbed_official | 340:28d1f895c6fe | 227 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 228 | { |
mbed_official | 340:28d1f895c6fe | 229 | if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 230 | { |
mbed_official | 340:28d1f895c6fe | 231 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 232 | } |
mbed_official | 340:28d1f895c6fe | 233 | } |
mbed_official | 340:28d1f895c6fe | 234 | } |
mbed_official | 340:28d1f895c6fe | 235 | } |
mbed_official | 340:28d1f895c6fe | 236 | } |
mbed_official | 340:28d1f895c6fe | 237 | /*----------------------------- HSI Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 238 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) |
mbed_official | 340:28d1f895c6fe | 239 | { |
mbed_official | 340:28d1f895c6fe | 240 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 241 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); |
mbed_official | 340:28d1f895c6fe | 242 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); |
mbed_official | 340:28d1f895c6fe | 243 | |
mbed_official | 340:28d1f895c6fe | 244 | /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ |
mbed_official | 340:28d1f895c6fe | 245 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || |
mbed_official | 340:28d1f895c6fe | 246 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) |
mbed_official | 340:28d1f895c6fe | 247 | { |
mbed_official | 340:28d1f895c6fe | 248 | /* When the HSI is used as system clock it is not allowed to be disabled */ |
mbed_official | 340:28d1f895c6fe | 249 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) |
mbed_official | 340:28d1f895c6fe | 250 | { |
mbed_official | 340:28d1f895c6fe | 251 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 252 | } |
mbed_official | 340:28d1f895c6fe | 253 | /* Otherwise, just the calibration is allowed */ |
mbed_official | 340:28d1f895c6fe | 254 | else |
mbed_official | 340:28d1f895c6fe | 255 | { |
mbed_official | 340:28d1f895c6fe | 256 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
mbed_official | 340:28d1f895c6fe | 257 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
mbed_official | 340:28d1f895c6fe | 258 | } |
mbed_official | 340:28d1f895c6fe | 259 | } |
mbed_official | 340:28d1f895c6fe | 260 | else |
mbed_official | 340:28d1f895c6fe | 261 | { |
mbed_official | 340:28d1f895c6fe | 262 | /* Check the HSI State */ |
mbed_official | 340:28d1f895c6fe | 263 | if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) |
mbed_official | 340:28d1f895c6fe | 264 | { |
mbed_official | 340:28d1f895c6fe | 265 | /* Enable the Internal High Speed oscillator (HSI). */ |
mbed_official | 340:28d1f895c6fe | 266 | __HAL_RCC_HSI_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 267 | |
mbed_official | 340:28d1f895c6fe | 268 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 269 | |
mbed_official | 340:28d1f895c6fe | 270 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 271 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 272 | { |
mbed_official | 340:28d1f895c6fe | 273 | if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 274 | { |
mbed_official | 340:28d1f895c6fe | 275 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 276 | } |
mbed_official | 340:28d1f895c6fe | 277 | } |
mbed_official | 340:28d1f895c6fe | 278 | |
mbed_official | 340:28d1f895c6fe | 279 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ |
mbed_official | 340:28d1f895c6fe | 280 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
mbed_official | 340:28d1f895c6fe | 281 | } |
mbed_official | 340:28d1f895c6fe | 282 | else |
mbed_official | 340:28d1f895c6fe | 283 | { |
mbed_official | 340:28d1f895c6fe | 284 | /* Disable the Internal High Speed oscillator (HSI). */ |
mbed_official | 340:28d1f895c6fe | 285 | __HAL_RCC_HSI_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 286 | |
mbed_official | 340:28d1f895c6fe | 287 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 288 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 289 | |
mbed_official | 340:28d1f895c6fe | 290 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 291 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 292 | { |
mbed_official | 340:28d1f895c6fe | 293 | if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 294 | { |
mbed_official | 340:28d1f895c6fe | 295 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 296 | } |
mbed_official | 340:28d1f895c6fe | 297 | } |
mbed_official | 340:28d1f895c6fe | 298 | } |
mbed_official | 340:28d1f895c6fe | 299 | } |
mbed_official | 340:28d1f895c6fe | 300 | } |
mbed_official | 340:28d1f895c6fe | 301 | /*------------------------------ LSI Configuration -------------------------*/ |
mbed_official | 340:28d1f895c6fe | 302 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) |
mbed_official | 340:28d1f895c6fe | 303 | { |
mbed_official | 340:28d1f895c6fe | 304 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 305 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); |
mbed_official | 340:28d1f895c6fe | 306 | |
mbed_official | 340:28d1f895c6fe | 307 | /* Check the LSI State */ |
mbed_official | 340:28d1f895c6fe | 308 | if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) |
mbed_official | 340:28d1f895c6fe | 309 | { |
mbed_official | 340:28d1f895c6fe | 310 | /* Enable the Internal Low Speed oscillator (LSI). */ |
mbed_official | 340:28d1f895c6fe | 311 | __HAL_RCC_LSI_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 312 | |
mbed_official | 340:28d1f895c6fe | 313 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 314 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 315 | |
mbed_official | 340:28d1f895c6fe | 316 | /* Wait till LSI is ready */ |
mbed_official | 340:28d1f895c6fe | 317 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 318 | { |
mbed_official | 340:28d1f895c6fe | 319 | if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 320 | { |
mbed_official | 340:28d1f895c6fe | 321 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 322 | } |
mbed_official | 340:28d1f895c6fe | 323 | } |
mbed_official | 340:28d1f895c6fe | 324 | } |
mbed_official | 340:28d1f895c6fe | 325 | else |
mbed_official | 340:28d1f895c6fe | 326 | { |
mbed_official | 340:28d1f895c6fe | 327 | /* Disable the Internal Low Speed oscillator (LSI). */ |
mbed_official | 340:28d1f895c6fe | 328 | __HAL_RCC_LSI_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 329 | |
mbed_official | 340:28d1f895c6fe | 330 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 331 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 332 | |
mbed_official | 340:28d1f895c6fe | 333 | /* Wait till LSI is ready */ |
mbed_official | 340:28d1f895c6fe | 334 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 335 | { |
mbed_official | 340:28d1f895c6fe | 336 | if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 337 | { |
mbed_official | 340:28d1f895c6fe | 338 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 339 | } |
mbed_official | 340:28d1f895c6fe | 340 | } |
mbed_official | 340:28d1f895c6fe | 341 | } |
mbed_official | 340:28d1f895c6fe | 342 | } |
mbed_official | 340:28d1f895c6fe | 343 | /*------------------------------ LSE Configuration -------------------------*/ |
mbed_official | 340:28d1f895c6fe | 344 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) |
mbed_official | 340:28d1f895c6fe | 345 | { |
mbed_official | 340:28d1f895c6fe | 346 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 347 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); |
mbed_official | 340:28d1f895c6fe | 348 | |
mbed_official | 340:28d1f895c6fe | 349 | /* Enable Power Clock */ |
mbed_official | 340:28d1f895c6fe | 350 | __PWR_CLK_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 351 | |
mbed_official | 340:28d1f895c6fe | 352 | /* Enable write access to Backup domain */ |
mbed_official | 340:28d1f895c6fe | 353 | SET_BIT(PWR->CR, PWR_CR_DBP); |
mbed_official | 340:28d1f895c6fe | 354 | |
mbed_official | 340:28d1f895c6fe | 355 | /* Wait for Backup domain Write protection disable */ |
mbed_official | 340:28d1f895c6fe | 356 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 357 | |
mbed_official | 340:28d1f895c6fe | 358 | while((PWR->CR & PWR_CR_DBP) == RESET) |
mbed_official | 340:28d1f895c6fe | 359 | { |
mbed_official | 340:28d1f895c6fe | 360 | if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 361 | { |
mbed_official | 340:28d1f895c6fe | 362 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 363 | } |
mbed_official | 340:28d1f895c6fe | 364 | } |
mbed_official | 340:28d1f895c6fe | 365 | |
mbed_official | 340:28d1f895c6fe | 366 | /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/ |
mbed_official | 340:28d1f895c6fe | 367 | __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF); |
mbed_official | 340:28d1f895c6fe | 368 | |
mbed_official | 340:28d1f895c6fe | 369 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 370 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 371 | |
mbed_official | 340:28d1f895c6fe | 372 | /* Wait till LSE is ready */ |
mbed_official | 340:28d1f895c6fe | 373 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 374 | { |
mbed_official | 340:28d1f895c6fe | 375 | if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 376 | { |
mbed_official | 340:28d1f895c6fe | 377 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 378 | } |
mbed_official | 340:28d1f895c6fe | 379 | } |
mbed_official | 340:28d1f895c6fe | 380 | |
mbed_official | 340:28d1f895c6fe | 381 | /* Set the new LSE configuration -----------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 382 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); |
mbed_official | 340:28d1f895c6fe | 383 | /* Check the LSE State */ |
mbed_official | 340:28d1f895c6fe | 384 | if(RCC_OscInitStruct->LSEState == RCC_LSE_ON) |
mbed_official | 340:28d1f895c6fe | 385 | { |
mbed_official | 340:28d1f895c6fe | 386 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 387 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 388 | |
mbed_official | 340:28d1f895c6fe | 389 | /* Wait till LSE is ready */ |
mbed_official | 340:28d1f895c6fe | 390 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 391 | { |
mbed_official | 340:28d1f895c6fe | 392 | if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 393 | { |
mbed_official | 340:28d1f895c6fe | 394 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 395 | } |
mbed_official | 340:28d1f895c6fe | 396 | } |
mbed_official | 340:28d1f895c6fe | 397 | } |
mbed_official | 340:28d1f895c6fe | 398 | else |
mbed_official | 340:28d1f895c6fe | 399 | { |
mbed_official | 340:28d1f895c6fe | 400 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 401 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 402 | |
mbed_official | 340:28d1f895c6fe | 403 | /* Wait till LSE is ready */ |
mbed_official | 340:28d1f895c6fe | 404 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 405 | { |
mbed_official | 340:28d1f895c6fe | 406 | if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 407 | { |
mbed_official | 340:28d1f895c6fe | 408 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 409 | } |
mbed_official | 340:28d1f895c6fe | 410 | } |
mbed_official | 340:28d1f895c6fe | 411 | } |
mbed_official | 340:28d1f895c6fe | 412 | } |
mbed_official | 340:28d1f895c6fe | 413 | |
mbed_official | 340:28d1f895c6fe | 414 | /*----------------------------- HSI14 Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 415 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) |
mbed_official | 340:28d1f895c6fe | 416 | { |
mbed_official | 340:28d1f895c6fe | 417 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 418 | assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State)); |
mbed_official | 340:28d1f895c6fe | 419 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue)); |
mbed_official | 340:28d1f895c6fe | 420 | |
mbed_official | 340:28d1f895c6fe | 421 | /* Check the HSI14 State */ |
mbed_official | 340:28d1f895c6fe | 422 | if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON) |
mbed_official | 340:28d1f895c6fe | 423 | { |
mbed_official | 340:28d1f895c6fe | 424 | /* Disable ADC control of the Internal High Speed oscillator HSI14 */ |
mbed_official | 340:28d1f895c6fe | 425 | __HAL_RCC_HSI14ADC_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 426 | |
mbed_official | 340:28d1f895c6fe | 427 | /* Enable the Internal High Speed oscillator (HSI). */ |
mbed_official | 340:28d1f895c6fe | 428 | __HAL_RCC_HSI14_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 429 | |
mbed_official | 340:28d1f895c6fe | 430 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 431 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 432 | |
mbed_official | 340:28d1f895c6fe | 433 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 434 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 435 | { |
mbed_official | 340:28d1f895c6fe | 436 | if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 437 | { |
mbed_official | 340:28d1f895c6fe | 438 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 439 | } |
mbed_official | 340:28d1f895c6fe | 440 | } |
mbed_official | 340:28d1f895c6fe | 441 | |
mbed_official | 340:28d1f895c6fe | 442 | /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ |
mbed_official | 340:28d1f895c6fe | 443 | __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); |
mbed_official | 340:28d1f895c6fe | 444 | } |
mbed_official | 340:28d1f895c6fe | 445 | else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL) |
mbed_official | 340:28d1f895c6fe | 446 | { |
mbed_official | 340:28d1f895c6fe | 447 | /* Enable ADC control of the Internal High Speed oscillator HSI14 */ |
mbed_official | 340:28d1f895c6fe | 448 | __HAL_RCC_HSI14ADC_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 449 | |
mbed_official | 340:28d1f895c6fe | 450 | /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */ |
mbed_official | 340:28d1f895c6fe | 451 | __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue); |
mbed_official | 340:28d1f895c6fe | 452 | } |
mbed_official | 340:28d1f895c6fe | 453 | else |
mbed_official | 340:28d1f895c6fe | 454 | { |
mbed_official | 340:28d1f895c6fe | 455 | /* Disable ADC control of the Internal High Speed oscillator HSI14 */ |
mbed_official | 340:28d1f895c6fe | 456 | __HAL_RCC_HSI14ADC_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 457 | |
mbed_official | 340:28d1f895c6fe | 458 | /* Disable the Internal High Speed oscillator (HSI). */ |
mbed_official | 340:28d1f895c6fe | 459 | __HAL_RCC_HSI14_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 460 | |
mbed_official | 340:28d1f895c6fe | 461 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 462 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 463 | |
mbed_official | 340:28d1f895c6fe | 464 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 465 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 466 | { |
mbed_official | 340:28d1f895c6fe | 467 | if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 468 | { |
mbed_official | 340:28d1f895c6fe | 469 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 470 | } |
mbed_official | 340:28d1f895c6fe | 471 | } |
mbed_official | 340:28d1f895c6fe | 472 | } |
mbed_official | 340:28d1f895c6fe | 473 | } |
mbed_official | 340:28d1f895c6fe | 474 | |
mbed_official | 340:28d1f895c6fe | 475 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 476 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 477 | /*----------------------------- HSI48 Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 478 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) |
mbed_official | 340:28d1f895c6fe | 479 | { |
mbed_official | 340:28d1f895c6fe | 480 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 481 | assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); |
mbed_official | 340:28d1f895c6fe | 482 | |
mbed_official | 340:28d1f895c6fe | 483 | /* When the HSI48 is used as system clock it is not allowed to be disabled */ |
mbed_official | 340:28d1f895c6fe | 484 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) || |
mbed_official | 340:28d1f895c6fe | 485 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48))) |
mbed_official | 340:28d1f895c6fe | 486 | { |
mbed_official | 340:28d1f895c6fe | 487 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON)) |
mbed_official | 340:28d1f895c6fe | 488 | { |
mbed_official | 340:28d1f895c6fe | 489 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 490 | } |
mbed_official | 340:28d1f895c6fe | 491 | } |
mbed_official | 340:28d1f895c6fe | 492 | else |
mbed_official | 340:28d1f895c6fe | 493 | { |
mbed_official | 340:28d1f895c6fe | 494 | /* Check the HSI State */ |
mbed_official | 340:28d1f895c6fe | 495 | if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) |
mbed_official | 340:28d1f895c6fe | 496 | { |
mbed_official | 340:28d1f895c6fe | 497 | /* Enable the Internal High Speed oscillator (HSI48). */ |
mbed_official | 340:28d1f895c6fe | 498 | __HAL_RCC_HSI48_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 499 | |
mbed_official | 340:28d1f895c6fe | 500 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 501 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 502 | |
mbed_official | 340:28d1f895c6fe | 503 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 504 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 505 | { |
mbed_official | 340:28d1f895c6fe | 506 | if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 507 | { |
mbed_official | 340:28d1f895c6fe | 508 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 509 | } |
mbed_official | 340:28d1f895c6fe | 510 | } |
mbed_official | 340:28d1f895c6fe | 511 | } |
mbed_official | 340:28d1f895c6fe | 512 | else |
mbed_official | 340:28d1f895c6fe | 513 | { |
mbed_official | 340:28d1f895c6fe | 514 | /* Disable the Internal High Speed oscillator (HSI48). */ |
mbed_official | 340:28d1f895c6fe | 515 | __HAL_RCC_HSI48_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 516 | |
mbed_official | 340:28d1f895c6fe | 517 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 518 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 519 | |
mbed_official | 340:28d1f895c6fe | 520 | /* Wait till HSI is ready */ |
mbed_official | 340:28d1f895c6fe | 521 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 522 | { |
mbed_official | 340:28d1f895c6fe | 523 | if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 524 | { |
mbed_official | 340:28d1f895c6fe | 525 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 526 | } |
mbed_official | 340:28d1f895c6fe | 527 | } |
mbed_official | 340:28d1f895c6fe | 528 | } |
mbed_official | 340:28d1f895c6fe | 529 | } |
mbed_official | 340:28d1f895c6fe | 530 | } |
mbed_official | 340:28d1f895c6fe | 531 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 532 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 533 | |
mbed_official | 340:28d1f895c6fe | 534 | /*-------------------------------- PLL Configuration -----------------------*/ |
mbed_official | 340:28d1f895c6fe | 535 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 536 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); |
mbed_official | 340:28d1f895c6fe | 537 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) |
mbed_official | 340:28d1f895c6fe | 538 | { |
mbed_official | 340:28d1f895c6fe | 539 | /* Check if the PLL is used as system clock or not */ |
mbed_official | 340:28d1f895c6fe | 540 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 541 | { |
mbed_official | 340:28d1f895c6fe | 542 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) |
mbed_official | 340:28d1f895c6fe | 543 | { |
mbed_official | 340:28d1f895c6fe | 544 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 545 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); |
mbed_official | 340:28d1f895c6fe | 546 | assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); |
mbed_official | 340:28d1f895c6fe | 547 | assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); |
mbed_official | 340:28d1f895c6fe | 548 | |
mbed_official | 340:28d1f895c6fe | 549 | /* Disable the main PLL. */ |
mbed_official | 340:28d1f895c6fe | 550 | __HAL_RCC_PLL_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 551 | |
mbed_official | 340:28d1f895c6fe | 552 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 553 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 554 | |
mbed_official | 340:28d1f895c6fe | 555 | /* Wait till PLL is ready */ |
mbed_official | 340:28d1f895c6fe | 556 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 557 | { |
mbed_official | 340:28d1f895c6fe | 558 | if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 559 | { |
mbed_official | 340:28d1f895c6fe | 560 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 561 | } |
mbed_official | 340:28d1f895c6fe | 562 | } |
mbed_official | 340:28d1f895c6fe | 563 | |
mbed_official | 340:28d1f895c6fe | 564 | /* Configure the main PLL clock source, predivider and multiplication factor. */ |
mbed_official | 340:28d1f895c6fe | 565 | __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, |
mbed_official | 340:28d1f895c6fe | 566 | RCC_OscInitStruct->PLL.PREDIV, |
mbed_official | 340:28d1f895c6fe | 567 | RCC_OscInitStruct->PLL.PLLMUL); |
mbed_official | 340:28d1f895c6fe | 568 | |
mbed_official | 340:28d1f895c6fe | 569 | /* Enable the main PLL. */ |
mbed_official | 340:28d1f895c6fe | 570 | __HAL_RCC_PLL_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 571 | |
mbed_official | 340:28d1f895c6fe | 572 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 573 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 574 | |
mbed_official | 340:28d1f895c6fe | 575 | /* Wait till PLL is ready */ |
mbed_official | 340:28d1f895c6fe | 576 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 577 | { |
mbed_official | 340:28d1f895c6fe | 578 | if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 579 | { |
mbed_official | 340:28d1f895c6fe | 580 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 581 | } |
mbed_official | 340:28d1f895c6fe | 582 | } |
mbed_official | 340:28d1f895c6fe | 583 | } |
mbed_official | 340:28d1f895c6fe | 584 | else |
mbed_official | 340:28d1f895c6fe | 585 | { |
mbed_official | 340:28d1f895c6fe | 586 | /* Disable the main PLL. */ |
mbed_official | 340:28d1f895c6fe | 587 | __HAL_RCC_PLL_DISABLE(); |
mbed_official | 340:28d1f895c6fe | 588 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 589 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 590 | |
mbed_official | 340:28d1f895c6fe | 591 | /* Wait till PLL is ready */ |
mbed_official | 340:28d1f895c6fe | 592 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
mbed_official | 340:28d1f895c6fe | 593 | { |
mbed_official | 340:28d1f895c6fe | 594 | if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 595 | { |
mbed_official | 340:28d1f895c6fe | 596 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 597 | } |
mbed_official | 340:28d1f895c6fe | 598 | } |
mbed_official | 340:28d1f895c6fe | 599 | } |
mbed_official | 340:28d1f895c6fe | 600 | } |
mbed_official | 340:28d1f895c6fe | 601 | else |
mbed_official | 340:28d1f895c6fe | 602 | { |
mbed_official | 340:28d1f895c6fe | 603 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 604 | } |
mbed_official | 340:28d1f895c6fe | 605 | } |
mbed_official | 340:28d1f895c6fe | 606 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 607 | } |
mbed_official | 340:28d1f895c6fe | 608 | |
mbed_official | 340:28d1f895c6fe | 609 | /** |
mbed_official | 340:28d1f895c6fe | 610 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified |
mbed_official | 340:28d1f895c6fe | 611 | * parameters in the RCC_ClkInitStruct. |
mbed_official | 340:28d1f895c6fe | 612 | * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that |
mbed_official | 340:28d1f895c6fe | 613 | * contains the configuration information for the RCC peripheral. |
mbed_official | 340:28d1f895c6fe | 614 | * @param FLatency: FLASH Latency |
mbed_official | 340:28d1f895c6fe | 615 | * This parameter can be one of the following values: |
mbed_official | 340:28d1f895c6fe | 616 | * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle |
mbed_official | 340:28d1f895c6fe | 617 | * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle |
mbed_official | 340:28d1f895c6fe | 618 | * |
mbed_official | 340:28d1f895c6fe | 619 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
mbed_official | 340:28d1f895c6fe | 620 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function |
mbed_official | 340:28d1f895c6fe | 621 | * |
mbed_official | 340:28d1f895c6fe | 622 | * @note The HSI is used (enabled by hardware) as system clock source after |
mbed_official | 340:28d1f895c6fe | 623 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case |
mbed_official | 340:28d1f895c6fe | 624 | * of failure of the HSE used directly or indirectly as system clock |
mbed_official | 340:28d1f895c6fe | 625 | * (if the Clock Security System CSS is enabled). |
mbed_official | 340:28d1f895c6fe | 626 | * |
mbed_official | 340:28d1f895c6fe | 627 | * @note A switch from one clock source to another occurs only if the target |
mbed_official | 340:28d1f895c6fe | 628 | * clock source is ready (clock stable after startup delay or PLL locked). |
mbed_official | 340:28d1f895c6fe | 629 | * If a clock source which is not yet ready is selected, the switch will |
mbed_official | 340:28d1f895c6fe | 630 | * occur when the clock source will be ready. |
mbed_official | 340:28d1f895c6fe | 631 | * @retval None |
mbed_official | 340:28d1f895c6fe | 632 | */ |
mbed_official | 340:28d1f895c6fe | 633 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
mbed_official | 340:28d1f895c6fe | 634 | { |
mbed_official | 340:28d1f895c6fe | 635 | uint32_t tickstart = 0; |
mbed_official | 340:28d1f895c6fe | 636 | |
mbed_official | 340:28d1f895c6fe | 637 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 638 | assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); |
mbed_official | 340:28d1f895c6fe | 639 | assert_param(IS_FLASH_LATENCY(FLatency)); |
mbed_official | 340:28d1f895c6fe | 640 | |
mbed_official | 340:28d1f895c6fe | 641 | /* To correctly read data from FLASH memory, the number of wait states (LATENCY) |
mbed_official | 340:28d1f895c6fe | 642 | must be correctly programmed according to the frequency of the CPU clock |
mbed_official | 340:28d1f895c6fe | 643 | (HCLK) of the device. */ |
mbed_official | 340:28d1f895c6fe | 644 | |
mbed_official | 340:28d1f895c6fe | 645 | /* Increasing the CPU frequency */ |
mbed_official | 340:28d1f895c6fe | 646 | if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) |
mbed_official | 340:28d1f895c6fe | 647 | { |
mbed_official | 340:28d1f895c6fe | 648 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
mbed_official | 340:28d1f895c6fe | 649 | __HAL_FLASH_SET_LATENCY(FLatency); |
mbed_official | 340:28d1f895c6fe | 650 | |
mbed_official | 340:28d1f895c6fe | 651 | /* Check that the new number of wait states is taken into account to access the Flash |
mbed_official | 340:28d1f895c6fe | 652 | memory by reading the FLASH_ACR register */ |
mbed_official | 340:28d1f895c6fe | 653 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
mbed_official | 340:28d1f895c6fe | 654 | { |
mbed_official | 340:28d1f895c6fe | 655 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 656 | } |
mbed_official | 340:28d1f895c6fe | 657 | |
mbed_official | 340:28d1f895c6fe | 658 | /*-------------------------- HCLK Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 659 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
mbed_official | 340:28d1f895c6fe | 660 | { |
mbed_official | 340:28d1f895c6fe | 661 | assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); |
mbed_official | 340:28d1f895c6fe | 662 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
mbed_official | 340:28d1f895c6fe | 663 | } |
mbed_official | 340:28d1f895c6fe | 664 | |
mbed_official | 340:28d1f895c6fe | 665 | /*------------------------- SYSCLK Configuration ---------------------------*/ |
mbed_official | 340:28d1f895c6fe | 666 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
mbed_official | 340:28d1f895c6fe | 667 | { |
mbed_official | 340:28d1f895c6fe | 668 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
mbed_official | 340:28d1f895c6fe | 669 | |
mbed_official | 340:28d1f895c6fe | 670 | /* HSE is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 671 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 340:28d1f895c6fe | 672 | { |
mbed_official | 340:28d1f895c6fe | 673 | /* Check the HSE ready flag */ |
mbed_official | 340:28d1f895c6fe | 674 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 675 | { |
mbed_official | 340:28d1f895c6fe | 676 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 677 | } |
mbed_official | 340:28d1f895c6fe | 678 | } |
mbed_official | 340:28d1f895c6fe | 679 | /* PLL is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 680 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 681 | { |
mbed_official | 340:28d1f895c6fe | 682 | /* Check the PLL ready flag */ |
mbed_official | 340:28d1f895c6fe | 683 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 684 | { |
mbed_official | 340:28d1f895c6fe | 685 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 686 | } |
mbed_official | 340:28d1f895c6fe | 687 | } |
mbed_official | 340:28d1f895c6fe | 688 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 689 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 690 | /* HSI48 is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 691 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) |
mbed_official | 340:28d1f895c6fe | 692 | { |
mbed_official | 340:28d1f895c6fe | 693 | /* Check the HSI48 ready flag */ |
mbed_official | 340:28d1f895c6fe | 694 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 695 | { |
mbed_official | 340:28d1f895c6fe | 696 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 697 | } |
mbed_official | 340:28d1f895c6fe | 698 | } |
mbed_official | 340:28d1f895c6fe | 699 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 700 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 701 | /* HSI is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 702 | else |
mbed_official | 340:28d1f895c6fe | 703 | { |
mbed_official | 340:28d1f895c6fe | 704 | /* Check the HSI ready flag */ |
mbed_official | 340:28d1f895c6fe | 705 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 706 | { |
mbed_official | 340:28d1f895c6fe | 707 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 708 | } |
mbed_official | 340:28d1f895c6fe | 709 | } |
mbed_official | 340:28d1f895c6fe | 710 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); |
mbed_official | 340:28d1f895c6fe | 711 | |
mbed_official | 340:28d1f895c6fe | 712 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 713 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 714 | |
mbed_official | 340:28d1f895c6fe | 715 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 340:28d1f895c6fe | 716 | { |
mbed_official | 340:28d1f895c6fe | 717 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) |
mbed_official | 340:28d1f895c6fe | 718 | { |
mbed_official | 340:28d1f895c6fe | 719 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 720 | { |
mbed_official | 340:28d1f895c6fe | 721 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 722 | } |
mbed_official | 340:28d1f895c6fe | 723 | } |
mbed_official | 340:28d1f895c6fe | 724 | } |
mbed_official | 340:28d1f895c6fe | 725 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 726 | { |
mbed_official | 340:28d1f895c6fe | 727 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 728 | { |
mbed_official | 340:28d1f895c6fe | 729 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 730 | { |
mbed_official | 340:28d1f895c6fe | 731 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 732 | } |
mbed_official | 340:28d1f895c6fe | 733 | } |
mbed_official | 340:28d1f895c6fe | 734 | } |
mbed_official | 340:28d1f895c6fe | 735 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 736 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 737 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) |
mbed_official | 340:28d1f895c6fe | 738 | { |
mbed_official | 340:28d1f895c6fe | 739 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) |
mbed_official | 340:28d1f895c6fe | 740 | { |
mbed_official | 340:28d1f895c6fe | 741 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 742 | { |
mbed_official | 340:28d1f895c6fe | 743 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 744 | } |
mbed_official | 340:28d1f895c6fe | 745 | } |
mbed_official | 340:28d1f895c6fe | 746 | } |
mbed_official | 340:28d1f895c6fe | 747 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 748 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 749 | else |
mbed_official | 340:28d1f895c6fe | 750 | { |
mbed_official | 340:28d1f895c6fe | 751 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) |
mbed_official | 340:28d1f895c6fe | 752 | { |
mbed_official | 340:28d1f895c6fe | 753 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 754 | { |
mbed_official | 340:28d1f895c6fe | 755 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 756 | } |
mbed_official | 340:28d1f895c6fe | 757 | } |
mbed_official | 340:28d1f895c6fe | 758 | } |
mbed_official | 340:28d1f895c6fe | 759 | } |
mbed_official | 340:28d1f895c6fe | 760 | } |
mbed_official | 340:28d1f895c6fe | 761 | /* Decreasing the CPU frequency */ |
mbed_official | 340:28d1f895c6fe | 762 | else |
mbed_official | 340:28d1f895c6fe | 763 | { |
mbed_official | 340:28d1f895c6fe | 764 | /*-------------------------- HCLK Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 765 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
mbed_official | 340:28d1f895c6fe | 766 | { |
mbed_official | 340:28d1f895c6fe | 767 | assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider)); |
mbed_official | 340:28d1f895c6fe | 768 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
mbed_official | 340:28d1f895c6fe | 769 | } |
mbed_official | 340:28d1f895c6fe | 770 | |
mbed_official | 340:28d1f895c6fe | 771 | /*------------------------- SYSCLK Configuration ---------------------------*/ |
mbed_official | 340:28d1f895c6fe | 772 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
mbed_official | 340:28d1f895c6fe | 773 | { |
mbed_official | 340:28d1f895c6fe | 774 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
mbed_official | 340:28d1f895c6fe | 775 | |
mbed_official | 340:28d1f895c6fe | 776 | /* HSE is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 777 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 340:28d1f895c6fe | 778 | { |
mbed_official | 340:28d1f895c6fe | 779 | /* Check the HSE ready flag */ |
mbed_official | 340:28d1f895c6fe | 780 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 781 | { |
mbed_official | 340:28d1f895c6fe | 782 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 783 | } |
mbed_official | 340:28d1f895c6fe | 784 | } |
mbed_official | 340:28d1f895c6fe | 785 | /* PLL is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 786 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 787 | { |
mbed_official | 340:28d1f895c6fe | 788 | /* Check the PLL ready flag */ |
mbed_official | 340:28d1f895c6fe | 789 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 790 | { |
mbed_official | 340:28d1f895c6fe | 791 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 792 | } |
mbed_official | 340:28d1f895c6fe | 793 | } |
mbed_official | 340:28d1f895c6fe | 794 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 795 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 796 | /* HSI48 is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 797 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) |
mbed_official | 340:28d1f895c6fe | 798 | { |
mbed_official | 340:28d1f895c6fe | 799 | /* Check the HSI48 ready flag */ |
mbed_official | 340:28d1f895c6fe | 800 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 801 | { |
mbed_official | 340:28d1f895c6fe | 802 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 803 | } |
mbed_official | 340:28d1f895c6fe | 804 | } |
mbed_official | 340:28d1f895c6fe | 805 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 806 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 807 | /* HSI is selected as System Clock Source */ |
mbed_official | 340:28d1f895c6fe | 808 | else |
mbed_official | 340:28d1f895c6fe | 809 | { |
mbed_official | 340:28d1f895c6fe | 810 | /* Check the HSI ready flag */ |
mbed_official | 340:28d1f895c6fe | 811 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 812 | { |
mbed_official | 340:28d1f895c6fe | 813 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 814 | } |
mbed_official | 340:28d1f895c6fe | 815 | } |
mbed_official | 340:28d1f895c6fe | 816 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); |
mbed_official | 340:28d1f895c6fe | 817 | |
mbed_official | 340:28d1f895c6fe | 818 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 819 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 820 | |
mbed_official | 340:28d1f895c6fe | 821 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
mbed_official | 340:28d1f895c6fe | 822 | { |
mbed_official | 340:28d1f895c6fe | 823 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) |
mbed_official | 340:28d1f895c6fe | 824 | { |
mbed_official | 340:28d1f895c6fe | 825 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 826 | { |
mbed_official | 340:28d1f895c6fe | 827 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 828 | } |
mbed_official | 340:28d1f895c6fe | 829 | } |
mbed_official | 340:28d1f895c6fe | 830 | } |
mbed_official | 340:28d1f895c6fe | 831 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 832 | { |
mbed_official | 340:28d1f895c6fe | 833 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) |
mbed_official | 340:28d1f895c6fe | 834 | { |
mbed_official | 340:28d1f895c6fe | 835 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 836 | { |
mbed_official | 340:28d1f895c6fe | 837 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 838 | } |
mbed_official | 340:28d1f895c6fe | 839 | } |
mbed_official | 340:28d1f895c6fe | 840 | } |
mbed_official | 340:28d1f895c6fe | 841 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 842 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 843 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48) |
mbed_official | 340:28d1f895c6fe | 844 | { |
mbed_official | 340:28d1f895c6fe | 845 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48) |
mbed_official | 340:28d1f895c6fe | 846 | { |
mbed_official | 340:28d1f895c6fe | 847 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 848 | { |
mbed_official | 340:28d1f895c6fe | 849 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 850 | } |
mbed_official | 340:28d1f895c6fe | 851 | } |
mbed_official | 340:28d1f895c6fe | 852 | } |
mbed_official | 340:28d1f895c6fe | 853 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 854 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 855 | else |
mbed_official | 340:28d1f895c6fe | 856 | { |
mbed_official | 340:28d1f895c6fe | 857 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) |
mbed_official | 340:28d1f895c6fe | 858 | { |
mbed_official | 340:28d1f895c6fe | 859 | if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 860 | { |
mbed_official | 340:28d1f895c6fe | 861 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 862 | } |
mbed_official | 340:28d1f895c6fe | 863 | } |
mbed_official | 340:28d1f895c6fe | 864 | } |
mbed_official | 340:28d1f895c6fe | 865 | } |
mbed_official | 340:28d1f895c6fe | 866 | |
mbed_official | 340:28d1f895c6fe | 867 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
mbed_official | 340:28d1f895c6fe | 868 | __HAL_FLASH_SET_LATENCY(FLatency); |
mbed_official | 340:28d1f895c6fe | 869 | |
mbed_official | 340:28d1f895c6fe | 870 | /* Check that the new number of wait states is taken into account to access the Flash |
mbed_official | 340:28d1f895c6fe | 871 | memory by reading the FLASH_ACR register */ |
mbed_official | 340:28d1f895c6fe | 872 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
mbed_official | 340:28d1f895c6fe | 873 | { |
mbed_official | 340:28d1f895c6fe | 874 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 875 | } |
mbed_official | 340:28d1f895c6fe | 876 | } |
mbed_official | 340:28d1f895c6fe | 877 | |
mbed_official | 340:28d1f895c6fe | 878 | /*-------------------------- PCLK1 Configuration ---------------------------*/ |
mbed_official | 340:28d1f895c6fe | 879 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
mbed_official | 340:28d1f895c6fe | 880 | { |
mbed_official | 340:28d1f895c6fe | 881 | assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider)); |
mbed_official | 340:28d1f895c6fe | 882 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); |
mbed_official | 340:28d1f895c6fe | 883 | } |
mbed_official | 340:28d1f895c6fe | 884 | |
mbed_official | 340:28d1f895c6fe | 885 | /* Configure the source of time base considering new system clocks settings*/ |
mbed_official | 340:28d1f895c6fe | 886 | HAL_InitTick (TICK_INT_PRIORITY); |
mbed_official | 340:28d1f895c6fe | 887 | |
mbed_official | 340:28d1f895c6fe | 888 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 889 | } |
mbed_official | 340:28d1f895c6fe | 890 | |
mbed_official | 340:28d1f895c6fe | 891 | /** |
mbed_official | 340:28d1f895c6fe | 892 | * @brief Returns the SYSCLK frequency |
mbed_official | 340:28d1f895c6fe | 893 | * @note The system frequency computed by this function is not the real |
mbed_official | 340:28d1f895c6fe | 894 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 340:28d1f895c6fe | 895 | * constant and the selected clock source: |
mbed_official | 340:28d1f895c6fe | 896 | * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*) |
mbed_official | 340:28d1f895c6fe | 897 | * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*) |
mbed_official | 340:28d1f895c6fe | 898 | * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE |
mbed_official | 340:28d1f895c6fe | 899 | * divided by PREDIV factor(**) |
mbed_official | 340:28d1f895c6fe | 900 | * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE |
mbed_official | 340:28d1f895c6fe | 901 | * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based |
mbed_official | 340:28d1f895c6fe | 902 | * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the |
mbed_official | 340:28d1f895c6fe | 903 | * PLL factor . |
mbed_official | 340:28d1f895c6fe | 904 | * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file |
mbed_official | 340:28d1f895c6fe | 905 | * (default values 8 MHz and 48MHz). |
mbed_official | 340:28d1f895c6fe | 906 | * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value |
mbed_official | 340:28d1f895c6fe | 907 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 340:28d1f895c6fe | 908 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 340:28d1f895c6fe | 909 | * have wrong result. |
mbed_official | 340:28d1f895c6fe | 910 | * |
mbed_official | 340:28d1f895c6fe | 911 | * @note The result of this function could be not correct when using fractional |
mbed_official | 340:28d1f895c6fe | 912 | * value for HSE crystal. |
mbed_official | 340:28d1f895c6fe | 913 | * |
mbed_official | 340:28d1f895c6fe | 914 | * @note This function can be used by the user application to compute the |
mbed_official | 340:28d1f895c6fe | 915 | * baudrate for the communication peripherals or configure other parameters. |
mbed_official | 340:28d1f895c6fe | 916 | * |
mbed_official | 340:28d1f895c6fe | 917 | * @note Each time SYSCLK changes, this function must be called to update the |
mbed_official | 340:28d1f895c6fe | 918 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
mbed_official | 340:28d1f895c6fe | 919 | * |
mbed_official | 340:28d1f895c6fe | 920 | * @retval SYSCLK frequency |
mbed_official | 340:28d1f895c6fe | 921 | */ |
mbed_official | 340:28d1f895c6fe | 922 | uint32_t HAL_RCC_GetSysClockFreq(void) |
mbed_official | 340:28d1f895c6fe | 923 | { |
mbed_official | 340:28d1f895c6fe | 924 | uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0; |
mbed_official | 340:28d1f895c6fe | 925 | uint32_t sysclockfreq = 0; |
mbed_official | 340:28d1f895c6fe | 926 | |
mbed_official | 340:28d1f895c6fe | 927 | tmpreg = RCC->CFGR; |
mbed_official | 340:28d1f895c6fe | 928 | |
mbed_official | 340:28d1f895c6fe | 929 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 930 | switch (tmpreg & RCC_CFGR_SWS) |
mbed_official | 340:28d1f895c6fe | 931 | { |
mbed_official | 340:28d1f895c6fe | 932 | case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ |
mbed_official | 340:28d1f895c6fe | 933 | sysclockfreq = HSE_VALUE; |
mbed_official | 340:28d1f895c6fe | 934 | break; |
mbed_official | 340:28d1f895c6fe | 935 | |
mbed_official | 340:28d1f895c6fe | 936 | case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ |
mbed_official | 340:28d1f895c6fe | 937 | pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER]; |
mbed_official | 340:28d1f895c6fe | 938 | prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER]; |
mbed_official | 340:28d1f895c6fe | 939 | if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE) |
mbed_official | 340:28d1f895c6fe | 940 | { |
mbed_official | 340:28d1f895c6fe | 941 | /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ |
mbed_official | 340:28d1f895c6fe | 942 | pllclk = (HSE_VALUE/prediv) * pllmul; |
mbed_official | 340:28d1f895c6fe | 943 | } |
mbed_official | 340:28d1f895c6fe | 944 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 945 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 946 | else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48) |
mbed_official | 340:28d1f895c6fe | 947 | { |
mbed_official | 340:28d1f895c6fe | 948 | /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */ |
mbed_official | 340:28d1f895c6fe | 949 | pllclk = (HSI48_VALUE/prediv) * pllmul; |
mbed_official | 340:28d1f895c6fe | 950 | } |
mbed_official | 340:28d1f895c6fe | 951 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 952 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 953 | else |
mbed_official | 340:28d1f895c6fe | 954 | { |
mbed_official | 340:28d1f895c6fe | 955 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 340:28d1f895c6fe | 956 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 957 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 958 | /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ |
mbed_official | 340:28d1f895c6fe | 959 | pllclk = (HSI_VALUE/prediv) * pllmul; |
mbed_official | 340:28d1f895c6fe | 960 | #else |
mbed_official | 340:28d1f895c6fe | 961 | /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ |
mbed_official | 340:28d1f895c6fe | 962 | pllclk = (HSI_VALUE >> 1) * pllmul; |
mbed_official | 340:28d1f895c6fe | 963 | #endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 964 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 965 | } |
mbed_official | 340:28d1f895c6fe | 966 | sysclockfreq = pllclk; |
mbed_official | 340:28d1f895c6fe | 967 | break; |
mbed_official | 340:28d1f895c6fe | 968 | |
mbed_official | 340:28d1f895c6fe | 969 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 970 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 971 | case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */ |
mbed_official | 340:28d1f895c6fe | 972 | sysclockfreq = HSI48_VALUE; |
mbed_official | 340:28d1f895c6fe | 973 | break; |
mbed_official | 340:28d1f895c6fe | 974 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 975 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 976 | |
mbed_official | 340:28d1f895c6fe | 977 | case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ |
mbed_official | 340:28d1f895c6fe | 978 | default: |
mbed_official | 340:28d1f895c6fe | 979 | sysclockfreq = HSI_VALUE; |
mbed_official | 340:28d1f895c6fe | 980 | break; |
mbed_official | 340:28d1f895c6fe | 981 | } |
mbed_official | 340:28d1f895c6fe | 982 | return sysclockfreq; |
mbed_official | 340:28d1f895c6fe | 983 | } |
mbed_official | 340:28d1f895c6fe | 984 | |
mbed_official | 340:28d1f895c6fe | 985 | /** |
mbed_official | 340:28d1f895c6fe | 986 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
mbed_official | 340:28d1f895c6fe | 987 | * parameters in the RCC_PeriphCLKInitTypeDef. |
mbed_official | 340:28d1f895c6fe | 988 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
mbed_official | 340:28d1f895c6fe | 989 | * contains the configuration information for the Extended Peripherals clocks |
mbed_official | 340:28d1f895c6fe | 990 | * (USART, RTC, I2C, CEC and USB). |
mbed_official | 340:28d1f895c6fe | 991 | * |
mbed_official | 340:28d1f895c6fe | 992 | * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select |
mbed_official | 340:28d1f895c6fe | 993 | * the RTC clock source; in this case the Backup domain will be reset in |
mbed_official | 340:28d1f895c6fe | 994 | * order to modify the RTC Clock source, as consequence RTC registers (including |
mbed_official | 340:28d1f895c6fe | 995 | * the backup registers) and RCC_BDCR register are set to their reset values. |
mbed_official | 340:28d1f895c6fe | 996 | * |
mbed_official | 340:28d1f895c6fe | 997 | * @retval None |
mbed_official | 340:28d1f895c6fe | 998 | */ |
mbed_official | 340:28d1f895c6fe | 999 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 340:28d1f895c6fe | 1000 | { |
mbed_official | 340:28d1f895c6fe | 1001 | uint32_t tickstart = 0; |
mbed_official | 340:28d1f895c6fe | 1002 | uint32_t tmpreg = 0; |
mbed_official | 340:28d1f895c6fe | 1003 | |
mbed_official | 340:28d1f895c6fe | 1004 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1005 | assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1006 | |
mbed_official | 340:28d1f895c6fe | 1007 | /*---------------------------- RTC configuration -------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1008 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) |
mbed_official | 340:28d1f895c6fe | 1009 | { |
mbed_official | 340:28d1f895c6fe | 1010 | /* Enable Power Clock*/ |
mbed_official | 340:28d1f895c6fe | 1011 | __PWR_CLK_ENABLE(); |
mbed_official | 340:28d1f895c6fe | 1012 | |
mbed_official | 340:28d1f895c6fe | 1013 | /* Enable write access to Backup domain */ |
mbed_official | 340:28d1f895c6fe | 1014 | SET_BIT(PWR->CR, PWR_CR_DBP); |
mbed_official | 340:28d1f895c6fe | 1015 | |
mbed_official | 340:28d1f895c6fe | 1016 | /* Wait for Backup domain Write protection disable */ |
mbed_official | 340:28d1f895c6fe | 1017 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 1018 | |
mbed_official | 340:28d1f895c6fe | 1019 | while((PWR->CR & PWR_CR_DBP) == RESET) |
mbed_official | 340:28d1f895c6fe | 1020 | { |
mbed_official | 340:28d1f895c6fe | 1021 | if((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 1022 | { |
mbed_official | 340:28d1f895c6fe | 1023 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1024 | } |
mbed_official | 340:28d1f895c6fe | 1025 | } |
mbed_official | 340:28d1f895c6fe | 1026 | |
mbed_official | 340:28d1f895c6fe | 1027 | /* Reset the Backup domain only if the RTC Clock source selction is modified */ |
mbed_official | 340:28d1f895c6fe | 1028 | if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) |
mbed_official | 340:28d1f895c6fe | 1029 | { |
mbed_official | 340:28d1f895c6fe | 1030 | /* Store the content of BDCR register before the reset of Backup Domain */ |
mbed_official | 340:28d1f895c6fe | 1031 | tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); |
mbed_official | 340:28d1f895c6fe | 1032 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
mbed_official | 340:28d1f895c6fe | 1033 | __HAL_RCC_BACKUPRESET_FORCE(); |
mbed_official | 340:28d1f895c6fe | 1034 | __HAL_RCC_BACKUPRESET_RELEASE(); |
mbed_official | 340:28d1f895c6fe | 1035 | /* Restore the Content of BDCR register */ |
mbed_official | 340:28d1f895c6fe | 1036 | RCC->BDCR = tmpreg; |
mbed_official | 340:28d1f895c6fe | 1037 | } |
mbed_official | 340:28d1f895c6fe | 1038 | |
mbed_official | 340:28d1f895c6fe | 1039 | /* If LSE is selected as RTC clock source, wait for LSE reactivation */ |
mbed_official | 340:28d1f895c6fe | 1040 | if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) |
mbed_official | 340:28d1f895c6fe | 1041 | { |
mbed_official | 340:28d1f895c6fe | 1042 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 1043 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 1044 | |
mbed_official | 340:28d1f895c6fe | 1045 | /* Wait till LSE is ready */ |
mbed_official | 340:28d1f895c6fe | 1046 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
mbed_official | 340:28d1f895c6fe | 1047 | { |
mbed_official | 340:28d1f895c6fe | 1048 | if((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE) |
mbed_official | 340:28d1f895c6fe | 1049 | { |
mbed_official | 340:28d1f895c6fe | 1050 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1051 | } |
mbed_official | 340:28d1f895c6fe | 1052 | } |
mbed_official | 340:28d1f895c6fe | 1053 | } |
mbed_official | 340:28d1f895c6fe | 1054 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
mbed_official | 340:28d1f895c6fe | 1055 | } |
mbed_official | 340:28d1f895c6fe | 1056 | |
mbed_official | 340:28d1f895c6fe | 1057 | /*------------------------------- USART1 Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1058 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) |
mbed_official | 340:28d1f895c6fe | 1059 | { |
mbed_official | 340:28d1f895c6fe | 1060 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1061 | assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1062 | |
mbed_official | 340:28d1f895c6fe | 1063 | /* Configure the USART1 clock source */ |
mbed_official | 340:28d1f895c6fe | 1064 | __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); |
mbed_official | 340:28d1f895c6fe | 1065 | } |
mbed_official | 340:28d1f895c6fe | 1066 | |
mbed_official | 340:28d1f895c6fe | 1067 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 1068 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1069 | /*----------------------------- USART2 Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1070 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) |
mbed_official | 340:28d1f895c6fe | 1071 | { |
mbed_official | 340:28d1f895c6fe | 1072 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1073 | assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1074 | |
mbed_official | 340:28d1f895c6fe | 1075 | /* Configure the USART2 clock source */ |
mbed_official | 340:28d1f895c6fe | 1076 | __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); |
mbed_official | 340:28d1f895c6fe | 1077 | } |
mbed_official | 340:28d1f895c6fe | 1078 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 1079 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1080 | |
mbed_official | 340:28d1f895c6fe | 1081 | #if defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1082 | /*----------------------------- USART3 Configuration --------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1083 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) |
mbed_official | 340:28d1f895c6fe | 1084 | { |
mbed_official | 340:28d1f895c6fe | 1085 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1086 | assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1087 | |
mbed_official | 340:28d1f895c6fe | 1088 | /* Configure the USART3 clock source */ |
mbed_official | 340:28d1f895c6fe | 1089 | __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); |
mbed_official | 340:28d1f895c6fe | 1090 | } |
mbed_official | 340:28d1f895c6fe | 1091 | #endif /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1092 | |
mbed_official | 340:28d1f895c6fe | 1093 | /*------------------------------ I2C1 Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1094 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) |
mbed_official | 340:28d1f895c6fe | 1095 | { |
mbed_official | 340:28d1f895c6fe | 1096 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1097 | assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1098 | |
mbed_official | 340:28d1f895c6fe | 1099 | /* Configure the I2C1 clock source */ |
mbed_official | 340:28d1f895c6fe | 1100 | __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); |
mbed_official | 340:28d1f895c6fe | 1101 | } |
mbed_official | 340:28d1f895c6fe | 1102 | |
mbed_official | 340:28d1f895c6fe | 1103 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 340:28d1f895c6fe | 1104 | /*------------------------------ USB Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1105 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) |
mbed_official | 340:28d1f895c6fe | 1106 | { |
mbed_official | 340:28d1f895c6fe | 1107 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1108 | assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1109 | |
mbed_official | 340:28d1f895c6fe | 1110 | /* Configure the USB clock source */ |
mbed_official | 340:28d1f895c6fe | 1111 | __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); |
mbed_official | 340:28d1f895c6fe | 1112 | } |
mbed_official | 340:28d1f895c6fe | 1113 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
mbed_official | 340:28d1f895c6fe | 1114 | |
mbed_official | 340:28d1f895c6fe | 1115 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 340:28d1f895c6fe | 1116 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 340:28d1f895c6fe | 1117 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 1118 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1119 | /*------------------------------ CEC clock Configuration -------------------*/ |
mbed_official | 340:28d1f895c6fe | 1120 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) |
mbed_official | 340:28d1f895c6fe | 1121 | { |
mbed_official | 340:28d1f895c6fe | 1122 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1123 | assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); |
mbed_official | 340:28d1f895c6fe | 1124 | |
mbed_official | 340:28d1f895c6fe | 1125 | /* Configure the CEC clock source */ |
mbed_official | 340:28d1f895c6fe | 1126 | __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); |
mbed_official | 340:28d1f895c6fe | 1127 | } |
mbed_official | 340:28d1f895c6fe | 1128 | #endif /* STM32F042x6 || STM32F048xx || */ |
mbed_official | 340:28d1f895c6fe | 1129 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 340:28d1f895c6fe | 1130 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 1131 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1132 | |
mbed_official | 340:28d1f895c6fe | 1133 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1134 | } |
mbed_official | 340:28d1f895c6fe | 1135 | |
mbed_official | 340:28d1f895c6fe | 1136 | /** |
mbed_official | 340:28d1f895c6fe | 1137 | * @brief Get the RCC_ClkInitStruct according to the internal |
mbed_official | 340:28d1f895c6fe | 1138 | * RCC configuration registers. |
mbed_official | 340:28d1f895c6fe | 1139 | * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that |
mbed_official | 340:28d1f895c6fe | 1140 | * returns the configuration information for the Extended Peripherals clocks |
mbed_official | 340:28d1f895c6fe | 1141 | * (USART, RTC, I2C, CEC and USB). |
mbed_official | 340:28d1f895c6fe | 1142 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1143 | */ |
mbed_official | 340:28d1f895c6fe | 1144 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
mbed_official | 340:28d1f895c6fe | 1145 | { |
mbed_official | 340:28d1f895c6fe | 1146 | /* Set all possible values for the extended clock type parameter------------*/ |
mbed_official | 340:28d1f895c6fe | 1147 | /* Common part first */ |
mbed_official | 340:28d1f895c6fe | 1148 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; |
mbed_official | 340:28d1f895c6fe | 1149 | /* Get the RTC configuration --------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1150 | PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1151 | /* Get the USART1 configuration --------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1152 | PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1153 | /* Get the I2C1 clock source -----------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1154 | PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1155 | |
mbed_official | 340:28d1f895c6fe | 1156 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 1157 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1158 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; |
mbed_official | 340:28d1f895c6fe | 1159 | /* Get the USART2 clock source ---------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1160 | PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1161 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 1162 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1163 | |
mbed_official | 340:28d1f895c6fe | 1164 | #if defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1165 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; |
mbed_official | 340:28d1f895c6fe | 1166 | /* Get the USART3 clock source ---------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1167 | PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1168 | #endif /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1169 | |
mbed_official | 340:28d1f895c6fe | 1170 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) |
mbed_official | 340:28d1f895c6fe | 1171 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; |
mbed_official | 340:28d1f895c6fe | 1172 | /* Get the USB clock source ---------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1173 | PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1174 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */ |
mbed_official | 340:28d1f895c6fe | 1175 | |
mbed_official | 340:28d1f895c6fe | 1176 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 340:28d1f895c6fe | 1177 | defined(STM32F051x8) || defined(STM32F058xx) || \ |
mbed_official | 340:28d1f895c6fe | 1178 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 1179 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1180 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; |
mbed_official | 340:28d1f895c6fe | 1181 | /* Get the CEC clock source ------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1182 | PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); |
mbed_official | 340:28d1f895c6fe | 1183 | #endif /* STM32F042x6 || STM32F048xx || */ |
mbed_official | 340:28d1f895c6fe | 1184 | /* STM32F051x8 || STM32F058xx || */ |
mbed_official | 340:28d1f895c6fe | 1185 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 1186 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1187 | |
mbed_official | 340:28d1f895c6fe | 1188 | } |
mbed_official | 340:28d1f895c6fe | 1189 | |
mbed_official | 340:28d1f895c6fe | 1190 | #if defined(STM32F042x6) || defined(STM32F048xx) || \ |
mbed_official | 340:28d1f895c6fe | 1191 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \ |
mbed_official | 340:28d1f895c6fe | 1192 | defined(STM32F091xC) || defined(STM32F098xx) |
mbed_official | 340:28d1f895c6fe | 1193 | /** |
mbed_official | 340:28d1f895c6fe | 1194 | * @brief Start automatic synchronization using polling mode |
mbed_official | 340:28d1f895c6fe | 1195 | * @param pInit Pointer on RCC_CRSInitTypeDef structure |
mbed_official | 340:28d1f895c6fe | 1196 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1197 | */ |
mbed_official | 340:28d1f895c6fe | 1198 | void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) |
mbed_official | 340:28d1f895c6fe | 1199 | { |
mbed_official | 340:28d1f895c6fe | 1200 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1201 | assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); |
mbed_official | 340:28d1f895c6fe | 1202 | assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); |
mbed_official | 340:28d1f895c6fe | 1203 | assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); |
mbed_official | 340:28d1f895c6fe | 1204 | assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); |
mbed_official | 340:28d1f895c6fe | 1205 | assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); |
mbed_official | 340:28d1f895c6fe | 1206 | assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); |
mbed_official | 340:28d1f895c6fe | 1207 | |
mbed_official | 340:28d1f895c6fe | 1208 | |
mbed_official | 340:28d1f895c6fe | 1209 | /* CONFIGURATION */ |
mbed_official | 340:28d1f895c6fe | 1210 | |
mbed_official | 340:28d1f895c6fe | 1211 | /* Before configuration, reset CRS registers to their default values*/ |
mbed_official | 340:28d1f895c6fe | 1212 | __CRS_FORCE_RESET(); |
mbed_official | 340:28d1f895c6fe | 1213 | __CRS_RELEASE_RESET(); |
mbed_official | 340:28d1f895c6fe | 1214 | |
mbed_official | 340:28d1f895c6fe | 1215 | /* Configure Synchronization input */ |
mbed_official | 340:28d1f895c6fe | 1216 | /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ |
mbed_official | 340:28d1f895c6fe | 1217 | CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL); |
mbed_official | 340:28d1f895c6fe | 1218 | |
mbed_official | 340:28d1f895c6fe | 1219 | /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */ |
mbed_official | 340:28d1f895c6fe | 1220 | CRS->CFGR |= pInit->Prescaler; |
mbed_official | 340:28d1f895c6fe | 1221 | |
mbed_official | 340:28d1f895c6fe | 1222 | /* Set the SYNCSRC[1:0] bits according to Source value */ |
mbed_official | 340:28d1f895c6fe | 1223 | CRS->CFGR |= pInit->Source; |
mbed_official | 340:28d1f895c6fe | 1224 | |
mbed_official | 340:28d1f895c6fe | 1225 | /* Set the SYNCSPOL bits according to Polarity value */ |
mbed_official | 340:28d1f895c6fe | 1226 | CRS->CFGR |= pInit->Polarity; |
mbed_official | 340:28d1f895c6fe | 1227 | |
mbed_official | 340:28d1f895c6fe | 1228 | /* Configure Frequency Error Measurement */ |
mbed_official | 340:28d1f895c6fe | 1229 | /* Clear RELOAD[15:0] & FELIM[7:0] bits*/ |
mbed_official | 340:28d1f895c6fe | 1230 | CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM); |
mbed_official | 340:28d1f895c6fe | 1231 | |
mbed_official | 340:28d1f895c6fe | 1232 | /* Set the RELOAD[15:0] bits according to ReloadValue value */ |
mbed_official | 340:28d1f895c6fe | 1233 | CRS->CFGR |= pInit->ReloadValue; |
mbed_official | 340:28d1f895c6fe | 1234 | |
mbed_official | 340:28d1f895c6fe | 1235 | /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ |
mbed_official | 340:28d1f895c6fe | 1236 | CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER); |
mbed_official | 340:28d1f895c6fe | 1237 | |
mbed_official | 340:28d1f895c6fe | 1238 | /* Adjust HSI48 oscillator smooth trimming */ |
mbed_official | 340:28d1f895c6fe | 1239 | /* Clear TRIM[5:0] bits */ |
mbed_official | 340:28d1f895c6fe | 1240 | CRS->CR &= ~CRS_CR_TRIM; |
mbed_official | 340:28d1f895c6fe | 1241 | |
mbed_official | 340:28d1f895c6fe | 1242 | /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ |
mbed_official | 340:28d1f895c6fe | 1243 | CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER); |
mbed_official | 340:28d1f895c6fe | 1244 | |
mbed_official | 340:28d1f895c6fe | 1245 | |
mbed_official | 340:28d1f895c6fe | 1246 | /* START AUTOMATIC SYNCHRONIZATION*/ |
mbed_official | 340:28d1f895c6fe | 1247 | |
mbed_official | 340:28d1f895c6fe | 1248 | /* Enable Automatic trimming */ |
mbed_official | 340:28d1f895c6fe | 1249 | __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB(); |
mbed_official | 340:28d1f895c6fe | 1250 | |
mbed_official | 340:28d1f895c6fe | 1251 | /* Enable Frequency error counter */ |
mbed_official | 340:28d1f895c6fe | 1252 | __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER(); |
mbed_official | 340:28d1f895c6fe | 1253 | |
mbed_official | 340:28d1f895c6fe | 1254 | } |
mbed_official | 340:28d1f895c6fe | 1255 | |
mbed_official | 340:28d1f895c6fe | 1256 | /** |
mbed_official | 340:28d1f895c6fe | 1257 | * @brief Generate the software synchronization event |
mbed_official | 340:28d1f895c6fe | 1258 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1259 | */ |
mbed_official | 340:28d1f895c6fe | 1260 | void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) |
mbed_official | 340:28d1f895c6fe | 1261 | { |
mbed_official | 340:28d1f895c6fe | 1262 | CRS->CR |= CRS_CR_SWSYNC; |
mbed_official | 340:28d1f895c6fe | 1263 | } |
mbed_official | 340:28d1f895c6fe | 1264 | |
mbed_official | 340:28d1f895c6fe | 1265 | |
mbed_official | 340:28d1f895c6fe | 1266 | /** |
mbed_official | 340:28d1f895c6fe | 1267 | * @brief Function to return synchronization info |
mbed_official | 340:28d1f895c6fe | 1268 | * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure |
mbed_official | 340:28d1f895c6fe | 1269 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1270 | */ |
mbed_official | 340:28d1f895c6fe | 1271 | void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) |
mbed_official | 340:28d1f895c6fe | 1272 | { |
mbed_official | 340:28d1f895c6fe | 1273 | /* Check the parameter */ |
mbed_official | 340:28d1f895c6fe | 1274 | assert_param(pSynchroInfo != HAL_NULL); |
mbed_official | 340:28d1f895c6fe | 1275 | |
mbed_official | 340:28d1f895c6fe | 1276 | /* Get the reload value */ |
mbed_official | 340:28d1f895c6fe | 1277 | pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); |
mbed_official | 340:28d1f895c6fe | 1278 | |
mbed_official | 340:28d1f895c6fe | 1279 | /* Get HSI48 oscillator smooth trimming */ |
mbed_official | 340:28d1f895c6fe | 1280 | pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER); |
mbed_official | 340:28d1f895c6fe | 1281 | |
mbed_official | 340:28d1f895c6fe | 1282 | /* Get Frequency error capture */ |
mbed_official | 340:28d1f895c6fe | 1283 | pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER); |
mbed_official | 340:28d1f895c6fe | 1284 | |
mbed_official | 340:28d1f895c6fe | 1285 | /* Get FFrequency error direction */ |
mbed_official | 340:28d1f895c6fe | 1286 | pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR); |
mbed_official | 340:28d1f895c6fe | 1287 | |
mbed_official | 340:28d1f895c6fe | 1288 | |
mbed_official | 340:28d1f895c6fe | 1289 | } |
mbed_official | 340:28d1f895c6fe | 1290 | |
mbed_official | 340:28d1f895c6fe | 1291 | /** |
mbed_official | 340:28d1f895c6fe | 1292 | * @brief This function handles CRS Synchronization Timeout. |
mbed_official | 340:28d1f895c6fe | 1293 | * @param Timeout: Duration of the timeout |
mbed_official | 340:28d1f895c6fe | 1294 | * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization |
mbed_official | 340:28d1f895c6fe | 1295 | * frequency. |
mbed_official | 340:28d1f895c6fe | 1296 | * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. |
mbed_official | 340:28d1f895c6fe | 1297 | * @retval Combination of Synchronization status |
mbed_official | 340:28d1f895c6fe | 1298 | * This parameter can be a combination of the following values: |
mbed_official | 340:28d1f895c6fe | 1299 | * @arg RCC_CRS_TIMEOUT |
mbed_official | 340:28d1f895c6fe | 1300 | * @arg RCC_CRS_SYNCOK |
mbed_official | 340:28d1f895c6fe | 1301 | * @arg RCC_CRS_SYNCWARM |
mbed_official | 340:28d1f895c6fe | 1302 | * @arg RCC_CRS_SYNCERR |
mbed_official | 340:28d1f895c6fe | 1303 | * @arg RCC_CRS_SYNCMISS |
mbed_official | 340:28d1f895c6fe | 1304 | * @arg RCC_CRS_TRIMOV |
mbed_official | 340:28d1f895c6fe | 1305 | */ |
mbed_official | 340:28d1f895c6fe | 1306 | RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) |
mbed_official | 340:28d1f895c6fe | 1307 | { |
mbed_official | 340:28d1f895c6fe | 1308 | RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE; |
mbed_official | 340:28d1f895c6fe | 1309 | uint32_t tickstart = 0; |
mbed_official | 340:28d1f895c6fe | 1310 | |
mbed_official | 340:28d1f895c6fe | 1311 | /* Get timeout */ |
mbed_official | 340:28d1f895c6fe | 1312 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 1313 | |
mbed_official | 340:28d1f895c6fe | 1314 | /* Check that if one of CRS flags have been set */ |
mbed_official | 340:28d1f895c6fe | 1315 | while(RCC_CRS_NONE == crsstatus) |
mbed_official | 340:28d1f895c6fe | 1316 | { |
mbed_official | 340:28d1f895c6fe | 1317 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 340:28d1f895c6fe | 1318 | { |
mbed_official | 340:28d1f895c6fe | 1319 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
mbed_official | 340:28d1f895c6fe | 1320 | { |
mbed_official | 340:28d1f895c6fe | 1321 | crsstatus = RCC_CRS_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1322 | } |
mbed_official | 340:28d1f895c6fe | 1323 | } |
mbed_official | 340:28d1f895c6fe | 1324 | /* Check CRS SYNCOK flag */ |
mbed_official | 340:28d1f895c6fe | 1325 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) |
mbed_official | 340:28d1f895c6fe | 1326 | { |
mbed_official | 340:28d1f895c6fe | 1327 | /* CRS SYNC event OK */ |
mbed_official | 340:28d1f895c6fe | 1328 | crsstatus |= RCC_CRS_SYNCOK; |
mbed_official | 340:28d1f895c6fe | 1329 | |
mbed_official | 340:28d1f895c6fe | 1330 | /* Clear CRS SYNC event OK bit */ |
mbed_official | 340:28d1f895c6fe | 1331 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); |
mbed_official | 340:28d1f895c6fe | 1332 | } |
mbed_official | 340:28d1f895c6fe | 1333 | |
mbed_official | 340:28d1f895c6fe | 1334 | /* Check CRS SYNCWARN flag */ |
mbed_official | 340:28d1f895c6fe | 1335 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) |
mbed_official | 340:28d1f895c6fe | 1336 | { |
mbed_official | 340:28d1f895c6fe | 1337 | /* CRS SYNC warning */ |
mbed_official | 340:28d1f895c6fe | 1338 | crsstatus |= RCC_CRS_SYNCWARM; |
mbed_official | 340:28d1f895c6fe | 1339 | |
mbed_official | 340:28d1f895c6fe | 1340 | /* Clear CRS SYNCWARN bit */ |
mbed_official | 340:28d1f895c6fe | 1341 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); |
mbed_official | 340:28d1f895c6fe | 1342 | } |
mbed_official | 340:28d1f895c6fe | 1343 | |
mbed_official | 340:28d1f895c6fe | 1344 | /* Check CRS TRIM overflow flag */ |
mbed_official | 340:28d1f895c6fe | 1345 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) |
mbed_official | 340:28d1f895c6fe | 1346 | { |
mbed_official | 340:28d1f895c6fe | 1347 | /* CRS SYNC Error */ |
mbed_official | 340:28d1f895c6fe | 1348 | crsstatus |= RCC_CRS_TRIMOV; |
mbed_official | 340:28d1f895c6fe | 1349 | |
mbed_official | 340:28d1f895c6fe | 1350 | /* Clear CRS Error bit */ |
mbed_official | 340:28d1f895c6fe | 1351 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); |
mbed_official | 340:28d1f895c6fe | 1352 | } |
mbed_official | 340:28d1f895c6fe | 1353 | |
mbed_official | 340:28d1f895c6fe | 1354 | /* Check CRS Error flag */ |
mbed_official | 340:28d1f895c6fe | 1355 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) |
mbed_official | 340:28d1f895c6fe | 1356 | { |
mbed_official | 340:28d1f895c6fe | 1357 | /* CRS SYNC Error */ |
mbed_official | 340:28d1f895c6fe | 1358 | crsstatus |= RCC_CRS_SYNCERR; |
mbed_official | 340:28d1f895c6fe | 1359 | |
mbed_official | 340:28d1f895c6fe | 1360 | /* Clear CRS Error bit */ |
mbed_official | 340:28d1f895c6fe | 1361 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); |
mbed_official | 340:28d1f895c6fe | 1362 | } |
mbed_official | 340:28d1f895c6fe | 1363 | |
mbed_official | 340:28d1f895c6fe | 1364 | /* Check CRS SYNC Missed flag */ |
mbed_official | 340:28d1f895c6fe | 1365 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) |
mbed_official | 340:28d1f895c6fe | 1366 | { |
mbed_official | 340:28d1f895c6fe | 1367 | /* CRS SYNC Missed */ |
mbed_official | 340:28d1f895c6fe | 1368 | crsstatus |= RCC_CRS_SYNCMISS; |
mbed_official | 340:28d1f895c6fe | 1369 | |
mbed_official | 340:28d1f895c6fe | 1370 | /* Clear CRS SYNC Missed bit */ |
mbed_official | 340:28d1f895c6fe | 1371 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); |
mbed_official | 340:28d1f895c6fe | 1372 | } |
mbed_official | 340:28d1f895c6fe | 1373 | |
mbed_official | 340:28d1f895c6fe | 1374 | /* Check CRS Expected SYNC flag */ |
mbed_official | 340:28d1f895c6fe | 1375 | if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) |
mbed_official | 340:28d1f895c6fe | 1376 | { |
mbed_official | 340:28d1f895c6fe | 1377 | /* frequency error counter reached a zero value */ |
mbed_official | 340:28d1f895c6fe | 1378 | __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); |
mbed_official | 340:28d1f895c6fe | 1379 | } |
mbed_official | 340:28d1f895c6fe | 1380 | } |
mbed_official | 340:28d1f895c6fe | 1381 | |
mbed_official | 340:28d1f895c6fe | 1382 | return crsstatus; |
mbed_official | 340:28d1f895c6fe | 1383 | } |
mbed_official | 340:28d1f895c6fe | 1384 | |
mbed_official | 340:28d1f895c6fe | 1385 | #endif /* STM32F042x6 || STM32F048xx || */ |
mbed_official | 340:28d1f895c6fe | 1386 | /* STM32F071xB || STM32F072xB || STM32F078xx || */ |
mbed_official | 340:28d1f895c6fe | 1387 | /* STM32F091xC || STM32F098xx */ |
mbed_official | 340:28d1f895c6fe | 1388 | |
mbed_official | 340:28d1f895c6fe | 1389 | /** |
mbed_official | 340:28d1f895c6fe | 1390 | * @} |
mbed_official | 340:28d1f895c6fe | 1391 | */ |
mbed_official | 340:28d1f895c6fe | 1392 | |
mbed_official | 340:28d1f895c6fe | 1393 | /** |
mbed_official | 340:28d1f895c6fe | 1394 | * @} |
mbed_official | 340:28d1f895c6fe | 1395 | */ |
mbed_official | 340:28d1f895c6fe | 1396 | |
mbed_official | 340:28d1f895c6fe | 1397 | #endif /* HAL_RCC_MODULE_ENABLED */ |
mbed_official | 340:28d1f895c6fe | 1398 | /** |
mbed_official | 340:28d1f895c6fe | 1399 | * @} |
mbed_official | 340:28d1f895c6fe | 1400 | */ |
mbed_official | 340:28d1f895c6fe | 1401 | |
mbed_official | 340:28d1f895c6fe | 1402 | /** |
mbed_official | 340:28d1f895c6fe | 1403 | * @} |
mbed_official | 340:28d1f895c6fe | 1404 | */ |
mbed_official | 340:28d1f895c6fe | 1405 | |
mbed_official | 340:28d1f895c6fe | 1406 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |