Diff: targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c

Revision:

129:0182c99221bc

Parent:

106:ced8cbb51063

Child:

139:e3413eddde57

--- a/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c	Wed Mar 19 18:20:52 2014 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c	Thu Mar 20 11:45:07 2014 +0000
@@ -3,7 +3,7 @@
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
   * @version V1.2.0
-  * @date    11-January-2014
+  * @date    14-March-2014
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *          This file contains the system clock configuration for STM32L1xx Ultra
   *          Low power devices, and is generated by the clock configuration 
@@ -43,11 +43,11 @@
   *=============================================================================
   *                         System Clock Configuration
   *=============================================================================
-  *        System clock source          | HSI
+  *        System Clock source          | PLL(HSI)
   *----------------------------------------------------------------------------- 
-  *        SYSCLK                       | 16000000 Hz
+  *        SYSCLK                       | 32000000 Hz
   *----------------------------------------------------------------------------- 
-  *        HCLK                         | 16000000 Hz
+  *        HCLK                         | 32000000 Hz
   *----------------------------------------------------------------------------- 
   *        AHB Prescaler                | 1
   *----------------------------------------------------------------------------- 
@@ -55,17 +55,17 @@
   *----------------------------------------------------------------------------- 
   *        APB2 Prescaler               | 1
   *----------------------------------------------------------------------------- 
-  *        HSE Frequency                | 8000000 Hz
+  *        HSE Frequency                | Not used
   *----------------------------------------------------------------------------- 
-  *        PLL DIV                      | Not Used
+  *        PLL DIV                      | 2
   *----------------------------------------------------------------------------- 
-  *        PLL MUL                      | Not Used
+  *        PLL MUL                      | 4
   *----------------------------------------------------------------------------- 
   *        VDD                          | 3.3 V
   *----------------------------------------------------------------------------- 
   *        Vcore                        | 1.8 V (Range 1)
   *----------------------------------------------------------------------------- 
-  *        Flash Latency                | 0 WS
+  *        Flash Latency                | 1 WS
   *----------------------------------------------------------------------------- 
   *        Require 48MHz for USB clock  | Disabled
   *----------------------------------------------------------------------------- 
@@ -149,7 +149,7 @@
 /** @addtogroup STM32L1xx_System_Private_Variables
   * @{
   */
-uint32_t SystemCoreClock    = 16000000;
+uint32_t SystemCoreClock = 32000000;
 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 
@@ -161,7 +161,7 @@
   * @{
   */
 
-static void SetSysClock(void);
+void SetSysClock(void);
 
 /**
   * @}
@@ -206,6 +206,23 @@
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 #endif
+
+  /* ADDED FOR MBED DEBUG PURPOSE */
+  /*
+  // Enable the GPIOA peripheral
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+  // Output the system clock on MCO pin (PA.08)
+  GPIO_InitTypeDef GPIO_InitStructure;
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
+  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;  
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+  // Select the clock to output on MCO pin (PA.08)
+  RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCODiv_1);
+  //RCC_MCOConfig(RCC_MCOSource_HSI, RCC_MCODiv_1);
+  */
 }
 
 /**
@@ -305,7 +322,7 @@
   * @param  None
   * @retval None
   */
-static void SetSysClock(void)
+void SetSysClock(void)
 {
   __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
   
@@ -330,42 +347,54 @@
     
   if (HSIStatus == (uint32_t)0x01)
   {
-    /* Flash 0 wait state */
-    FLASH->ACR &= ~FLASH_ACR_LATENCY;
+    /* Enable 64-bit access */
+    FLASH->ACR |= FLASH_ACR_ACC64;
     
-    /* Disable Prefetch Buffer */
-    FLASH->ACR &= ~FLASH_ACR_PRFTEN;
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
 
-    /* Disable 64-bit access */
-    FLASH->ACR &= ~FLASH_ACR_ACC64;
+    /* Flash 1 wait state (latency) */
+    FLASH->ACR |= FLASH_ACR_LATENCY;
     
-
     /* Power enable */
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
   
     /* Select the Voltage Range 1 (1.8 V) */
     PWR->CR = PWR_CR_VOS_0;
-  
-  
+
     /* Wait Until the Voltage Regulator is ready */
     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
     {
     }
-      
-    /* HCLK = SYSCLK /1*/
+
+    /* PLL configuration */
+    /* SYSCLK = (HSI 16 MHz * 4) / 2 = 32 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2);
+
+    /* HCLK = 32 MHz */
     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-    /* PCLK2 = HCLK /1*/
+  
+    /* PCLK2 = 32 MHz */
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
     
-    /* PCLK1 = HCLK /1*/
+    /* PCLK1 = 32 MHz */
     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
-    
-    /* Select HSI as system clock source */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+        
+    /* Select PLL as system clock source */
     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 
-    /* Wait till HSI is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
     {
     }
   }