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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c@441:d2c15dda23c1, 2015-01-06 (annotated)

Committer:: mbed_official
Date:: Tue Jan 06 16:15:36 2015 +0000
Revision:: 441:d2c15dda23c1
Parent:: 392:2b59412bb664

Synchronized with git revision 245a60b29caabb42eabdd19658eeac7c3f68313b

Full URL: https://github.com/mbedmicro/mbed/commit/245a60b29caabb42eabdd19658eeac7c3f68313b/

NUCLEO_F072RB/F091RC - adding target to rtos lib and exporter for coide and gcc_arm

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_tim.c
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	441:d2c15dda23c1	5	* @version V1.2.0
mbed_official	441:d2c15dda23c1	6	* @date 11-December-2014
mbed_official	340:28d1f895c6fe	7	* @brief TIM HAL module driver.
mbed_official	340:28d1f895c6fe	8	* This file provides firmware functions to manage the following
mbed_official	340:28d1f895c6fe	9	* functionalities of the Timer (TIM) peripheral:
mbed_official	340:28d1f895c6fe	10	* + Time Base Initialization
mbed_official	340:28d1f895c6fe	11	* + Time Base Start
mbed_official	340:28d1f895c6fe	12	* + Time Base Start Interruption
mbed_official	340:28d1f895c6fe	13	* + Time Base Start DMA
mbed_official	340:28d1f895c6fe	14	* + Time Output Compare/PWM Initialization
mbed_official	340:28d1f895c6fe	15	* + Time Output Compare/PWM Channel Configuration
mbed_official	340:28d1f895c6fe	16	* + Time Output Compare/PWM Start
mbed_official	340:28d1f895c6fe	17	* + Time Output Compare/PWM Start Interruption
mbed_official	340:28d1f895c6fe	18	* + Time Output Compare/PWM Start DMA
mbed_official	340:28d1f895c6fe	19	* + Time Input Capture Initialization
mbed_official	340:28d1f895c6fe	20	* + Time Input Capture Channel Configuration
mbed_official	340:28d1f895c6fe	21	* + Time Input Capture Start
mbed_official	340:28d1f895c6fe	22	* + Time Input Capture Start Interruption
mbed_official	340:28d1f895c6fe	23	* + Time Input Capture Start DMA
mbed_official	340:28d1f895c6fe	24	* + Time One Pulse Initialization
mbed_official	340:28d1f895c6fe	25	* + Time One Pulse Channel Configuration
mbed_official	340:28d1f895c6fe	26	* + Time One Pulse Start
mbed_official	340:28d1f895c6fe	27	* + Time Encoder Interface Initialization
mbed_official	340:28d1f895c6fe	28	* + Time Encoder Interface Start
mbed_official	340:28d1f895c6fe	29	* + Time Encoder Interface Start Interruption
mbed_official	340:28d1f895c6fe	30	* + Time Encoder Interface Start DMA
mbed_official	340:28d1f895c6fe	31	* + Commutation Event configuration with Interruption and DMA
mbed_official	340:28d1f895c6fe	32	* + Time OCRef clear configuration
mbed_official	340:28d1f895c6fe	33	* + Time External Clock configuration
mbed_official	340:28d1f895c6fe	34	@verbatim
mbed_official	340:28d1f895c6fe	35	==============================================================================
mbed_official	340:28d1f895c6fe	36	##### TIMER Generic features #####
mbed_official	340:28d1f895c6fe	37	==============================================================================
mbed_official	340:28d1f895c6fe	38	[..] The Timer features include:
mbed_official	340:28d1f895c6fe	39	(#) 16-bit up, down, up/down auto-reload counter.
mbed_official	340:28d1f895c6fe	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official	340:28d1f895c6fe	41	counter clock frequency either by any factor between 1 and 65536.
mbed_official	340:28d1f895c6fe	42	(#) Up to 4 independent channels for:
mbed_official	340:28d1f895c6fe	43	(++) Input Capture
mbed_official	340:28d1f895c6fe	44	(++) Output Compare
mbed_official	340:28d1f895c6fe	45	(++) PWM generation (Edge and Center-aligned Mode)
mbed_official	340:28d1f895c6fe	46	(++) One-pulse mode output
mbed_official	340:28d1f895c6fe	47
mbed_official	340:28d1f895c6fe	48	##### How to use this driver #####
mbed_official	340:28d1f895c6fe	49	==============================================================================
mbed_official	340:28d1f895c6fe	50	[..]
mbed_official	340:28d1f895c6fe	51	(#) Initialize the TIM low level resources by implementing the following functions
mbed_official	340:28d1f895c6fe	52	depending from feature used :
mbed_official	340:28d1f895c6fe	53	(++) Time Base : HAL_TIM_Base_MspInit()
mbed_official	340:28d1f895c6fe	54	(++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official	340:28d1f895c6fe	55	(++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official	340:28d1f895c6fe	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official	340:28d1f895c6fe	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official	340:28d1f895c6fe	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official	340:28d1f895c6fe	59
mbed_official	340:28d1f895c6fe	60	(#) Initialize the TIM low level resources :
mbed_official	340:28d1f895c6fe	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official	340:28d1f895c6fe	62	(##) TIM pins configuration
mbed_official	340:28d1f895c6fe	63	(+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official	340:28d1f895c6fe	64	__GPIOx_CLK_ENABLE();
mbed_official	340:28d1f895c6fe	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official	340:28d1f895c6fe	66
mbed_official	340:28d1f895c6fe	67	(#) The external Clock can be configured, if needed (the default clock is the
mbed_official	340:28d1f895c6fe	68	internal clock from the APBx), using the following function:
mbed_official	340:28d1f895c6fe	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official	340:28d1f895c6fe	70	any start function.
mbed_official	340:28d1f895c6fe	71
mbed_official	340:28d1f895c6fe	72	(#) Configure the TIM in the desired functioning mode using one of the
mbed_official	340:28d1f895c6fe	73	Initialization function of this driver:
mbed_official	340:28d1f895c6fe	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official	340:28d1f895c6fe	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official	340:28d1f895c6fe	76	Output Compare signal.
mbed_official	340:28d1f895c6fe	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official	340:28d1f895c6fe	78	PWM signal.
mbed_official	340:28d1f895c6fe	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official	340:28d1f895c6fe	80	external signal.
mbed_official	340:28d1f895c6fe	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official	340:28d1f895c6fe	82	in One Pulse Mode.
mbed_official	340:28d1f895c6fe	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official	340:28d1f895c6fe	84
mbed_official	340:28d1f895c6fe	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official	340:28d1f895c6fe	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official	340:28d1f895c6fe	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official	340:28d1f895c6fe	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official	340:28d1f895c6fe	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official	340:28d1f895c6fe	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official	340:28d1f895c6fe	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official	340:28d1f895c6fe	92
mbed_official	340:28d1f895c6fe	93	(#) The DMA Burst is managed with the two following functions:
mbed_official	340:28d1f895c6fe	94	HAL_TIM_DMABurst_WriteStart()
mbed_official	340:28d1f895c6fe	95	HAL_TIM_DMABurst_ReadStart()
mbed_official	340:28d1f895c6fe	96
mbed_official	340:28d1f895c6fe	97	@endverbatim
mbed_official	340:28d1f895c6fe	98	******************************************************************************
mbed_official	340:28d1f895c6fe	99	* @attention
mbed_official	340:28d1f895c6fe	100	*
mbed_official	340:28d1f895c6fe	101	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	102	*
mbed_official	340:28d1f895c6fe	103	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	104	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	105	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	106	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	108	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	109	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	111	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	112	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	113	*
mbed_official	340:28d1f895c6fe	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	124	*
mbed_official	340:28d1f895c6fe	125	******************************************************************************
mbed_official	340:28d1f895c6fe	126	*/
mbed_official	340:28d1f895c6fe	127
mbed_official	340:28d1f895c6fe	128	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	129	#include "stm32f0xx_hal.h"
mbed_official	340:28d1f895c6fe	130
mbed_official	340:28d1f895c6fe	131	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	132	* @{
mbed_official	340:28d1f895c6fe	133	*/
mbed_official	340:28d1f895c6fe	134
mbed_official	340:28d1f895c6fe	135	/** @defgroup TIM TIM HAL module driver
mbed_official	340:28d1f895c6fe	136	* @brief TIM HAL module driver
mbed_official	340:28d1f895c6fe	137	* @{
mbed_official	340:28d1f895c6fe	138	*/
mbed_official	340:28d1f895c6fe	139
mbed_official	340:28d1f895c6fe	140	#ifdef HAL_TIM_MODULE_ENABLED
mbed_official	340:28d1f895c6fe	141
mbed_official	340:28d1f895c6fe	142	/* Private typedef -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	143	/* Private define ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	144	/* Private macro -------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	145	/* Private variables ---------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	146	/* Private function prototypes -----------------------------------------------*/
mbed_official	340:28d1f895c6fe	147
mbed_official	340:28d1f895c6fe	148	/** @defgroup TIM_Private_Functions TIM_Private_Functions
mbed_official	340:28d1f895c6fe	149	* @{
mbed_official	340:28d1f895c6fe	150	*/
mbed_official	340:28d1f895c6fe	151	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	340:28d1f895c6fe	152	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	340:28d1f895c6fe	153	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	340:28d1f895c6fe	154	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	155	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	156	uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	157	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	158	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	159	uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	160	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	161	uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	162	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	340:28d1f895c6fe	163	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official	340:28d1f895c6fe	164	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
mbed_official	340:28d1f895c6fe	165	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	166	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	167	static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official	340:28d1f895c6fe	168	TIM_SlaveConfigTypeDef * sSlaveConfig);
mbed_official	340:28d1f895c6fe	169
mbed_official	340:28d1f895c6fe	170	/**
mbed_official	340:28d1f895c6fe	171	* @}
mbed_official	340:28d1f895c6fe	172	*/
mbed_official	340:28d1f895c6fe	173
mbed_official	340:28d1f895c6fe	174	/* Exported functions ---------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	175
mbed_official	340:28d1f895c6fe	176	/** @defgroup TIM_Exported_Functions TIM Exported Functions
mbed_official	340:28d1f895c6fe	177	* @{
mbed_official	340:28d1f895c6fe	178	*/
mbed_official	340:28d1f895c6fe	179
mbed_official	340:28d1f895c6fe	180	/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
mbed_official	340:28d1f895c6fe	181	* @brief Time Base functions
mbed_official	340:28d1f895c6fe	182	*
mbed_official	340:28d1f895c6fe	183	@verbatim
mbed_official	340:28d1f895c6fe	184	==============================================================================
mbed_official	340:28d1f895c6fe	185	##### Time Base functions #####
mbed_official	340:28d1f895c6fe	186	==============================================================================
mbed_official	340:28d1f895c6fe	187	[..]
mbed_official	340:28d1f895c6fe	188	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	189	(+) Initialize and configure the TIM base.
mbed_official	340:28d1f895c6fe	190	(+) De-initialize the TIM base.
mbed_official	340:28d1f895c6fe	191	(+) Start the Time Base.
mbed_official	340:28d1f895c6fe	192	(+) Stop the Time Base.
mbed_official	340:28d1f895c6fe	193	(+) Start the Time Base and enable interrupt.
mbed_official	340:28d1f895c6fe	194	(+) Stop the Time Base and disable interrupt.
mbed_official	340:28d1f895c6fe	195	(+) Start the Time Base and enable DMA transfer.
mbed_official	340:28d1f895c6fe	196	(+) Stop the Time Base and disable DMA transfer.
mbed_official	340:28d1f895c6fe	197
mbed_official	340:28d1f895c6fe	198	@endverbatim
mbed_official	340:28d1f895c6fe	199	* @{
mbed_official	340:28d1f895c6fe	200	*/
mbed_official	340:28d1f895c6fe	201	/**
mbed_official	340:28d1f895c6fe	202	* @brief Initializes the TIM Time base Unit according to the specified
mbed_official	340:28d1f895c6fe	203	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	204	* @param htim : TIM Base handle
mbed_official	340:28d1f895c6fe	205	* @retval HAL status
mbed_official	340:28d1f895c6fe	206	*/
mbed_official	340:28d1f895c6fe	207	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	208	{
mbed_official	340:28d1f895c6fe	209	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	210	if(htim == NULL)
mbed_official	340:28d1f895c6fe	211	{
mbed_official	340:28d1f895c6fe	212	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	213	}
mbed_official	340:28d1f895c6fe	214
mbed_official	340:28d1f895c6fe	215	/* Check the parameters */
mbed_official	340:28d1f895c6fe	216	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	217	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	340:28d1f895c6fe	218	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	340:28d1f895c6fe	219
mbed_official	340:28d1f895c6fe	220	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	221	{
mbed_official	340:28d1f895c6fe	222	/* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	223	HAL_TIM_Base_MspInit(htim);
mbed_official	340:28d1f895c6fe	224	}
mbed_official	340:28d1f895c6fe	225
mbed_official	340:28d1f895c6fe	226	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	227	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	228
mbed_official	340:28d1f895c6fe	229	/* Set the Time Base configuration */
mbed_official	340:28d1f895c6fe	230	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	231
mbed_official	340:28d1f895c6fe	232	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	233	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	234
mbed_official	340:28d1f895c6fe	235	return HAL_OK;
mbed_official	340:28d1f895c6fe	236	}
mbed_official	340:28d1f895c6fe	237
mbed_official	340:28d1f895c6fe	238	/**
mbed_official	340:28d1f895c6fe	239	* @brief DeInitializes the TIM Base peripheral
mbed_official	340:28d1f895c6fe	240	* @param htim : TIM Base handle
mbed_official	340:28d1f895c6fe	241	* @retval HAL status
mbed_official	340:28d1f895c6fe	242	*/
mbed_official	340:28d1f895c6fe	243	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	244	{
mbed_official	340:28d1f895c6fe	245	/* Check the parameters */
mbed_official	340:28d1f895c6fe	246	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	247
mbed_official	340:28d1f895c6fe	248	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	249
mbed_official	340:28d1f895c6fe	250	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	251	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	252
mbed_official	340:28d1f895c6fe	253	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	254	HAL_TIM_Base_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	255
mbed_official	340:28d1f895c6fe	256	/* Change TIM state */
mbed_official	340:28d1f895c6fe	257	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	258
mbed_official	340:28d1f895c6fe	259	/* Release Lock */
mbed_official	340:28d1f895c6fe	260	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	261
mbed_official	340:28d1f895c6fe	262	return HAL_OK;
mbed_official	340:28d1f895c6fe	263	}
mbed_official	340:28d1f895c6fe	264
mbed_official	340:28d1f895c6fe	265	/**
mbed_official	340:28d1f895c6fe	266	* @brief Initializes the TIM Base MSP.
mbed_official	340:28d1f895c6fe	267	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	268	* @retval None
mbed_official	340:28d1f895c6fe	269	*/
mbed_official	340:28d1f895c6fe	270	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	271	{
mbed_official	340:28d1f895c6fe	272	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	273	the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	274	*/
mbed_official	340:28d1f895c6fe	275	}
mbed_official	340:28d1f895c6fe	276
mbed_official	340:28d1f895c6fe	277	/**
mbed_official	340:28d1f895c6fe	278	* @brief DeInitializes TIM Base MSP.
mbed_official	340:28d1f895c6fe	279	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	280	* @retval None
mbed_official	340:28d1f895c6fe	281	*/
mbed_official	340:28d1f895c6fe	282	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	283	{
mbed_official	340:28d1f895c6fe	284	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	285	the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	286	*/
mbed_official	340:28d1f895c6fe	287	}
mbed_official	340:28d1f895c6fe	288
mbed_official	340:28d1f895c6fe	289
mbed_official	340:28d1f895c6fe	290	/**
mbed_official	340:28d1f895c6fe	291	* @brief Starts the TIM Base generation.
mbed_official	340:28d1f895c6fe	292	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	293	* @retval HAL status
mbed_official	340:28d1f895c6fe	294	*/
mbed_official	340:28d1f895c6fe	295	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	296	{
mbed_official	340:28d1f895c6fe	297	/* Check the parameters */
mbed_official	340:28d1f895c6fe	298	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	299
mbed_official	340:28d1f895c6fe	300	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	301	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	302
mbed_official	340:28d1f895c6fe	303	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	304	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	305
mbed_official	340:28d1f895c6fe	306	/* Change the TIM state*/
mbed_official	340:28d1f895c6fe	307	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	308
mbed_official	340:28d1f895c6fe	309	/* Return function status */
mbed_official	340:28d1f895c6fe	310	return HAL_OK;
mbed_official	340:28d1f895c6fe	311	}
mbed_official	340:28d1f895c6fe	312
mbed_official	340:28d1f895c6fe	313	/**
mbed_official	340:28d1f895c6fe	314	* @brief Stops the TIM Base generation.
mbed_official	340:28d1f895c6fe	315	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	316	* @retval HAL status
mbed_official	340:28d1f895c6fe	317	*/
mbed_official	340:28d1f895c6fe	318	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	319	{
mbed_official	340:28d1f895c6fe	320	/* Check the parameters */
mbed_official	340:28d1f895c6fe	321	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	322
mbed_official	340:28d1f895c6fe	323	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	324	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	325
mbed_official	340:28d1f895c6fe	326	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	327	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	328
mbed_official	340:28d1f895c6fe	329	/* Change the TIM state*/
mbed_official	340:28d1f895c6fe	330	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	331
mbed_official	340:28d1f895c6fe	332	/* Return function status */
mbed_official	340:28d1f895c6fe	333	return HAL_OK;
mbed_official	340:28d1f895c6fe	334	}
mbed_official	340:28d1f895c6fe	335
mbed_official	340:28d1f895c6fe	336	/**
mbed_official	340:28d1f895c6fe	337	* @brief Starts the TIM Base generation in interrupt mode.
mbed_official	340:28d1f895c6fe	338	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	339	* @retval HAL status
mbed_official	340:28d1f895c6fe	340	*/
mbed_official	340:28d1f895c6fe	341	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	342	{
mbed_official	340:28d1f895c6fe	343	/* Check the parameters */
mbed_official	340:28d1f895c6fe	344	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	345
mbed_official	340:28d1f895c6fe	346	/* Enable the TIM Update interrupt */
mbed_official	340:28d1f895c6fe	347	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	340:28d1f895c6fe	348
mbed_official	340:28d1f895c6fe	349	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	350	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	351
mbed_official	340:28d1f895c6fe	352	/* Return function status */
mbed_official	340:28d1f895c6fe	353	return HAL_OK;
mbed_official	340:28d1f895c6fe	354	}
mbed_official	340:28d1f895c6fe	355
mbed_official	340:28d1f895c6fe	356	/**
mbed_official	340:28d1f895c6fe	357	* @brief Stops the TIM Base generation in interrupt mode.
mbed_official	340:28d1f895c6fe	358	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	359	* @retval HAL status
mbed_official	340:28d1f895c6fe	360	*/
mbed_official	340:28d1f895c6fe	361	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	362	{
mbed_official	340:28d1f895c6fe	363	/* Check the parameters */
mbed_official	340:28d1f895c6fe	364	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	365	/* Disable the TIM Update interrupt */
mbed_official	340:28d1f895c6fe	366	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	340:28d1f895c6fe	367
mbed_official	340:28d1f895c6fe	368	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	369	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	370
mbed_official	340:28d1f895c6fe	371	/* Return function status */
mbed_official	340:28d1f895c6fe	372	return HAL_OK;
mbed_official	340:28d1f895c6fe	373	}
mbed_official	340:28d1f895c6fe	374
mbed_official	340:28d1f895c6fe	375	/**
mbed_official	340:28d1f895c6fe	376	* @brief Starts the TIM Base generation in DMA mode.
mbed_official	340:28d1f895c6fe	377	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	378	* @param pData : The source Buffer address.
mbed_official	340:28d1f895c6fe	379	* @param Length : The length of data to be transferred from memory to peripheral.
mbed_official	340:28d1f895c6fe	380	* @retval HAL status
mbed_official	340:28d1f895c6fe	381	*/
mbed_official	340:28d1f895c6fe	382	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
mbed_official	340:28d1f895c6fe	383	{
mbed_official	340:28d1f895c6fe	384	/* Check the parameters */
mbed_official	340:28d1f895c6fe	385	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	386
mbed_official	340:28d1f895c6fe	387	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	388	{
mbed_official	340:28d1f895c6fe	389	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	390	}
mbed_official	340:28d1f895c6fe	391	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	392	{
mbed_official	340:28d1f895c6fe	393	if((pData == 0 ) && (Length > 0))
mbed_official	340:28d1f895c6fe	394	{
mbed_official	340:28d1f895c6fe	395	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	396	}
mbed_official	340:28d1f895c6fe	397	else
mbed_official	340:28d1f895c6fe	398	{
mbed_official	340:28d1f895c6fe	399	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	400	}
mbed_official	340:28d1f895c6fe	401	}
mbed_official	340:28d1f895c6fe	402	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	403	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	340:28d1f895c6fe	404
mbed_official	340:28d1f895c6fe	405	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	406	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	407
mbed_official	340:28d1f895c6fe	408	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	409	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official	340:28d1f895c6fe	410
mbed_official	340:28d1f895c6fe	411	/* Enable the TIM Update DMA request */
mbed_official	340:28d1f895c6fe	412	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	340:28d1f895c6fe	413
mbed_official	340:28d1f895c6fe	414	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	415	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	416
mbed_official	340:28d1f895c6fe	417	/* Return function status */
mbed_official	340:28d1f895c6fe	418	return HAL_OK;
mbed_official	340:28d1f895c6fe	419	}
mbed_official	340:28d1f895c6fe	420
mbed_official	340:28d1f895c6fe	421	/**
mbed_official	340:28d1f895c6fe	422	* @brief Stops the TIM Base generation in DMA mode.
mbed_official	340:28d1f895c6fe	423	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	424	* @retval HAL status
mbed_official	340:28d1f895c6fe	425	*/
mbed_official	340:28d1f895c6fe	426	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	427	{
mbed_official	340:28d1f895c6fe	428	/* Check the parameters */
mbed_official	340:28d1f895c6fe	429	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	430
mbed_official	340:28d1f895c6fe	431	/* Disable the TIM Update DMA request */
mbed_official	340:28d1f895c6fe	432	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	340:28d1f895c6fe	433
mbed_official	340:28d1f895c6fe	434	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	435	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	436
mbed_official	340:28d1f895c6fe	437	/* Change the htim state */
mbed_official	340:28d1f895c6fe	438	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	439
mbed_official	340:28d1f895c6fe	440	/* Return function status */
mbed_official	340:28d1f895c6fe	441	return HAL_OK;
mbed_official	340:28d1f895c6fe	442	}
mbed_official	340:28d1f895c6fe	443
mbed_official	340:28d1f895c6fe	444	/**
mbed_official	340:28d1f895c6fe	445	* @}
mbed_official	340:28d1f895c6fe	446	*/
mbed_official	340:28d1f895c6fe	447
mbed_official	340:28d1f895c6fe	448	/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
mbed_official	340:28d1f895c6fe	449	* @brief Time Output Compare functions
mbed_official	340:28d1f895c6fe	450	*
mbed_official	340:28d1f895c6fe	451	@verbatim
mbed_official	340:28d1f895c6fe	452	==============================================================================
mbed_official	340:28d1f895c6fe	453	##### Time Output Compare functions #####
mbed_official	340:28d1f895c6fe	454	==============================================================================
mbed_official	340:28d1f895c6fe	455	[..]
mbed_official	340:28d1f895c6fe	456	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	457	(+) Initialize and configure the TIM Output Compare.
mbed_official	340:28d1f895c6fe	458	(+) De-initialize the TIM Output Compare.
mbed_official	340:28d1f895c6fe	459	(+) Start the Time Output Compare.
mbed_official	340:28d1f895c6fe	460	(+) Stop the Time Output Compare.
mbed_official	340:28d1f895c6fe	461	(+) Start the Time Output Compare and enable interrupt.
mbed_official	340:28d1f895c6fe	462	(+) Stop the Time Output Compare and disable interrupt.
mbed_official	340:28d1f895c6fe	463	(+) Start the Time Output Compare and enable DMA transfer.
mbed_official	340:28d1f895c6fe	464	(+) Stop the Time Output Compare and disable DMA transfer.
mbed_official	340:28d1f895c6fe	465
mbed_official	340:28d1f895c6fe	466	@endverbatim
mbed_official	340:28d1f895c6fe	467	* @{
mbed_official	340:28d1f895c6fe	468	*/
mbed_official	340:28d1f895c6fe	469	/**
mbed_official	340:28d1f895c6fe	470	* @brief Initializes the TIM Output Compare according to the specified
mbed_official	340:28d1f895c6fe	471	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	472	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	473	* @retval HAL status
mbed_official	340:28d1f895c6fe	474	*/
mbed_official	340:28d1f895c6fe	475	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official	340:28d1f895c6fe	476	{
mbed_official	340:28d1f895c6fe	477	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	478	if(htim == NULL)
mbed_official	340:28d1f895c6fe	479	{
mbed_official	340:28d1f895c6fe	480	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	481	}
mbed_official	340:28d1f895c6fe	482
mbed_official	340:28d1f895c6fe	483	/* Check the parameters */
mbed_official	340:28d1f895c6fe	484	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	485	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	340:28d1f895c6fe	486	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	340:28d1f895c6fe	487
mbed_official	340:28d1f895c6fe	488	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	489	{
mbed_official	340:28d1f895c6fe	490	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	491	HAL_TIM_OC_MspInit(htim);
mbed_official	340:28d1f895c6fe	492	}
mbed_official	340:28d1f895c6fe	493
mbed_official	340:28d1f895c6fe	494	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	495	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	496
mbed_official	340:28d1f895c6fe	497	/* Init the base time for the Output Compare */
mbed_official	340:28d1f895c6fe	498	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	499
mbed_official	340:28d1f895c6fe	500	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	501	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	502
mbed_official	340:28d1f895c6fe	503	return HAL_OK;
mbed_official	340:28d1f895c6fe	504	}
mbed_official	340:28d1f895c6fe	505
mbed_official	340:28d1f895c6fe	506	/**
mbed_official	340:28d1f895c6fe	507	* @brief DeInitializes the TIM peripheral
mbed_official	340:28d1f895c6fe	508	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	509	* @retval HAL status
mbed_official	340:28d1f895c6fe	510	*/
mbed_official	340:28d1f895c6fe	511	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	512	{
mbed_official	340:28d1f895c6fe	513	/* Check the parameters */
mbed_official	340:28d1f895c6fe	514	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	515
mbed_official	340:28d1f895c6fe	516	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	517
mbed_official	340:28d1f895c6fe	518	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	519	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	520
mbed_official	340:28d1f895c6fe	521	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	522	HAL_TIM_OC_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	523
mbed_official	340:28d1f895c6fe	524	/* Change TIM state */
mbed_official	340:28d1f895c6fe	525	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	526
mbed_official	340:28d1f895c6fe	527	/* Release Lock */
mbed_official	340:28d1f895c6fe	528	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	529
mbed_official	340:28d1f895c6fe	530	return HAL_OK;
mbed_official	340:28d1f895c6fe	531	}
mbed_official	340:28d1f895c6fe	532
mbed_official	340:28d1f895c6fe	533	/**
mbed_official	340:28d1f895c6fe	534	* @brief Initializes the TIM Output Compare MSP.
mbed_official	340:28d1f895c6fe	535	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	536	* @retval None
mbed_official	340:28d1f895c6fe	537	*/
mbed_official	340:28d1f895c6fe	538	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	539	{
mbed_official	340:28d1f895c6fe	540	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	541	the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	542	*/
mbed_official	340:28d1f895c6fe	543	}
mbed_official	340:28d1f895c6fe	544
mbed_official	340:28d1f895c6fe	545	/**
mbed_official	340:28d1f895c6fe	546	* @brief DeInitializes TIM Output Compare MSP.
mbed_official	340:28d1f895c6fe	547	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	548	* @retval None
mbed_official	340:28d1f895c6fe	549	*/
mbed_official	340:28d1f895c6fe	550	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	551	{
mbed_official	340:28d1f895c6fe	552	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	553	the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	554	*/
mbed_official	340:28d1f895c6fe	555	}
mbed_official	340:28d1f895c6fe	556
mbed_official	340:28d1f895c6fe	557	/**
mbed_official	340:28d1f895c6fe	558	* @brief Starts the TIM Output Compare signal generation.
mbed_official	340:28d1f895c6fe	559	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	560	* @param Channel : TIM Channel to be enabled
mbed_official	340:28d1f895c6fe	561	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	562	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	563	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	564	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	565	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	566	* @retval HAL status
mbed_official	340:28d1f895c6fe	567	*/
mbed_official	340:28d1f895c6fe	568	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	569	{
mbed_official	340:28d1f895c6fe	570	/* Check the parameters */
mbed_official	340:28d1f895c6fe	571	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	572
mbed_official	340:28d1f895c6fe	573	/* Enable the Output compare channel */
mbed_official	340:28d1f895c6fe	574	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	575
mbed_official	340:28d1f895c6fe	576	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	577	{
mbed_official	340:28d1f895c6fe	578	/* Enable the main output */
mbed_official	340:28d1f895c6fe	579	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	580	}
mbed_official	340:28d1f895c6fe	581
mbed_official	340:28d1f895c6fe	582	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	583	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	584
mbed_official	340:28d1f895c6fe	585	/* Return function status */
mbed_official	340:28d1f895c6fe	586	return HAL_OK;
mbed_official	340:28d1f895c6fe	587	}
mbed_official	340:28d1f895c6fe	588
mbed_official	340:28d1f895c6fe	589	/**
mbed_official	340:28d1f895c6fe	590	* @brief Stops the TIM Output Compare signal generation.
mbed_official	340:28d1f895c6fe	591	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	592	* @param Channel : TIM Channel to be disabled
mbed_official	340:28d1f895c6fe	593	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	594	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	595	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	596	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	597	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	598	* @retval HAL status
mbed_official	340:28d1f895c6fe	599	*/
mbed_official	340:28d1f895c6fe	600	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	601	{
mbed_official	340:28d1f895c6fe	602	/* Check the parameters */
mbed_official	340:28d1f895c6fe	603	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	604
mbed_official	340:28d1f895c6fe	605	/* Disable the Output compare channel */
mbed_official	340:28d1f895c6fe	606	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	607
mbed_official	340:28d1f895c6fe	608	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	609	{
mbed_official	340:28d1f895c6fe	610	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	611	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	612	}
mbed_official	340:28d1f895c6fe	613
mbed_official	340:28d1f895c6fe	614	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	615	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	616
mbed_official	340:28d1f895c6fe	617	/* Return function status */
mbed_official	340:28d1f895c6fe	618	return HAL_OK;
mbed_official	340:28d1f895c6fe	619	}
mbed_official	340:28d1f895c6fe	620
mbed_official	340:28d1f895c6fe	621	/**
mbed_official	340:28d1f895c6fe	622	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	623	* @param htim : TIM OC handle
mbed_official	340:28d1f895c6fe	624	* @param Channel : TIM Channel to be enabled
mbed_official	340:28d1f895c6fe	625	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	626	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	627	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	628	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	629	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	630	* @retval HAL status
mbed_official	340:28d1f895c6fe	631	*/
mbed_official	340:28d1f895c6fe	632	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	633	{
mbed_official	340:28d1f895c6fe	634	/* Check the parameters */
mbed_official	340:28d1f895c6fe	635	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	636
mbed_official	340:28d1f895c6fe	637	switch (Channel)
mbed_official	340:28d1f895c6fe	638	{
mbed_official	340:28d1f895c6fe	639	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	640	{
mbed_official	340:28d1f895c6fe	641	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	642	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	643	}
mbed_official	340:28d1f895c6fe	644	break;
mbed_official	340:28d1f895c6fe	645
mbed_official	340:28d1f895c6fe	646	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	647	{
mbed_official	340:28d1f895c6fe	648	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	649	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	650	}
mbed_official	340:28d1f895c6fe	651	break;
mbed_official	340:28d1f895c6fe	652
mbed_official	340:28d1f895c6fe	653	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	654	{
mbed_official	340:28d1f895c6fe	655	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	656	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	657	}
mbed_official	340:28d1f895c6fe	658	break;
mbed_official	340:28d1f895c6fe	659
mbed_official	340:28d1f895c6fe	660	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	661	{
mbed_official	340:28d1f895c6fe	662	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	663	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	664	}
mbed_official	340:28d1f895c6fe	665	break;
mbed_official	340:28d1f895c6fe	666
mbed_official	340:28d1f895c6fe	667	default:
mbed_official	340:28d1f895c6fe	668	break;
mbed_official	340:28d1f895c6fe	669	}
mbed_official	340:28d1f895c6fe	670
mbed_official	340:28d1f895c6fe	671	/* Enable the Output compare channel */
mbed_official	340:28d1f895c6fe	672	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	673
mbed_official	340:28d1f895c6fe	674	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	675	{
mbed_official	340:28d1f895c6fe	676	/* Enable the main output */
mbed_official	340:28d1f895c6fe	677	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	678	}
mbed_official	340:28d1f895c6fe	679
mbed_official	340:28d1f895c6fe	680	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	681	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	682
mbed_official	340:28d1f895c6fe	683	/* Return function status */
mbed_official	340:28d1f895c6fe	684	return HAL_OK;
mbed_official	340:28d1f895c6fe	685	}
mbed_official	340:28d1f895c6fe	686
mbed_official	340:28d1f895c6fe	687	/**
mbed_official	340:28d1f895c6fe	688	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	689	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	690	* @param Channel : TIM Channel to be disabled
mbed_official	340:28d1f895c6fe	691	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	692	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	693	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	694	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	695	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	696	* @retval HAL status
mbed_official	340:28d1f895c6fe	697	*/
mbed_official	340:28d1f895c6fe	698	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	699	{
mbed_official	340:28d1f895c6fe	700	/* Check the parameters */
mbed_official	340:28d1f895c6fe	701	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	702
mbed_official	340:28d1f895c6fe	703	switch (Channel)
mbed_official	340:28d1f895c6fe	704	{
mbed_official	340:28d1f895c6fe	705	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	706	{
mbed_official	340:28d1f895c6fe	707	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	708	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	709	}
mbed_official	340:28d1f895c6fe	710	break;
mbed_official	340:28d1f895c6fe	711
mbed_official	340:28d1f895c6fe	712	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	713	{
mbed_official	340:28d1f895c6fe	714	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	716	}
mbed_official	340:28d1f895c6fe	717	break;
mbed_official	340:28d1f895c6fe	718
mbed_official	340:28d1f895c6fe	719	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	720	{
mbed_official	340:28d1f895c6fe	721	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	723	}
mbed_official	340:28d1f895c6fe	724	break;
mbed_official	340:28d1f895c6fe	725
mbed_official	340:28d1f895c6fe	726	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	727	{
mbed_official	340:28d1f895c6fe	728	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	730	}
mbed_official	340:28d1f895c6fe	731	break;
mbed_official	340:28d1f895c6fe	732
mbed_official	340:28d1f895c6fe	733	default:
mbed_official	340:28d1f895c6fe	734	break;
mbed_official	340:28d1f895c6fe	735	}
mbed_official	340:28d1f895c6fe	736
mbed_official	340:28d1f895c6fe	737	/* Disable the Output compare channel */
mbed_official	340:28d1f895c6fe	738	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	739
mbed_official	340:28d1f895c6fe	740	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	741	{
mbed_official	340:28d1f895c6fe	742	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	743	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	744	}
mbed_official	340:28d1f895c6fe	745
mbed_official	340:28d1f895c6fe	746	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	747	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	748
mbed_official	340:28d1f895c6fe	749	/* Return function status */
mbed_official	340:28d1f895c6fe	750	return HAL_OK;
mbed_official	340:28d1f895c6fe	751	}
mbed_official	340:28d1f895c6fe	752
mbed_official	340:28d1f895c6fe	753	/**
mbed_official	340:28d1f895c6fe	754	* @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official	340:28d1f895c6fe	755	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	756	* @param Channel : TIM Channel to be enabled
mbed_official	340:28d1f895c6fe	757	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	758	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	759	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	760	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	761	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	762	* @param pData : The source Buffer address.
mbed_official	340:28d1f895c6fe	763	* @param Length : The length of data to be transferred from memory to TIM peripheral
mbed_official	340:28d1f895c6fe	764	* @retval HAL status
mbed_official	340:28d1f895c6fe	765	*/
mbed_official	340:28d1f895c6fe	766	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	340:28d1f895c6fe	767	{
mbed_official	340:28d1f895c6fe	768	/* Check the parameters */
mbed_official	340:28d1f895c6fe	769	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	770
mbed_official	340:28d1f895c6fe	771	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	772	{
mbed_official	340:28d1f895c6fe	773	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	774	}
mbed_official	340:28d1f895c6fe	775	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	776	{
mbed_official	340:28d1f895c6fe	777	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	340:28d1f895c6fe	778	{
mbed_official	340:28d1f895c6fe	779	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	780	}
mbed_official	340:28d1f895c6fe	781	else
mbed_official	340:28d1f895c6fe	782	{
mbed_official	340:28d1f895c6fe	783	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	784	}
mbed_official	340:28d1f895c6fe	785	}
mbed_official	340:28d1f895c6fe	786	switch (Channel)
mbed_official	340:28d1f895c6fe	787	{
mbed_official	340:28d1f895c6fe	788	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	789	{
mbed_official	340:28d1f895c6fe	790	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	791	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	792
mbed_official	340:28d1f895c6fe	793	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	794	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	795
mbed_official	340:28d1f895c6fe	796	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	797	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	340:28d1f895c6fe	798
mbed_official	340:28d1f895c6fe	799	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	800	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	801	}
mbed_official	340:28d1f895c6fe	802	break;
mbed_official	340:28d1f895c6fe	803
mbed_official	340:28d1f895c6fe	804	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	805	{
mbed_official	340:28d1f895c6fe	806	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	807	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	808
mbed_official	340:28d1f895c6fe	809	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	810	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	811
mbed_official	340:28d1f895c6fe	812	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	813	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	340:28d1f895c6fe	814
mbed_official	340:28d1f895c6fe	815	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	816	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	817	}
mbed_official	340:28d1f895c6fe	818	break;
mbed_official	340:28d1f895c6fe	819
mbed_official	340:28d1f895c6fe	820	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	821	{
mbed_official	340:28d1f895c6fe	822	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	823	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	824
mbed_official	340:28d1f895c6fe	825	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	826	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	827
mbed_official	340:28d1f895c6fe	828	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	829	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	340:28d1f895c6fe	830
mbed_official	340:28d1f895c6fe	831	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	340:28d1f895c6fe	832	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	833	}
mbed_official	340:28d1f895c6fe	834	break;
mbed_official	340:28d1f895c6fe	835
mbed_official	340:28d1f895c6fe	836	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	837	{
mbed_official	340:28d1f895c6fe	838	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	839	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	840
mbed_official	340:28d1f895c6fe	841	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	842	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	843
mbed_official	340:28d1f895c6fe	844	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	845	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	340:28d1f895c6fe	846
mbed_official	340:28d1f895c6fe	847	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	340:28d1f895c6fe	848	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	849	}
mbed_official	340:28d1f895c6fe	850	break;
mbed_official	340:28d1f895c6fe	851
mbed_official	340:28d1f895c6fe	852	default:
mbed_official	340:28d1f895c6fe	853	break;
mbed_official	340:28d1f895c6fe	854	}
mbed_official	340:28d1f895c6fe	855
mbed_official	340:28d1f895c6fe	856	/* Enable the Output compare channel */
mbed_official	340:28d1f895c6fe	857	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	858
mbed_official	340:28d1f895c6fe	859	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	860	{
mbed_official	340:28d1f895c6fe	861	/* Enable the main output */
mbed_official	340:28d1f895c6fe	862	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	863	}
mbed_official	340:28d1f895c6fe	864
mbed_official	340:28d1f895c6fe	865	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	866	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	867
mbed_official	340:28d1f895c6fe	868	/* Return function status */
mbed_official	340:28d1f895c6fe	869	return HAL_OK;
mbed_official	340:28d1f895c6fe	870	}
mbed_official	340:28d1f895c6fe	871
mbed_official	340:28d1f895c6fe	872	/**
mbed_official	340:28d1f895c6fe	873	* @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official	340:28d1f895c6fe	874	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	875	* @param Channel : TIM Channel to be disabled
mbed_official	340:28d1f895c6fe	876	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	877	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	878	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	879	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	880	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	881	* @retval HAL status
mbed_official	340:28d1f895c6fe	882	*/
mbed_official	340:28d1f895c6fe	883	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	884	{
mbed_official	340:28d1f895c6fe	885	/* Check the parameters */
mbed_official	340:28d1f895c6fe	886	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	887
mbed_official	340:28d1f895c6fe	888	switch (Channel)
mbed_official	340:28d1f895c6fe	889	{
mbed_official	340:28d1f895c6fe	890	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	891	{
mbed_official	340:28d1f895c6fe	892	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	893	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	894	}
mbed_official	340:28d1f895c6fe	895	break;
mbed_official	340:28d1f895c6fe	896
mbed_official	340:28d1f895c6fe	897	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	898	{
mbed_official	340:28d1f895c6fe	899	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	900	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	901	}
mbed_official	340:28d1f895c6fe	902	break;
mbed_official	340:28d1f895c6fe	903
mbed_official	340:28d1f895c6fe	904	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	905	{
mbed_official	340:28d1f895c6fe	906	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	340:28d1f895c6fe	907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	908	}
mbed_official	340:28d1f895c6fe	909	break;
mbed_official	340:28d1f895c6fe	910
mbed_official	340:28d1f895c6fe	911	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	912	{
mbed_official	340:28d1f895c6fe	913	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	914	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	915	}
mbed_official	340:28d1f895c6fe	916	break;
mbed_official	340:28d1f895c6fe	917
mbed_official	340:28d1f895c6fe	918	default:
mbed_official	340:28d1f895c6fe	919	break;
mbed_official	340:28d1f895c6fe	920	}
mbed_official	340:28d1f895c6fe	921
mbed_official	340:28d1f895c6fe	922	/* Disable the Output compare channel */
mbed_official	340:28d1f895c6fe	923	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	924
mbed_official	340:28d1f895c6fe	925	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	926	{
mbed_official	340:28d1f895c6fe	927	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	928	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	929	}
mbed_official	340:28d1f895c6fe	930
mbed_official	340:28d1f895c6fe	931	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	932	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	933
mbed_official	340:28d1f895c6fe	934	/* Change the htim state */
mbed_official	340:28d1f895c6fe	935	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	936
mbed_official	340:28d1f895c6fe	937	/* Return function status */
mbed_official	340:28d1f895c6fe	938	return HAL_OK;
mbed_official	340:28d1f895c6fe	939	}
mbed_official	340:28d1f895c6fe	940
mbed_official	340:28d1f895c6fe	941	/**
mbed_official	340:28d1f895c6fe	942	* @}
mbed_official	340:28d1f895c6fe	943	*/
mbed_official	340:28d1f895c6fe	944
mbed_official	340:28d1f895c6fe	945	/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
mbed_official	340:28d1f895c6fe	946	* @brief Time PWM functions
mbed_official	340:28d1f895c6fe	947	*
mbed_official	340:28d1f895c6fe	948	@verbatim
mbed_official	340:28d1f895c6fe	949	==============================================================================
mbed_official	340:28d1f895c6fe	950	##### Time PWM functions #####
mbed_official	340:28d1f895c6fe	951	==============================================================================
mbed_official	340:28d1f895c6fe	952	[..]
mbed_official	340:28d1f895c6fe	953	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	954	(+) Initialize and configure the TIM OPWM.
mbed_official	340:28d1f895c6fe	955	(+) De-initialize the TIM PWM.
mbed_official	340:28d1f895c6fe	956	(+) Start the Time PWM.
mbed_official	340:28d1f895c6fe	957	(+) Stop the Time PWM.
mbed_official	340:28d1f895c6fe	958	(+) Start the Time PWM and enable interrupt.
mbed_official	340:28d1f895c6fe	959	(+) Stop the Time PWM and disable interrupt.
mbed_official	340:28d1f895c6fe	960	(+) Start the Time PWM and enable DMA transfer.
mbed_official	340:28d1f895c6fe	961	(+) Stop the Time PWM and disable DMA transfer.
mbed_official	340:28d1f895c6fe	962
mbed_official	340:28d1f895c6fe	963	@endverbatim
mbed_official	340:28d1f895c6fe	964	* @{
mbed_official	340:28d1f895c6fe	965	*/
mbed_official	340:28d1f895c6fe	966	/**
mbed_official	340:28d1f895c6fe	967	* @brief Initializes the TIM PWM Time Base according to the specified
mbed_official	340:28d1f895c6fe	968	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	969	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	970	* @retval HAL status
mbed_official	340:28d1f895c6fe	971	*/
mbed_official	340:28d1f895c6fe	972	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	973	{
mbed_official	340:28d1f895c6fe	974	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	975	if(htim == NULL)
mbed_official	340:28d1f895c6fe	976	{
mbed_official	340:28d1f895c6fe	977	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	978	}
mbed_official	340:28d1f895c6fe	979
mbed_official	340:28d1f895c6fe	980	/* Check the parameters */
mbed_official	340:28d1f895c6fe	981	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	982	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	340:28d1f895c6fe	983	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	340:28d1f895c6fe	984
mbed_official	340:28d1f895c6fe	985	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	986	{
mbed_official	340:28d1f895c6fe	987	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	988	HAL_TIM_PWM_MspInit(htim);
mbed_official	340:28d1f895c6fe	989	}
mbed_official	340:28d1f895c6fe	990
mbed_official	340:28d1f895c6fe	991	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	992	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	993
mbed_official	340:28d1f895c6fe	994	/* Init the base time for the PWM */
mbed_official	340:28d1f895c6fe	995	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	996
mbed_official	340:28d1f895c6fe	997	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	998	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	999
mbed_official	340:28d1f895c6fe	1000	return HAL_OK;
mbed_official	340:28d1f895c6fe	1001	}
mbed_official	340:28d1f895c6fe	1002
mbed_official	340:28d1f895c6fe	1003	/**
mbed_official	340:28d1f895c6fe	1004	* @brief DeInitializes the TIM peripheral
mbed_official	340:28d1f895c6fe	1005	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1006	* @retval HAL status
mbed_official	340:28d1f895c6fe	1007	*/
mbed_official	340:28d1f895c6fe	1008	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1009	{
mbed_official	340:28d1f895c6fe	1010	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1011	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1012
mbed_official	340:28d1f895c6fe	1013	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1014
mbed_official	340:28d1f895c6fe	1015	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	1016	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1017
mbed_official	340:28d1f895c6fe	1018	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	1019	HAL_TIM_PWM_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	1020
mbed_official	340:28d1f895c6fe	1021	/* Change TIM state */
mbed_official	340:28d1f895c6fe	1022	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	1023
mbed_official	340:28d1f895c6fe	1024	/* Release Lock */
mbed_official	340:28d1f895c6fe	1025	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	1026
mbed_official	340:28d1f895c6fe	1027	return HAL_OK;
mbed_official	340:28d1f895c6fe	1028	}
mbed_official	340:28d1f895c6fe	1029
mbed_official	340:28d1f895c6fe	1030	/**
mbed_official	340:28d1f895c6fe	1031	* @brief Initializes the TIM PWM MSP.
mbed_official	340:28d1f895c6fe	1032	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1033	* @retval None
mbed_official	340:28d1f895c6fe	1034	*/
mbed_official	340:28d1f895c6fe	1035	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1036	{
mbed_official	340:28d1f895c6fe	1037	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1038	the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	1039	*/
mbed_official	340:28d1f895c6fe	1040	}
mbed_official	340:28d1f895c6fe	1041
mbed_official	340:28d1f895c6fe	1042	/**
mbed_official	340:28d1f895c6fe	1043	* @brief DeInitializes TIM PWM MSP.
mbed_official	340:28d1f895c6fe	1044	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1045	* @retval None
mbed_official	340:28d1f895c6fe	1046	*/
mbed_official	340:28d1f895c6fe	1047	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1048	{
mbed_official	340:28d1f895c6fe	1049	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1050	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	1051	*/
mbed_official	340:28d1f895c6fe	1052	}
mbed_official	340:28d1f895c6fe	1053
mbed_official	340:28d1f895c6fe	1054	/**
mbed_official	340:28d1f895c6fe	1055	* @brief Starts the PWM signal generation.
mbed_official	340:28d1f895c6fe	1056	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1057	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	1058	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1059	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1060	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1061	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1062	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1063	* @retval HAL status
mbed_official	340:28d1f895c6fe	1064	*/
mbed_official	340:28d1f895c6fe	1065	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1066	{
mbed_official	340:28d1f895c6fe	1067	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1068	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1069
mbed_official	340:28d1f895c6fe	1070	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1071	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1072
mbed_official	340:28d1f895c6fe	1073	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1074	{
mbed_official	340:28d1f895c6fe	1075	/* Enable the main output */
mbed_official	340:28d1f895c6fe	1076	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1077	}
mbed_official	340:28d1f895c6fe	1078
mbed_official	340:28d1f895c6fe	1079	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1080	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1081
mbed_official	340:28d1f895c6fe	1082	/* Return function status */
mbed_official	340:28d1f895c6fe	1083	return HAL_OK;
mbed_official	340:28d1f895c6fe	1084	}
mbed_official	340:28d1f895c6fe	1085
mbed_official	340:28d1f895c6fe	1086	/**
mbed_official	340:28d1f895c6fe	1087	* @brief Stops the PWM signal generation.
mbed_official	340:28d1f895c6fe	1088	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1089	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1090	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1091	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1092	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1093	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1094	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1095	* @retval HAL status
mbed_official	340:28d1f895c6fe	1096	*/
mbed_official	340:28d1f895c6fe	1097	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1098	{
mbed_official	340:28d1f895c6fe	1099	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1100	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1101
mbed_official	340:28d1f895c6fe	1102	/* Disable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1103	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1104
mbed_official	340:28d1f895c6fe	1105	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1106	{
mbed_official	340:28d1f895c6fe	1107	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	1108	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1109	}
mbed_official	340:28d1f895c6fe	1110
mbed_official	340:28d1f895c6fe	1111	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1112	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1113
mbed_official	340:28d1f895c6fe	1114	/* Change the htim state */
mbed_official	340:28d1f895c6fe	1115	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	1116
mbed_official	340:28d1f895c6fe	1117	/* Return function status */
mbed_official	340:28d1f895c6fe	1118	return HAL_OK;
mbed_official	340:28d1f895c6fe	1119	}
mbed_official	340:28d1f895c6fe	1120
mbed_official	340:28d1f895c6fe	1121	/**
mbed_official	340:28d1f895c6fe	1122	* @brief Starts the PWM signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	1123	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1124	* @param Channel : TIM Channel to be disabled
mbed_official	340:28d1f895c6fe	1125	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1126	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1127	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1128	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1129	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1130	* @retval HAL status
mbed_official	340:28d1f895c6fe	1131	*/
mbed_official	340:28d1f895c6fe	1132	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1133	{
mbed_official	340:28d1f895c6fe	1134	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1135	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1136
mbed_official	340:28d1f895c6fe	1137	switch (Channel)
mbed_official	340:28d1f895c6fe	1138	{
mbed_official	340:28d1f895c6fe	1139	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1140	{
mbed_official	340:28d1f895c6fe	1141	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	1142	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	1143	}
mbed_official	340:28d1f895c6fe	1144	break;
mbed_official	340:28d1f895c6fe	1145
mbed_official	340:28d1f895c6fe	1146	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1147	{
mbed_official	340:28d1f895c6fe	1148	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	1149	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	1150	}
mbed_official	340:28d1f895c6fe	1151	break;
mbed_official	340:28d1f895c6fe	1152
mbed_official	340:28d1f895c6fe	1153	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1154	{
mbed_official	340:28d1f895c6fe	1155	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	1156	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	1157	}
mbed_official	340:28d1f895c6fe	1158	break;
mbed_official	340:28d1f895c6fe	1159
mbed_official	340:28d1f895c6fe	1160	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1161	{
mbed_official	340:28d1f895c6fe	1162	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	1163	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	1164	}
mbed_official	340:28d1f895c6fe	1165	break;
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	default:
mbed_official	340:28d1f895c6fe	1168	break;
mbed_official	340:28d1f895c6fe	1169	}
mbed_official	340:28d1f895c6fe	1170
mbed_official	340:28d1f895c6fe	1171	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1172	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1173
mbed_official	340:28d1f895c6fe	1174	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1175	{
mbed_official	340:28d1f895c6fe	1176	/* Enable the main output */
mbed_official	340:28d1f895c6fe	1177	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1178	}
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1181	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1182
mbed_official	340:28d1f895c6fe	1183	/* Return function status */
mbed_official	340:28d1f895c6fe	1184	return HAL_OK;
mbed_official	340:28d1f895c6fe	1185	}
mbed_official	340:28d1f895c6fe	1186
mbed_official	340:28d1f895c6fe	1187	/**
mbed_official	340:28d1f895c6fe	1188	* @brief Stops the PWM signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	1189	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1190	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1191	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1192	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1193	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1194	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1195	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1196	* @retval HAL status
mbed_official	340:28d1f895c6fe	1197	*/
mbed_official	340:28d1f895c6fe	1198	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1199	{
mbed_official	340:28d1f895c6fe	1200	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1201	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1202
mbed_official	340:28d1f895c6fe	1203	switch (Channel)
mbed_official	340:28d1f895c6fe	1204	{
mbed_official	340:28d1f895c6fe	1205	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1206	{
mbed_official	340:28d1f895c6fe	1207	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	1208	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	1209	}
mbed_official	340:28d1f895c6fe	1210	break;
mbed_official	340:28d1f895c6fe	1211
mbed_official	340:28d1f895c6fe	1212	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1213	{
mbed_official	340:28d1f895c6fe	1214	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	1215	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	1216	}
mbed_official	340:28d1f895c6fe	1217	break;
mbed_official	340:28d1f895c6fe	1218
mbed_official	340:28d1f895c6fe	1219	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1220	{
mbed_official	340:28d1f895c6fe	1221	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	1222	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	1223	}
mbed_official	340:28d1f895c6fe	1224	break;
mbed_official	340:28d1f895c6fe	1225
mbed_official	340:28d1f895c6fe	1226	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1227	{
mbed_official	340:28d1f895c6fe	1228	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	1229	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	1230	}
mbed_official	340:28d1f895c6fe	1231	break;
mbed_official	340:28d1f895c6fe	1232
mbed_official	340:28d1f895c6fe	1233	default:
mbed_official	340:28d1f895c6fe	1234	break;
mbed_official	340:28d1f895c6fe	1235	}
mbed_official	340:28d1f895c6fe	1236
mbed_official	340:28d1f895c6fe	1237	/* Disable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1238	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1239
mbed_official	340:28d1f895c6fe	1240	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1241	{
mbed_official	340:28d1f895c6fe	1242	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	1243	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1244	}
mbed_official	340:28d1f895c6fe	1245
mbed_official	340:28d1f895c6fe	1246	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1247	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1248
mbed_official	340:28d1f895c6fe	1249	/* Return function status */
mbed_official	340:28d1f895c6fe	1250	return HAL_OK;
mbed_official	340:28d1f895c6fe	1251	}
mbed_official	340:28d1f895c6fe	1252
mbed_official	340:28d1f895c6fe	1253	/**
mbed_official	340:28d1f895c6fe	1254	* @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official	340:28d1f895c6fe	1255	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1256	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	1257	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1258	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1259	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1260	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1261	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1262	* @param pData : The source Buffer address.
mbed_official	340:28d1f895c6fe	1263	* @param Length : The length of data to be transferred from memory to TIM peripheral
mbed_official	340:28d1f895c6fe	1264	* @retval HAL status
mbed_official	340:28d1f895c6fe	1265	*/
mbed_official	340:28d1f895c6fe	1266	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	340:28d1f895c6fe	1267	{
mbed_official	340:28d1f895c6fe	1268	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1269	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1270
mbed_official	340:28d1f895c6fe	1271	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	1272	{
mbed_official	340:28d1f895c6fe	1273	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1274	}
mbed_official	340:28d1f895c6fe	1275	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	1276	{
mbed_official	340:28d1f895c6fe	1277	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	340:28d1f895c6fe	1278	{
mbed_official	340:28d1f895c6fe	1279	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1280	}
mbed_official	340:28d1f895c6fe	1281	else
mbed_official	340:28d1f895c6fe	1282	{
mbed_official	340:28d1f895c6fe	1283	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1284	}
mbed_official	340:28d1f895c6fe	1285	}
mbed_official	340:28d1f895c6fe	1286	switch (Channel)
mbed_official	340:28d1f895c6fe	1287	{
mbed_official	340:28d1f895c6fe	1288	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1289	{
mbed_official	340:28d1f895c6fe	1290	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1291	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	1292
mbed_official	340:28d1f895c6fe	1293	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1294	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1295
mbed_official	340:28d1f895c6fe	1296	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1297	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	340:28d1f895c6fe	1298
mbed_official	340:28d1f895c6fe	1299	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	1300	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	1301	}
mbed_official	340:28d1f895c6fe	1302	break;
mbed_official	340:28d1f895c6fe	1303
mbed_official	340:28d1f895c6fe	1304	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1305	{
mbed_official	340:28d1f895c6fe	1306	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1307	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	1308
mbed_official	340:28d1f895c6fe	1309	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1310	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1311
mbed_official	340:28d1f895c6fe	1312	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1313	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	340:28d1f895c6fe	1314
mbed_official	340:28d1f895c6fe	1315	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	1316	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	1317	}
mbed_official	340:28d1f895c6fe	1318	break;
mbed_official	340:28d1f895c6fe	1319
mbed_official	340:28d1f895c6fe	1320	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1321	{
mbed_official	340:28d1f895c6fe	1322	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1323	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	1324
mbed_official	340:28d1f895c6fe	1325	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1326	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1327
mbed_official	340:28d1f895c6fe	1328	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1329	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	340:28d1f895c6fe	1330
mbed_official	340:28d1f895c6fe	1331	/* Enable the TIM Output Capture/Compare 3 request */
mbed_official	340:28d1f895c6fe	1332	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	1333	}
mbed_official	340:28d1f895c6fe	1334	break;
mbed_official	340:28d1f895c6fe	1335
mbed_official	340:28d1f895c6fe	1336	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1337	{
mbed_official	340:28d1f895c6fe	1338	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1339	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	1340
mbed_official	340:28d1f895c6fe	1341	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1342	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1343
mbed_official	340:28d1f895c6fe	1344	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1345	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	340:28d1f895c6fe	1346
mbed_official	340:28d1f895c6fe	1347	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	340:28d1f895c6fe	1348	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	1349	}
mbed_official	340:28d1f895c6fe	1350	break;
mbed_official	340:28d1f895c6fe	1351
mbed_official	340:28d1f895c6fe	1352	default:
mbed_official	340:28d1f895c6fe	1353	break;
mbed_official	340:28d1f895c6fe	1354	}
mbed_official	340:28d1f895c6fe	1355
mbed_official	340:28d1f895c6fe	1356	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1357	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1358
mbed_official	340:28d1f895c6fe	1359	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1360	{
mbed_official	340:28d1f895c6fe	1361	/* Enable the main output */
mbed_official	340:28d1f895c6fe	1362	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1363	}
mbed_official	340:28d1f895c6fe	1364
mbed_official	340:28d1f895c6fe	1365	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1366	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1367
mbed_official	340:28d1f895c6fe	1368	/* Return function status */
mbed_official	340:28d1f895c6fe	1369	return HAL_OK;
mbed_official	340:28d1f895c6fe	1370	}
mbed_official	340:28d1f895c6fe	1371
mbed_official	340:28d1f895c6fe	1372	/**
mbed_official	340:28d1f895c6fe	1373	* @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official	340:28d1f895c6fe	1374	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1375	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1376	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1377	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1378	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1379	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1380	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1381	* @retval HAL status
mbed_official	340:28d1f895c6fe	1382	*/
mbed_official	340:28d1f895c6fe	1383	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1384	{
mbed_official	340:28d1f895c6fe	1385	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1386	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1387
mbed_official	340:28d1f895c6fe	1388	switch (Channel)
mbed_official	340:28d1f895c6fe	1389	{
mbed_official	340:28d1f895c6fe	1390	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1391	{
mbed_official	340:28d1f895c6fe	1392	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	1393	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	1394	}
mbed_official	340:28d1f895c6fe	1395	break;
mbed_official	340:28d1f895c6fe	1396
mbed_official	340:28d1f895c6fe	1397	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1398	{
mbed_official	340:28d1f895c6fe	1399	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	1400	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	1401	}
mbed_official	340:28d1f895c6fe	1402	break;
mbed_official	340:28d1f895c6fe	1403
mbed_official	340:28d1f895c6fe	1404	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1405	{
mbed_official	340:28d1f895c6fe	1406	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	340:28d1f895c6fe	1407	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	1408	}
mbed_official	340:28d1f895c6fe	1409	break;
mbed_official	340:28d1f895c6fe	1410
mbed_official	340:28d1f895c6fe	1411	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1412	{
mbed_official	340:28d1f895c6fe	1413	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	1414	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	1415	}
mbed_official	340:28d1f895c6fe	1416	break;
mbed_official	340:28d1f895c6fe	1417
mbed_official	340:28d1f895c6fe	1418	default:
mbed_official	340:28d1f895c6fe	1419	break;
mbed_official	340:28d1f895c6fe	1420	}
mbed_official	340:28d1f895c6fe	1421
mbed_official	340:28d1f895c6fe	1422	/* Disable the Capture compare channel */
mbed_official	340:28d1f895c6fe	1423	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1424
mbed_official	340:28d1f895c6fe	1425	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	1426	{
mbed_official	340:28d1f895c6fe	1427	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	1428	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1429	}
mbed_official	340:28d1f895c6fe	1430
mbed_official	340:28d1f895c6fe	1431	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1432	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1433
mbed_official	340:28d1f895c6fe	1434	/* Change the htim state */
mbed_official	340:28d1f895c6fe	1435	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	1436
mbed_official	340:28d1f895c6fe	1437	/* Return function status */
mbed_official	340:28d1f895c6fe	1438	return HAL_OK;
mbed_official	340:28d1f895c6fe	1439	}
mbed_official	340:28d1f895c6fe	1440
mbed_official	340:28d1f895c6fe	1441	/**
mbed_official	340:28d1f895c6fe	1442	* @}
mbed_official	340:28d1f895c6fe	1443	*/
mbed_official	340:28d1f895c6fe	1444
mbed_official	340:28d1f895c6fe	1445	/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
mbed_official	340:28d1f895c6fe	1446	* @brief Time Input Capture functions
mbed_official	340:28d1f895c6fe	1447	*
mbed_official	340:28d1f895c6fe	1448	@verbatim
mbed_official	340:28d1f895c6fe	1449	==============================================================================
mbed_official	340:28d1f895c6fe	1450	##### Time Input Capture functions #####
mbed_official	340:28d1f895c6fe	1451	==============================================================================
mbed_official	340:28d1f895c6fe	1452	[..]
mbed_official	340:28d1f895c6fe	1453	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	1454	(+) Initialize and configure the TIM Input Capture.
mbed_official	340:28d1f895c6fe	1455	(+) De-initialize the TIM Input Capture.
mbed_official	340:28d1f895c6fe	1456	(+) Start the Time Input Capture.
mbed_official	340:28d1f895c6fe	1457	(+) Stop the Time Input Capture.
mbed_official	340:28d1f895c6fe	1458	(+) Start the Time Input Capture and enable interrupt.
mbed_official	340:28d1f895c6fe	1459	(+) Stop the Time Input Capture and disable interrupt.
mbed_official	340:28d1f895c6fe	1460	(+) Start the Time Input Capture and enable DMA transfer.
mbed_official	340:28d1f895c6fe	1461	(+) Stop the Time Input Capture and disable DMA transfer.
mbed_official	340:28d1f895c6fe	1462
mbed_official	340:28d1f895c6fe	1463	@endverbatim
mbed_official	340:28d1f895c6fe	1464	* @{
mbed_official	340:28d1f895c6fe	1465	*/
mbed_official	340:28d1f895c6fe	1466	/**
mbed_official	340:28d1f895c6fe	1467	* @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official	340:28d1f895c6fe	1468	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	1469	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1470	* @retval HAL status
mbed_official	340:28d1f895c6fe	1471	*/
mbed_official	340:28d1f895c6fe	1472	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1473	{
mbed_official	340:28d1f895c6fe	1474	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	1475	if(htim == NULL)
mbed_official	340:28d1f895c6fe	1476	{
mbed_official	340:28d1f895c6fe	1477	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1478	}
mbed_official	340:28d1f895c6fe	1479
mbed_official	340:28d1f895c6fe	1480	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1481	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1482	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	340:28d1f895c6fe	1483	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	340:28d1f895c6fe	1484
mbed_official	340:28d1f895c6fe	1485	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	1486	{
mbed_official	340:28d1f895c6fe	1487	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	1488	HAL_TIM_IC_MspInit(htim);
mbed_official	340:28d1f895c6fe	1489	}
mbed_official	340:28d1f895c6fe	1490
mbed_official	340:28d1f895c6fe	1491	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	1492	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1493
mbed_official	340:28d1f895c6fe	1494	/* Init the base time for the input capture */
mbed_official	340:28d1f895c6fe	1495	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	1496
mbed_official	340:28d1f895c6fe	1497	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	1498	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	1499
mbed_official	340:28d1f895c6fe	1500	return HAL_OK;
mbed_official	340:28d1f895c6fe	1501	}
mbed_official	340:28d1f895c6fe	1502
mbed_official	340:28d1f895c6fe	1503	/**
mbed_official	340:28d1f895c6fe	1504	* @brief DeInitializes the TIM peripheral
mbed_official	340:28d1f895c6fe	1505	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1506	* @retval HAL status
mbed_official	340:28d1f895c6fe	1507	*/
mbed_official	340:28d1f895c6fe	1508	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1509	{
mbed_official	340:28d1f895c6fe	1510	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1511	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1512
mbed_official	340:28d1f895c6fe	1513	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1514
mbed_official	340:28d1f895c6fe	1515	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	1516	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1517
mbed_official	340:28d1f895c6fe	1518	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	1519	HAL_TIM_IC_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	1520
mbed_official	340:28d1f895c6fe	1521	/* Change TIM state */
mbed_official	340:28d1f895c6fe	1522	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	1523
mbed_official	340:28d1f895c6fe	1524	/* Release Lock */
mbed_official	340:28d1f895c6fe	1525	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	1526
mbed_official	340:28d1f895c6fe	1527	return HAL_OK;
mbed_official	340:28d1f895c6fe	1528	}
mbed_official	340:28d1f895c6fe	1529
mbed_official	340:28d1f895c6fe	1530	/**
mbed_official	340:28d1f895c6fe	1531	* @brief Initializes the TIM Input Capture MSP.
mbed_official	340:28d1f895c6fe	1532	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1533	* @retval None
mbed_official	340:28d1f895c6fe	1534	*/
mbed_official	340:28d1f895c6fe	1535	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1536	{
mbed_official	340:28d1f895c6fe	1537	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1538	the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	1539	*/
mbed_official	340:28d1f895c6fe	1540	}
mbed_official	340:28d1f895c6fe	1541
mbed_official	340:28d1f895c6fe	1542	/**
mbed_official	340:28d1f895c6fe	1543	* @brief DeInitializes TIM Input Capture MSP.
mbed_official	340:28d1f895c6fe	1544	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1545	* @retval None
mbed_official	340:28d1f895c6fe	1546	*/
mbed_official	340:28d1f895c6fe	1547	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1548	{
mbed_official	340:28d1f895c6fe	1549	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1550	the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	1551	*/
mbed_official	340:28d1f895c6fe	1552	}
mbed_official	340:28d1f895c6fe	1553
mbed_official	340:28d1f895c6fe	1554	/**
mbed_official	340:28d1f895c6fe	1555	* @brief Starts the TIM Input Capture measurement.
mbed_official	340:28d1f895c6fe	1556	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1557	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	1558	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1559	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1560	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1561	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1562	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1563	* @retval HAL status
mbed_official	340:28d1f895c6fe	1564	*/
mbed_official	340:28d1f895c6fe	1565	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1566	{
mbed_official	340:28d1f895c6fe	1567	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1568	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1569
mbed_official	340:28d1f895c6fe	1570	/* Enable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1571	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1572
mbed_official	340:28d1f895c6fe	1573	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1574	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1575
mbed_official	340:28d1f895c6fe	1576	/* Return function status */
mbed_official	340:28d1f895c6fe	1577	return HAL_OK;
mbed_official	340:28d1f895c6fe	1578	}
mbed_official	340:28d1f895c6fe	1579
mbed_official	340:28d1f895c6fe	1580	/**
mbed_official	340:28d1f895c6fe	1581	* @brief Stops the TIM Input Capture measurement.
mbed_official	340:28d1f895c6fe	1582	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1583	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1584	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1585	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1586	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1587	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1588	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1589	* @retval HAL status
mbed_official	340:28d1f895c6fe	1590	*/
mbed_official	340:28d1f895c6fe	1591	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1592	{
mbed_official	340:28d1f895c6fe	1593	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1594	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1595
mbed_official	340:28d1f895c6fe	1596	/* Disable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1597	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1598
mbed_official	340:28d1f895c6fe	1599	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1600	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1601
mbed_official	340:28d1f895c6fe	1602	/* Return function status */
mbed_official	340:28d1f895c6fe	1603	return HAL_OK;
mbed_official	340:28d1f895c6fe	1604	}
mbed_official	340:28d1f895c6fe	1605
mbed_official	340:28d1f895c6fe	1606	/**
mbed_official	340:28d1f895c6fe	1607	* @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official	340:28d1f895c6fe	1608	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1609	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	1610	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1611	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1612	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1613	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1614	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1615	* @retval HAL status
mbed_official	340:28d1f895c6fe	1616	*/
mbed_official	340:28d1f895c6fe	1617	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1618	{
mbed_official	340:28d1f895c6fe	1619	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1620	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1621
mbed_official	340:28d1f895c6fe	1622	switch (Channel)
mbed_official	340:28d1f895c6fe	1623	{
mbed_official	340:28d1f895c6fe	1624	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1625	{
mbed_official	340:28d1f895c6fe	1626	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	1627	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	1628	}
mbed_official	340:28d1f895c6fe	1629	break;
mbed_official	340:28d1f895c6fe	1630
mbed_official	340:28d1f895c6fe	1631	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1632	{
mbed_official	340:28d1f895c6fe	1633	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	1634	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	1635	}
mbed_official	340:28d1f895c6fe	1636	break;
mbed_official	340:28d1f895c6fe	1637
mbed_official	340:28d1f895c6fe	1638	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1639	{
mbed_official	340:28d1f895c6fe	1640	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	1641	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	1642	}
mbed_official	340:28d1f895c6fe	1643	break;
mbed_official	340:28d1f895c6fe	1644
mbed_official	340:28d1f895c6fe	1645	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1646	{
mbed_official	340:28d1f895c6fe	1647	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	1648	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	1649	}
mbed_official	340:28d1f895c6fe	1650	break;
mbed_official	340:28d1f895c6fe	1651
mbed_official	340:28d1f895c6fe	1652	default:
mbed_official	340:28d1f895c6fe	1653	break;
mbed_official	340:28d1f895c6fe	1654	}
mbed_official	340:28d1f895c6fe	1655	/* Enable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1656	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1657
mbed_official	340:28d1f895c6fe	1658	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1659	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1660
mbed_official	340:28d1f895c6fe	1661	/* Return function status */
mbed_official	340:28d1f895c6fe	1662	return HAL_OK;
mbed_official	340:28d1f895c6fe	1663	}
mbed_official	340:28d1f895c6fe	1664
mbed_official	340:28d1f895c6fe	1665	/**
mbed_official	340:28d1f895c6fe	1666	* @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official	340:28d1f895c6fe	1667	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	1668	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1669	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1670	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1671	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1672	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1673	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1674	* @retval HAL status
mbed_official	340:28d1f895c6fe	1675	*/
mbed_official	340:28d1f895c6fe	1676	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1677	{
mbed_official	340:28d1f895c6fe	1678	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1679	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1680
mbed_official	340:28d1f895c6fe	1681	switch (Channel)
mbed_official	340:28d1f895c6fe	1682	{
mbed_official	340:28d1f895c6fe	1683	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1684	{
mbed_official	340:28d1f895c6fe	1685	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	1686	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	1687	}
mbed_official	340:28d1f895c6fe	1688	break;
mbed_official	340:28d1f895c6fe	1689
mbed_official	340:28d1f895c6fe	1690	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1691	{
mbed_official	340:28d1f895c6fe	1692	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	1693	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	1694	}
mbed_official	340:28d1f895c6fe	1695	break;
mbed_official	340:28d1f895c6fe	1696
mbed_official	340:28d1f895c6fe	1697	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1698	{
mbed_official	340:28d1f895c6fe	1699	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	340:28d1f895c6fe	1700	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	1701	}
mbed_official	340:28d1f895c6fe	1702	break;
mbed_official	340:28d1f895c6fe	1703
mbed_official	340:28d1f895c6fe	1704	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1705	{
mbed_official	340:28d1f895c6fe	1706	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	340:28d1f895c6fe	1707	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	1708	}
mbed_official	340:28d1f895c6fe	1709	break;
mbed_official	340:28d1f895c6fe	1710
mbed_official	340:28d1f895c6fe	1711	default:
mbed_official	340:28d1f895c6fe	1712	break;
mbed_official	340:28d1f895c6fe	1713	}
mbed_official	340:28d1f895c6fe	1714
mbed_official	340:28d1f895c6fe	1715	/* Disable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1716	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1717
mbed_official	340:28d1f895c6fe	1718	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1719	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1720
mbed_official	340:28d1f895c6fe	1721	/* Return function status */
mbed_official	340:28d1f895c6fe	1722	return HAL_OK;
mbed_official	340:28d1f895c6fe	1723	}
mbed_official	340:28d1f895c6fe	1724
mbed_official	340:28d1f895c6fe	1725	/**
mbed_official	340:28d1f895c6fe	1726	* @brief Starts the TIM Input Capture measurement in DMA mode.
mbed_official	340:28d1f895c6fe	1727	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1728	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	1729	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1730	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1731	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1732	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1733	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1734	* @param pData : The destination Buffer address.
mbed_official	340:28d1f895c6fe	1735	* @param Length : The length of data to be transferred from TIM peripheral to memory.
mbed_official	340:28d1f895c6fe	1736	* @retval HAL status
mbed_official	340:28d1f895c6fe	1737	*/
mbed_official	340:28d1f895c6fe	1738	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	340:28d1f895c6fe	1739	{
mbed_official	340:28d1f895c6fe	1740	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1741	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1742	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1743
mbed_official	340:28d1f895c6fe	1744	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	1745	{
mbed_official	340:28d1f895c6fe	1746	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1747	}
mbed_official	340:28d1f895c6fe	1748	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	1749	{
mbed_official	340:28d1f895c6fe	1750	if((pData == 0 ) && (Length > 0))
mbed_official	340:28d1f895c6fe	1751	{
mbed_official	340:28d1f895c6fe	1752	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1753	}
mbed_official	340:28d1f895c6fe	1754	else
mbed_official	340:28d1f895c6fe	1755	{
mbed_official	340:28d1f895c6fe	1756	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1757	}
mbed_official	340:28d1f895c6fe	1758	}
mbed_official	340:28d1f895c6fe	1759
mbed_official	340:28d1f895c6fe	1760	switch (Channel)
mbed_official	340:28d1f895c6fe	1761	{
mbed_official	340:28d1f895c6fe	1762	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1763	{
mbed_official	340:28d1f895c6fe	1764	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1765	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	1766
mbed_official	340:28d1f895c6fe	1767	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1768	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1769
mbed_official	340:28d1f895c6fe	1770	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1771	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official	340:28d1f895c6fe	1772
mbed_official	340:28d1f895c6fe	1773	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	1774	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	1775	}
mbed_official	340:28d1f895c6fe	1776	break;
mbed_official	340:28d1f895c6fe	1777
mbed_official	340:28d1f895c6fe	1778	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1779	{
mbed_official	340:28d1f895c6fe	1780	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1781	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	1782
mbed_official	340:28d1f895c6fe	1783	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1784	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1785
mbed_official	340:28d1f895c6fe	1786	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1787	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official	340:28d1f895c6fe	1788
mbed_official	340:28d1f895c6fe	1789	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	1790	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	1791	}
mbed_official	340:28d1f895c6fe	1792	break;
mbed_official	340:28d1f895c6fe	1793
mbed_official	340:28d1f895c6fe	1794	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1795	{
mbed_official	340:28d1f895c6fe	1796	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1797	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	1798
mbed_official	340:28d1f895c6fe	1799	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1800	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1801
mbed_official	340:28d1f895c6fe	1802	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1803	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official	340:28d1f895c6fe	1804
mbed_official	340:28d1f895c6fe	1805	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	340:28d1f895c6fe	1806	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	1807	}
mbed_official	340:28d1f895c6fe	1808	break;
mbed_official	340:28d1f895c6fe	1809
mbed_official	340:28d1f895c6fe	1810	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1811	{
mbed_official	340:28d1f895c6fe	1812	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	1813	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	1814
mbed_official	340:28d1f895c6fe	1815	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1816	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	1817
mbed_official	340:28d1f895c6fe	1818	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	1819	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official	340:28d1f895c6fe	1820
mbed_official	340:28d1f895c6fe	1821	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	340:28d1f895c6fe	1822	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	1823	}
mbed_official	340:28d1f895c6fe	1824	break;
mbed_official	340:28d1f895c6fe	1825
mbed_official	340:28d1f895c6fe	1826	default:
mbed_official	340:28d1f895c6fe	1827	break;
mbed_official	340:28d1f895c6fe	1828	}
mbed_official	340:28d1f895c6fe	1829
mbed_official	340:28d1f895c6fe	1830	/* Enable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1831	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	1832
mbed_official	340:28d1f895c6fe	1833	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	1834	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	1835
mbed_official	340:28d1f895c6fe	1836	/* Return function status */
mbed_official	340:28d1f895c6fe	1837	return HAL_OK;
mbed_official	340:28d1f895c6fe	1838	}
mbed_official	340:28d1f895c6fe	1839
mbed_official	340:28d1f895c6fe	1840	/**
mbed_official	340:28d1f895c6fe	1841	* @brief Stops the TIM Input Capture measurement in DMA mode.
mbed_official	340:28d1f895c6fe	1842	* @param htim : TIM Input Capture handle
mbed_official	340:28d1f895c6fe	1843	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	1844	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1845	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1846	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1847	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1848	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1849	* @retval HAL status
mbed_official	340:28d1f895c6fe	1850	*/
mbed_official	340:28d1f895c6fe	1851	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	1852	{
mbed_official	340:28d1f895c6fe	1853	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1854	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	340:28d1f895c6fe	1855	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1856
mbed_official	340:28d1f895c6fe	1857	switch (Channel)
mbed_official	340:28d1f895c6fe	1858	{
mbed_official	340:28d1f895c6fe	1859	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	1860	{
mbed_official	340:28d1f895c6fe	1861	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	340:28d1f895c6fe	1862	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	1863	}
mbed_official	340:28d1f895c6fe	1864	break;
mbed_official	340:28d1f895c6fe	1865
mbed_official	340:28d1f895c6fe	1866	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	1867	{
mbed_official	340:28d1f895c6fe	1868	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	340:28d1f895c6fe	1869	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	1870	}
mbed_official	340:28d1f895c6fe	1871	break;
mbed_official	340:28d1f895c6fe	1872
mbed_official	340:28d1f895c6fe	1873	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	1874	{
mbed_official	340:28d1f895c6fe	1875	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	340:28d1f895c6fe	1876	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	340:28d1f895c6fe	1877	}
mbed_official	340:28d1f895c6fe	1878	break;
mbed_official	340:28d1f895c6fe	1879
mbed_official	340:28d1f895c6fe	1880	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	1881	{
mbed_official	340:28d1f895c6fe	1882	/* Disable the TIM Capture/Compare 4 DMA request */
mbed_official	340:28d1f895c6fe	1883	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	340:28d1f895c6fe	1884	}
mbed_official	340:28d1f895c6fe	1885	break;
mbed_official	340:28d1f895c6fe	1886
mbed_official	340:28d1f895c6fe	1887	default:
mbed_official	340:28d1f895c6fe	1888	break;
mbed_official	340:28d1f895c6fe	1889	}
mbed_official	340:28d1f895c6fe	1890
mbed_official	340:28d1f895c6fe	1891	/* Disable the Input Capture channel */
mbed_official	340:28d1f895c6fe	1892	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	1893
mbed_official	340:28d1f895c6fe	1894	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	1895	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1896
mbed_official	340:28d1f895c6fe	1897	/* Change the htim state */
mbed_official	340:28d1f895c6fe	1898	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	1899
mbed_official	340:28d1f895c6fe	1900	/* Return function status */
mbed_official	340:28d1f895c6fe	1901	return HAL_OK;
mbed_official	340:28d1f895c6fe	1902	}
mbed_official	340:28d1f895c6fe	1903	/**
mbed_official	340:28d1f895c6fe	1904	* @}
mbed_official	340:28d1f895c6fe	1905	*/
mbed_official	340:28d1f895c6fe	1906
mbed_official	340:28d1f895c6fe	1907	/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
mbed_official	340:28d1f895c6fe	1908	* @brief Time One Pulse functions
mbed_official	340:28d1f895c6fe	1909	*
mbed_official	340:28d1f895c6fe	1910	@verbatim
mbed_official	340:28d1f895c6fe	1911	==============================================================================
mbed_official	340:28d1f895c6fe	1912	##### Time One Pulse functions #####
mbed_official	340:28d1f895c6fe	1913	==============================================================================
mbed_official	340:28d1f895c6fe	1914	[..]
mbed_official	340:28d1f895c6fe	1915	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	1916	(+) Initialize and configure the TIM One Pulse.
mbed_official	340:28d1f895c6fe	1917	(+) De-initialize the TIM One Pulse.
mbed_official	340:28d1f895c6fe	1918	(+) Start the Time One Pulse.
mbed_official	340:28d1f895c6fe	1919	(+) Stop the Time One Pulse.
mbed_official	340:28d1f895c6fe	1920	(+) Start the Time One Pulse and enable interrupt.
mbed_official	340:28d1f895c6fe	1921	(+) Stop the Time One Pulse and disable interrupt.
mbed_official	340:28d1f895c6fe	1922	(+) Start the Time One Pulse and enable DMA transfer.
mbed_official	340:28d1f895c6fe	1923	(+) Stop the Time One Pulse and disable DMA transfer.
mbed_official	340:28d1f895c6fe	1924
mbed_official	340:28d1f895c6fe	1925	@endverbatim
mbed_official	340:28d1f895c6fe	1926	* @{
mbed_official	340:28d1f895c6fe	1927	*/
mbed_official	340:28d1f895c6fe	1928	/**
mbed_official	340:28d1f895c6fe	1929	* @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official	340:28d1f895c6fe	1930	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	1931	* @param htim : TIM OnePulse handle
mbed_official	340:28d1f895c6fe	1932	* @param OnePulseMode : Select the One pulse mode.
mbed_official	340:28d1f895c6fe	1933	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1934	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official	340:28d1f895c6fe	1935	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official	340:28d1f895c6fe	1936	* @retval HAL status
mbed_official	340:28d1f895c6fe	1937	*/
mbed_official	340:28d1f895c6fe	1938	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official	340:28d1f895c6fe	1939	{
mbed_official	340:28d1f895c6fe	1940	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	1941	if(htim == NULL)
mbed_official	340:28d1f895c6fe	1942	{
mbed_official	340:28d1f895c6fe	1943	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1944	}
mbed_official	340:28d1f895c6fe	1945
mbed_official	340:28d1f895c6fe	1946	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1947	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1948	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	340:28d1f895c6fe	1949	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	340:28d1f895c6fe	1950	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official	340:28d1f895c6fe	1951
mbed_official	340:28d1f895c6fe	1952	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	1953	{
mbed_official	340:28d1f895c6fe	1954	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	1955	HAL_TIM_OnePulse_MspInit(htim);
mbed_official	340:28d1f895c6fe	1956	}
mbed_official	340:28d1f895c6fe	1957
mbed_official	340:28d1f895c6fe	1958	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	1959	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1960
mbed_official	340:28d1f895c6fe	1961	/* Configure the Time base in the One Pulse Mode */
mbed_official	340:28d1f895c6fe	1962	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	1963
mbed_official	340:28d1f895c6fe	1964	/* Reset the OPM Bit */
mbed_official	340:28d1f895c6fe	1965	htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official	340:28d1f895c6fe	1966
mbed_official	340:28d1f895c6fe	1967	/* Configure the OPM Mode */
mbed_official	340:28d1f895c6fe	1968	htim->Instance->CR1 \|= OnePulseMode;
mbed_official	340:28d1f895c6fe	1969
mbed_official	340:28d1f895c6fe	1970	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	1971	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	1972
mbed_official	340:28d1f895c6fe	1973	return HAL_OK;
mbed_official	340:28d1f895c6fe	1974	}
mbed_official	340:28d1f895c6fe	1975
mbed_official	340:28d1f895c6fe	1976	/**
mbed_official	340:28d1f895c6fe	1977	* @brief DeInitializes the TIM One Pulse
mbed_official	340:28d1f895c6fe	1978	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	1979	* @retval HAL status
mbed_official	340:28d1f895c6fe	1980	*/
mbed_official	340:28d1f895c6fe	1981	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	1982	{
mbed_official	340:28d1f895c6fe	1983	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1984	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	1985
mbed_official	340:28d1f895c6fe	1986	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	1987
mbed_official	340:28d1f895c6fe	1988	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	1989	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	1990
mbed_official	340:28d1f895c6fe	1991	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	1992	HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	1993
mbed_official	340:28d1f895c6fe	1994	/* Change TIM state */
mbed_official	340:28d1f895c6fe	1995	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	1996
mbed_official	340:28d1f895c6fe	1997	/* Release Lock */
mbed_official	340:28d1f895c6fe	1998	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	1999
mbed_official	340:28d1f895c6fe	2000	return HAL_OK;
mbed_official	340:28d1f895c6fe	2001	}
mbed_official	340:28d1f895c6fe	2002
mbed_official	340:28d1f895c6fe	2003	/**
mbed_official	340:28d1f895c6fe	2004	* @brief Initializes the TIM One Pulse MSP.
mbed_official	340:28d1f895c6fe	2005	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	2006	* @retval None
mbed_official	340:28d1f895c6fe	2007	*/
mbed_official	340:28d1f895c6fe	2008	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2009	{
mbed_official	340:28d1f895c6fe	2010	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	2011	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	2012	*/
mbed_official	340:28d1f895c6fe	2013	}
mbed_official	340:28d1f895c6fe	2014
mbed_official	340:28d1f895c6fe	2015	/**
mbed_official	340:28d1f895c6fe	2016	* @brief DeInitializes TIM One Pulse MSP.
mbed_official	340:28d1f895c6fe	2017	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	2018	* @retval None
mbed_official	340:28d1f895c6fe	2019	*/
mbed_official	340:28d1f895c6fe	2020	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2021	{
mbed_official	340:28d1f895c6fe	2022	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	2023	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	2024	*/
mbed_official	340:28d1f895c6fe	2025	}
mbed_official	340:28d1f895c6fe	2026
mbed_official	340:28d1f895c6fe	2027	/**
mbed_official	340:28d1f895c6fe	2028	* @brief Starts the TIM One Pulse signal generation.
mbed_official	340:28d1f895c6fe	2029	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	2030	* @param OutputChannel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2031	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2032	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2033	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2034	* @retval HAL status
mbed_official	340:28d1f895c6fe	2035	*/
mbed_official	340:28d1f895c6fe	2036	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	340:28d1f895c6fe	2037	{
mbed_official	340:28d1f895c6fe	2038	/* Enable the Capture compare and the Input Capture channels
mbed_official	340:28d1f895c6fe	2039	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2040	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	340:28d1f895c6fe	2041	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	340:28d1f895c6fe	2042	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	340:28d1f895c6fe	2043
mbed_official	340:28d1f895c6fe	2044	No need to enable the counter, it's enabled automatically by hardware
mbed_official	340:28d1f895c6fe	2045	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	340:28d1f895c6fe	2046
mbed_official	340:28d1f895c6fe	2047	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2048	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2049
mbed_official	340:28d1f895c6fe	2050	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	2051	{
mbed_official	340:28d1f895c6fe	2052	/* Enable the main output */
mbed_official	340:28d1f895c6fe	2053	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2054	}
mbed_official	340:28d1f895c6fe	2055
mbed_official	340:28d1f895c6fe	2056	/* Return function status */
mbed_official	340:28d1f895c6fe	2057	return HAL_OK;
mbed_official	340:28d1f895c6fe	2058	}
mbed_official	340:28d1f895c6fe	2059
mbed_official	340:28d1f895c6fe	2060	/**
mbed_official	340:28d1f895c6fe	2061	* @brief Stops the TIM One Pulse signal generation.
mbed_official	340:28d1f895c6fe	2062	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	2063	* @param OutputChannel : TIM Channels to be disable
mbed_official	340:28d1f895c6fe	2064	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2065	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2066	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2067	* @retval HAL status
mbed_official	340:28d1f895c6fe	2068	*/
mbed_official	340:28d1f895c6fe	2069	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	340:28d1f895c6fe	2070	{
mbed_official	340:28d1f895c6fe	2071	/* Disable the Capture compare and the Input Capture channels
mbed_official	340:28d1f895c6fe	2072	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2073	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	340:28d1f895c6fe	2074	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	340:28d1f895c6fe	2075	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	340:28d1f895c6fe	2076
mbed_official	340:28d1f895c6fe	2077	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2078	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2079
mbed_official	340:28d1f895c6fe	2080	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	2081	{
mbed_official	340:28d1f895c6fe	2082	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	2083	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2084	}
mbed_official	340:28d1f895c6fe	2085
mbed_official	340:28d1f895c6fe	2086	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	2087	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2088
mbed_official	340:28d1f895c6fe	2089	/* Return function status */
mbed_official	340:28d1f895c6fe	2090	return HAL_OK;
mbed_official	340:28d1f895c6fe	2091	}
mbed_official	340:28d1f895c6fe	2092
mbed_official	340:28d1f895c6fe	2093	/**
mbed_official	340:28d1f895c6fe	2094	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	2095	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	2096	* @param OutputChannel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2097	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2098	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2099	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2100	* @retval HAL status
mbed_official	340:28d1f895c6fe	2101	*/
mbed_official	340:28d1f895c6fe	2102	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	340:28d1f895c6fe	2103	{
mbed_official	340:28d1f895c6fe	2104	/* Enable the Capture compare and the Input Capture channels
mbed_official	340:28d1f895c6fe	2105	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2106	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	340:28d1f895c6fe	2107	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	340:28d1f895c6fe	2108	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	340:28d1f895c6fe	2109
mbed_official	340:28d1f895c6fe	2110	No need to enable the counter, it's enabled automatically by hardware
mbed_official	340:28d1f895c6fe	2111	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	340:28d1f895c6fe	2112
mbed_official	340:28d1f895c6fe	2113	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	2114	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2115
mbed_official	340:28d1f895c6fe	2116	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	2117	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2118
mbed_official	340:28d1f895c6fe	2119	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2120	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2121
mbed_official	340:28d1f895c6fe	2122	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	2123	{
mbed_official	340:28d1f895c6fe	2124	/* Enable the main output */
mbed_official	340:28d1f895c6fe	2125	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2126	}
mbed_official	340:28d1f895c6fe	2127
mbed_official	340:28d1f895c6fe	2128	/* Return function status */
mbed_official	340:28d1f895c6fe	2129	return HAL_OK;
mbed_official	340:28d1f895c6fe	2130	}
mbed_official	340:28d1f895c6fe	2131
mbed_official	340:28d1f895c6fe	2132	/**
mbed_official	340:28d1f895c6fe	2133	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official	340:28d1f895c6fe	2134	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	2135	* @param OutputChannel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2136	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2137	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2138	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2139	* @retval HAL status
mbed_official	340:28d1f895c6fe	2140	*/
mbed_official	340:28d1f895c6fe	2141	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	340:28d1f895c6fe	2142	{
mbed_official	340:28d1f895c6fe	2143	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	340:28d1f895c6fe	2144	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2145
mbed_official	340:28d1f895c6fe	2146	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	340:28d1f895c6fe	2147	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2148
mbed_official	340:28d1f895c6fe	2149	/* Disable the Capture compare and the Input Capture channels
mbed_official	340:28d1f895c6fe	2150	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2151	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	340:28d1f895c6fe	2152	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	340:28d1f895c6fe	2153	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	340:28d1f895c6fe	2154	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2155	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2156
mbed_official	340:28d1f895c6fe	2157	if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
mbed_official	340:28d1f895c6fe	2158	{
mbed_official	340:28d1f895c6fe	2159	/* Disable the Main Ouput */
mbed_official	340:28d1f895c6fe	2160	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2161	}
mbed_official	340:28d1f895c6fe	2162
mbed_official	340:28d1f895c6fe	2163	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	2164	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2165
mbed_official	340:28d1f895c6fe	2166	/* Return function status */
mbed_official	340:28d1f895c6fe	2167	return HAL_OK;
mbed_official	340:28d1f895c6fe	2168	}
mbed_official	340:28d1f895c6fe	2169
mbed_official	340:28d1f895c6fe	2170	/**
mbed_official	340:28d1f895c6fe	2171	* @}
mbed_official	340:28d1f895c6fe	2172	*/
mbed_official	340:28d1f895c6fe	2173
mbed_official	340:28d1f895c6fe	2174	/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
mbed_official	340:28d1f895c6fe	2175	* @brief Time Encoder functions
mbed_official	340:28d1f895c6fe	2176	*
mbed_official	340:28d1f895c6fe	2177	@verbatim
mbed_official	340:28d1f895c6fe	2178	==============================================================================
mbed_official	340:28d1f895c6fe	2179	##### Time Encoder functions #####
mbed_official	340:28d1f895c6fe	2180	==============================================================================
mbed_official	340:28d1f895c6fe	2181	[..]
mbed_official	340:28d1f895c6fe	2182	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	2183	(+) Initialize and configure the TIM Encoder.
mbed_official	340:28d1f895c6fe	2184	(+) De-initialize the TIM Encoder.
mbed_official	340:28d1f895c6fe	2185	(+) Start the Time Encoder.
mbed_official	340:28d1f895c6fe	2186	(+) Stop the Time Encoder.
mbed_official	340:28d1f895c6fe	2187	(+) Start the Time Encoder and enable interrupt.
mbed_official	340:28d1f895c6fe	2188	(+) Stop the Time Encoder and disable interrupt.
mbed_official	340:28d1f895c6fe	2189	(+) Start the Time Encoder and enable DMA transfer.
mbed_official	340:28d1f895c6fe	2190	(+) Stop the Time Encoder and disable DMA transfer.
mbed_official	340:28d1f895c6fe	2191
mbed_official	340:28d1f895c6fe	2192	@endverbatim
mbed_official	340:28d1f895c6fe	2193	* @{
mbed_official	340:28d1f895c6fe	2194	*/
mbed_official	340:28d1f895c6fe	2195	/**
mbed_official	340:28d1f895c6fe	2196	* @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official	340:28d1f895c6fe	2197	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2198	* @param sConfig : TIM Encoder Interface configuration structure
mbed_official	340:28d1f895c6fe	2199	* @retval HAL status
mbed_official	340:28d1f895c6fe	2200	*/
mbed_official	340:28d1f895c6fe	2201	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
mbed_official	340:28d1f895c6fe	2202	{
mbed_official	340:28d1f895c6fe	2203	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	2204	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	2205	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	2206
mbed_official	340:28d1f895c6fe	2207	/* Check the TIM handle allocation */
mbed_official	441:d2c15dda23c1	2208	if(htim == NULL)
mbed_official	340:28d1f895c6fe	2209	{
mbed_official	340:28d1f895c6fe	2210	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	2211	}
mbed_official	340:28d1f895c6fe	2212
mbed_official	340:28d1f895c6fe	2213	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2214	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2215	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official	340:28d1f895c6fe	2216	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official	340:28d1f895c6fe	2217	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official	340:28d1f895c6fe	2218	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official	340:28d1f895c6fe	2219	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official	340:28d1f895c6fe	2220	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official	340:28d1f895c6fe	2221	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official	340:28d1f895c6fe	2222	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official	340:28d1f895c6fe	2223	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official	340:28d1f895c6fe	2224
mbed_official	340:28d1f895c6fe	2225	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	2226	{
mbed_official	340:28d1f895c6fe	2227	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	340:28d1f895c6fe	2228	HAL_TIM_Encoder_MspInit(htim);
mbed_official	340:28d1f895c6fe	2229	}
mbed_official	340:28d1f895c6fe	2230
mbed_official	340:28d1f895c6fe	2231	/* Set the TIM state */
mbed_official	340:28d1f895c6fe	2232	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	2233
mbed_official	340:28d1f895c6fe	2234	/* Reset the SMS bits */
mbed_official	340:28d1f895c6fe	2235	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	340:28d1f895c6fe	2236
mbed_official	340:28d1f895c6fe	2237	/* Configure the Time base in the Encoder Mode */
mbed_official	340:28d1f895c6fe	2238	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	340:28d1f895c6fe	2239
mbed_official	340:28d1f895c6fe	2240	/* Get the TIMx SMCR register value */
mbed_official	340:28d1f895c6fe	2241	tmpsmcr = htim->Instance->SMCR;
mbed_official	340:28d1f895c6fe	2242
mbed_official	340:28d1f895c6fe	2243	/* Get the TIMx CCMR1 register value */
mbed_official	340:28d1f895c6fe	2244	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	340:28d1f895c6fe	2245
mbed_official	340:28d1f895c6fe	2246	/* Get the TIMx CCER register value */
mbed_official	340:28d1f895c6fe	2247	tmpccer = htim->Instance->CCER;
mbed_official	340:28d1f895c6fe	2248
mbed_official	340:28d1f895c6fe	2249	/* Set the encoder Mode */
mbed_official	340:28d1f895c6fe	2250	tmpsmcr \|= sConfig->EncoderMode;
mbed_official	340:28d1f895c6fe	2251
mbed_official	340:28d1f895c6fe	2252	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official	340:28d1f895c6fe	2253	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
mbed_official	340:28d1f895c6fe	2254	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
mbed_official	340:28d1f895c6fe	2255
mbed_official	340:28d1f895c6fe	2256	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official	340:28d1f895c6fe	2257	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
mbed_official	340:28d1f895c6fe	2258	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
mbed_official	340:28d1f895c6fe	2259	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
mbed_official	340:28d1f895c6fe	2260	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
mbed_official	340:28d1f895c6fe	2261
mbed_official	340:28d1f895c6fe	2262	/* Set the TI1 and the TI2 Polarities */
mbed_official	340:28d1f895c6fe	2263	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
mbed_official	340:28d1f895c6fe	2264	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
mbed_official	340:28d1f895c6fe	2265	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
mbed_official	340:28d1f895c6fe	2266
mbed_official	340:28d1f895c6fe	2267	/* Write to TIMx SMCR */
mbed_official	340:28d1f895c6fe	2268	htim->Instance->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	2269
mbed_official	340:28d1f895c6fe	2270	/* Write to TIMx CCMR1 */
mbed_official	340:28d1f895c6fe	2271	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	340:28d1f895c6fe	2272
mbed_official	340:28d1f895c6fe	2273	/* Write to TIMx CCER */
mbed_official	340:28d1f895c6fe	2274	htim->Instance->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	2275
mbed_official	340:28d1f895c6fe	2276	/* Initialize the TIM state*/
mbed_official	340:28d1f895c6fe	2277	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	2278
mbed_official	340:28d1f895c6fe	2279	return HAL_OK;
mbed_official	340:28d1f895c6fe	2280	}
mbed_official	340:28d1f895c6fe	2281
mbed_official	340:28d1f895c6fe	2282
mbed_official	340:28d1f895c6fe	2283	/**
mbed_official	340:28d1f895c6fe	2284	* @brief DeInitializes the TIM Encoder interface
mbed_official	340:28d1f895c6fe	2285	* @param htim : TIM Encoder handle
mbed_official	340:28d1f895c6fe	2286	* @retval HAL status
mbed_official	340:28d1f895c6fe	2287	*/
mbed_official	340:28d1f895c6fe	2288	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2289	{
mbed_official	340:28d1f895c6fe	2290	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2291	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2292
mbed_official	340:28d1f895c6fe	2293	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	2294
mbed_official	340:28d1f895c6fe	2295	/* Disable the TIM Peripheral Clock */
mbed_official	340:28d1f895c6fe	2296	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2297
mbed_official	340:28d1f895c6fe	2298	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	2299	HAL_TIM_Encoder_MspDeInit(htim);
mbed_official	340:28d1f895c6fe	2300
mbed_official	340:28d1f895c6fe	2301	/* Change TIM state */
mbed_official	340:28d1f895c6fe	2302	htim->State = HAL_TIM_STATE_RESET;
mbed_official	340:28d1f895c6fe	2303
mbed_official	340:28d1f895c6fe	2304	/* Release Lock */
mbed_official	340:28d1f895c6fe	2305	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	2306
mbed_official	340:28d1f895c6fe	2307	return HAL_OK;
mbed_official	340:28d1f895c6fe	2308	}
mbed_official	340:28d1f895c6fe	2309
mbed_official	340:28d1f895c6fe	2310	/**
mbed_official	340:28d1f895c6fe	2311	* @brief Initializes the TIM Encoder Interface MSP.
mbed_official	340:28d1f895c6fe	2312	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	2313	* @retval None
mbed_official	340:28d1f895c6fe	2314	*/
mbed_official	340:28d1f895c6fe	2315	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2316	{
mbed_official	340:28d1f895c6fe	2317	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	2318	the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	2319	*/
mbed_official	340:28d1f895c6fe	2320	}
mbed_official	340:28d1f895c6fe	2321
mbed_official	340:28d1f895c6fe	2322	/**
mbed_official	340:28d1f895c6fe	2323	* @brief DeInitializes TIM Encoder Interface MSP.
mbed_official	340:28d1f895c6fe	2324	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	2325	* @retval None
mbed_official	340:28d1f895c6fe	2326	*/
mbed_official	340:28d1f895c6fe	2327	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2328	{
mbed_official	340:28d1f895c6fe	2329	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	2330	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	2331	*/
mbed_official	340:28d1f895c6fe	2332	}
mbed_official	340:28d1f895c6fe	2333
mbed_official	340:28d1f895c6fe	2334	/**
mbed_official	340:28d1f895c6fe	2335	* @brief Starts the TIM Encoder Interface.
mbed_official	340:28d1f895c6fe	2336	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2337	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2338	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2339	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2340	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2341	* @retval HAL status
mbed_official	340:28d1f895c6fe	2342	*/
mbed_official	340:28d1f895c6fe	2343	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2344	{
mbed_official	340:28d1f895c6fe	2345	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2346	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2347
mbed_official	340:28d1f895c6fe	2348	/* Enable the encoder interface channels */
mbed_official	340:28d1f895c6fe	2349	switch (Channel)
mbed_official	340:28d1f895c6fe	2350	{
mbed_official	340:28d1f895c6fe	2351	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	2352	{
mbed_official	340:28d1f895c6fe	2353	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2354	break;
mbed_official	340:28d1f895c6fe	2355	}
mbed_official	340:28d1f895c6fe	2356	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	2357	{
mbed_official	340:28d1f895c6fe	2358	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2359	break;
mbed_official	340:28d1f895c6fe	2360	}
mbed_official	340:28d1f895c6fe	2361	default :
mbed_official	340:28d1f895c6fe	2362	{
mbed_official	340:28d1f895c6fe	2363	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2364	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2365	break;
mbed_official	340:28d1f895c6fe	2366	}
mbed_official	340:28d1f895c6fe	2367	}
mbed_official	340:28d1f895c6fe	2368	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	2369	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2370
mbed_official	340:28d1f895c6fe	2371	/* Return function status */
mbed_official	340:28d1f895c6fe	2372	return HAL_OK;
mbed_official	340:28d1f895c6fe	2373	}
mbed_official	340:28d1f895c6fe	2374
mbed_official	340:28d1f895c6fe	2375	/**
mbed_official	340:28d1f895c6fe	2376	* @brief Stops the TIM Encoder Interface.
mbed_official	340:28d1f895c6fe	2377	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2378	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	2379	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2380	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2381	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2382	* @retval HAL status
mbed_official	340:28d1f895c6fe	2383	*/
mbed_official	340:28d1f895c6fe	2384	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2385	{
mbed_official	340:28d1f895c6fe	2386	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2387	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2388
mbed_official	340:28d1f895c6fe	2389	/* Disable the Input Capture channels 1 and 2
mbed_official	340:28d1f895c6fe	2390	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	340:28d1f895c6fe	2391	switch (Channel)
mbed_official	340:28d1f895c6fe	2392	{
mbed_official	340:28d1f895c6fe	2393	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	2394	{
mbed_official	340:28d1f895c6fe	2395	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2396	break;
mbed_official	340:28d1f895c6fe	2397	}
mbed_official	340:28d1f895c6fe	2398	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	2399	{
mbed_official	340:28d1f895c6fe	2400	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2401	break;
mbed_official	340:28d1f895c6fe	2402	}
mbed_official	340:28d1f895c6fe	2403	default :
mbed_official	340:28d1f895c6fe	2404	{
mbed_official	340:28d1f895c6fe	2405	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2406	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2407	break;
mbed_official	340:28d1f895c6fe	2408	}
mbed_official	340:28d1f895c6fe	2409	}
mbed_official	340:28d1f895c6fe	2410
mbed_official	340:28d1f895c6fe	2411	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	2412	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2413
mbed_official	340:28d1f895c6fe	2414	/* Return function status */
mbed_official	340:28d1f895c6fe	2415	return HAL_OK;
mbed_official	340:28d1f895c6fe	2416	}
mbed_official	340:28d1f895c6fe	2417
mbed_official	340:28d1f895c6fe	2418	/**
mbed_official	340:28d1f895c6fe	2419	* @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official	340:28d1f895c6fe	2420	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2421	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2422	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2423	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2424	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2425	* @retval HAL status
mbed_official	340:28d1f895c6fe	2426	*/
mbed_official	340:28d1f895c6fe	2427	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2428	{
mbed_official	340:28d1f895c6fe	2429	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2430	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2431
mbed_official	340:28d1f895c6fe	2432	/* Enable the encoder interface channels */
mbed_official	340:28d1f895c6fe	2433	/* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official	340:28d1f895c6fe	2434	switch (Channel)
mbed_official	340:28d1f895c6fe	2435	{
mbed_official	340:28d1f895c6fe	2436	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	2437	{
mbed_official	340:28d1f895c6fe	2438	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2439	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2440	break;
mbed_official	340:28d1f895c6fe	2441	}
mbed_official	340:28d1f895c6fe	2442	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	2443	{
mbed_official	340:28d1f895c6fe	2444	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2445	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2446	break;
mbed_official	340:28d1f895c6fe	2447	}
mbed_official	340:28d1f895c6fe	2448	default :
mbed_official	340:28d1f895c6fe	2449	{
mbed_official	340:28d1f895c6fe	2450	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2451	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2452	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2453	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2454	break;
mbed_official	340:28d1f895c6fe	2455	}
mbed_official	340:28d1f895c6fe	2456	}
mbed_official	340:28d1f895c6fe	2457
mbed_official	340:28d1f895c6fe	2458	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	2459	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2460
mbed_official	340:28d1f895c6fe	2461	/* Return function status */
mbed_official	340:28d1f895c6fe	2462	return HAL_OK;
mbed_official	340:28d1f895c6fe	2463	}
mbed_official	340:28d1f895c6fe	2464
mbed_official	340:28d1f895c6fe	2465	/**
mbed_official	340:28d1f895c6fe	2466	* @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official	340:28d1f895c6fe	2467	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2468	* @param Channel : TIM Channels to be disabled
mbed_official	340:28d1f895c6fe	2469	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2472	* @retval HAL status
mbed_official	340:28d1f895c6fe	2473	*/
mbed_official	340:28d1f895c6fe	2474	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2475	{
mbed_official	340:28d1f895c6fe	2476	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2477	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2478
mbed_official	340:28d1f895c6fe	2479	/* Disable the Input Capture channels 1 and 2
mbed_official	340:28d1f895c6fe	2480	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	340:28d1f895c6fe	2481	if(Channel == TIM_CHANNEL_1)
mbed_official	340:28d1f895c6fe	2482	{
mbed_official	340:28d1f895c6fe	2483	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2484
mbed_official	340:28d1f895c6fe	2485	/* Disable the capture compare Interrupts 1 */
mbed_official	340:28d1f895c6fe	2486	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2487	}
mbed_official	340:28d1f895c6fe	2488	else if(Channel == TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2489	{
mbed_official	340:28d1f895c6fe	2490	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2491
mbed_official	340:28d1f895c6fe	2492	/* Disable the capture compare Interrupts 2 */
mbed_official	340:28d1f895c6fe	2493	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2494	}
mbed_official	340:28d1f895c6fe	2495	else
mbed_official	340:28d1f895c6fe	2496	{
mbed_official	340:28d1f895c6fe	2497	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2498	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2499
mbed_official	340:28d1f895c6fe	2500	/* Disable the capture compare Interrupts 1 and 2 */
mbed_official	340:28d1f895c6fe	2501	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2502	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2503	}
mbed_official	340:28d1f895c6fe	2504
mbed_official	340:28d1f895c6fe	2505	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	2506	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2507
mbed_official	340:28d1f895c6fe	2508	/* Change the htim state */
mbed_official	340:28d1f895c6fe	2509	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	2510
mbed_official	340:28d1f895c6fe	2511	/* Return function status */
mbed_official	340:28d1f895c6fe	2512	return HAL_OK;
mbed_official	340:28d1f895c6fe	2513	}
mbed_official	340:28d1f895c6fe	2514
mbed_official	340:28d1f895c6fe	2515	/**
mbed_official	340:28d1f895c6fe	2516	* @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official	340:28d1f895c6fe	2517	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2518	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2519	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2520	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2521	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2522	* @param pData1 : The destination Buffer address for IC1.
mbed_official	340:28d1f895c6fe	2523	* @param pData2 : The destination Buffer address for IC2.
mbed_official	340:28d1f895c6fe	2524	* @param Length : The length of data to be transferred from TIM peripheral to memory.
mbed_official	340:28d1f895c6fe	2525	* @retval HAL status
mbed_official	340:28d1f895c6fe	2526	*/
mbed_official	340:28d1f895c6fe	2527	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
mbed_official	340:28d1f895c6fe	2528	{
mbed_official	340:28d1f895c6fe	2529	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2530	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2531
mbed_official	340:28d1f895c6fe	2532	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	2533	{
mbed_official	340:28d1f895c6fe	2534	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	2535	}
mbed_official	340:28d1f895c6fe	2536	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	2537	{
mbed_official	340:28d1f895c6fe	2538	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
mbed_official	340:28d1f895c6fe	2539	{
mbed_official	340:28d1f895c6fe	2540	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	2541	}
mbed_official	340:28d1f895c6fe	2542	else
mbed_official	340:28d1f895c6fe	2543	{
mbed_official	340:28d1f895c6fe	2544	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	2545	}
mbed_official	340:28d1f895c6fe	2546	}
mbed_official	340:28d1f895c6fe	2547
mbed_official	340:28d1f895c6fe	2548	switch (Channel)
mbed_official	340:28d1f895c6fe	2549	{
mbed_official	340:28d1f895c6fe	2550	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	2551	{
mbed_official	340:28d1f895c6fe	2552	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	2553	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	2554
mbed_official	340:28d1f895c6fe	2555	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	2556	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	2557
mbed_official	340:28d1f895c6fe	2558	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	2559	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official	340:28d1f895c6fe	2560
mbed_official	340:28d1f895c6fe	2561	/* Enable the TIM Input Capture DMA request */
mbed_official	340:28d1f895c6fe	2562	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	2563
mbed_official	340:28d1f895c6fe	2564	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	2565	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2566
mbed_official	340:28d1f895c6fe	2567	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	2568	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2569	}
mbed_official	340:28d1f895c6fe	2570	break;
mbed_official	340:28d1f895c6fe	2571
mbed_official	340:28d1f895c6fe	2572	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	2573	{
mbed_official	340:28d1f895c6fe	2574	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	2575	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	2576
mbed_official	340:28d1f895c6fe	2577	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	2578	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official	340:28d1f895c6fe	2579	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	2580	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	340:28d1f895c6fe	2581
mbed_official	340:28d1f895c6fe	2582	/* Enable the TIM Input Capture DMA request */
mbed_official	340:28d1f895c6fe	2583	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	2584
mbed_official	340:28d1f895c6fe	2585	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	2586	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2587
mbed_official	340:28d1f895c6fe	2588	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	2589	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2590	}
mbed_official	340:28d1f895c6fe	2591	break;
mbed_official	340:28d1f895c6fe	2592
mbed_official	340:28d1f895c6fe	2593	case TIM_CHANNEL_ALL:
mbed_official	340:28d1f895c6fe	2594	{
mbed_official	340:28d1f895c6fe	2595	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	2596	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	2597
mbed_official	340:28d1f895c6fe	2598	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	2599	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	2600
mbed_official	340:28d1f895c6fe	2601	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	2602	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official	340:28d1f895c6fe	2603
mbed_official	340:28d1f895c6fe	2604	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	2605	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	2606
mbed_official	340:28d1f895c6fe	2607	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	2608	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	2609
mbed_official	340:28d1f895c6fe	2610	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	2611	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	340:28d1f895c6fe	2612
mbed_official	340:28d1f895c6fe	2613	/* Enable the Peripheral */
mbed_official	340:28d1f895c6fe	2614	__HAL_TIM_ENABLE(htim);
mbed_official	340:28d1f895c6fe	2615
mbed_official	340:28d1f895c6fe	2616	/* Enable the Capture compare channel */
mbed_official	340:28d1f895c6fe	2617	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2618	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	340:28d1f895c6fe	2619
mbed_official	340:28d1f895c6fe	2620	/* Enable the TIM Input Capture DMA request */
mbed_official	340:28d1f895c6fe	2621	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	2622	/* Enable the TIM Input Capture DMA request */
mbed_official	340:28d1f895c6fe	2623	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	2624	}
mbed_official	340:28d1f895c6fe	2625	break;
mbed_official	340:28d1f895c6fe	2626
mbed_official	340:28d1f895c6fe	2627	default:
mbed_official	340:28d1f895c6fe	2628	break;
mbed_official	340:28d1f895c6fe	2629	}
mbed_official	340:28d1f895c6fe	2630	/* Return function status */
mbed_official	340:28d1f895c6fe	2631	return HAL_OK;
mbed_official	340:28d1f895c6fe	2632	}
mbed_official	340:28d1f895c6fe	2633
mbed_official	340:28d1f895c6fe	2634	/**
mbed_official	340:28d1f895c6fe	2635	* @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official	340:28d1f895c6fe	2636	* @param htim : TIM Encoder Interface handle
mbed_official	340:28d1f895c6fe	2637	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2638	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2639	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2640	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2641	* @retval HAL status
mbed_official	340:28d1f895c6fe	2642	*/
mbed_official	340:28d1f895c6fe	2643	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2644	{
mbed_official	340:28d1f895c6fe	2645	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2646	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2647
mbed_official	340:28d1f895c6fe	2648	/* Disable the Input Capture channels 1 and 2
mbed_official	340:28d1f895c6fe	2649	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	340:28d1f895c6fe	2650	if(Channel == TIM_CHANNEL_1)
mbed_official	340:28d1f895c6fe	2651	{
mbed_official	340:28d1f895c6fe	2652	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2653
mbed_official	340:28d1f895c6fe	2654	/* Disable the capture compare DMA Request 1 */
mbed_official	340:28d1f895c6fe	2655	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	2656	}
mbed_official	340:28d1f895c6fe	2657	else if(Channel == TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2658	{
mbed_official	340:28d1f895c6fe	2659	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2660
mbed_official	340:28d1f895c6fe	2661	/* Disable the capture compare DMA Request 2 */
mbed_official	340:28d1f895c6fe	2662	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	2663	}
mbed_official	340:28d1f895c6fe	2664	else
mbed_official	340:28d1f895c6fe	2665	{
mbed_official	340:28d1f895c6fe	2666	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2667	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	340:28d1f895c6fe	2668
mbed_official	340:28d1f895c6fe	2669	/* Disable the capture compare DMA Request 1 and 2 */
mbed_official	340:28d1f895c6fe	2670	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	340:28d1f895c6fe	2671	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	340:28d1f895c6fe	2672	}
mbed_official	340:28d1f895c6fe	2673
mbed_official	340:28d1f895c6fe	2674	/* Disable the Peripheral */
mbed_official	340:28d1f895c6fe	2675	__HAL_TIM_DISABLE(htim);
mbed_official	340:28d1f895c6fe	2676
mbed_official	340:28d1f895c6fe	2677	/* Change the htim state */
mbed_official	340:28d1f895c6fe	2678	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	2679
mbed_official	340:28d1f895c6fe	2680	/* Return function status */
mbed_official	340:28d1f895c6fe	2681	return HAL_OK;
mbed_official	340:28d1f895c6fe	2682	}
mbed_official	340:28d1f895c6fe	2683
mbed_official	340:28d1f895c6fe	2684	/**
mbed_official	340:28d1f895c6fe	2685	* @}
mbed_official	340:28d1f895c6fe	2686	*/
mbed_official	340:28d1f895c6fe	2687	/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
mbed_official	340:28d1f895c6fe	2688	* @brief IRQ handler management
mbed_official	340:28d1f895c6fe	2689	*
mbed_official	340:28d1f895c6fe	2690	@verbatim
mbed_official	340:28d1f895c6fe	2691	==============================================================================
mbed_official	340:28d1f895c6fe	2692	##### IRQ handler management #####
mbed_official	340:28d1f895c6fe	2693	==============================================================================
mbed_official	340:28d1f895c6fe	2694	[..]
mbed_official	340:28d1f895c6fe	2695	This section provides Timer IRQ handler function.
mbed_official	340:28d1f895c6fe	2696
mbed_official	340:28d1f895c6fe	2697	@endverbatim
mbed_official	340:28d1f895c6fe	2698	* @{
mbed_official	340:28d1f895c6fe	2699	*/
mbed_official	340:28d1f895c6fe	2700	/**
mbed_official	340:28d1f895c6fe	2701	* @brief This function handles TIM interrupts requests.
mbed_official	340:28d1f895c6fe	2702	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	2703	* @retval None
mbed_official	340:28d1f895c6fe	2704	*/
mbed_official	340:28d1f895c6fe	2705	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	2706	{
mbed_official	340:28d1f895c6fe	2707	/* Capture compare 1 event */
mbed_official	340:28d1f895c6fe	2708	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official	340:28d1f895c6fe	2709	{
mbed_official	340:28d1f895c6fe	2710	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official	340:28d1f895c6fe	2711	{
mbed_official	340:28d1f895c6fe	2712	{
mbed_official	340:28d1f895c6fe	2713	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official	340:28d1f895c6fe	2714	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official	340:28d1f895c6fe	2715
mbed_official	340:28d1f895c6fe	2716	/* Input capture event */
mbed_official	340:28d1f895c6fe	2717	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official	340:28d1f895c6fe	2718	{
mbed_official	340:28d1f895c6fe	2719	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	340:28d1f895c6fe	2720	}
mbed_official	340:28d1f895c6fe	2721	/* Output compare event */
mbed_official	340:28d1f895c6fe	2722	else
mbed_official	340:28d1f895c6fe	2723	{
mbed_official	340:28d1f895c6fe	2724	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	2725	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	340:28d1f895c6fe	2726	}
mbed_official	340:28d1f895c6fe	2727	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	2728	}
mbed_official	340:28d1f895c6fe	2729	}
mbed_official	340:28d1f895c6fe	2730	}
mbed_official	340:28d1f895c6fe	2731	/* Capture compare 2 event */
mbed_official	340:28d1f895c6fe	2732	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official	340:28d1f895c6fe	2733	{
mbed_official	340:28d1f895c6fe	2734	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official	340:28d1f895c6fe	2735	{
mbed_official	340:28d1f895c6fe	2736	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official	340:28d1f895c6fe	2737	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official	340:28d1f895c6fe	2738	/* Input capture event */
mbed_official	340:28d1f895c6fe	2739	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official	340:28d1f895c6fe	2740	{
mbed_official	340:28d1f895c6fe	2741	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	340:28d1f895c6fe	2742	}
mbed_official	340:28d1f895c6fe	2743	/* Output compare event */
mbed_official	340:28d1f895c6fe	2744	else
mbed_official	340:28d1f895c6fe	2745	{
mbed_official	340:28d1f895c6fe	2746	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	2747	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	340:28d1f895c6fe	2748	}
mbed_official	340:28d1f895c6fe	2749	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	2750	}
mbed_official	340:28d1f895c6fe	2751	}
mbed_official	340:28d1f895c6fe	2752	/* Capture compare 3 event */
mbed_official	340:28d1f895c6fe	2753	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official	340:28d1f895c6fe	2754	{
mbed_official	340:28d1f895c6fe	2755	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official	340:28d1f895c6fe	2756	{
mbed_official	340:28d1f895c6fe	2757	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official	340:28d1f895c6fe	2758	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official	340:28d1f895c6fe	2759	/* Input capture event */
mbed_official	340:28d1f895c6fe	2760	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official	340:28d1f895c6fe	2761	{
mbed_official	340:28d1f895c6fe	2762	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	340:28d1f895c6fe	2763	}
mbed_official	340:28d1f895c6fe	2764	/* Output compare event */
mbed_official	340:28d1f895c6fe	2765	else
mbed_official	340:28d1f895c6fe	2766	{
mbed_official	340:28d1f895c6fe	2767	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	2768	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	340:28d1f895c6fe	2769	}
mbed_official	340:28d1f895c6fe	2770	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	2771	}
mbed_official	340:28d1f895c6fe	2772	}
mbed_official	340:28d1f895c6fe	2773	/* Capture compare 4 event */
mbed_official	340:28d1f895c6fe	2774	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official	340:28d1f895c6fe	2775	{
mbed_official	340:28d1f895c6fe	2776	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official	340:28d1f895c6fe	2777	{
mbed_official	340:28d1f895c6fe	2778	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official	340:28d1f895c6fe	2779	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official	340:28d1f895c6fe	2780	/* Input capture event */
mbed_official	340:28d1f895c6fe	2781	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official	340:28d1f895c6fe	2782	{
mbed_official	340:28d1f895c6fe	2783	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	340:28d1f895c6fe	2784	}
mbed_official	340:28d1f895c6fe	2785	/* Output compare event */
mbed_official	340:28d1f895c6fe	2786	else
mbed_official	340:28d1f895c6fe	2787	{
mbed_official	340:28d1f895c6fe	2788	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	2789	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	340:28d1f895c6fe	2790	}
mbed_official	340:28d1f895c6fe	2791	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	2792	}
mbed_official	340:28d1f895c6fe	2793	}
mbed_official	340:28d1f895c6fe	2794	/* TIM Update event */
mbed_official	340:28d1f895c6fe	2795	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official	340:28d1f895c6fe	2796	{
mbed_official	340:28d1f895c6fe	2797	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official	340:28d1f895c6fe	2798	{
mbed_official	340:28d1f895c6fe	2799	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official	340:28d1f895c6fe	2800	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	2801	}
mbed_official	340:28d1f895c6fe	2802	}
mbed_official	340:28d1f895c6fe	2803	/* TIM Break input event */
mbed_official	340:28d1f895c6fe	2804	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official	340:28d1f895c6fe	2805	{
mbed_official	340:28d1f895c6fe	2806	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
mbed_official	340:28d1f895c6fe	2807	{
mbed_official	340:28d1f895c6fe	2808	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official	340:28d1f895c6fe	2809	HAL_TIMEx_BreakCallback(htim);
mbed_official	340:28d1f895c6fe	2810	}
mbed_official	340:28d1f895c6fe	2811	}
mbed_official	340:28d1f895c6fe	2812	/* TIM Trigger detection event */
mbed_official	340:28d1f895c6fe	2813	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official	340:28d1f895c6fe	2814	{
mbed_official	340:28d1f895c6fe	2815	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official	340:28d1f895c6fe	2816	{
mbed_official	340:28d1f895c6fe	2817	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official	340:28d1f895c6fe	2818	HAL_TIM_TriggerCallback(htim);
mbed_official	340:28d1f895c6fe	2819	}
mbed_official	340:28d1f895c6fe	2820	}
mbed_official	340:28d1f895c6fe	2821	/* TIM commutation event */
mbed_official	340:28d1f895c6fe	2822	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official	340:28d1f895c6fe	2823	{
mbed_official	340:28d1f895c6fe	2824	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
mbed_official	340:28d1f895c6fe	2825	{
mbed_official	340:28d1f895c6fe	2826	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official	340:28d1f895c6fe	2827	HAL_TIMEx_CommutationCallback(htim);
mbed_official	340:28d1f895c6fe	2828	}
mbed_official	340:28d1f895c6fe	2829	}
mbed_official	340:28d1f895c6fe	2830	}
mbed_official	340:28d1f895c6fe	2831
mbed_official	340:28d1f895c6fe	2832	/**
mbed_official	340:28d1f895c6fe	2833	* @}
mbed_official	340:28d1f895c6fe	2834	*/
mbed_official	340:28d1f895c6fe	2835
mbed_official	340:28d1f895c6fe	2836	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official	340:28d1f895c6fe	2837	* @brief Peripheral Control functions
mbed_official	340:28d1f895c6fe	2838	*
mbed_official	340:28d1f895c6fe	2839	@verbatim
mbed_official	340:28d1f895c6fe	2840	==============================================================================
mbed_official	340:28d1f895c6fe	2841	##### Peripheral Control functions #####
mbed_official	340:28d1f895c6fe	2842	==============================================================================
mbed_official	340:28d1f895c6fe	2843	[..]
mbed_official	340:28d1f895c6fe	2844	This section provides functions allowing to:
mbed_official	340:28d1f895c6fe	2845	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official	340:28d1f895c6fe	2846	(+) Configure External Clock source.
mbed_official	340:28d1f895c6fe	2847	(+) Configure Complementary channels, break features and dead time.
mbed_official	340:28d1f895c6fe	2848	(+) Configure Master and the Slave synchronization.
mbed_official	340:28d1f895c6fe	2849	(+) Configure the DMA Burst Mode.
mbed_official	340:28d1f895c6fe	2850
mbed_official	340:28d1f895c6fe	2851	@endverbatim
mbed_official	340:28d1f895c6fe	2852	* @{
mbed_official	340:28d1f895c6fe	2853	*/
mbed_official	340:28d1f895c6fe	2854
mbed_official	340:28d1f895c6fe	2855	/**
mbed_official	340:28d1f895c6fe	2856	* @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official	340:28d1f895c6fe	2857	* parameters in the TIM_OC_InitTypeDef.
mbed_official	340:28d1f895c6fe	2858	* @param htim : TIM Output Compare handle
mbed_official	340:28d1f895c6fe	2859	* @param sConfig : TIM Output Compare configuration structure
mbed_official	340:28d1f895c6fe	2860	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2861	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2862	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2863	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2864	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	2865	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	2866	* @retval HAL status
mbed_official	340:28d1f895c6fe	2867	*/
mbed_official	340:28d1f895c6fe	2868	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2869	{
mbed_official	340:28d1f895c6fe	2870	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2871	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	340:28d1f895c6fe	2872	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official	340:28d1f895c6fe	2873	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	340:28d1f895c6fe	2874	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	340:28d1f895c6fe	2875	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	340:28d1f895c6fe	2876	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	340:28d1f895c6fe	2877
mbed_official	340:28d1f895c6fe	2878	/* Check input state */
mbed_official	340:28d1f895c6fe	2879	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	2880
mbed_official	340:28d1f895c6fe	2881	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	2882
mbed_official	340:28d1f895c6fe	2883	switch (Channel)
mbed_official	340:28d1f895c6fe	2884	{
mbed_official	340:28d1f895c6fe	2885	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	2886	{
mbed_official	340:28d1f895c6fe	2887	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2888	/* Configure the TIM Channel 1 in Output Compare */
mbed_official	340:28d1f895c6fe	2889	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	2890	}
mbed_official	340:28d1f895c6fe	2891	break;
mbed_official	340:28d1f895c6fe	2892
mbed_official	340:28d1f895c6fe	2893	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	2894	{
mbed_official	340:28d1f895c6fe	2895	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2896	/* Configure the TIM Channel 2 in Output Compare */
mbed_official	340:28d1f895c6fe	2897	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	2898	}
mbed_official	340:28d1f895c6fe	2899	break;
mbed_official	340:28d1f895c6fe	2900
mbed_official	340:28d1f895c6fe	2901	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	2902	{
mbed_official	340:28d1f895c6fe	2903	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2904	/* Configure the TIM Channel 3 in Output Compare */
mbed_official	340:28d1f895c6fe	2905	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	2906	}
mbed_official	340:28d1f895c6fe	2907	break;
mbed_official	340:28d1f895c6fe	2908
mbed_official	340:28d1f895c6fe	2909	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	2910	{
mbed_official	340:28d1f895c6fe	2911	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2912	/* Configure the TIM Channel 4 in Output Compare */
mbed_official	340:28d1f895c6fe	2913	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	2914	}
mbed_official	340:28d1f895c6fe	2915	break;
mbed_official	340:28d1f895c6fe	2916
mbed_official	340:28d1f895c6fe	2917	default:
mbed_official	340:28d1f895c6fe	2918	break;
mbed_official	340:28d1f895c6fe	2919	}
mbed_official	340:28d1f895c6fe	2920	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	2921
mbed_official	340:28d1f895c6fe	2922	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	2923
mbed_official	340:28d1f895c6fe	2924	return HAL_OK;
mbed_official	340:28d1f895c6fe	2925	}
mbed_official	340:28d1f895c6fe	2926
mbed_official	340:28d1f895c6fe	2927	/**
mbed_official	340:28d1f895c6fe	2928	* @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official	340:28d1f895c6fe	2929	* parameters in the TIM_IC_InitTypeDef.
mbed_official	340:28d1f895c6fe	2930	* @param htim : TIM IC handle
mbed_official	340:28d1f895c6fe	2931	* @param sConfig : TIM Input Capture configuration structure
mbed_official	340:28d1f895c6fe	2932	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	2933	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	2934	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	2935	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	2936	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	2937	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	2938	* @retval HAL status
mbed_official	340:28d1f895c6fe	2939	*/
mbed_official	340:28d1f895c6fe	2940	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	340:28d1f895c6fe	2941	{
mbed_official	340:28d1f895c6fe	2942	/* Check the parameters */
mbed_official	340:28d1f895c6fe	2943	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2944	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official	340:28d1f895c6fe	2945	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official	340:28d1f895c6fe	2946	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official	340:28d1f895c6fe	2947	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official	340:28d1f895c6fe	2948
mbed_official	340:28d1f895c6fe	2949	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	2950
mbed_official	340:28d1f895c6fe	2951	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	2952
mbed_official	340:28d1f895c6fe	2953	if (Channel == TIM_CHANNEL_1)
mbed_official	340:28d1f895c6fe	2954	{
mbed_official	340:28d1f895c6fe	2955	/* TI1 Configuration */
mbed_official	340:28d1f895c6fe	2956	TIM_TI1_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	2957	sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	2958	sConfig->ICSelection,
mbed_official	340:28d1f895c6fe	2959	sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	2960
mbed_official	340:28d1f895c6fe	2961	/* Reset the IC1PSC Bits */
mbed_official	340:28d1f895c6fe	2962	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	340:28d1f895c6fe	2963
mbed_official	340:28d1f895c6fe	2964	/* Set the IC1PSC value */
mbed_official	340:28d1f895c6fe	2965	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
mbed_official	340:28d1f895c6fe	2966	}
mbed_official	340:28d1f895c6fe	2967	else if (Channel == TIM_CHANNEL_2)
mbed_official	340:28d1f895c6fe	2968	{
mbed_official	340:28d1f895c6fe	2969	/* TI2 Configuration */
mbed_official	340:28d1f895c6fe	2970	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2971
mbed_official	340:28d1f895c6fe	2972	TIM_TI2_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	2973	sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	2974	sConfig->ICSelection,
mbed_official	340:28d1f895c6fe	2975	sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	2976
mbed_official	340:28d1f895c6fe	2977	/* Reset the IC2PSC Bits */
mbed_official	340:28d1f895c6fe	2978	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	340:28d1f895c6fe	2979
mbed_official	340:28d1f895c6fe	2980	/* Set the IC2PSC value */
mbed_official	340:28d1f895c6fe	2981	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
mbed_official	340:28d1f895c6fe	2982	}
mbed_official	340:28d1f895c6fe	2983	else if (Channel == TIM_CHANNEL_3)
mbed_official	340:28d1f895c6fe	2984	{
mbed_official	340:28d1f895c6fe	2985	/* TI3 Configuration */
mbed_official	340:28d1f895c6fe	2986	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	2987
mbed_official	340:28d1f895c6fe	2988	TIM_TI3_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	2989	sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	2990	sConfig->ICSelection,
mbed_official	340:28d1f895c6fe	2991	sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	2992
mbed_official	340:28d1f895c6fe	2993	/* Reset the IC3PSC Bits */
mbed_official	340:28d1f895c6fe	2994	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official	340:28d1f895c6fe	2995
mbed_official	340:28d1f895c6fe	2996	/* Set the IC3PSC value */
mbed_official	340:28d1f895c6fe	2997	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
mbed_official	340:28d1f895c6fe	2998	}
mbed_official	340:28d1f895c6fe	2999	else
mbed_official	340:28d1f895c6fe	3000	{
mbed_official	340:28d1f895c6fe	3001	/* TI4 Configuration */
mbed_official	340:28d1f895c6fe	3002	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3003
mbed_official	340:28d1f895c6fe	3004	TIM_TI4_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	3005	sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	3006	sConfig->ICSelection,
mbed_official	340:28d1f895c6fe	3007	sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	3008
mbed_official	340:28d1f895c6fe	3009	/* Reset the IC4PSC Bits */
mbed_official	340:28d1f895c6fe	3010	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official	340:28d1f895c6fe	3011
mbed_official	340:28d1f895c6fe	3012	/* Set the IC4PSC value */
mbed_official	340:28d1f895c6fe	3013	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
mbed_official	340:28d1f895c6fe	3014	}
mbed_official	340:28d1f895c6fe	3015
mbed_official	340:28d1f895c6fe	3016	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3017
mbed_official	340:28d1f895c6fe	3018	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	3019
mbed_official	340:28d1f895c6fe	3020	return HAL_OK;
mbed_official	340:28d1f895c6fe	3021	}
mbed_official	340:28d1f895c6fe	3022
mbed_official	340:28d1f895c6fe	3023	/**
mbed_official	340:28d1f895c6fe	3024	* @brief Initializes the TIM PWM channels according to the specified
mbed_official	340:28d1f895c6fe	3025	* parameters in the TIM_OC_InitTypeDef.
mbed_official	340:28d1f895c6fe	3026	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3027	* @param sConfig : TIM PWM configuration structure
mbed_official	340:28d1f895c6fe	3028	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	3029	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3030	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	3031	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	3032	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	3033	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	3034	* @retval HAL status
mbed_official	340:28d1f895c6fe	3035	*/
mbed_official	340:28d1f895c6fe	3036	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	340:28d1f895c6fe	3037	{
mbed_official	340:28d1f895c6fe	3038	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	3039
mbed_official	340:28d1f895c6fe	3040	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3041	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	340:28d1f895c6fe	3042	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official	340:28d1f895c6fe	3043	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	340:28d1f895c6fe	3044	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	340:28d1f895c6fe	3045	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official	340:28d1f895c6fe	3046	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	340:28d1f895c6fe	3047	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	340:28d1f895c6fe	3048
mbed_official	340:28d1f895c6fe	3049	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3050
mbed_official	340:28d1f895c6fe	3051	switch (Channel)
mbed_official	340:28d1f895c6fe	3052	{
mbed_official	340:28d1f895c6fe	3053	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	3054	{
mbed_official	340:28d1f895c6fe	3055	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3056	/* Configure the Channel 1 in PWM mode */
mbed_official	340:28d1f895c6fe	3057	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	3058
mbed_official	340:28d1f895c6fe	3059	/* Set the Preload enable bit for channel1 */
mbed_official	340:28d1f895c6fe	3060	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
mbed_official	340:28d1f895c6fe	3061
mbed_official	340:28d1f895c6fe	3062	/* Configure the Output Fast mode */
mbed_official	340:28d1f895c6fe	3063	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official	340:28d1f895c6fe	3064	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
mbed_official	340:28d1f895c6fe	3065	}
mbed_official	340:28d1f895c6fe	3066	break;
mbed_official	340:28d1f895c6fe	3067
mbed_official	340:28d1f895c6fe	3068	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	3069	{
mbed_official	340:28d1f895c6fe	3070	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3071	/* Configure the Channel 2 in PWM mode */
mbed_official	340:28d1f895c6fe	3072	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	3073
mbed_official	340:28d1f895c6fe	3074	/* Set the Preload enable bit for channel2 */
mbed_official	340:28d1f895c6fe	3075	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
mbed_official	340:28d1f895c6fe	3076
mbed_official	340:28d1f895c6fe	3077	/* Configure the Output Fast mode */
mbed_official	340:28d1f895c6fe	3078	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official	340:28d1f895c6fe	3079	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
mbed_official	340:28d1f895c6fe	3080	}
mbed_official	340:28d1f895c6fe	3081	break;
mbed_official	340:28d1f895c6fe	3082
mbed_official	340:28d1f895c6fe	3083	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	3084	{
mbed_official	340:28d1f895c6fe	3085	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3086	/* Configure the Channel 3 in PWM mode */
mbed_official	340:28d1f895c6fe	3087	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	3088
mbed_official	340:28d1f895c6fe	3089	/* Set the Preload enable bit for channel3 */
mbed_official	340:28d1f895c6fe	3090	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
mbed_official	340:28d1f895c6fe	3091
mbed_official	340:28d1f895c6fe	3092	/* Configure the Output Fast mode */
mbed_official	340:28d1f895c6fe	3093	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official	340:28d1f895c6fe	3094	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
mbed_official	340:28d1f895c6fe	3095	}
mbed_official	340:28d1f895c6fe	3096	break;
mbed_official	340:28d1f895c6fe	3097
mbed_official	340:28d1f895c6fe	3098	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	3099	{
mbed_official	340:28d1f895c6fe	3100	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3101	/* Configure the Channel 4 in PWM mode */
mbed_official	340:28d1f895c6fe	3102	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	340:28d1f895c6fe	3103
mbed_official	340:28d1f895c6fe	3104	/* Set the Preload enable bit for channel4 */
mbed_official	340:28d1f895c6fe	3105	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
mbed_official	340:28d1f895c6fe	3106
mbed_official	340:28d1f895c6fe	3107	/* Configure the Output Fast mode */
mbed_official	340:28d1f895c6fe	3108	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official	340:28d1f895c6fe	3109	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
mbed_official	340:28d1f895c6fe	3110	}
mbed_official	340:28d1f895c6fe	3111	break;
mbed_official	340:28d1f895c6fe	3112
mbed_official	340:28d1f895c6fe	3113	default:
mbed_official	340:28d1f895c6fe	3114	break;
mbed_official	340:28d1f895c6fe	3115	}
mbed_official	340:28d1f895c6fe	3116
mbed_official	340:28d1f895c6fe	3117	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3118
mbed_official	340:28d1f895c6fe	3119	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	3120
mbed_official	340:28d1f895c6fe	3121	return HAL_OK;
mbed_official	340:28d1f895c6fe	3122	}
mbed_official	340:28d1f895c6fe	3123
mbed_official	340:28d1f895c6fe	3124	/**
mbed_official	340:28d1f895c6fe	3125	* @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official	340:28d1f895c6fe	3126	* parameters in the TIM_OnePulse_InitTypeDef.
mbed_official	340:28d1f895c6fe	3127	* @param htim : TIM One Pulse handle
mbed_official	340:28d1f895c6fe	3128	* @param sConfig : TIM One Pulse configuration structure
mbed_official	340:28d1f895c6fe	3129	* @param OutputChannel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	3130	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3131	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	3132	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	3133	* @param InputChannel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	3134	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3135	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	3136	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	3137	* @retval HAL status
mbed_official	340:28d1f895c6fe	3138	*/
mbed_official	340:28d1f895c6fe	3139	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official	340:28d1f895c6fe	3140	{
mbed_official	340:28d1f895c6fe	3141	TIM_OC_InitTypeDef temp1;
mbed_official	340:28d1f895c6fe	3142
mbed_official	340:28d1f895c6fe	3143	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3144	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official	340:28d1f895c6fe	3145	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official	340:28d1f895c6fe	3146
mbed_official	340:28d1f895c6fe	3147	if(OutputChannel != InputChannel)
mbed_official	340:28d1f895c6fe	3148	{
mbed_official	340:28d1f895c6fe	3149	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	3150
mbed_official	340:28d1f895c6fe	3151	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3152
mbed_official	340:28d1f895c6fe	3153	/* Extract the Ouput compare configuration from sConfig structure */
mbed_official	340:28d1f895c6fe	3154	temp1.OCMode = sConfig->OCMode;
mbed_official	340:28d1f895c6fe	3155	temp1.Pulse = sConfig->Pulse;
mbed_official	340:28d1f895c6fe	3156	temp1.OCPolarity = sConfig->OCPolarity;
mbed_official	340:28d1f895c6fe	3157	temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official	340:28d1f895c6fe	3158	temp1.OCIdleState = sConfig->OCIdleState;
mbed_official	340:28d1f895c6fe	3159	temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official	340:28d1f895c6fe	3160
mbed_official	340:28d1f895c6fe	3161	switch (OutputChannel)
mbed_official	340:28d1f895c6fe	3162	{
mbed_official	340:28d1f895c6fe	3163	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	3164	{
mbed_official	340:28d1f895c6fe	3165	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3166
mbed_official	340:28d1f895c6fe	3167	TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official	340:28d1f895c6fe	3168	}
mbed_official	340:28d1f895c6fe	3169	break;
mbed_official	340:28d1f895c6fe	3170	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	3171	{
mbed_official	340:28d1f895c6fe	3172	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3173
mbed_official	340:28d1f895c6fe	3174	TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official	340:28d1f895c6fe	3175	}
mbed_official	340:28d1f895c6fe	3176	break;
mbed_official	340:28d1f895c6fe	3177	default:
mbed_official	340:28d1f895c6fe	3178	break;
mbed_official	340:28d1f895c6fe	3179	}
mbed_official	340:28d1f895c6fe	3180	switch (InputChannel)
mbed_official	340:28d1f895c6fe	3181	{
mbed_official	340:28d1f895c6fe	3182	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	3183	{
mbed_official	340:28d1f895c6fe	3184	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3185
mbed_official	340:28d1f895c6fe	3186	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	3187	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	3188
mbed_official	340:28d1f895c6fe	3189	/* Reset the IC1PSC Bits */
mbed_official	340:28d1f895c6fe	3190	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	340:28d1f895c6fe	3191
mbed_official	340:28d1f895c6fe	3192	/* Select the Trigger source */
mbed_official	340:28d1f895c6fe	3193	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	340:28d1f895c6fe	3194	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
mbed_official	340:28d1f895c6fe	3195
mbed_official	340:28d1f895c6fe	3196	/* Select the Slave Mode */
mbed_official	340:28d1f895c6fe	3197	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	340:28d1f895c6fe	3198	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	340:28d1f895c6fe	3199	}
mbed_official	340:28d1f895c6fe	3200	break;
mbed_official	340:28d1f895c6fe	3201	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	3202	{
mbed_official	340:28d1f895c6fe	3203	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3204
mbed_official	340:28d1f895c6fe	3205	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	340:28d1f895c6fe	3206	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	340:28d1f895c6fe	3207
mbed_official	340:28d1f895c6fe	3208	/* Reset the IC2PSC Bits */
mbed_official	340:28d1f895c6fe	3209	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	340:28d1f895c6fe	3210
mbed_official	340:28d1f895c6fe	3211	/* Select the Trigger source */
mbed_official	340:28d1f895c6fe	3212	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	340:28d1f895c6fe	3213	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
mbed_official	340:28d1f895c6fe	3214
mbed_official	340:28d1f895c6fe	3215	/* Select the Slave Mode */
mbed_official	340:28d1f895c6fe	3216	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	340:28d1f895c6fe	3217	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	340:28d1f895c6fe	3218	}
mbed_official	340:28d1f895c6fe	3219	break;
mbed_official	340:28d1f895c6fe	3220
mbed_official	340:28d1f895c6fe	3221	default:
mbed_official	340:28d1f895c6fe	3222	break;
mbed_official	340:28d1f895c6fe	3223	}
mbed_official	340:28d1f895c6fe	3224
mbed_official	340:28d1f895c6fe	3225	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3226
mbed_official	340:28d1f895c6fe	3227	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	3228
mbed_official	340:28d1f895c6fe	3229	return HAL_OK;
mbed_official	340:28d1f895c6fe	3230	}
mbed_official	340:28d1f895c6fe	3231	else
mbed_official	340:28d1f895c6fe	3232	{
mbed_official	340:28d1f895c6fe	3233	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	3234	}
mbed_official	340:28d1f895c6fe	3235	}
mbed_official	340:28d1f895c6fe	3236
mbed_official	340:28d1f895c6fe	3237	/**
mbed_official	340:28d1f895c6fe	3238	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official	340:28d1f895c6fe	3239	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3240	* @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
mbed_official	340:28d1f895c6fe	3241	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3242	* @arg TIM_DMABase_CR1
mbed_official	340:28d1f895c6fe	3243	* @arg TIM_DMABase_CR2
mbed_official	340:28d1f895c6fe	3244	* @arg TIM_DMABase_SMCR
mbed_official	340:28d1f895c6fe	3245	* @arg TIM_DMABase_DIER
mbed_official	340:28d1f895c6fe	3246	* @arg TIM_DMABase_SR
mbed_official	340:28d1f895c6fe	3247	* @arg TIM_DMABase_EGR
mbed_official	340:28d1f895c6fe	3248	* @arg TIM_DMABase_CCMR1
mbed_official	340:28d1f895c6fe	3249	* @arg TIM_DMABase_CCMR2
mbed_official	340:28d1f895c6fe	3250	* @arg TIM_DMABase_CCER
mbed_official	340:28d1f895c6fe	3251	* @arg TIM_DMABase_CNT
mbed_official	340:28d1f895c6fe	3252	* @arg TIM_DMABase_PSC
mbed_official	340:28d1f895c6fe	3253	* @arg TIM_DMABase_ARR
mbed_official	340:28d1f895c6fe	3254	* @arg TIM_DMABase_RCR
mbed_official	340:28d1f895c6fe	3255	* @arg TIM_DMABase_CCR1
mbed_official	340:28d1f895c6fe	3256	* @arg TIM_DMABase_CCR2
mbed_official	340:28d1f895c6fe	3257	* @arg TIM_DMABase_CCR3
mbed_official	340:28d1f895c6fe	3258	* @arg TIM_DMABase_CCR4
mbed_official	340:28d1f895c6fe	3259	* @arg TIM_DMABase_BDTR
mbed_official	340:28d1f895c6fe	3260	* @arg TIM_DMABase_DCR
mbed_official	340:28d1f895c6fe	3261	* @param BurstRequestSrc : TIM DMA Request sources
mbed_official	340:28d1f895c6fe	3262	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3263	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	340:28d1f895c6fe	3264	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	340:28d1f895c6fe	3265	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	340:28d1f895c6fe	3266	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	340:28d1f895c6fe	3267	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	340:28d1f895c6fe	3268	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	340:28d1f895c6fe	3269	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	340:28d1f895c6fe	3270	* @param BurstBuffer : The Buffer address.
mbed_official	340:28d1f895c6fe	3271	* @param BurstLength : DMA Burst length. This parameter can be one value
mbed_official	340:28d1f895c6fe	3272	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	340:28d1f895c6fe	3273	* @retval HAL status
mbed_official	340:28d1f895c6fe	3274	*/
mbed_official	340:28d1f895c6fe	3275	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	340:28d1f895c6fe	3276	uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official	340:28d1f895c6fe	3277	{
mbed_official	340:28d1f895c6fe	3278	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3279	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3280	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	340:28d1f895c6fe	3281	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	340:28d1f895c6fe	3282	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	340:28d1f895c6fe	3283
mbed_official	340:28d1f895c6fe	3284	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	3285	{
mbed_official	340:28d1f895c6fe	3286	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	3287	}
mbed_official	340:28d1f895c6fe	3288	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	3289	{
mbed_official	340:28d1f895c6fe	3290	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	340:28d1f895c6fe	3291	{
mbed_official	340:28d1f895c6fe	3292	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	3293	}
mbed_official	340:28d1f895c6fe	3294	else
mbed_official	340:28d1f895c6fe	3295	{
mbed_official	340:28d1f895c6fe	3296	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3297	}
mbed_official	340:28d1f895c6fe	3298	}
mbed_official	340:28d1f895c6fe	3299	switch(BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3300	{
mbed_official	340:28d1f895c6fe	3301	case TIM_DMA_UPDATE:
mbed_official	340:28d1f895c6fe	3302	{
mbed_official	340:28d1f895c6fe	3303	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3304	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	340:28d1f895c6fe	3305
mbed_official	340:28d1f895c6fe	3306	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3307	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3308
mbed_official	340:28d1f895c6fe	3309	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3310	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3311	}
mbed_official	340:28d1f895c6fe	3312	break;
mbed_official	340:28d1f895c6fe	3313	case TIM_DMA_CC1:
mbed_official	340:28d1f895c6fe	3314	{
mbed_official	340:28d1f895c6fe	3315	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3316	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	3317
mbed_official	340:28d1f895c6fe	3318	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3319	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3320
mbed_official	340:28d1f895c6fe	3321	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3322	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3323	}
mbed_official	340:28d1f895c6fe	3324	break;
mbed_official	340:28d1f895c6fe	3325	case TIM_DMA_CC2:
mbed_official	340:28d1f895c6fe	3326	{
mbed_official	340:28d1f895c6fe	3327	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3328	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	3329
mbed_official	340:28d1f895c6fe	3330	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3331	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3332
mbed_official	340:28d1f895c6fe	3333	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3334	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3335	}
mbed_official	340:28d1f895c6fe	3336	break;
mbed_official	340:28d1f895c6fe	3337	case TIM_DMA_CC3:
mbed_official	340:28d1f895c6fe	3338	{
mbed_official	340:28d1f895c6fe	3339	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3340	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	3341
mbed_official	340:28d1f895c6fe	3342	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3343	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3344
mbed_official	340:28d1f895c6fe	3345	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3346	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3347	}
mbed_official	340:28d1f895c6fe	3348	break;
mbed_official	340:28d1f895c6fe	3349	case TIM_DMA_CC4:
mbed_official	340:28d1f895c6fe	3350	{
mbed_official	340:28d1f895c6fe	3351	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3352	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	340:28d1f895c6fe	3353
mbed_official	340:28d1f895c6fe	3354	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3355	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3356
mbed_official	340:28d1f895c6fe	3357	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3358	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3359	}
mbed_official	340:28d1f895c6fe	3360	break;
mbed_official	340:28d1f895c6fe	3361	case TIM_DMA_COM:
mbed_official	340:28d1f895c6fe	3362	{
mbed_official	340:28d1f895c6fe	3363	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3364	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	340:28d1f895c6fe	3365
mbed_official	340:28d1f895c6fe	3366	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3367	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3368
mbed_official	340:28d1f895c6fe	3369	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3370	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3371	}
mbed_official	340:28d1f895c6fe	3372	break;
mbed_official	340:28d1f895c6fe	3373	case TIM_DMA_TRIGGER:
mbed_official	340:28d1f895c6fe	3374	{
mbed_official	340:28d1f895c6fe	3375	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3376	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	340:28d1f895c6fe	3377
mbed_official	340:28d1f895c6fe	3378	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3379	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3380
mbed_official	340:28d1f895c6fe	3381	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3382	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3383	}
mbed_official	340:28d1f895c6fe	3384	break;
mbed_official	340:28d1f895c6fe	3385	default:
mbed_official	340:28d1f895c6fe	3386	break;
mbed_official	340:28d1f895c6fe	3387	}
mbed_official	340:28d1f895c6fe	3388	/* configure the DMA Burst Mode */
mbed_official	340:28d1f895c6fe	3389	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	340:28d1f895c6fe	3390
mbed_official	340:28d1f895c6fe	3391	/* Enable the TIM DMA Request */
mbed_official	340:28d1f895c6fe	3392	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	340:28d1f895c6fe	3393
mbed_official	340:28d1f895c6fe	3394	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3395
mbed_official	340:28d1f895c6fe	3396	/* Return function status */
mbed_official	340:28d1f895c6fe	3397	return HAL_OK;
mbed_official	340:28d1f895c6fe	3398	}
mbed_official	340:28d1f895c6fe	3399
mbed_official	340:28d1f895c6fe	3400	/**
mbed_official	340:28d1f895c6fe	3401	* @brief Stops the TIM DMA Burst mode
mbed_official	340:28d1f895c6fe	3402	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3403	* @param BurstRequestSrc : TIM DMA Request sources to disable
mbed_official	340:28d1f895c6fe	3404	* @retval HAL status
mbed_official	340:28d1f895c6fe	3405	*/
mbed_official	340:28d1f895c6fe	3406	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3407	{
mbed_official	340:28d1f895c6fe	3408	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3409	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	340:28d1f895c6fe	3410
mbed_official	340:28d1f895c6fe	3411	/* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official	340:28d1f895c6fe	3412	switch(BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3413	{
mbed_official	340:28d1f895c6fe	3414	case TIM_DMA_UPDATE:
mbed_official	340:28d1f895c6fe	3415	{
mbed_official	340:28d1f895c6fe	3416	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official	340:28d1f895c6fe	3417	}
mbed_official	340:28d1f895c6fe	3418	break;
mbed_official	340:28d1f895c6fe	3419	case TIM_DMA_CC1:
mbed_official	340:28d1f895c6fe	3420	{
mbed_official	340:28d1f895c6fe	3421	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official	340:28d1f895c6fe	3422	}
mbed_official	340:28d1f895c6fe	3423	break;
mbed_official	340:28d1f895c6fe	3424	case TIM_DMA_CC2:
mbed_official	340:28d1f895c6fe	3425	{
mbed_official	340:28d1f895c6fe	3426	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official	340:28d1f895c6fe	3427	}
mbed_official	340:28d1f895c6fe	3428	break;
mbed_official	340:28d1f895c6fe	3429	case TIM_DMA_CC3:
mbed_official	340:28d1f895c6fe	3430	{
mbed_official	340:28d1f895c6fe	3431	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official	340:28d1f895c6fe	3432	}
mbed_official	340:28d1f895c6fe	3433	break;
mbed_official	340:28d1f895c6fe	3434	case TIM_DMA_CC4:
mbed_official	340:28d1f895c6fe	3435	{
mbed_official	340:28d1f895c6fe	3436	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official	340:28d1f895c6fe	3437	}
mbed_official	340:28d1f895c6fe	3438	break;
mbed_official	340:28d1f895c6fe	3439	case TIM_DMA_COM:
mbed_official	340:28d1f895c6fe	3440	{
mbed_official	340:28d1f895c6fe	3441	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official	340:28d1f895c6fe	3442	}
mbed_official	340:28d1f895c6fe	3443	break;
mbed_official	340:28d1f895c6fe	3444	case TIM_DMA_TRIGGER:
mbed_official	340:28d1f895c6fe	3445	{
mbed_official	340:28d1f895c6fe	3446	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official	340:28d1f895c6fe	3447	}
mbed_official	340:28d1f895c6fe	3448	break;
mbed_official	340:28d1f895c6fe	3449	default:
mbed_official	340:28d1f895c6fe	3450	break;
mbed_official	340:28d1f895c6fe	3451	}
mbed_official	340:28d1f895c6fe	3452
mbed_official	340:28d1f895c6fe	3453	/* Disable the TIM Update DMA request */
mbed_official	340:28d1f895c6fe	3454	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	340:28d1f895c6fe	3455
mbed_official	340:28d1f895c6fe	3456	/* Return function status */
mbed_official	340:28d1f895c6fe	3457	return HAL_OK;
mbed_official	340:28d1f895c6fe	3458	}
mbed_official	340:28d1f895c6fe	3459
mbed_official	340:28d1f895c6fe	3460	/**
mbed_official	340:28d1f895c6fe	3461	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official	340:28d1f895c6fe	3462	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3463	* @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
mbed_official	340:28d1f895c6fe	3464	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3465	* @arg TIM_DMABase_CR1
mbed_official	340:28d1f895c6fe	3466	* @arg TIM_DMABase_CR2
mbed_official	340:28d1f895c6fe	3467	* @arg TIM_DMABase_SMCR
mbed_official	340:28d1f895c6fe	3468	* @arg TIM_DMABase_DIER
mbed_official	340:28d1f895c6fe	3469	* @arg TIM_DMABase_SR
mbed_official	340:28d1f895c6fe	3470	* @arg TIM_DMABase_EGR
mbed_official	340:28d1f895c6fe	3471	* @arg TIM_DMABase_CCMR1
mbed_official	340:28d1f895c6fe	3472	* @arg TIM_DMABase_CCMR2
mbed_official	340:28d1f895c6fe	3473	* @arg TIM_DMABase_CCER
mbed_official	340:28d1f895c6fe	3474	* @arg TIM_DMABase_CNT
mbed_official	340:28d1f895c6fe	3475	* @arg TIM_DMABase_PSC
mbed_official	340:28d1f895c6fe	3476	* @arg TIM_DMABase_ARR
mbed_official	340:28d1f895c6fe	3477	* @arg TIM_DMABase_RCR
mbed_official	340:28d1f895c6fe	3478	* @arg TIM_DMABase_CCR1
mbed_official	340:28d1f895c6fe	3479	* @arg TIM_DMABase_CCR2
mbed_official	340:28d1f895c6fe	3480	* @arg TIM_DMABase_CCR3
mbed_official	340:28d1f895c6fe	3481	* @arg TIM_DMABase_CCR4
mbed_official	340:28d1f895c6fe	3482	* @arg TIM_DMABase_BDTR
mbed_official	340:28d1f895c6fe	3483	* @arg TIM_DMABase_DCR
mbed_official	340:28d1f895c6fe	3484	* @param BurstRequestSrc : TIM DMA Request sources
mbed_official	340:28d1f895c6fe	3485	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3486	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	340:28d1f895c6fe	3487	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	340:28d1f895c6fe	3488	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	340:28d1f895c6fe	3489	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	340:28d1f895c6fe	3490	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	340:28d1f895c6fe	3491	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	340:28d1f895c6fe	3492	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	340:28d1f895c6fe	3493	* @param BurstBuffer : The Buffer address.
mbed_official	340:28d1f895c6fe	3494	* @param BurstLength : DMA Burst length. This parameter can be one value
mbed_official	340:28d1f895c6fe	3495	* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	340:28d1f895c6fe	3496	* @retval HAL status
mbed_official	340:28d1f895c6fe	3497	*/
mbed_official	340:28d1f895c6fe	3498	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	340:28d1f895c6fe	3499	uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official	340:28d1f895c6fe	3500	{
mbed_official	340:28d1f895c6fe	3501	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3502	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3503	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	340:28d1f895c6fe	3504	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	340:28d1f895c6fe	3505	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	340:28d1f895c6fe	3506
mbed_official	340:28d1f895c6fe	3507	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	340:28d1f895c6fe	3508	{
mbed_official	340:28d1f895c6fe	3509	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	3510	}
mbed_official	340:28d1f895c6fe	3511	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	340:28d1f895c6fe	3512	{
mbed_official	340:28d1f895c6fe	3513	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	340:28d1f895c6fe	3514	{
mbed_official	340:28d1f895c6fe	3515	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	3516	}
mbed_official	340:28d1f895c6fe	3517	else
mbed_official	340:28d1f895c6fe	3518	{
mbed_official	340:28d1f895c6fe	3519	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3520	}
mbed_official	340:28d1f895c6fe	3521	}
mbed_official	340:28d1f895c6fe	3522	switch(BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3523	{
mbed_official	340:28d1f895c6fe	3524	case TIM_DMA_UPDATE:
mbed_official	340:28d1f895c6fe	3525	{
mbed_official	340:28d1f895c6fe	3526	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3527	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	340:28d1f895c6fe	3528
mbed_official	340:28d1f895c6fe	3529	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3530	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3531
mbed_official	340:28d1f895c6fe	3532	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3533	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3534	}
mbed_official	340:28d1f895c6fe	3535	break;
mbed_official	340:28d1f895c6fe	3536	case TIM_DMA_CC1:
mbed_official	340:28d1f895c6fe	3537	{
mbed_official	340:28d1f895c6fe	3538	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3539	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	3540
mbed_official	340:28d1f895c6fe	3541	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3542	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3543
mbed_official	340:28d1f895c6fe	3544	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3545	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3546	}
mbed_official	340:28d1f895c6fe	3547	break;
mbed_official	340:28d1f895c6fe	3548	case TIM_DMA_CC2:
mbed_official	340:28d1f895c6fe	3549	{
mbed_official	340:28d1f895c6fe	3550	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3551	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	3552
mbed_official	340:28d1f895c6fe	3553	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3554	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3555
mbed_official	340:28d1f895c6fe	3556	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3557	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3558	}
mbed_official	340:28d1f895c6fe	3559	break;
mbed_official	340:28d1f895c6fe	3560	case TIM_DMA_CC3:
mbed_official	340:28d1f895c6fe	3561	{
mbed_official	340:28d1f895c6fe	3562	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3563	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	3564
mbed_official	340:28d1f895c6fe	3565	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3566	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3567
mbed_official	340:28d1f895c6fe	3568	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3569	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3570	}
mbed_official	340:28d1f895c6fe	3571	break;
mbed_official	340:28d1f895c6fe	3572	case TIM_DMA_CC4:
mbed_official	340:28d1f895c6fe	3573	{
mbed_official	340:28d1f895c6fe	3574	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3575	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	340:28d1f895c6fe	3576
mbed_official	340:28d1f895c6fe	3577	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3578	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3579
mbed_official	340:28d1f895c6fe	3580	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3581	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3582	}
mbed_official	340:28d1f895c6fe	3583	break;
mbed_official	340:28d1f895c6fe	3584	case TIM_DMA_COM:
mbed_official	340:28d1f895c6fe	3585	{
mbed_official	340:28d1f895c6fe	3586	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3587	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	340:28d1f895c6fe	3588
mbed_official	340:28d1f895c6fe	3589	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3590	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3591
mbed_official	340:28d1f895c6fe	3592	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3593	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3594	}
mbed_official	340:28d1f895c6fe	3595	break;
mbed_official	340:28d1f895c6fe	3596	case TIM_DMA_TRIGGER:
mbed_official	340:28d1f895c6fe	3597	{
mbed_official	340:28d1f895c6fe	3598	/* Set the DMA Period elapsed callback */
mbed_official	340:28d1f895c6fe	3599	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	340:28d1f895c6fe	3600
mbed_official	340:28d1f895c6fe	3601	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	3602	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	340:28d1f895c6fe	3603
mbed_official	340:28d1f895c6fe	3604	/* Enable the DMA channel */
mbed_official	340:28d1f895c6fe	3605	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	340:28d1f895c6fe	3606	}
mbed_official	340:28d1f895c6fe	3607	break;
mbed_official	340:28d1f895c6fe	3608	default:
mbed_official	340:28d1f895c6fe	3609	break;
mbed_official	340:28d1f895c6fe	3610	}
mbed_official	340:28d1f895c6fe	3611
mbed_official	340:28d1f895c6fe	3612	/* configure the DMA Burst Mode */
mbed_official	340:28d1f895c6fe	3613	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	340:28d1f895c6fe	3614
mbed_official	340:28d1f895c6fe	3615	/* Enable the TIM DMA Request */
mbed_official	340:28d1f895c6fe	3616	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	340:28d1f895c6fe	3617
mbed_official	340:28d1f895c6fe	3618	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3619
mbed_official	340:28d1f895c6fe	3620	/* Return function status */
mbed_official	340:28d1f895c6fe	3621	return HAL_OK;
mbed_official	340:28d1f895c6fe	3622	}
mbed_official	340:28d1f895c6fe	3623
mbed_official	340:28d1f895c6fe	3624	/**
mbed_official	340:28d1f895c6fe	3625	* @brief Stop the DMA burst reading
mbed_official	340:28d1f895c6fe	3626	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3627	* @param BurstRequestSrc : TIM DMA Request sources to disable.
mbed_official	340:28d1f895c6fe	3628	* @retval HAL status
mbed_official	340:28d1f895c6fe	3629	*/
mbed_official	340:28d1f895c6fe	3630	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3631	{
mbed_official	340:28d1f895c6fe	3632	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3633	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	340:28d1f895c6fe	3634
mbed_official	340:28d1f895c6fe	3635	/* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official	340:28d1f895c6fe	3636	switch(BurstRequestSrc)
mbed_official	340:28d1f895c6fe	3637	{
mbed_official	340:28d1f895c6fe	3638	case TIM_DMA_UPDATE:
mbed_official	340:28d1f895c6fe	3639	{
mbed_official	340:28d1f895c6fe	3640	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official	340:28d1f895c6fe	3641	}
mbed_official	340:28d1f895c6fe	3642	break;
mbed_official	340:28d1f895c6fe	3643	case TIM_DMA_CC1:
mbed_official	340:28d1f895c6fe	3644	{
mbed_official	340:28d1f895c6fe	3645	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official	340:28d1f895c6fe	3646	}
mbed_official	340:28d1f895c6fe	3647	break;
mbed_official	340:28d1f895c6fe	3648	case TIM_DMA_CC2:
mbed_official	340:28d1f895c6fe	3649	{
mbed_official	340:28d1f895c6fe	3650	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official	340:28d1f895c6fe	3651	}
mbed_official	340:28d1f895c6fe	3652	break;
mbed_official	340:28d1f895c6fe	3653	case TIM_DMA_CC3:
mbed_official	340:28d1f895c6fe	3654	{
mbed_official	340:28d1f895c6fe	3655	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official	340:28d1f895c6fe	3656	}
mbed_official	340:28d1f895c6fe	3657	break;
mbed_official	340:28d1f895c6fe	3658	case TIM_DMA_CC4:
mbed_official	340:28d1f895c6fe	3659	{
mbed_official	340:28d1f895c6fe	3660	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official	340:28d1f895c6fe	3661	}
mbed_official	340:28d1f895c6fe	3662	break;
mbed_official	340:28d1f895c6fe	3663	case TIM_DMA_COM:
mbed_official	340:28d1f895c6fe	3664	{
mbed_official	340:28d1f895c6fe	3665	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official	340:28d1f895c6fe	3666	}
mbed_official	340:28d1f895c6fe	3667	break;
mbed_official	340:28d1f895c6fe	3668	case TIM_DMA_TRIGGER:
mbed_official	340:28d1f895c6fe	3669	{
mbed_official	340:28d1f895c6fe	3670	HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official	340:28d1f895c6fe	3671	}
mbed_official	340:28d1f895c6fe	3672	break;
mbed_official	340:28d1f895c6fe	3673	default:
mbed_official	340:28d1f895c6fe	3674	break;
mbed_official	340:28d1f895c6fe	3675	}
mbed_official	340:28d1f895c6fe	3676
mbed_official	340:28d1f895c6fe	3677	/* Disable the TIM Update DMA request */
mbed_official	340:28d1f895c6fe	3678	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	340:28d1f895c6fe	3679
mbed_official	340:28d1f895c6fe	3680	/* Return function status */
mbed_official	340:28d1f895c6fe	3681	return HAL_OK;
mbed_official	340:28d1f895c6fe	3682	}
mbed_official	340:28d1f895c6fe	3683
mbed_official	340:28d1f895c6fe	3684	/**
mbed_official	340:28d1f895c6fe	3685	* @brief Generate a software event
mbed_official	340:28d1f895c6fe	3686	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3687	* @param EventSource : specifies the event source.
mbed_official	340:28d1f895c6fe	3688	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3689	* @arg TIM_EventSource_Update: Timer update Event source
mbed_official	340:28d1f895c6fe	3690	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official	340:28d1f895c6fe	3691	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official	340:28d1f895c6fe	3692	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official	340:28d1f895c6fe	3693	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official	340:28d1f895c6fe	3694	* @arg TIM_EventSource_COM: Timer COM event source
mbed_official	340:28d1f895c6fe	3695	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official	340:28d1f895c6fe	3696	* @arg TIM_EventSource_Break: Timer Break event source
mbed_official	340:28d1f895c6fe	3697	* @note TIM6 and TIM7 can only generate an update event.
mbed_official	340:28d1f895c6fe	3698	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1, TIM15, TIM16 and TIM17.
mbed_official	340:28d1f895c6fe	3699	* @retval HAL status
mbed_official	340:28d1f895c6fe	3700	*/
mbed_official	340:28d1f895c6fe	3701
mbed_official	340:28d1f895c6fe	3702	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official	340:28d1f895c6fe	3703	{
mbed_official	340:28d1f895c6fe	3704	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3705	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3706	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official	340:28d1f895c6fe	3707
mbed_official	340:28d1f895c6fe	3708	/* Process Locked */
mbed_official	340:28d1f895c6fe	3709	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	3710
mbed_official	340:28d1f895c6fe	3711	/* Change the TIM state */
mbed_official	340:28d1f895c6fe	3712	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3713
mbed_official	340:28d1f895c6fe	3714	/* Set the event sources */
mbed_official	340:28d1f895c6fe	3715	htim->Instance->EGR = EventSource;
mbed_official	340:28d1f895c6fe	3716
mbed_official	340:28d1f895c6fe	3717	/* Change the TIM state */
mbed_official	340:28d1f895c6fe	3718	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3719
mbed_official	340:28d1f895c6fe	3720	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	3721
mbed_official	340:28d1f895c6fe	3722	/* Return function status */
mbed_official	340:28d1f895c6fe	3723	return HAL_OK;
mbed_official	340:28d1f895c6fe	3724	}
mbed_official	340:28d1f895c6fe	3725
mbed_official	340:28d1f895c6fe	3726	/**
mbed_official	340:28d1f895c6fe	3727	* @brief Configures the OCRef clear feature
mbed_official	340:28d1f895c6fe	3728	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3729	* @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official	340:28d1f895c6fe	3730	* contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official	340:28d1f895c6fe	3731	* @param Channel : specifies the TIM Channel
mbed_official	340:28d1f895c6fe	3732	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	3733	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	340:28d1f895c6fe	3734	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	340:28d1f895c6fe	3735	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	340:28d1f895c6fe	3736	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	340:28d1f895c6fe	3737	* @retval HAL status
mbed_official	340:28d1f895c6fe	3738	*/
mbed_official	340:28d1f895c6fe	3739	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
mbed_official	340:28d1f895c6fe	3740	{
mbed_official	340:28d1f895c6fe	3741	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	3742
mbed_official	340:28d1f895c6fe	3743	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3744	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3745	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official	340:28d1f895c6fe	3746	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official	340:28d1f895c6fe	3747	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official	340:28d1f895c6fe	3748	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official	340:28d1f895c6fe	3749
mbed_official	340:28d1f895c6fe	3750	/* Process Locked */
mbed_official	340:28d1f895c6fe	3751	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	3752
mbed_official	340:28d1f895c6fe	3753	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3754
mbed_official	340:28d1f895c6fe	3755	switch (sClearInputConfig->ClearInputSource)
mbed_official	340:28d1f895c6fe	3756	{
mbed_official	340:28d1f895c6fe	3757	case TIM_CLEARINPUTSOURCE_NONE:
mbed_official	340:28d1f895c6fe	3758	{
mbed_official	340:28d1f895c6fe	3759	/* Clear the OCREF clear selection bit */
mbed_official	340:28d1f895c6fe	3760	tmpsmcr &= ~TIM_SMCR_OCCS;
mbed_official	340:28d1f895c6fe	3761
mbed_official	340:28d1f895c6fe	3762	/* Clear the ETR Bits */
mbed_official	340:28d1f895c6fe	3763	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	340:28d1f895c6fe	3764
mbed_official	340:28d1f895c6fe	3765	/* Set TIMx_SMCR */
mbed_official	340:28d1f895c6fe	3766	htim->Instance->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	3767	}
mbed_official	340:28d1f895c6fe	3768	break;
mbed_official	340:28d1f895c6fe	3769
mbed_official	340:28d1f895c6fe	3770	case TIM_CLEARINPUTSOURCE_ETR:
mbed_official	340:28d1f895c6fe	3771	{
mbed_official	340:28d1f895c6fe	3772	TIM_ETR_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	3773	sClearInputConfig->ClearInputPrescaler,
mbed_official	340:28d1f895c6fe	3774	sClearInputConfig->ClearInputPolarity,
mbed_official	340:28d1f895c6fe	3775	sClearInputConfig->ClearInputFilter);
mbed_official	340:28d1f895c6fe	3776
mbed_official	340:28d1f895c6fe	3777	/* Set the OCREF clear selection bit */
mbed_official	340:28d1f895c6fe	3778	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
mbed_official	340:28d1f895c6fe	3779	}
mbed_official	340:28d1f895c6fe	3780	break;
mbed_official	340:28d1f895c6fe	3781	default:
mbed_official	340:28d1f895c6fe	3782	break;
mbed_official	340:28d1f895c6fe	3783	}
mbed_official	340:28d1f895c6fe	3784
mbed_official	340:28d1f895c6fe	3785	switch (Channel)
mbed_official	340:28d1f895c6fe	3786	{
mbed_official	340:28d1f895c6fe	3787	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	3788	{
mbed_official	340:28d1f895c6fe	3789	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	340:28d1f895c6fe	3790	{
mbed_official	340:28d1f895c6fe	3791	/* Enable the Ocref clear feature for Channel 1 */
mbed_official	340:28d1f895c6fe	3792	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
mbed_official	340:28d1f895c6fe	3793	}
mbed_official	340:28d1f895c6fe	3794	else
mbed_official	340:28d1f895c6fe	3795	{
mbed_official	340:28d1f895c6fe	3796	/* Disable the Ocref clear feature for Channel 1 */
mbed_official	340:28d1f895c6fe	3797	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official	340:28d1f895c6fe	3798	}
mbed_official	340:28d1f895c6fe	3799	}
mbed_official	340:28d1f895c6fe	3800	break;
mbed_official	340:28d1f895c6fe	3801	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	3802	{
mbed_official	340:28d1f895c6fe	3803	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3804	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	340:28d1f895c6fe	3805	{
mbed_official	340:28d1f895c6fe	3806	/* Enable the Ocref clear feature for Channel 2 */
mbed_official	340:28d1f895c6fe	3807	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
mbed_official	340:28d1f895c6fe	3808	}
mbed_official	340:28d1f895c6fe	3809	else
mbed_official	340:28d1f895c6fe	3810	{
mbed_official	340:28d1f895c6fe	3811	/* Disable the Ocref clear feature for Channel 2 */
mbed_official	340:28d1f895c6fe	3812	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official	340:28d1f895c6fe	3813	}
mbed_official	340:28d1f895c6fe	3814	}
mbed_official	340:28d1f895c6fe	3815	break;
mbed_official	340:28d1f895c6fe	3816	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	3817	{
mbed_official	340:28d1f895c6fe	3818	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3819	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	340:28d1f895c6fe	3820	{
mbed_official	340:28d1f895c6fe	3821	/* Enable the Ocref clear feature for Channel 3 */
mbed_official	340:28d1f895c6fe	3822	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
mbed_official	340:28d1f895c6fe	3823	}
mbed_official	340:28d1f895c6fe	3824	else
mbed_official	340:28d1f895c6fe	3825	{
mbed_official	340:28d1f895c6fe	3826	/* Disable the Ocref clear feature for Channel 3 */
mbed_official	340:28d1f895c6fe	3827	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official	340:28d1f895c6fe	3828	}
mbed_official	340:28d1f895c6fe	3829	}
mbed_official	340:28d1f895c6fe	3830	break;
mbed_official	340:28d1f895c6fe	3831	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	3832	{
mbed_official	340:28d1f895c6fe	3833	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3834	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	340:28d1f895c6fe	3835	{
mbed_official	340:28d1f895c6fe	3836	/* Enable the Ocref clear feature for Channel 4 */
mbed_official	340:28d1f895c6fe	3837	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
mbed_official	340:28d1f895c6fe	3838	}
mbed_official	340:28d1f895c6fe	3839	else
mbed_official	340:28d1f895c6fe	3840	{
mbed_official	340:28d1f895c6fe	3841	/* Disable the Ocref clear feature for Channel 4 */
mbed_official	340:28d1f895c6fe	3842	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official	340:28d1f895c6fe	3843	}
mbed_official	340:28d1f895c6fe	3844	}
mbed_official	340:28d1f895c6fe	3845	break;
mbed_official	340:28d1f895c6fe	3846	default:
mbed_official	340:28d1f895c6fe	3847	break;
mbed_official	340:28d1f895c6fe	3848	}
mbed_official	340:28d1f895c6fe	3849
mbed_official	340:28d1f895c6fe	3850	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	3851
mbed_official	340:28d1f895c6fe	3852	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	3853
mbed_official	340:28d1f895c6fe	3854	return HAL_OK;
mbed_official	340:28d1f895c6fe	3855	}
mbed_official	340:28d1f895c6fe	3856
mbed_official	340:28d1f895c6fe	3857	/**
mbed_official	340:28d1f895c6fe	3858	* @brief Configures the clock source to be used
mbed_official	340:28d1f895c6fe	3859	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	3860	* @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
mbed_official	340:28d1f895c6fe	3861	* contains the clock source information for the TIM peripheral.
mbed_official	340:28d1f895c6fe	3862	* @retval HAL status
mbed_official	340:28d1f895c6fe	3863	*/
mbed_official	340:28d1f895c6fe	3864	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
mbed_official	340:28d1f895c6fe	3865	{
mbed_official	340:28d1f895c6fe	3866	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	3867
mbed_official	340:28d1f895c6fe	3868	/* Process Locked */
mbed_official	340:28d1f895c6fe	3869	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	3870
mbed_official	340:28d1f895c6fe	3871	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	3872
mbed_official	340:28d1f895c6fe	3873	/* Check the parameters */
mbed_official	340:28d1f895c6fe	3874	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official	340:28d1f895c6fe	3875	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	340:28d1f895c6fe	3876	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	340:28d1f895c6fe	3877	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	340:28d1f895c6fe	3878
mbed_official	340:28d1f895c6fe	3879	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official	340:28d1f895c6fe	3880	tmpsmcr = htim->Instance->SMCR;
mbed_official	340:28d1f895c6fe	3881	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	340:28d1f895c6fe	3882	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	340:28d1f895c6fe	3883	htim->Instance->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	3884
mbed_official	340:28d1f895c6fe	3885	switch (sClockSourceConfig->ClockSource)
mbed_official	340:28d1f895c6fe	3886	{
mbed_official	340:28d1f895c6fe	3887	case TIM_CLOCKSOURCE_INTERNAL:
mbed_official	340:28d1f895c6fe	3888	{
mbed_official	340:28d1f895c6fe	3889	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3890	/* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official	340:28d1f895c6fe	3891	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	340:28d1f895c6fe	3892	}
mbed_official	340:28d1f895c6fe	3893	break;
mbed_official	340:28d1f895c6fe	3894
mbed_official	340:28d1f895c6fe	3895	case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official	340:28d1f895c6fe	3896	{
mbed_official	340:28d1f895c6fe	3897	/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
mbed_official	340:28d1f895c6fe	3898	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3899
mbed_official	340:28d1f895c6fe	3900	/* Configure the ETR Clock source */
mbed_official	340:28d1f895c6fe	3901	TIM_ETR_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	3902	sClockSourceConfig->ClockPrescaler,
mbed_official	340:28d1f895c6fe	3903	sClockSourceConfig->ClockPolarity,
mbed_official	340:28d1f895c6fe	3904	sClockSourceConfig->ClockFilter);
mbed_official	340:28d1f895c6fe	3905	/* Get the TIMx SMCR register value */
mbed_official	340:28d1f895c6fe	3906	tmpsmcr = htim->Instance->SMCR;
mbed_official	340:28d1f895c6fe	3907	/* Reset the SMS and TS Bits */
mbed_official	340:28d1f895c6fe	3908	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	340:28d1f895c6fe	3909	/* Select the External clock mode1 and the ETRF trigger */
mbed_official	340:28d1f895c6fe	3910	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
mbed_official	340:28d1f895c6fe	3911	/* Write to TIMx SMCR */
mbed_official	340:28d1f895c6fe	3912	htim->Instance->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	3913	}
mbed_official	340:28d1f895c6fe	3914	break;
mbed_official	340:28d1f895c6fe	3915
mbed_official	340:28d1f895c6fe	3916	case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official	340:28d1f895c6fe	3917	{
mbed_official	340:28d1f895c6fe	3918	/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
mbed_official	340:28d1f895c6fe	3919	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3920
mbed_official	340:28d1f895c6fe	3921	/* Configure the ETR Clock source */
mbed_official	340:28d1f895c6fe	3922	TIM_ETR_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	3923	sClockSourceConfig->ClockPrescaler,
mbed_official	340:28d1f895c6fe	3924	sClockSourceConfig->ClockPolarity,
mbed_official	340:28d1f895c6fe	3925	sClockSourceConfig->ClockFilter);
mbed_official	340:28d1f895c6fe	3926	/* Enable the External clock mode2 */
mbed_official	340:28d1f895c6fe	3927	htim->Instance->SMCR \|= TIM_SMCR_ECE;
mbed_official	340:28d1f895c6fe	3928	}
mbed_official	340:28d1f895c6fe	3929	break;
mbed_official	340:28d1f895c6fe	3930
mbed_official	340:28d1f895c6fe	3931	case TIM_CLOCKSOURCE_TI1:
mbed_official	340:28d1f895c6fe	3932	{
mbed_official	340:28d1f895c6fe	3933	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3934	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3935
mbed_official	340:28d1f895c6fe	3936	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	340:28d1f895c6fe	3937	sClockSourceConfig->ClockPolarity,
mbed_official	340:28d1f895c6fe	3938	sClockSourceConfig->ClockFilter);
mbed_official	340:28d1f895c6fe	3939	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official	340:28d1f895c6fe	3940	}
mbed_official	340:28d1f895c6fe	3941	break;
mbed_official	340:28d1f895c6fe	3942	case TIM_CLOCKSOURCE_TI2:
mbed_official	340:28d1f895c6fe	3943	{
mbed_official	340:28d1f895c6fe	3944	/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
mbed_official	340:28d1f895c6fe	3945	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3946
mbed_official	340:28d1f895c6fe	3947	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	340:28d1f895c6fe	3948	sClockSourceConfig->ClockPolarity,
mbed_official	340:28d1f895c6fe	3949	sClockSourceConfig->ClockFilter);
mbed_official	340:28d1f895c6fe	3950	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official	340:28d1f895c6fe	3951	}
mbed_official	340:28d1f895c6fe	3952	break;
mbed_official	340:28d1f895c6fe	3953	case TIM_CLOCKSOURCE_TI1ED:
mbed_official	340:28d1f895c6fe	3954	{
mbed_official	340:28d1f895c6fe	3955	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3956	assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3957
mbed_official	340:28d1f895c6fe	3958	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	340:28d1f895c6fe	3959	sClockSourceConfig->ClockPolarity,
mbed_official	340:28d1f895c6fe	3960	sClockSourceConfig->ClockFilter);
mbed_official	340:28d1f895c6fe	3961	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official	340:28d1f895c6fe	3962	}
mbed_official	340:28d1f895c6fe	3963	break;
mbed_official	340:28d1f895c6fe	3964	case TIM_CLOCKSOURCE_ITR0:
mbed_official	340:28d1f895c6fe	3965	{
mbed_official	340:28d1f895c6fe	3966	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3967	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3968
mbed_official	340:28d1f895c6fe	3969	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official	340:28d1f895c6fe	3970	}
mbed_official	340:28d1f895c6fe	3971	break;
mbed_official	340:28d1f895c6fe	3972	case TIM_CLOCKSOURCE_ITR1:
mbed_official	340:28d1f895c6fe	3973	{
mbed_official	340:28d1f895c6fe	3974	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3975	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3976
mbed_official	340:28d1f895c6fe	3977	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official	340:28d1f895c6fe	3978	}
mbed_official	340:28d1f895c6fe	3979	break;
mbed_official	340:28d1f895c6fe	3980	case TIM_CLOCKSOURCE_ITR2:
mbed_official	340:28d1f895c6fe	3981	{
mbed_official	340:28d1f895c6fe	3982	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3983	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3984
mbed_official	340:28d1f895c6fe	3985	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official	340:28d1f895c6fe	3986	}
mbed_official	340:28d1f895c6fe	3987	break;
mbed_official	340:28d1f895c6fe	3988	case TIM_CLOCKSOURCE_ITR3:
mbed_official	340:28d1f895c6fe	3989	{
mbed_official	340:28d1f895c6fe	3990	/* Check whether or not the timer instance supports external clock mode 1 */
mbed_official	340:28d1f895c6fe	3991	assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	3992
mbed_official	340:28d1f895c6fe	3993	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official	340:28d1f895c6fe	3994	}
mbed_official	340:28d1f895c6fe	3995	break;
mbed_official	340:28d1f895c6fe	3996
mbed_official	340:28d1f895c6fe	3997	default:
mbed_official	340:28d1f895c6fe	3998	break;
mbed_official	340:28d1f895c6fe	3999	}
mbed_official	340:28d1f895c6fe	4000	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4001
mbed_official	340:28d1f895c6fe	4002	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	4003
mbed_official	340:28d1f895c6fe	4004	return HAL_OK;
mbed_official	340:28d1f895c6fe	4005	}
mbed_official	340:28d1f895c6fe	4006
mbed_official	340:28d1f895c6fe	4007	/**
mbed_official	340:28d1f895c6fe	4008	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official	340:28d1f895c6fe	4009	* or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official	340:28d1f895c6fe	4010	* @param htim : TIM handle.
mbed_official	340:28d1f895c6fe	4011	* @param TI1_Selection : Indicate whether or not channel 1 is connected to the
mbed_official	340:28d1f895c6fe	4012	* output of a XOR gate.
mbed_official	340:28d1f895c6fe	4013	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	4014	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official	340:28d1f895c6fe	4015	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official	340:28d1f895c6fe	4016	* pins are connected to the TI1 input (XOR combination)
mbed_official	340:28d1f895c6fe	4017	* @retval HAL status
mbed_official	340:28d1f895c6fe	4018	*/
mbed_official	340:28d1f895c6fe	4019	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official	340:28d1f895c6fe	4020	{
mbed_official	340:28d1f895c6fe	4021	uint32_t tmpcr2 = 0;
mbed_official	340:28d1f895c6fe	4022
mbed_official	340:28d1f895c6fe	4023	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4024	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4025	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official	340:28d1f895c6fe	4026
mbed_official	340:28d1f895c6fe	4027	/* Get the TIMx CR2 register value */
mbed_official	340:28d1f895c6fe	4028	tmpcr2 = htim->Instance->CR2;
mbed_official	340:28d1f895c6fe	4029
mbed_official	340:28d1f895c6fe	4030	/* Reset the TI1 selection */
mbed_official	340:28d1f895c6fe	4031	tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official	340:28d1f895c6fe	4032
mbed_official	340:28d1f895c6fe	4033	/* Set the the TI1 selection */
mbed_official	340:28d1f895c6fe	4034	tmpcr2 \|= TI1_Selection;
mbed_official	340:28d1f895c6fe	4035
mbed_official	340:28d1f895c6fe	4036	/* Write to TIMxCR2 */
mbed_official	340:28d1f895c6fe	4037	htim->Instance->CR2 = tmpcr2;
mbed_official	340:28d1f895c6fe	4038
mbed_official	340:28d1f895c6fe	4039	return HAL_OK;
mbed_official	340:28d1f895c6fe	4040	}
mbed_official	340:28d1f895c6fe	4041
mbed_official	340:28d1f895c6fe	4042	/**
mbed_official	340:28d1f895c6fe	4043	* @brief Configures the TIM in Slave mode
mbed_official	340:28d1f895c6fe	4044	* @param htim : TIM handle.
mbed_official	340:28d1f895c6fe	4045	* @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official	340:28d1f895c6fe	4046	* contains the selected trigger (internal trigger input, filtered
mbed_official	340:28d1f895c6fe	4047	* timer input or external trigger input) and the ) and the Slave
mbed_official	340:28d1f895c6fe	4048	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official	340:28d1f895c6fe	4049	* @retval HAL status
mbed_official	340:28d1f895c6fe	4050	*/
mbed_official	340:28d1f895c6fe	4051	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
mbed_official	340:28d1f895c6fe	4052	{
mbed_official	340:28d1f895c6fe	4053	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4054	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4055	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official	340:28d1f895c6fe	4056	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official	340:28d1f895c6fe	4057
mbed_official	340:28d1f895c6fe	4058	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	4059
mbed_official	340:28d1f895c6fe	4060	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	4061
mbed_official	340:28d1f895c6fe	4062	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official	340:28d1f895c6fe	4063
mbed_official	340:28d1f895c6fe	4064	/* Disable Trigger Interrupt */
mbed_official	340:28d1f895c6fe	4065	__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official	340:28d1f895c6fe	4066
mbed_official	340:28d1f895c6fe	4067	/* Disable Trigger DMA request */
mbed_official	340:28d1f895c6fe	4068	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official	340:28d1f895c6fe	4069
mbed_official	340:28d1f895c6fe	4070	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4071
mbed_official	340:28d1f895c6fe	4072	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	4073
mbed_official	340:28d1f895c6fe	4074	return HAL_OK;
mbed_official	340:28d1f895c6fe	4075	}
mbed_official	340:28d1f895c6fe	4076
mbed_official	340:28d1f895c6fe	4077	/**
mbed_official	340:28d1f895c6fe	4078	* @brief Configures the TIM in Slave mode in interrupt mode
mbed_official	340:28d1f895c6fe	4079	* @param htim: TIM handle.
mbed_official	340:28d1f895c6fe	4080	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official	340:28d1f895c6fe	4081	* contains the selected trigger (internal trigger input, filtered
mbed_official	340:28d1f895c6fe	4082	* timer input or external trigger input) and the ) and the Slave
mbed_official	340:28d1f895c6fe	4083	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official	340:28d1f895c6fe	4084	* @retval HAL status
mbed_official	340:28d1f895c6fe	4085	*/
mbed_official	340:28d1f895c6fe	4086	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
mbed_official	340:28d1f895c6fe	4087	TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official	340:28d1f895c6fe	4088	{
mbed_official	340:28d1f895c6fe	4089	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4090	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4091	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official	340:28d1f895c6fe	4092	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official	340:28d1f895c6fe	4093
mbed_official	340:28d1f895c6fe	4094	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	4095
mbed_official	340:28d1f895c6fe	4096	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	340:28d1f895c6fe	4097
mbed_official	340:28d1f895c6fe	4098	TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official	340:28d1f895c6fe	4099
mbed_official	340:28d1f895c6fe	4100	/* Enable Trigger Interrupt */
mbed_official	340:28d1f895c6fe	4101	__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official	340:28d1f895c6fe	4102
mbed_official	340:28d1f895c6fe	4103	/* Disable Trigger DMA request */
mbed_official	340:28d1f895c6fe	4104	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official	340:28d1f895c6fe	4105
mbed_official	340:28d1f895c6fe	4106	htim->State = HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4107
mbed_official	340:28d1f895c6fe	4108	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	4109
mbed_official	340:28d1f895c6fe	4110	return HAL_OK;
mbed_official	340:28d1f895c6fe	4111	}
mbed_official	340:28d1f895c6fe	4112
mbed_official	340:28d1f895c6fe	4113	/**
mbed_official	340:28d1f895c6fe	4114	* @brief Read the captured value from Capture Compare unit
mbed_official	340:28d1f895c6fe	4115	* @param htim : TIM handle.
mbed_official	340:28d1f895c6fe	4116	* @param Channel : TIM Channels to be enabled
mbed_official	340:28d1f895c6fe	4117	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	4118	* @arg TIM_CHANNEL_1 : TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	4119	* @arg TIM_CHANNEL_2 : TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	4120	* @arg TIM_CHANNEL_3 : TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	4121	* @arg TIM_CHANNEL_4 : TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	4122	* @retval Captured value
mbed_official	340:28d1f895c6fe	4123	*/
mbed_official	340:28d1f895c6fe	4124	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	340:28d1f895c6fe	4125	{
mbed_official	340:28d1f895c6fe	4126	uint32_t tmpreg = 0;
mbed_official	340:28d1f895c6fe	4127
mbed_official	340:28d1f895c6fe	4128	__HAL_LOCK(htim);
mbed_official	340:28d1f895c6fe	4129
mbed_official	340:28d1f895c6fe	4130	switch (Channel)
mbed_official	340:28d1f895c6fe	4131	{
mbed_official	340:28d1f895c6fe	4132	case TIM_CHANNEL_1:
mbed_official	340:28d1f895c6fe	4133	{
mbed_official	340:28d1f895c6fe	4134	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4135	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4136
mbed_official	340:28d1f895c6fe	4137	/* Return the capture 1 value */
mbed_official	340:28d1f895c6fe	4138	tmpreg = htim->Instance->CCR1;
mbed_official	340:28d1f895c6fe	4139
mbed_official	340:28d1f895c6fe	4140	break;
mbed_official	340:28d1f895c6fe	4141	}
mbed_official	340:28d1f895c6fe	4142	case TIM_CHANNEL_2:
mbed_official	340:28d1f895c6fe	4143	{
mbed_official	340:28d1f895c6fe	4144	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4145	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4146
mbed_official	340:28d1f895c6fe	4147	/* Return the capture 2 value */
mbed_official	340:28d1f895c6fe	4148	tmpreg = htim->Instance->CCR2;
mbed_official	340:28d1f895c6fe	4149
mbed_official	340:28d1f895c6fe	4150	break;
mbed_official	340:28d1f895c6fe	4151	}
mbed_official	340:28d1f895c6fe	4152
mbed_official	340:28d1f895c6fe	4153	case TIM_CHANNEL_3:
mbed_official	340:28d1f895c6fe	4154	{
mbed_official	340:28d1f895c6fe	4155	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4156	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4157
mbed_official	340:28d1f895c6fe	4158	/* Return the capture 3 value */
mbed_official	340:28d1f895c6fe	4159	tmpreg = htim->Instance->CCR3;
mbed_official	340:28d1f895c6fe	4160
mbed_official	340:28d1f895c6fe	4161	break;
mbed_official	340:28d1f895c6fe	4162	}
mbed_official	340:28d1f895c6fe	4163
mbed_official	340:28d1f895c6fe	4164	case TIM_CHANNEL_4:
mbed_official	340:28d1f895c6fe	4165	{
mbed_official	340:28d1f895c6fe	4166	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4167	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4168
mbed_official	340:28d1f895c6fe	4169	/* Return the capture 4 value */
mbed_official	340:28d1f895c6fe	4170	tmpreg = htim->Instance->CCR4;
mbed_official	340:28d1f895c6fe	4171
mbed_official	340:28d1f895c6fe	4172	break;
mbed_official	340:28d1f895c6fe	4173	}
mbed_official	340:28d1f895c6fe	4174
mbed_official	340:28d1f895c6fe	4175	default:
mbed_official	340:28d1f895c6fe	4176	break;
mbed_official	340:28d1f895c6fe	4177	}
mbed_official	340:28d1f895c6fe	4178
mbed_official	340:28d1f895c6fe	4179	__HAL_UNLOCK(htim);
mbed_official	340:28d1f895c6fe	4180	return tmpreg;
mbed_official	340:28d1f895c6fe	4181	}
mbed_official	340:28d1f895c6fe	4182
mbed_official	340:28d1f895c6fe	4183	/**
mbed_official	340:28d1f895c6fe	4184	* @}
mbed_official	340:28d1f895c6fe	4185	*/
mbed_official	340:28d1f895c6fe	4186
mbed_official	340:28d1f895c6fe	4187	/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
mbed_official	340:28d1f895c6fe	4188	* @brief TIM Callbacks functions
mbed_official	340:28d1f895c6fe	4189	*
mbed_official	340:28d1f895c6fe	4190	@verbatim
mbed_official	340:28d1f895c6fe	4191	==============================================================================
mbed_official	340:28d1f895c6fe	4192	##### TIM Callbacks functions #####
mbed_official	340:28d1f895c6fe	4193	==============================================================================
mbed_official	340:28d1f895c6fe	4194	[..]
mbed_official	340:28d1f895c6fe	4195	This section provides TIM callback functions:
mbed_official	340:28d1f895c6fe	4196	(+) Timer Period elapsed callback
mbed_official	340:28d1f895c6fe	4197	(+) Timer Output Compare callback
mbed_official	340:28d1f895c6fe	4198	(+) Timer Input capture callback
mbed_official	340:28d1f895c6fe	4199	(+) Timer Trigger callback
mbed_official	340:28d1f895c6fe	4200	(+) Timer Error callback
mbed_official	340:28d1f895c6fe	4201
mbed_official	340:28d1f895c6fe	4202	@endverbatim
mbed_official	340:28d1f895c6fe	4203	* @{
mbed_official	340:28d1f895c6fe	4204	*/
mbed_official	340:28d1f895c6fe	4205
mbed_official	340:28d1f895c6fe	4206	/**
mbed_official	340:28d1f895c6fe	4207	* @brief Period elapsed callback in non blocking mode
mbed_official	340:28d1f895c6fe	4208	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	4209	* @retval None
mbed_official	340:28d1f895c6fe	4210	*/
mbed_official	340:28d1f895c6fe	4211	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4212	{
mbed_official	340:28d1f895c6fe	4213	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4214	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4215	*/
mbed_official	340:28d1f895c6fe	4216
mbed_official	340:28d1f895c6fe	4217	}
mbed_official	340:28d1f895c6fe	4218	/**
mbed_official	340:28d1f895c6fe	4219	* @brief Output Compare callback in non blocking mode
mbed_official	340:28d1f895c6fe	4220	* @param htim : TIM OC handle
mbed_official	340:28d1f895c6fe	4221	* @retval None
mbed_official	340:28d1f895c6fe	4222	*/
mbed_official	340:28d1f895c6fe	4223	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4224	{
mbed_official	340:28d1f895c6fe	4225	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4226	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4227	*/
mbed_official	340:28d1f895c6fe	4228	}
mbed_official	340:28d1f895c6fe	4229	/**
mbed_official	340:28d1f895c6fe	4230	* @brief Input Capture callback in non blocking mode
mbed_official	340:28d1f895c6fe	4231	* @param htim : TIM IC handle
mbed_official	340:28d1f895c6fe	4232	* @retval None
mbed_official	340:28d1f895c6fe	4233	*/
mbed_official	340:28d1f895c6fe	4234	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4235	{
mbed_official	340:28d1f895c6fe	4236	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4237	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4238	*/
mbed_official	340:28d1f895c6fe	4239	}
mbed_official	340:28d1f895c6fe	4240
mbed_official	340:28d1f895c6fe	4241	/**
mbed_official	340:28d1f895c6fe	4242	* @brief PWM Pulse finished callback in non blocking mode
mbed_official	340:28d1f895c6fe	4243	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	4244	* @retval None
mbed_official	340:28d1f895c6fe	4245	*/
mbed_official	340:28d1f895c6fe	4246	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4247	{
mbed_official	340:28d1f895c6fe	4248	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4249	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4250	*/
mbed_official	340:28d1f895c6fe	4251	}
mbed_official	340:28d1f895c6fe	4252
mbed_official	340:28d1f895c6fe	4253	/**
mbed_official	340:28d1f895c6fe	4254	* @brief Hall Trigger detection callback in non blocking mode
mbed_official	340:28d1f895c6fe	4255	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	4256	* @retval None
mbed_official	340:28d1f895c6fe	4257	*/
mbed_official	340:28d1f895c6fe	4258	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4259	{
mbed_official	340:28d1f895c6fe	4260	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4261	the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4262	*/
mbed_official	340:28d1f895c6fe	4263	}
mbed_official	340:28d1f895c6fe	4264
mbed_official	340:28d1f895c6fe	4265	/**
mbed_official	340:28d1f895c6fe	4266	* @brief Timer error callback in non blocking mode
mbed_official	340:28d1f895c6fe	4267	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	4268	* @retval None
mbed_official	340:28d1f895c6fe	4269	*/
mbed_official	340:28d1f895c6fe	4270	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4271	{
mbed_official	340:28d1f895c6fe	4272	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	4273	the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official	340:28d1f895c6fe	4274	*/
mbed_official	340:28d1f895c6fe	4275	}
mbed_official	340:28d1f895c6fe	4276
mbed_official	340:28d1f895c6fe	4277	/**
mbed_official	340:28d1f895c6fe	4278	* @}
mbed_official	340:28d1f895c6fe	4279	*/
mbed_official	340:28d1f895c6fe	4280
mbed_official	340:28d1f895c6fe	4281	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
mbed_official	340:28d1f895c6fe	4282	* @brief Peripheral State functions
mbed_official	340:28d1f895c6fe	4283	*
mbed_official	340:28d1f895c6fe	4284	@verbatim
mbed_official	340:28d1f895c6fe	4285	==============================================================================
mbed_official	340:28d1f895c6fe	4286	##### Peripheral State functions #####
mbed_official	340:28d1f895c6fe	4287	==============================================================================
mbed_official	340:28d1f895c6fe	4288	[..]
mbed_official	340:28d1f895c6fe	4289	This subsection permit to get in run-time the status of the peripheral
mbed_official	340:28d1f895c6fe	4290	and the data flow.
mbed_official	340:28d1f895c6fe	4291
mbed_official	340:28d1f895c6fe	4292	@endverbatim
mbed_official	340:28d1f895c6fe	4293	* @{
mbed_official	340:28d1f895c6fe	4294	*/
mbed_official	340:28d1f895c6fe	4295
mbed_official	340:28d1f895c6fe	4296	/**
mbed_official	340:28d1f895c6fe	4297	* @brief Return the TIM Base state
mbed_official	340:28d1f895c6fe	4298	* @param htim : TIM Base handle
mbed_official	340:28d1f895c6fe	4299	* @retval HAL state
mbed_official	340:28d1f895c6fe	4300	*/
mbed_official	340:28d1f895c6fe	4301	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4302	{
mbed_official	340:28d1f895c6fe	4303	return htim->State;
mbed_official	340:28d1f895c6fe	4304	}
mbed_official	340:28d1f895c6fe	4305
mbed_official	340:28d1f895c6fe	4306	/**
mbed_official	340:28d1f895c6fe	4307	* @brief Return the TIM OC state
mbed_official	340:28d1f895c6fe	4308	* @param htim : TIM Ouput Compare handle
mbed_official	340:28d1f895c6fe	4309	* @retval HAL state
mbed_official	340:28d1f895c6fe	4310	*/
mbed_official	340:28d1f895c6fe	4311	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4312	{
mbed_official	340:28d1f895c6fe	4313	return htim->State;
mbed_official	340:28d1f895c6fe	4314	}
mbed_official	340:28d1f895c6fe	4315
mbed_official	340:28d1f895c6fe	4316	/**
mbed_official	340:28d1f895c6fe	4317	* @brief Return the TIM PWM state
mbed_official	340:28d1f895c6fe	4318	* @param htim : TIM handle
mbed_official	340:28d1f895c6fe	4319	* @retval HAL state
mbed_official	340:28d1f895c6fe	4320	*/
mbed_official	340:28d1f895c6fe	4321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4322	{
mbed_official	340:28d1f895c6fe	4323	return htim->State;
mbed_official	340:28d1f895c6fe	4324	}
mbed_official	340:28d1f895c6fe	4325
mbed_official	340:28d1f895c6fe	4326	/**
mbed_official	340:28d1f895c6fe	4327	* @brief Return the TIM Input Capture state
mbed_official	340:28d1f895c6fe	4328	* @param htim : TIM IC handle
mbed_official	340:28d1f895c6fe	4329	* @retval HAL state
mbed_official	340:28d1f895c6fe	4330	*/
mbed_official	340:28d1f895c6fe	4331	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4332	{
mbed_official	340:28d1f895c6fe	4333	return htim->State;
mbed_official	340:28d1f895c6fe	4334	}
mbed_official	340:28d1f895c6fe	4335
mbed_official	340:28d1f895c6fe	4336	/**
mbed_official	340:28d1f895c6fe	4337	* @brief Return the TIM One Pulse Mode state
mbed_official	340:28d1f895c6fe	4338	* @param htim : TIM OPM handle
mbed_official	340:28d1f895c6fe	4339	* @retval HAL state
mbed_official	340:28d1f895c6fe	4340	*/
mbed_official	340:28d1f895c6fe	4341	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4342	{
mbed_official	340:28d1f895c6fe	4343	return htim->State;
mbed_official	340:28d1f895c6fe	4344	}
mbed_official	340:28d1f895c6fe	4345
mbed_official	340:28d1f895c6fe	4346	/**
mbed_official	340:28d1f895c6fe	4347	* @brief Return the TIM Encoder Mode state
mbed_official	340:28d1f895c6fe	4348	* @param htim : TIM Encoder handle
mbed_official	340:28d1f895c6fe	4349	* @retval HAL state
mbed_official	340:28d1f895c6fe	4350	*/
mbed_official	340:28d1f895c6fe	4351	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official	340:28d1f895c6fe	4352	{
mbed_official	340:28d1f895c6fe	4353	return htim->State;
mbed_official	340:28d1f895c6fe	4354	}
mbed_official	340:28d1f895c6fe	4355
mbed_official	340:28d1f895c6fe	4356	/**
mbed_official	340:28d1f895c6fe	4357	* @}
mbed_official	340:28d1f895c6fe	4358	*/
mbed_official	340:28d1f895c6fe	4359
mbed_official	340:28d1f895c6fe	4360	/**
mbed_official	340:28d1f895c6fe	4361	* @}
mbed_official	340:28d1f895c6fe	4362	*/
mbed_official	340:28d1f895c6fe	4363
mbed_official	340:28d1f895c6fe	4364	/** @addtogroup TIM_Private_Functions TIM_Private_Functions
mbed_official	340:28d1f895c6fe	4365	* @{
mbed_official	340:28d1f895c6fe	4366	*/
mbed_official	340:28d1f895c6fe	4367
mbed_official	340:28d1f895c6fe	4368	/**
mbed_official	340:28d1f895c6fe	4369	* @brief TIM DMA error callback
mbed_official	340:28d1f895c6fe	4370	* @param hdma : pointer to DMA handle.
mbed_official	340:28d1f895c6fe	4371	* @retval None
mbed_official	340:28d1f895c6fe	4372	*/
mbed_official	340:28d1f895c6fe	4373	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	4374	{
mbed_official	340:28d1f895c6fe	4375	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	4376
mbed_official	340:28d1f895c6fe	4377	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4378
mbed_official	340:28d1f895c6fe	4379	HAL_TIM_ErrorCallback(htim);
mbed_official	340:28d1f895c6fe	4380	}
mbed_official	340:28d1f895c6fe	4381
mbed_official	340:28d1f895c6fe	4382	/**
mbed_official	340:28d1f895c6fe	4383	* @brief TIM DMA Delay Pulse complete callback.
mbed_official	340:28d1f895c6fe	4384	* @param hdma : pointer to DMA handle.
mbed_official	340:28d1f895c6fe	4385	* @retval None
mbed_official	340:28d1f895c6fe	4386	*/
mbed_official	340:28d1f895c6fe	4387	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	4388	{
mbed_official	340:28d1f895c6fe	4389	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	4390
mbed_official	340:28d1f895c6fe	4391	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4392
mbed_official	340:28d1f895c6fe	4393	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official	340:28d1f895c6fe	4394	{
mbed_official	340:28d1f895c6fe	4395	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official	340:28d1f895c6fe	4396	}
mbed_official	340:28d1f895c6fe	4397	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official	340:28d1f895c6fe	4398	{
mbed_official	340:28d1f895c6fe	4399	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official	340:28d1f895c6fe	4400	}
mbed_official	340:28d1f895c6fe	4401	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official	340:28d1f895c6fe	4402	{
mbed_official	340:28d1f895c6fe	4403	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official	340:28d1f895c6fe	4404	}
mbed_official	340:28d1f895c6fe	4405	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official	340:28d1f895c6fe	4406	{
mbed_official	340:28d1f895c6fe	4407	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official	340:28d1f895c6fe	4408	}
mbed_official	340:28d1f895c6fe	4409
mbed_official	340:28d1f895c6fe	4410	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	340:28d1f895c6fe	4411
mbed_official	340:28d1f895c6fe	4412	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	4413	}
mbed_official	340:28d1f895c6fe	4414	/**
mbed_official	340:28d1f895c6fe	4415	* @brief TIM DMA Capture complete callback.
mbed_official	340:28d1f895c6fe	4416	* @param hdma : pointer to DMA handle.
mbed_official	340:28d1f895c6fe	4417	* @retval None
mbed_official	340:28d1f895c6fe	4418	*/
mbed_official	340:28d1f895c6fe	4419	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	4420	{
mbed_official	340:28d1f895c6fe	4421	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	4422
mbed_official	340:28d1f895c6fe	4423	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4424
mbed_official	340:28d1f895c6fe	4425	if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official	340:28d1f895c6fe	4426	{
mbed_official	340:28d1f895c6fe	4427	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official	340:28d1f895c6fe	4428	}
mbed_official	340:28d1f895c6fe	4429	else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official	340:28d1f895c6fe	4430	{
mbed_official	340:28d1f895c6fe	4431	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official	340:28d1f895c6fe	4432	}
mbed_official	340:28d1f895c6fe	4433	else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official	340:28d1f895c6fe	4434	{
mbed_official	340:28d1f895c6fe	4435	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official	340:28d1f895c6fe	4436	}
mbed_official	340:28d1f895c6fe	4437	else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official	340:28d1f895c6fe	4438	{
mbed_official	340:28d1f895c6fe	4439	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official	340:28d1f895c6fe	4440	}
mbed_official	340:28d1f895c6fe	4441
mbed_official	340:28d1f895c6fe	4442	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	340:28d1f895c6fe	4443
mbed_official	340:28d1f895c6fe	4444	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	340:28d1f895c6fe	4445	}
mbed_official	340:28d1f895c6fe	4446
mbed_official	340:28d1f895c6fe	4447	/**
mbed_official	340:28d1f895c6fe	4448	* @brief TIM DMA Period Elapse complete callback.
mbed_official	340:28d1f895c6fe	4449	* @param hdma : pointer to DMA handle.
mbed_official	340:28d1f895c6fe	4450	* @retval None
mbed_official	340:28d1f895c6fe	4451	*/
mbed_official	340:28d1f895c6fe	4452	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	4453	{
mbed_official	340:28d1f895c6fe	4454	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	4455
mbed_official	340:28d1f895c6fe	4456	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4457
mbed_official	340:28d1f895c6fe	4458	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	340:28d1f895c6fe	4459	}
mbed_official	340:28d1f895c6fe	4460
mbed_official	340:28d1f895c6fe	4461	/**
mbed_official	340:28d1f895c6fe	4462	* @brief TIM DMA Trigger callback.
mbed_official	340:28d1f895c6fe	4463	* @param hdma : pointer to DMA handle.
mbed_official	340:28d1f895c6fe	4464	* @retval None
mbed_official	340:28d1f895c6fe	4465	*/
mbed_official	340:28d1f895c6fe	4466	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	4467	{
mbed_official	340:28d1f895c6fe	4468	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	4469
mbed_official	340:28d1f895c6fe	4470	htim->State= HAL_TIM_STATE_READY;
mbed_official	340:28d1f895c6fe	4471
mbed_official	340:28d1f895c6fe	4472	HAL_TIM_TriggerCallback(htim);
mbed_official	340:28d1f895c6fe	4473	}
mbed_official	340:28d1f895c6fe	4474
mbed_official	340:28d1f895c6fe	4475	/**
mbed_official	340:28d1f895c6fe	4476	* @brief Time Base configuration
mbed_official	340:28d1f895c6fe	4477	* @param TIMx : TIM periheral
mbed_official	340:28d1f895c6fe	4478	* @param Structure : TIM Base configuration structure
mbed_official	340:28d1f895c6fe	4479	* @retval None
mbed_official	340:28d1f895c6fe	4480	*/
mbed_official	340:28d1f895c6fe	4481	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
mbed_official	340:28d1f895c6fe	4482	{
mbed_official	340:28d1f895c6fe	4483	uint32_t tmpcr1 = 0;
mbed_official	340:28d1f895c6fe	4484	tmpcr1 = TIMx->CR1;
mbed_official	340:28d1f895c6fe	4485
mbed_official	340:28d1f895c6fe	4486	/* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official	340:28d1f895c6fe	4487	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4488	{
mbed_official	340:28d1f895c6fe	4489	/* Select the Counter Mode */
mbed_official	340:28d1f895c6fe	4490	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
mbed_official	340:28d1f895c6fe	4491	tmpcr1 \|= Structure->CounterMode;
mbed_official	340:28d1f895c6fe	4492	}
mbed_official	340:28d1f895c6fe	4493
mbed_official	340:28d1f895c6fe	4494	if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4495	{
mbed_official	340:28d1f895c6fe	4496	/* Set the clock division */
mbed_official	340:28d1f895c6fe	4497	tmpcr1 &= ~TIM_CR1_CKD;
mbed_official	340:28d1f895c6fe	4498	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
mbed_official	340:28d1f895c6fe	4499	}
mbed_official	340:28d1f895c6fe	4500
mbed_official	340:28d1f895c6fe	4501	TIMx->CR1 = tmpcr1;
mbed_official	340:28d1f895c6fe	4502
mbed_official	340:28d1f895c6fe	4503	/* Set the Autoreload value */
mbed_official	340:28d1f895c6fe	4504	TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official	340:28d1f895c6fe	4505
mbed_official	340:28d1f895c6fe	4506	/* Set the Prescaler value */
mbed_official	340:28d1f895c6fe	4507	TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official	340:28d1f895c6fe	4508
mbed_official	340:28d1f895c6fe	4509	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4510	{
mbed_official	340:28d1f895c6fe	4511	/* Set the Repetition Counter value */
mbed_official	340:28d1f895c6fe	4512	TIMx->RCR = Structure->RepetitionCounter;
mbed_official	340:28d1f895c6fe	4513	}
mbed_official	340:28d1f895c6fe	4514
mbed_official	340:28d1f895c6fe	4515	/* Generate an update event to reload the Prescaler
mbed_official	340:28d1f895c6fe	4516	and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official	340:28d1f895c6fe	4517	TIMx->EGR = TIM_EGR_UG;
mbed_official	340:28d1f895c6fe	4518	}
mbed_official	340:28d1f895c6fe	4519
mbed_official	340:28d1f895c6fe	4520	/**
mbed_official	340:28d1f895c6fe	4521	* @brief Time Ouput Compare 1 configuration
mbed_official	340:28d1f895c6fe	4522	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	4523	* @param OC_Config : The ouput configuration structure
mbed_official	340:28d1f895c6fe	4524	* @retval None
mbed_official	340:28d1f895c6fe	4525	*/
mbed_official	340:28d1f895c6fe	4526	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	340:28d1f895c6fe	4527	{
mbed_official	340:28d1f895c6fe	4528	uint32_t tmpccmrx = 0;
mbed_official	340:28d1f895c6fe	4529	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4530	uint32_t tmpcr2 = 0;
mbed_official	340:28d1f895c6fe	4531
mbed_official	340:28d1f895c6fe	4532	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	340:28d1f895c6fe	4533	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	340:28d1f895c6fe	4534
mbed_official	340:28d1f895c6fe	4535	/* Get the TIMx CCER register value */
mbed_official	340:28d1f895c6fe	4536	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	4537	/* Get the TIMx CR2 register value */
mbed_official	340:28d1f895c6fe	4538	tmpcr2 = TIMx->CR2;
mbed_official	340:28d1f895c6fe	4539
mbed_official	340:28d1f895c6fe	4540	/* Get the TIMx CCMR1 register value */
mbed_official	340:28d1f895c6fe	4541	tmpccmrx = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	4542
mbed_official	340:28d1f895c6fe	4543	/* Reset the Output Compare Mode Bits */
mbed_official	340:28d1f895c6fe	4544	tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official	340:28d1f895c6fe	4545	tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official	340:28d1f895c6fe	4546	/* Select the Output Compare Mode */
mbed_official	340:28d1f895c6fe	4547	tmpccmrx \|= OC_Config->OCMode;
mbed_official	340:28d1f895c6fe	4548
mbed_official	340:28d1f895c6fe	4549	/* Reset the Output Polarity level */
mbed_official	340:28d1f895c6fe	4550	tmpccer &= ~TIM_CCER_CC1P;
mbed_official	340:28d1f895c6fe	4551	/* Set the Output Compare Polarity */
mbed_official	340:28d1f895c6fe	4552	tmpccer \|= OC_Config->OCPolarity;
mbed_official	340:28d1f895c6fe	4553
mbed_official	340:28d1f895c6fe	4554	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
mbed_official	340:28d1f895c6fe	4555	{
mbed_official	340:28d1f895c6fe	4556	/* Check parameters */
mbed_official	340:28d1f895c6fe	4557	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	340:28d1f895c6fe	4558
mbed_official	340:28d1f895c6fe	4559	/* Reset the Output N Polarity level */
mbed_official	340:28d1f895c6fe	4560	tmpccer &= ~TIM_CCER_CC1NP;
mbed_official	340:28d1f895c6fe	4561	/* Set the Output N Polarity */
mbed_official	340:28d1f895c6fe	4562	tmpccer \|= OC_Config->OCNPolarity;
mbed_official	340:28d1f895c6fe	4563	/* Reset the Output N State */
mbed_official	340:28d1f895c6fe	4564	tmpccer &= ~TIM_CCER_CC1NE;
mbed_official	340:28d1f895c6fe	4565	}
mbed_official	340:28d1f895c6fe	4566
mbed_official	340:28d1f895c6fe	4567	if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4568	{
mbed_official	340:28d1f895c6fe	4569	/* Check parameters */
mbed_official	340:28d1f895c6fe	4570	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	340:28d1f895c6fe	4571	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4572
mbed_official	340:28d1f895c6fe	4573	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	340:28d1f895c6fe	4574	tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official	340:28d1f895c6fe	4575	tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official	340:28d1f895c6fe	4576	/* Set the Output Idle state */
mbed_official	340:28d1f895c6fe	4577	tmpcr2 \|= OC_Config->OCIdleState;
mbed_official	340:28d1f895c6fe	4578	/* Set the Output N Idle state */
mbed_official	340:28d1f895c6fe	4579	tmpcr2 \|= OC_Config->OCNIdleState;
mbed_official	340:28d1f895c6fe	4580	}
mbed_official	340:28d1f895c6fe	4581	/* Write to TIMx CR2 */
mbed_official	340:28d1f895c6fe	4582	TIMx->CR2 = tmpcr2;
mbed_official	340:28d1f895c6fe	4583
mbed_official	340:28d1f895c6fe	4584	/* Write to TIMx CCMR1 */
mbed_official	340:28d1f895c6fe	4585	TIMx->CCMR1 = tmpccmrx;
mbed_official	340:28d1f895c6fe	4586
mbed_official	340:28d1f895c6fe	4587	/* Set the Capture Compare Register value */
mbed_official	340:28d1f895c6fe	4588	TIMx->CCR1 = OC_Config->Pulse;
mbed_official	340:28d1f895c6fe	4589
mbed_official	340:28d1f895c6fe	4590	/* Write to TIMx CCER */
mbed_official	340:28d1f895c6fe	4591	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4592	}
mbed_official	340:28d1f895c6fe	4593
mbed_official	340:28d1f895c6fe	4594	/**
mbed_official	340:28d1f895c6fe	4595	* @brief Time Ouput Compare 2 configuration
mbed_official	340:28d1f895c6fe	4596	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	4597	* @param OC_Config : The ouput configuration structure
mbed_official	340:28d1f895c6fe	4598	* @retval None
mbed_official	340:28d1f895c6fe	4599	*/
mbed_official	340:28d1f895c6fe	4600	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	340:28d1f895c6fe	4601	{
mbed_official	340:28d1f895c6fe	4602	uint32_t tmpccmrx = 0;
mbed_official	340:28d1f895c6fe	4603	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4604	uint32_t tmpcr2 = 0;
mbed_official	340:28d1f895c6fe	4605
mbed_official	340:28d1f895c6fe	4606	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	340:28d1f895c6fe	4607	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	340:28d1f895c6fe	4608
mbed_official	340:28d1f895c6fe	4609	/* Get the TIMx CCER register value */
mbed_official	340:28d1f895c6fe	4610	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	4611	/* Get the TIMx CR2 register value */
mbed_official	340:28d1f895c6fe	4612	tmpcr2 = TIMx->CR2;
mbed_official	340:28d1f895c6fe	4613
mbed_official	340:28d1f895c6fe	4614	/* Get the TIMx CCMR1 register value */
mbed_official	340:28d1f895c6fe	4615	tmpccmrx = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	4616
mbed_official	340:28d1f895c6fe	4617	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	340:28d1f895c6fe	4618	tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official	340:28d1f895c6fe	4619	tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official	340:28d1f895c6fe	4620
mbed_official	340:28d1f895c6fe	4621	/* Select the Output Compare Mode */
mbed_official	340:28d1f895c6fe	4622	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	340:28d1f895c6fe	4623
mbed_official	340:28d1f895c6fe	4624	/* Reset the Output Polarity level */
mbed_official	340:28d1f895c6fe	4625	tmpccer &= ~TIM_CCER_CC2P;
mbed_official	340:28d1f895c6fe	4626	/* Set the Output Compare Polarity */
mbed_official	340:28d1f895c6fe	4627	tmpccer \|= (OC_Config->OCPolarity << 4);
mbed_official	340:28d1f895c6fe	4628
mbed_official	340:28d1f895c6fe	4629	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
mbed_official	340:28d1f895c6fe	4630	{
mbed_official	340:28d1f895c6fe	4631	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	340:28d1f895c6fe	4632	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	340:28d1f895c6fe	4633	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4634
mbed_official	340:28d1f895c6fe	4635	/* Reset the Output N Polarity level */
mbed_official	340:28d1f895c6fe	4636	tmpccer &= ~TIM_CCER_CC2NP;
mbed_official	340:28d1f895c6fe	4637	/* Set the Output N Polarity */
mbed_official	340:28d1f895c6fe	4638	tmpccer \|= (OC_Config->OCNPolarity << 4);
mbed_official	340:28d1f895c6fe	4639	/* Reset the Output N State */
mbed_official	340:28d1f895c6fe	4640	tmpccer &= ~TIM_CCER_CC2NE;
mbed_official	340:28d1f895c6fe	4641
mbed_official	340:28d1f895c6fe	4642	}
mbed_official	340:28d1f895c6fe	4643
mbed_official	340:28d1f895c6fe	4644	if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4645	{
mbed_official	340:28d1f895c6fe	4646	/* Check parameters */
mbed_official	340:28d1f895c6fe	4647	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	340:28d1f895c6fe	4648	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4649
mbed_official	340:28d1f895c6fe	4650	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	340:28d1f895c6fe	4651	tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official	340:28d1f895c6fe	4652	tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official	340:28d1f895c6fe	4653	/* Set the Output Idle state */
mbed_official	340:28d1f895c6fe	4654	tmpcr2 \|= (OC_Config->OCIdleState << 2);
mbed_official	340:28d1f895c6fe	4655	/* Set the Output N Idle state */
mbed_official	340:28d1f895c6fe	4656	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
mbed_official	340:28d1f895c6fe	4657	}
mbed_official	340:28d1f895c6fe	4658
mbed_official	340:28d1f895c6fe	4659	/* Write to TIMx CR2 */
mbed_official	340:28d1f895c6fe	4660	TIMx->CR2 = tmpcr2;
mbed_official	340:28d1f895c6fe	4661
mbed_official	340:28d1f895c6fe	4662	/* Write to TIMx CCMR1 */
mbed_official	340:28d1f895c6fe	4663	TIMx->CCMR1 = tmpccmrx;
mbed_official	340:28d1f895c6fe	4664
mbed_official	340:28d1f895c6fe	4665	/* Set the Capture Compare Register value */
mbed_official	340:28d1f895c6fe	4666	TIMx->CCR2 = OC_Config->Pulse;
mbed_official	340:28d1f895c6fe	4667
mbed_official	340:28d1f895c6fe	4668	/* Write to TIMx CCER */
mbed_official	340:28d1f895c6fe	4669	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4670	}
mbed_official	340:28d1f895c6fe	4671
mbed_official	340:28d1f895c6fe	4672	/**
mbed_official	340:28d1f895c6fe	4673	* @brief Time Ouput Compare 3 configuration
mbed_official	340:28d1f895c6fe	4674	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	4675	* @param OC_Config : The ouput configuration structure
mbed_official	340:28d1f895c6fe	4676	* @retval None
mbed_official	340:28d1f895c6fe	4677	*/
mbed_official	340:28d1f895c6fe	4678	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	340:28d1f895c6fe	4679	{
mbed_official	340:28d1f895c6fe	4680	uint32_t tmpccmrx = 0;
mbed_official	340:28d1f895c6fe	4681	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4682	uint32_t tmpcr2 = 0;
mbed_official	340:28d1f895c6fe	4683
mbed_official	340:28d1f895c6fe	4684	/* Disable the Channel 3: Reset the CC2E Bit */
mbed_official	340:28d1f895c6fe	4685	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	340:28d1f895c6fe	4686
mbed_official	340:28d1f895c6fe	4687	/* Get the TIMx CCER register value */
mbed_official	340:28d1f895c6fe	4688	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	4689	/* Get the TIMx CR2 register value */
mbed_official	340:28d1f895c6fe	4690	tmpcr2 = TIMx->CR2;
mbed_official	340:28d1f895c6fe	4691
mbed_official	340:28d1f895c6fe	4692	/* Get the TIMx CCMR2 register value */
mbed_official	340:28d1f895c6fe	4693	tmpccmrx = TIMx->CCMR2;
mbed_official	340:28d1f895c6fe	4694
mbed_official	340:28d1f895c6fe	4695	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	340:28d1f895c6fe	4696	tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official	340:28d1f895c6fe	4697	tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official	340:28d1f895c6fe	4698	/* Select the Output Compare Mode */
mbed_official	340:28d1f895c6fe	4699	tmpccmrx \|= OC_Config->OCMode;
mbed_official	340:28d1f895c6fe	4700
mbed_official	340:28d1f895c6fe	4701	/* Reset the Output Polarity level */
mbed_official	340:28d1f895c6fe	4702	tmpccer &= ~TIM_CCER_CC3P;
mbed_official	340:28d1f895c6fe	4703	/* Set the Output Compare Polarity */
mbed_official	340:28d1f895c6fe	4704	tmpccer \|= (OC_Config->OCPolarity << 8);
mbed_official	340:28d1f895c6fe	4705
mbed_official	340:28d1f895c6fe	4706	if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
mbed_official	340:28d1f895c6fe	4707	{
mbed_official	340:28d1f895c6fe	4708	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	340:28d1f895c6fe	4709	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	340:28d1f895c6fe	4710	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4711
mbed_official	340:28d1f895c6fe	4712	/* Reset the Output N Polarity level */
mbed_official	340:28d1f895c6fe	4713	tmpccer &= ~TIM_CCER_CC3NP;
mbed_official	340:28d1f895c6fe	4714	/* Set the Output N Polarity */
mbed_official	340:28d1f895c6fe	4715	tmpccer \|= (OC_Config->OCNPolarity << 8);
mbed_official	340:28d1f895c6fe	4716	/* Reset the Output N State */
mbed_official	340:28d1f895c6fe	4717	tmpccer &= ~TIM_CCER_CC3NE;
mbed_official	340:28d1f895c6fe	4718	}
mbed_official	340:28d1f895c6fe	4719
mbed_official	340:28d1f895c6fe	4720	if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4721	{
mbed_official	340:28d1f895c6fe	4722	/* Check parameters */
mbed_official	340:28d1f895c6fe	4723	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	340:28d1f895c6fe	4724	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4725
mbed_official	340:28d1f895c6fe	4726	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	340:28d1f895c6fe	4727	tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official	340:28d1f895c6fe	4728	tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official	340:28d1f895c6fe	4729	/* Set the Output Idle state */
mbed_official	340:28d1f895c6fe	4730	tmpcr2 \|= (OC_Config->OCIdleState << 4);
mbed_official	340:28d1f895c6fe	4731	/* Set the Output N Idle state */
mbed_official	340:28d1f895c6fe	4732	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
mbed_official	340:28d1f895c6fe	4733	}
mbed_official	340:28d1f895c6fe	4734
mbed_official	340:28d1f895c6fe	4735	/* Write to TIMx CR2 */
mbed_official	340:28d1f895c6fe	4736	TIMx->CR2 = tmpcr2;
mbed_official	340:28d1f895c6fe	4737
mbed_official	340:28d1f895c6fe	4738	/* Write to TIMx CCMR2 */
mbed_official	340:28d1f895c6fe	4739	TIMx->CCMR2 = tmpccmrx;
mbed_official	340:28d1f895c6fe	4740
mbed_official	340:28d1f895c6fe	4741	/* Set the Capture Compare Register value */
mbed_official	340:28d1f895c6fe	4742	TIMx->CCR3 = OC_Config->Pulse;
mbed_official	340:28d1f895c6fe	4743
mbed_official	340:28d1f895c6fe	4744	/* Write to TIMx CCER */
mbed_official	340:28d1f895c6fe	4745	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4746	}
mbed_official	340:28d1f895c6fe	4747
mbed_official	340:28d1f895c6fe	4748	/**
mbed_official	340:28d1f895c6fe	4749	* @brief Time Ouput Compare 4 configuration
mbed_official	340:28d1f895c6fe	4750	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	4751	* @param OC_Config : The ouput configuration structure
mbed_official	340:28d1f895c6fe	4752	* @retval None
mbed_official	340:28d1f895c6fe	4753	*/
mbed_official	340:28d1f895c6fe	4754	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	340:28d1f895c6fe	4755	{
mbed_official	340:28d1f895c6fe	4756	uint32_t tmpccmrx = 0;
mbed_official	340:28d1f895c6fe	4757	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4758	uint32_t tmpcr2 = 0;
mbed_official	340:28d1f895c6fe	4759
mbed_official	340:28d1f895c6fe	4760	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	340:28d1f895c6fe	4761	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	340:28d1f895c6fe	4762
mbed_official	340:28d1f895c6fe	4763	/* Get the TIMx CCER register value */
mbed_official	340:28d1f895c6fe	4764	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	4765	/* Get the TIMx CR2 register value */
mbed_official	340:28d1f895c6fe	4766	tmpcr2 = TIMx->CR2;
mbed_official	340:28d1f895c6fe	4767
mbed_official	340:28d1f895c6fe	4768	/* Get the TIMx CCMR2 register value */
mbed_official	340:28d1f895c6fe	4769	tmpccmrx = TIMx->CCMR2;
mbed_official	340:28d1f895c6fe	4770
mbed_official	340:28d1f895c6fe	4771	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	340:28d1f895c6fe	4772	tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official	340:28d1f895c6fe	4773	tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official	340:28d1f895c6fe	4774
mbed_official	340:28d1f895c6fe	4775	/* Select the Output Compare Mode */
mbed_official	340:28d1f895c6fe	4776	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	340:28d1f895c6fe	4777
mbed_official	340:28d1f895c6fe	4778	/* Reset the Output Polarity level */
mbed_official	340:28d1f895c6fe	4779	tmpccer &= ~TIM_CCER_CC4P;
mbed_official	340:28d1f895c6fe	4780	/* Set the Output Compare Polarity */
mbed_official	340:28d1f895c6fe	4781	tmpccer \|= (OC_Config->OCPolarity << 12);
mbed_official	340:28d1f895c6fe	4782
mbed_official	340:28d1f895c6fe	4783	if(IS_TIM_BREAK_INSTANCE(TIMx))
mbed_official	340:28d1f895c6fe	4784	{
mbed_official	340:28d1f895c6fe	4785	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	340:28d1f895c6fe	4786
mbed_official	340:28d1f895c6fe	4787	/* Reset the Output Compare IDLE State */
mbed_official	340:28d1f895c6fe	4788	tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official	340:28d1f895c6fe	4789	/* Set the Output Idle state */
mbed_official	340:28d1f895c6fe	4790	tmpcr2 \|= (OC_Config->OCIdleState << 6);
mbed_official	340:28d1f895c6fe	4791	}
mbed_official	340:28d1f895c6fe	4792
mbed_official	340:28d1f895c6fe	4793	/* Write to TIMx CR2 */
mbed_official	340:28d1f895c6fe	4794	TIMx->CR2 = tmpcr2;
mbed_official	340:28d1f895c6fe	4795
mbed_official	340:28d1f895c6fe	4796	/* Write to TIMx CCMR2 */
mbed_official	340:28d1f895c6fe	4797	TIMx->CCMR2 = tmpccmrx;
mbed_official	340:28d1f895c6fe	4798
mbed_official	340:28d1f895c6fe	4799	/* Set the Capture Compare Register value */
mbed_official	340:28d1f895c6fe	4800	TIMx->CCR4 = OC_Config->Pulse;
mbed_official	340:28d1f895c6fe	4801
mbed_official	340:28d1f895c6fe	4802	/* Write to TIMx CCER */
mbed_official	340:28d1f895c6fe	4803	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4804	}
mbed_official	340:28d1f895c6fe	4805
mbed_official	340:28d1f895c6fe	4806	void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official	340:28d1f895c6fe	4807	TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official	340:28d1f895c6fe	4808	{
mbed_official	340:28d1f895c6fe	4809	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	4810	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	4811	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4812
mbed_official	340:28d1f895c6fe	4813	/* Get the TIMx SMCR register value */
mbed_official	340:28d1f895c6fe	4814	tmpsmcr = htim->Instance->SMCR;
mbed_official	340:28d1f895c6fe	4815
mbed_official	340:28d1f895c6fe	4816	/* Reset the Trigger Selection Bits */
mbed_official	340:28d1f895c6fe	4817	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	340:28d1f895c6fe	4818	/* Set the Input Trigger source */
mbed_official	340:28d1f895c6fe	4819	tmpsmcr \|= sSlaveConfig->InputTrigger;
mbed_official	340:28d1f895c6fe	4820
mbed_official	340:28d1f895c6fe	4821	/* Reset the slave mode Bits */
mbed_official	340:28d1f895c6fe	4822	tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official	340:28d1f895c6fe	4823	/* Set the slave mode */
mbed_official	340:28d1f895c6fe	4824	tmpsmcr \|= sSlaveConfig->SlaveMode;
mbed_official	340:28d1f895c6fe	4825
mbed_official	340:28d1f895c6fe	4826	/* Write to TIMx SMCR */
mbed_official	340:28d1f895c6fe	4827	htim->Instance->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	4828
mbed_official	340:28d1f895c6fe	4829	/* Configure the trigger prescaler, filter, and polarity */
mbed_official	340:28d1f895c6fe	4830	switch (sSlaveConfig->InputTrigger)
mbed_official	340:28d1f895c6fe	4831	{
mbed_official	340:28d1f895c6fe	4832	case TIM_TS_ETRF:
mbed_official	340:28d1f895c6fe	4833	{
mbed_official	340:28d1f895c6fe	4834	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4835	assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4836	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official	340:28d1f895c6fe	4837	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	340:28d1f895c6fe	4838	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	340:28d1f895c6fe	4839	/* Configure the ETR Trigger source */
mbed_official	340:28d1f895c6fe	4840	TIM_ETR_SetConfig(htim->Instance,
mbed_official	340:28d1f895c6fe	4841	sSlaveConfig->TriggerPrescaler,
mbed_official	340:28d1f895c6fe	4842	sSlaveConfig->TriggerPolarity,
mbed_official	340:28d1f895c6fe	4843	sSlaveConfig->TriggerFilter);
mbed_official	340:28d1f895c6fe	4844	}
mbed_official	340:28d1f895c6fe	4845	break;
mbed_official	340:28d1f895c6fe	4846
mbed_official	340:28d1f895c6fe	4847	case TIM_TS_TI1F_ED:
mbed_official	340:28d1f895c6fe	4848	{
mbed_official	340:28d1f895c6fe	4849	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4850	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4851	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	340:28d1f895c6fe	4852	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	340:28d1f895c6fe	4853
mbed_official	340:28d1f895c6fe	4854	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	340:28d1f895c6fe	4855	tmpccer = htim->Instance->CCER;
mbed_official	340:28d1f895c6fe	4856	htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official	340:28d1f895c6fe	4857	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	340:28d1f895c6fe	4858
mbed_official	340:28d1f895c6fe	4859	/* Set the filter */
mbed_official	340:28d1f895c6fe	4860	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	340:28d1f895c6fe	4861	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official	340:28d1f895c6fe	4862
mbed_official	340:28d1f895c6fe	4863	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	340:28d1f895c6fe	4864	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	340:28d1f895c6fe	4865	htim->Instance->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4866
mbed_official	340:28d1f895c6fe	4867	}
mbed_official	340:28d1f895c6fe	4868	break;
mbed_official	340:28d1f895c6fe	4869
mbed_official	340:28d1f895c6fe	4870	case TIM_TS_TI1FP1:
mbed_official	340:28d1f895c6fe	4871	{
mbed_official	340:28d1f895c6fe	4872	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4873	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4874	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	340:28d1f895c6fe	4875	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	340:28d1f895c6fe	4876
mbed_official	340:28d1f895c6fe	4877	/* Configure TI1 Filter and Polarity */
mbed_official	340:28d1f895c6fe	4878	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	340:28d1f895c6fe	4879	sSlaveConfig->TriggerPolarity,
mbed_official	340:28d1f895c6fe	4880	sSlaveConfig->TriggerFilter);
mbed_official	340:28d1f895c6fe	4881	}
mbed_official	340:28d1f895c6fe	4882	break;
mbed_official	340:28d1f895c6fe	4883
mbed_official	340:28d1f895c6fe	4884	case TIM_TS_TI2FP2:
mbed_official	340:28d1f895c6fe	4885	{
mbed_official	340:28d1f895c6fe	4886	/* Check the parameters */
mbed_official	340:28d1f895c6fe	4887	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4888	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	340:28d1f895c6fe	4889	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	340:28d1f895c6fe	4890
mbed_official	340:28d1f895c6fe	4891	/* Configure TI2 Filter and Polarity */
mbed_official	340:28d1f895c6fe	4892	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	340:28d1f895c6fe	4893	sSlaveConfig->TriggerPolarity,
mbed_official	340:28d1f895c6fe	4894	sSlaveConfig->TriggerFilter);
mbed_official	340:28d1f895c6fe	4895	}
mbed_official	340:28d1f895c6fe	4896	break;
mbed_official	340:28d1f895c6fe	4897
mbed_official	340:28d1f895c6fe	4898	case TIM_TS_ITR0:
mbed_official	340:28d1f895c6fe	4899	{
mbed_official	340:28d1f895c6fe	4900	/* Check the parameter */
mbed_official	340:28d1f895c6fe	4901	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4902	}
mbed_official	340:28d1f895c6fe	4903	break;
mbed_official	340:28d1f895c6fe	4904
mbed_official	340:28d1f895c6fe	4905	case TIM_TS_ITR1:
mbed_official	340:28d1f895c6fe	4906	{
mbed_official	340:28d1f895c6fe	4907	/* Check the parameter */
mbed_official	340:28d1f895c6fe	4908	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4909	}
mbed_official	340:28d1f895c6fe	4910	break;
mbed_official	340:28d1f895c6fe	4911
mbed_official	340:28d1f895c6fe	4912	case TIM_TS_ITR2:
mbed_official	340:28d1f895c6fe	4913	{
mbed_official	340:28d1f895c6fe	4914	/* Check the parameter */
mbed_official	340:28d1f895c6fe	4915	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4916	}
mbed_official	340:28d1f895c6fe	4917	break;
mbed_official	340:28d1f895c6fe	4918
mbed_official	340:28d1f895c6fe	4919	case TIM_TS_ITR3:
mbed_official	340:28d1f895c6fe	4920	{
mbed_official	340:28d1f895c6fe	4921	/* Check the parameter */
mbed_official	340:28d1f895c6fe	4922	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	340:28d1f895c6fe	4923	}
mbed_official	340:28d1f895c6fe	4924	break;
mbed_official	340:28d1f895c6fe	4925
mbed_official	340:28d1f895c6fe	4926	default:
mbed_official	340:28d1f895c6fe	4927	break;
mbed_official	340:28d1f895c6fe	4928	}
mbed_official	340:28d1f895c6fe	4929	}
mbed_official	340:28d1f895c6fe	4930
mbed_official	340:28d1f895c6fe	4931	/**
mbed_official	340:28d1f895c6fe	4932	* @brief Configure the TI1 as Input.
mbed_official	340:28d1f895c6fe	4933	* @param TIMx to select the TIM peripheral.
mbed_official	340:28d1f895c6fe	4934	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	4935	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	4936	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	4937	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	4938	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	4939	* @param TIM_ICSelection : specifies the input to be used.
mbed_official	340:28d1f895c6fe	4940	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	4941	* @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
mbed_official	340:28d1f895c6fe	4942	* @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
mbed_official	340:28d1f895c6fe	4943	* @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
mbed_official	340:28d1f895c6fe	4944	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	4945	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	4946	* @retval None
mbed_official	340:28d1f895c6fe	4947	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
mbed_official	340:28d1f895c6fe	4948	* (on channel2 path) is used as the input signal. Therefore CCMR1 must be
mbed_official	340:28d1f895c6fe	4949	* protected against un-initialized filter and polarity values.
mbed_official	340:28d1f895c6fe	4950	*/
mbed_official	340:28d1f895c6fe	4951	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	4952	uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	4953	{
mbed_official	340:28d1f895c6fe	4954	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	4955	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	4956
mbed_official	340:28d1f895c6fe	4957	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	340:28d1f895c6fe	4958	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	340:28d1f895c6fe	4959	tmpccmr1 = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	4960	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	4961
mbed_official	340:28d1f895c6fe	4962	/* Select the Input */
mbed_official	340:28d1f895c6fe	4963	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official	340:28d1f895c6fe	4964	{
mbed_official	340:28d1f895c6fe	4965	tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official	340:28d1f895c6fe	4966	tmpccmr1 \|= TIM_ICSelection;
mbed_official	340:28d1f895c6fe	4967	}
mbed_official	340:28d1f895c6fe	4968	else
mbed_official	340:28d1f895c6fe	4969	{
mbed_official	340:28d1f895c6fe	4970	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
mbed_official	340:28d1f895c6fe	4971	}
mbed_official	340:28d1f895c6fe	4972
mbed_official	340:28d1f895c6fe	4973	/* Set the filter */
mbed_official	340:28d1f895c6fe	4974	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	340:28d1f895c6fe	4975	tmpccmr1 \|= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
mbed_official	340:28d1f895c6fe	4976
mbed_official	340:28d1f895c6fe	4977	/* Select the Polarity and set the CC1E Bit */
mbed_official	340:28d1f895c6fe	4978	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	340:28d1f895c6fe	4979	tmpccer \|= (TIM_ICPolarity & (TIM_CCER_CC1P \| TIM_CCER_CC1NP));
mbed_official	340:28d1f895c6fe	4980
mbed_official	340:28d1f895c6fe	4981	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	340:28d1f895c6fe	4982	TIMx->CCMR1 = tmpccmr1;
mbed_official	340:28d1f895c6fe	4983	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	4984	}
mbed_official	340:28d1f895c6fe	4985
mbed_official	340:28d1f895c6fe	4986	/**
mbed_official	340:28d1f895c6fe	4987	* @brief Configure the Polarity and Filter for TI1.
mbed_official	340:28d1f895c6fe	4988	* @param TIMx to select the TIM peripheral.
mbed_official	340:28d1f895c6fe	4989	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	4990	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	4991	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	4992	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	4993	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	4994	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	4995	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	4996	* @retval None
mbed_official	340:28d1f895c6fe	4997	*/
mbed_official	340:28d1f895c6fe	4998	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	4999	{
mbed_official	340:28d1f895c6fe	5000	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	5001	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	5002
mbed_official	340:28d1f895c6fe	5003	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	340:28d1f895c6fe	5004	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	5005	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	340:28d1f895c6fe	5006	tmpccmr1 = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	5007
mbed_official	340:28d1f895c6fe	5008	/* Set the filter */
mbed_official	340:28d1f895c6fe	5009	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	340:28d1f895c6fe	5010	tmpccmr1 \|= (TIM_ICFilter << 4);
mbed_official	340:28d1f895c6fe	5011
mbed_official	340:28d1f895c6fe	5012	/* Select the Polarity and set the CC1E Bit */
mbed_official	340:28d1f895c6fe	5013	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	340:28d1f895c6fe	5014	tmpccer \|= TIM_ICPolarity;
mbed_official	340:28d1f895c6fe	5015
mbed_official	340:28d1f895c6fe	5016	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	340:28d1f895c6fe	5017	TIMx->CCMR1 = tmpccmr1;
mbed_official	340:28d1f895c6fe	5018	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	5019	}
mbed_official	340:28d1f895c6fe	5020
mbed_official	340:28d1f895c6fe	5021	/**
mbed_official	340:28d1f895c6fe	5022	* @brief Configure the TI2 as Input.
mbed_official	340:28d1f895c6fe	5023	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5024	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	5025	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5026	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	5027	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	5028	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	5029	* @param TIM_ICSelection : specifies the input to be used.
mbed_official	340:28d1f895c6fe	5030	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5031	* @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
mbed_official	340:28d1f895c6fe	5032	* @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
mbed_official	340:28d1f895c6fe	5033	* @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
mbed_official	340:28d1f895c6fe	5034	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	5035	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	5036	* @retval None
mbed_official	340:28d1f895c6fe	5037	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
mbed_official	340:28d1f895c6fe	5038	* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
mbed_official	340:28d1f895c6fe	5039	* protected against un-initialized filter and polarity values.
mbed_official	340:28d1f895c6fe	5040	*/
mbed_official	340:28d1f895c6fe	5041	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	5042	uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	5043	{
mbed_official	340:28d1f895c6fe	5044	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	5045	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	5046
mbed_official	340:28d1f895c6fe	5047	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	340:28d1f895c6fe	5048	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	340:28d1f895c6fe	5049	tmpccmr1 = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	5050	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	5051
mbed_official	340:28d1f895c6fe	5052	/* Select the Input */
mbed_official	340:28d1f895c6fe	5053	tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official	340:28d1f895c6fe	5054	tmpccmr1 \|= (TIM_ICSelection << 8);
mbed_official	340:28d1f895c6fe	5055
mbed_official	340:28d1f895c6fe	5056	/* Set the filter */
mbed_official	340:28d1f895c6fe	5057	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	340:28d1f895c6fe	5058	tmpccmr1 \|= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
mbed_official	340:28d1f895c6fe	5059
mbed_official	340:28d1f895c6fe	5060	/* Select the Polarity and set the CC2E Bit */
mbed_official	340:28d1f895c6fe	5061	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	340:28d1f895c6fe	5062	tmpccer \|= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P \| TIM_CCER_CC2NP));
mbed_official	340:28d1f895c6fe	5063
mbed_official	340:28d1f895c6fe	5064	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	340:28d1f895c6fe	5065	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	340:28d1f895c6fe	5066	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	5067	}
mbed_official	340:28d1f895c6fe	5068
mbed_official	340:28d1f895c6fe	5069	/**
mbed_official	340:28d1f895c6fe	5070	* @brief Configure the Polarity and Filter for TI2.
mbed_official	340:28d1f895c6fe	5071	* @param TIMx to select the TIM peripheral.
mbed_official	340:28d1f895c6fe	5072	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	5073	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5074	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	5075	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	5076	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	5077	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	5078	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	5079	* @retval None
mbed_official	340:28d1f895c6fe	5080	*/
mbed_official	340:28d1f895c6fe	5081	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	5082	{
mbed_official	340:28d1f895c6fe	5083	uint32_t tmpccmr1 = 0;
mbed_official	340:28d1f895c6fe	5084	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	5085
mbed_official	340:28d1f895c6fe	5086	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	340:28d1f895c6fe	5087	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	340:28d1f895c6fe	5088	tmpccmr1 = TIMx->CCMR1;
mbed_official	340:28d1f895c6fe	5089	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	5090
mbed_official	340:28d1f895c6fe	5091	/* Set the filter */
mbed_official	340:28d1f895c6fe	5092	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	340:28d1f895c6fe	5093	tmpccmr1 \|= (TIM_ICFilter << 12);
mbed_official	340:28d1f895c6fe	5094
mbed_official	340:28d1f895c6fe	5095	/* Select the Polarity and set the CC2E Bit */
mbed_official	340:28d1f895c6fe	5096	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	340:28d1f895c6fe	5097	tmpccer \|= (TIM_ICPolarity << 4);
mbed_official	340:28d1f895c6fe	5098
mbed_official	340:28d1f895c6fe	5099	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	340:28d1f895c6fe	5100	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	340:28d1f895c6fe	5101	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	5102	}
mbed_official	340:28d1f895c6fe	5103
mbed_official	340:28d1f895c6fe	5104	/**
mbed_official	340:28d1f895c6fe	5105	* @brief Configure the TI3 as Input.
mbed_official	340:28d1f895c6fe	5106	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5107	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	5108	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5109	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	5110	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	5111	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	5112	* @param TIM_ICSelection : specifies the input to be used.
mbed_official	340:28d1f895c6fe	5113	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5114	* @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
mbed_official	340:28d1f895c6fe	5115	* @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
mbed_official	340:28d1f895c6fe	5116	* @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
mbed_official	340:28d1f895c6fe	5117	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	5118	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	5119	* @retval None
mbed_official	340:28d1f895c6fe	5120	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
mbed_official	340:28d1f895c6fe	5121	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
mbed_official	340:28d1f895c6fe	5122	* protected against un-initialized filter and polarity values.
mbed_official	340:28d1f895c6fe	5123	*/
mbed_official	340:28d1f895c6fe	5124	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	5125	uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	5126	{
mbed_official	340:28d1f895c6fe	5127	uint32_t tmpccmr2 = 0;
mbed_official	340:28d1f895c6fe	5128	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	5129
mbed_official	340:28d1f895c6fe	5130	/* Disable the Channel 3: Reset the CC3E Bit */
mbed_official	340:28d1f895c6fe	5131	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	340:28d1f895c6fe	5132	tmpccmr2 = TIMx->CCMR2;
mbed_official	340:28d1f895c6fe	5133	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	5134
mbed_official	340:28d1f895c6fe	5135	/* Select the Input */
mbed_official	340:28d1f895c6fe	5136	tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official	340:28d1f895c6fe	5137	tmpccmr2 \|= TIM_ICSelection;
mbed_official	340:28d1f895c6fe	5138
mbed_official	340:28d1f895c6fe	5139	/* Set the filter */
mbed_official	340:28d1f895c6fe	5140	tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official	340:28d1f895c6fe	5141	tmpccmr2 \|= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
mbed_official	340:28d1f895c6fe	5142
mbed_official	340:28d1f895c6fe	5143	/* Select the Polarity and set the CC3E Bit */
mbed_official	340:28d1f895c6fe	5144	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
mbed_official	340:28d1f895c6fe	5145	tmpccer \|= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P \| TIM_CCER_CC3NP));
mbed_official	340:28d1f895c6fe	5146
mbed_official	340:28d1f895c6fe	5147	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	340:28d1f895c6fe	5148	TIMx->CCMR2 = tmpccmr2;
mbed_official	340:28d1f895c6fe	5149	TIMx->CCER = tmpccer;
mbed_official	340:28d1f895c6fe	5150	}
mbed_official	340:28d1f895c6fe	5151
mbed_official	340:28d1f895c6fe	5152	/**
mbed_official	340:28d1f895c6fe	5153	* @brief Configure the TI4 as Input.
mbed_official	340:28d1f895c6fe	5154	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5155	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	340:28d1f895c6fe	5156	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5157	* @arg TIM_ICPolarity_Rising
mbed_official	340:28d1f895c6fe	5158	* @arg TIM_ICPolarity_Falling
mbed_official	340:28d1f895c6fe	5159	* @arg TIM_ICPolarity_BothEdge
mbed_official	340:28d1f895c6fe	5160	* @param TIM_ICSelection : specifies the input to be used.
mbed_official	340:28d1f895c6fe	5161	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5162	* @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
mbed_official	340:28d1f895c6fe	5163	* @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
mbed_official	340:28d1f895c6fe	5164	* @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
mbed_official	340:28d1f895c6fe	5165	* @param TIM_ICFilter : Specifies the Input Capture Filter.
mbed_official	340:28d1f895c6fe	5166	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	340:28d1f895c6fe	5167	* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
mbed_official	340:28d1f895c6fe	5168	* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
mbed_official	340:28d1f895c6fe	5169	* protected against un-initialized filter and polarity values.
mbed_official	340:28d1f895c6fe	5170	* @retval None
mbed_official	340:28d1f895c6fe	5171	*/
mbed_official	340:28d1f895c6fe	5172	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	340:28d1f895c6fe	5173	uint32_t TIM_ICFilter)
mbed_official	340:28d1f895c6fe	5174	{
mbed_official	340:28d1f895c6fe	5175	uint32_t tmpccmr2 = 0;
mbed_official	340:28d1f895c6fe	5176	uint32_t tmpccer = 0;
mbed_official	340:28d1f895c6fe	5177
mbed_official	340:28d1f895c6fe	5178	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	340:28d1f895c6fe	5179	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	340:28d1f895c6fe	5180	tmpccmr2 = TIMx->CCMR2;
mbed_official	340:28d1f895c6fe	5181	tmpccer = TIMx->CCER;
mbed_official	340:28d1f895c6fe	5182
mbed_official	340:28d1f895c6fe	5183	/* Select the Input */
mbed_official	340:28d1f895c6fe	5184	tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official	340:28d1f895c6fe	5185	tmpccmr2 \|= (TIM_ICSelection << 8);
mbed_official	340:28d1f895c6fe	5186
mbed_official	340:28d1f895c6fe	5187	/* Set the filter */
mbed_official	340:28d1f895c6fe	5188	tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official	340:28d1f895c6fe	5189	tmpccmr2 \|= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
mbed_official	340:28d1f895c6fe	5190
mbed_official	340:28d1f895c6fe	5191	/* Select the Polarity and set the CC4E Bit */
mbed_official	340:28d1f895c6fe	5192	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
mbed_official	340:28d1f895c6fe	5193	tmpccer \|= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P \| TIM_CCER_CC4NP));
mbed_official	340:28d1f895c6fe	5194
mbed_official	340:28d1f895c6fe	5195	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	340:28d1f895c6fe	5196	TIMx->CCMR2 = tmpccmr2;
mbed_official	340:28d1f895c6fe	5197	TIMx->CCER = tmpccer ;
mbed_official	340:28d1f895c6fe	5198	}
mbed_official	340:28d1f895c6fe	5199
mbed_official	340:28d1f895c6fe	5200	/**
mbed_official	340:28d1f895c6fe	5201	* @brief Selects the Input Trigger source
mbed_official	340:28d1f895c6fe	5202	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5203	* @param InputTriggerSource : The Input Trigger source.
mbed_official	340:28d1f895c6fe	5204	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5205	* @arg TIM_TS_ITR0 : Internal Trigger 0
mbed_official	340:28d1f895c6fe	5206	* @arg TIM_TS_ITR1 : Internal Trigger 1
mbed_official	340:28d1f895c6fe	5207	* @arg TIM_TS_ITR2 : Internal Trigger 2
mbed_official	340:28d1f895c6fe	5208	* @arg TIM_TS_ITR3 : Internal Trigger 3
mbed_official	340:28d1f895c6fe	5209	* @arg TIM_TS_TI1F_ED : TI1 Edge Detector
mbed_official	340:28d1f895c6fe	5210	* @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
mbed_official	340:28d1f895c6fe	5211	* @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
mbed_official	340:28d1f895c6fe	5212	* @arg TIM_TS_ETRF : External Trigger input
mbed_official	340:28d1f895c6fe	5213	* @retval None
mbed_official	340:28d1f895c6fe	5214	*/
mbed_official	340:28d1f895c6fe	5215	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
mbed_official	340:28d1f895c6fe	5216	{
mbed_official	340:28d1f895c6fe	5217	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	5218
mbed_official	340:28d1f895c6fe	5219	/* Get the TIMx SMCR register value */
mbed_official	340:28d1f895c6fe	5220	tmpsmcr = TIMx->SMCR;
mbed_official	340:28d1f895c6fe	5221	/* Reset the TS Bits */
mbed_official	340:28d1f895c6fe	5222	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	340:28d1f895c6fe	5223	/* Set the Input Trigger source and the slave mode*/
mbed_official	340:28d1f895c6fe	5224	tmpsmcr \|= InputTriggerSource \| TIM_SLAVEMODE_EXTERNAL1;
mbed_official	340:28d1f895c6fe	5225	/* Write to TIMx SMCR */
mbed_official	340:28d1f895c6fe	5226	TIMx->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	5227	}
mbed_official	340:28d1f895c6fe	5228	/**
mbed_official	340:28d1f895c6fe	5229	* @brief Configures the TIMx External Trigger (ETR).
mbed_official	340:28d1f895c6fe	5230	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5231	* @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
mbed_official	340:28d1f895c6fe	5232	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5233	* @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
mbed_official	340:28d1f895c6fe	5234	* @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
mbed_official	340:28d1f895c6fe	5235	* @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
mbed_official	340:28d1f895c6fe	5236	* @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
mbed_official	340:28d1f895c6fe	5237	* @param TIM_ExtTRGPolarity : The external Trigger Polarity.
mbed_official	340:28d1f895c6fe	5238	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5239	* @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
mbed_official	340:28d1f895c6fe	5240	* @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
mbed_official	340:28d1f895c6fe	5241	* @param ExtTRGFilter : External Trigger Filter.
mbed_official	340:28d1f895c6fe	5242	* This parameter must be a value between 0x00 and 0x0F
mbed_official	340:28d1f895c6fe	5243	* @retval None
mbed_official	340:28d1f895c6fe	5244	*/
mbed_official	340:28d1f895c6fe	5245	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	340:28d1f895c6fe	5246	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official	340:28d1f895c6fe	5247	{
mbed_official	340:28d1f895c6fe	5248	uint32_t tmpsmcr = 0;
mbed_official	340:28d1f895c6fe	5249
mbed_official	340:28d1f895c6fe	5250	tmpsmcr = TIMx->SMCR;
mbed_official	340:28d1f895c6fe	5251
mbed_official	340:28d1f895c6fe	5252	/* Reset the ETR Bits */
mbed_official	340:28d1f895c6fe	5253	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	340:28d1f895c6fe	5254
mbed_official	340:28d1f895c6fe	5255	/* Set the Prescaler, the Filter value and the Polarity */
mbed_official	340:28d1f895c6fe	5256	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
mbed_official	340:28d1f895c6fe	5257
mbed_official	340:28d1f895c6fe	5258	/* Write to TIMx SMCR */
mbed_official	340:28d1f895c6fe	5259	TIMx->SMCR = tmpsmcr;
mbed_official	340:28d1f895c6fe	5260	}
mbed_official	340:28d1f895c6fe	5261
mbed_official	340:28d1f895c6fe	5262	/**
mbed_official	340:28d1f895c6fe	5263	* @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official	340:28d1f895c6fe	5264	* @param TIMx to select the TIM peripheral
mbed_official	340:28d1f895c6fe	5265	* @param Channel : specifies the TIM Channel
mbed_official	340:28d1f895c6fe	5266	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	5267	* @arg TIM_Channel_1 : TIM Channel 1
mbed_official	340:28d1f895c6fe	5268	* @arg TIM_Channel_2 : TIM Channel 2
mbed_official	340:28d1f895c6fe	5269	* @arg TIM_Channel_3 : TIM Channel 3
mbed_official	340:28d1f895c6fe	5270	* @arg TIM_Channel_4 : TIM Channel 4
mbed_official	340:28d1f895c6fe	5271	* @param ChannelState : specifies the TIM Channel CCxE bit new state.
mbed_official	340:28d1f895c6fe	5272	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official	340:28d1f895c6fe	5273	* @retval None
mbed_official	340:28d1f895c6fe	5274	*/
mbed_official	340:28d1f895c6fe	5275	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official	340:28d1f895c6fe	5276	{
mbed_official	340:28d1f895c6fe	5277	uint32_t tmp = 0;
mbed_official	340:28d1f895c6fe	5278
mbed_official	340:28d1f895c6fe	5279	/* Check the parameters */
mbed_official	340:28d1f895c6fe	5280	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official	340:28d1f895c6fe	5281	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	340:28d1f895c6fe	5282
mbed_official	340:28d1f895c6fe	5283	tmp = TIM_CCER_CC1E << Channel;
mbed_official	340:28d1f895c6fe	5284
mbed_official	340:28d1f895c6fe	5285	/* Reset the CCxE Bit */
mbed_official	340:28d1f895c6fe	5286	TIMx->CCER &= ~tmp;
mbed_official	340:28d1f895c6fe	5287
mbed_official	340:28d1f895c6fe	5288	/* Set or reset the CCxE Bit */
mbed_official	340:28d1f895c6fe	5289	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
mbed_official	340:28d1f895c6fe	5290	}
mbed_official	340:28d1f895c6fe	5291
mbed_official	340:28d1f895c6fe	5292
mbed_official	340:28d1f895c6fe	5293	/**
mbed_official	340:28d1f895c6fe	5294	* @}
mbed_official	340:28d1f895c6fe	5295	*/
mbed_official	340:28d1f895c6fe	5296
mbed_official	340:28d1f895c6fe	5297	#endif /* HAL_TIM_MODULE_ENABLED */
mbed_official	340:28d1f895c6fe	5298	/**
mbed_official	340:28d1f895c6fe	5299	* @}
mbed_official	340:28d1f895c6fe	5300	*/
mbed_official	340:28d1f895c6fe	5301
mbed_official	340:28d1f895c6fe	5302	/**
mbed_official	340:28d1f895c6fe	5303	* @}
mbed_official	340:28d1f895c6fe	5304	*/
mbed_official	340:28d1f895c6fe	5305	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	14 Jan 2015
Imports:	4
Forks:	0
Commits:	446
Dependents:	0
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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.c@441:d2c15dda23c1, 2015-01-06 (annotated)

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