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mbed library sources

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targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c@439:c4382fcbbaed, 2014-12-15 (annotated)

Committer:
mbed_official
Date:
Mon Dec 15 09:30:07 2014 +0000
Revision:
439:c4382fcbbaed
Parent:
382:ee426a420dbb 
Synchronized with git revision 6172cbea1a558a9a2ebbd965e77f83a9ceeec670



Full URL: https://github.com/mbedmicro/mbed/commit/6172cbea1a558a9a2ebbd965e77f83a9ceeec670/



Targets: DISCO_L053C8 - update from nucleo latest changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 376:cb4d9db17537 1 /**
mbed_official 376:cb4d9db17537 2 ******************************************************************************
mbed_official 376:cb4d9db17537 3 * @file system_stm32l0xx.c
mbed_official 376:cb4d9db17537 4 * @author MCD Application Team
mbed_official 376:cb4d9db17537 5 * @version V1.1.0
mbed_official 376:cb4d9db17537 6 * @date 18-June-2014
mbed_official 376:cb4d9db17537 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
mbed_official 376:cb4d9db17537 8 *
mbed_official 376:cb4d9db17537 9 * This file provides two functions and one global variable to be called from
mbed_official 376:cb4d9db17537 10 * user application:
mbed_official 376:cb4d9db17537 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 376:cb4d9db17537 12 * before branch to main program. This call is made inside
mbed_official 376:cb4d9db17537 13 * the "startup_stm32l0xx.s" file.
mbed_official 376:cb4d9db17537 14 *
mbed_official 376:cb4d9db17537 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 376:cb4d9db17537 16 * by the user application to setup the SysTick
mbed_official 376:cb4d9db17537 17 * timer or configure other parameters.
mbed_official 376:cb4d9db17537 18 *
mbed_official 376:cb4d9db17537 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 376:cb4d9db17537 20 * be called whenever the core clock is changed
mbed_official 376:cb4d9db17537 21 * during program execution.
mbed_official 376:cb4d9db17537 22 *
mbed_official 376:cb4d9db17537 23 * This file configures the system clock as follows:
mbed_official 376:cb4d9db17537 24 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 376:cb4d9db17537 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 376:cb4d9db17537 27 * | 2- PLL_HSE_XTAL |
mbed_official 376:cb4d9db17537 28 * | (external 8 MHz xtal) |
mbed_official 376:cb4d9db17537 29 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 30 * SYSCLK(MHz) | 32 | 32
mbed_official 376:cb4d9db17537 31 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 32 * AHBCLK (MHz) | 32 | 32
mbed_official 376:cb4d9db17537 33 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 34 * APB1CLK (MHz) | 32 | 32
mbed_official 376:cb4d9db17537 35 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 36 * APB2CLK (MHz) | 32 | 32
mbed_official 376:cb4d9db17537 37 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 38 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 439:c4382fcbbaed 39 *-----------------------------------------------------------------------------
mbed_official 376:cb4d9db17537 40 ******************************************************************************
mbed_official 376:cb4d9db17537 41 * @attention
mbed_official 376:cb4d9db17537 42 *
mbed_official 376:cb4d9db17537 43 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 376:cb4d9db17537 44 *
mbed_official 376:cb4d9db17537 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 376:cb4d9db17537 46 * are permitted provided that the following conditions are met:
mbed_official 376:cb4d9db17537 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 376:cb4d9db17537 48 * this list of conditions and the following disclaimer.
mbed_official 376:cb4d9db17537 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 376:cb4d9db17537 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 376:cb4d9db17537 51 * and/or other materials provided with the distribution.
mbed_official 376:cb4d9db17537 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 376:cb4d9db17537 53 * may be used to endorse or promote products derived from this software
mbed_official 376:cb4d9db17537 54 * without specific prior written permission.
mbed_official 376:cb4d9db17537 55 *
mbed_official 376:cb4d9db17537 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 376:cb4d9db17537 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 376:cb4d9db17537 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 376:cb4d9db17537 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 376:cb4d9db17537 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 376:cb4d9db17537 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 376:cb4d9db17537 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 376:cb4d9db17537 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 376:cb4d9db17537 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 376:cb4d9db17537 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 376:cb4d9db17537 66 *
mbed_official 376:cb4d9db17537 67 ******************************************************************************
mbed_official 376:cb4d9db17537 68 */
mbed_official 376:cb4d9db17537 69
mbed_official 376:cb4d9db17537 70 /** @addtogroup CMSIS
mbed_official 376:cb4d9db17537 71 * @{
mbed_official 376:cb4d9db17537 72 */
mbed_official 376:cb4d9db17537 73
mbed_official 376:cb4d9db17537 74 /** @addtogroup stm32l0xx_system
mbed_official 376:cb4d9db17537 75 * @{
mbed_official 376:cb4d9db17537 76 */
mbed_official 376:cb4d9db17537 77
mbed_official 376:cb4d9db17537 78 /** @addtogroup STM32L0xx_System_Private_Includes
mbed_official 376:cb4d9db17537 79 * @{
mbed_official 376:cb4d9db17537 80 */
mbed_official 376:cb4d9db17537 81
mbed_official 376:cb4d9db17537 82 #include "stm32l0xx.h"
mbed_official 439:c4382fcbbaed 83 #include "hal_tick.h"
mbed_official 376:cb4d9db17537 84
mbed_official 376:cb4d9db17537 85 #if !defined (HSE_VALUE)
mbed_official 376:cb4d9db17537 86 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
mbed_official 376:cb4d9db17537 87 #endif /* HSE_VALUE */
mbed_official 376:cb4d9db17537 88
mbed_official 376:cb4d9db17537 89 #if !defined (MSI_VALUE)
mbed_official 376:cb4d9db17537 90 #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 376:cb4d9db17537 91 #endif /* MSI_VALUE */
mbed_official 376:cb4d9db17537 92
mbed_official 376:cb4d9db17537 93 #if !defined (HSI_VALUE)
mbed_official 376:cb4d9db17537 94 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 376:cb4d9db17537 95 #endif /* HSI_VALUE */
mbed_official 376:cb4d9db17537 96
mbed_official 376:cb4d9db17537 97
mbed_official 376:cb4d9db17537 98 /**
mbed_official 376:cb4d9db17537 99 * @}
mbed_official 376:cb4d9db17537 100 */
mbed_official 376:cb4d9db17537 101
mbed_official 376:cb4d9db17537 102 /** @addtogroup STM32L0xx_System_Private_TypesDefinitions
mbed_official 376:cb4d9db17537 103 * @{
mbed_official 376:cb4d9db17537 104 */
mbed_official 376:cb4d9db17537 105
mbed_official 376:cb4d9db17537 106 /**
mbed_official 376:cb4d9db17537 107 * @}
mbed_official 376:cb4d9db17537 108 */
mbed_official 376:cb4d9db17537 109
mbed_official 376:cb4d9db17537 110 /** @addtogroup STM32L0xx_System_Private_Defines
mbed_official 376:cb4d9db17537 111 * @{
mbed_official 376:cb4d9db17537 112 */
mbed_official 376:cb4d9db17537 113 /************************* Miscellaneous Configuration ************************/
mbed_official 376:cb4d9db17537 114
mbed_official 376:cb4d9db17537 115 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 376:cb4d9db17537 116 Internal SRAM. */
mbed_official 376:cb4d9db17537 117 /* #define VECT_TAB_SRAM */
mbed_official 376:cb4d9db17537 118 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 376:cb4d9db17537 119 This value must be a multiple of 0x200. */
mbed_official 376:cb4d9db17537 120 /******************************************************************************/
mbed_official 376:cb4d9db17537 121 /**
mbed_official 376:cb4d9db17537 122 * @}
mbed_official 376:cb4d9db17537 123 */
mbed_official 376:cb4d9db17537 124
mbed_official 376:cb4d9db17537 125 /** @addtogroup STM32L0xx_System_Private_Macros
mbed_official 376:cb4d9db17537 126 * @{
mbed_official 376:cb4d9db17537 127 */
mbed_official 376:cb4d9db17537 128
mbed_official 376:cb4d9db17537 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 376:cb4d9db17537 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 376:cb4d9db17537 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 376:cb4d9db17537 132
mbed_official 376:cb4d9db17537 133 /**
mbed_official 376:cb4d9db17537 134 * @}
mbed_official 376:cb4d9db17537 135 */
mbed_official 376:cb4d9db17537 136
mbed_official 376:cb4d9db17537 137 /** @addtogroup STM32L0xx_System_Private_Variables
mbed_official 376:cb4d9db17537 138 * @{
mbed_official 376:cb4d9db17537 139 */
mbed_official 376:cb4d9db17537 140 /* This variable is updated in three ways:
mbed_official 376:cb4d9db17537 141 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 376:cb4d9db17537 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 376:cb4d9db17537 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 376:cb4d9db17537 144 Note: If you use this function to configure the system clock; then there
mbed_official 376:cb4d9db17537 145 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 376:cb4d9db17537 146 variable is updated automatically.
mbed_official 376:cb4d9db17537 147 */
mbed_official 376:cb4d9db17537 148 uint32_t SystemCoreClock = 32000000;
mbed_official 376:cb4d9db17537 149 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 376:cb4d9db17537 150 __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 376:cb4d9db17537 151
mbed_official 376:cb4d9db17537 152 /**
mbed_official 376:cb4d9db17537 153 * @}
mbed_official 376:cb4d9db17537 154 */
mbed_official 376:cb4d9db17537 155
mbed_official 376:cb4d9db17537 156 /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
mbed_official 376:cb4d9db17537 157 * @{
mbed_official 376:cb4d9db17537 158 */
mbed_official 376:cb4d9db17537 159
mbed_official 376:cb4d9db17537 160 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 376:cb4d9db17537 161 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 376:cb4d9db17537 162 #endif
mbed_official 376:cb4d9db17537 163
mbed_official 376:cb4d9db17537 164 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 376:cb4d9db17537 165
mbed_official 376:cb4d9db17537 166 /**
mbed_official 376:cb4d9db17537 167 * @}
mbed_official 376:cb4d9db17537 168 */
mbed_official 376:cb4d9db17537 169
mbed_official 376:cb4d9db17537 170 /** @addtogroup STM32L0xx_System_Private_Functions
mbed_official 376:cb4d9db17537 171 * @{
mbed_official 376:cb4d9db17537 172 */
mbed_official 376:cb4d9db17537 173
mbed_official 376:cb4d9db17537 174 /**
mbed_official 376:cb4d9db17537 175 * @brief Setup the microcontroller system.
mbed_official 376:cb4d9db17537 176 * @param None
mbed_official 376:cb4d9db17537 177 * @retval None
mbed_official 376:cb4d9db17537 178 */
mbed_official 376:cb4d9db17537 179 void SystemInit (void)
mbed_official 376:cb4d9db17537 180 {
mbed_official 376:cb4d9db17537 181 /*!< Set MSION bit */
mbed_official 376:cb4d9db17537 182 RCC->CR |= (uint32_t)0x00000100;
mbed_official 376:cb4d9db17537 183
mbed_official 376:cb4d9db17537 184 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 376:cb4d9db17537 185 RCC->CFGR &= (uint32_t) 0x88FF400C;
mbed_official 376:cb4d9db17537 186
mbed_official 376:cb4d9db17537 187 /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
mbed_official 376:cb4d9db17537 188 RCC->CR &= (uint32_t)0xFEF6FFF6;
mbed_official 376:cb4d9db17537 189
mbed_official 376:cb4d9db17537 190 /*!< Reset HSI48ON bit */
mbed_official 376:cb4d9db17537 191 RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
mbed_official 376:cb4d9db17537 192
mbed_official 376:cb4d9db17537 193 /*!< Reset HSEBYP bit */
mbed_official 376:cb4d9db17537 194 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 376:cb4d9db17537 195
mbed_official 376:cb4d9db17537 196 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 376:cb4d9db17537 197 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 376:cb4d9db17537 198
mbed_official 376:cb4d9db17537 199 /*!< Disable all interrupts */
mbed_official 376:cb4d9db17537 200 RCC->CIER = 0x00000000;
mbed_official 376:cb4d9db17537 201
mbed_official 376:cb4d9db17537 202 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 376:cb4d9db17537 203 #ifdef VECT_TAB_SRAM
mbed_official 376:cb4d9db17537 204 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 376:cb4d9db17537 205 #else
mbed_official 376:cb4d9db17537 206 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 376:cb4d9db17537 207 #endif
mbed_official 376:cb4d9db17537 208
mbed_official 376:cb4d9db17537 209 /* Configure the Cube driver */
mbed_official 439:c4382fcbbaed 210 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 376:cb4d9db17537 211 HAL_Init();
mbed_official 376:cb4d9db17537 212
mbed_official 376:cb4d9db17537 213 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 376:cb4d9db17537 214 AHB/APBx prescalers and Flash settings */
mbed_official 376:cb4d9db17537 215 SetSysClock();
mbed_official 439:c4382fcbbaed 216
mbed_official 439:c4382fcbbaed 217 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 439:c4382fcbbaed 218 TIM_MST_RESET_ON;
mbed_official 439:c4382fcbbaed 219 TIM_MST_RESET_OFF;
mbed_official 376:cb4d9db17537 220 }
mbed_official 376:cb4d9db17537 221
mbed_official 376:cb4d9db17537 222 /**
mbed_official 376:cb4d9db17537 223 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 376:cb4d9db17537 224 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 376:cb4d9db17537 225 * be used by the user application to setup the SysTick timer or configure
mbed_official 376:cb4d9db17537 226 * other parameters.
mbed_official 376:cb4d9db17537 227 *
mbed_official 376:cb4d9db17537 228 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 376:cb4d9db17537 229 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 376:cb4d9db17537 230 * based on this variable will be incorrect.
mbed_official 376:cb4d9db17537 231 *
mbed_official 376:cb4d9db17537 232 * @note - The system frequency computed by this function is not the real
mbed_official 376:cb4d9db17537 233 * frequency in the chip. It is calculated based on the predefined
mbed_official 376:cb4d9db17537 234 * constant and the selected clock source:
mbed_official 376:cb4d9db17537 235 *
mbed_official 376:cb4d9db17537 236 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 376:cb4d9db17537 237 * value as defined by the MSI range.
mbed_official 376:cb4d9db17537 238 *
mbed_official 376:cb4d9db17537 239 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 376:cb4d9db17537 240 *
mbed_official 376:cb4d9db17537 241 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 376:cb4d9db17537 242 *
mbed_official 376:cb4d9db17537 243 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 376:cb4d9db17537 244 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 376:cb4d9db17537 245 *
mbed_official 376:cb4d9db17537 246 * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 376:cb4d9db17537 247 * 16 MHz) but the real value may vary depending on the variations
mbed_official 376:cb4d9db17537 248 * in voltage and temperature.
mbed_official 376:cb4d9db17537 249 *
mbed_official 376:cb4d9db17537 250 * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
mbed_official 376:cb4d9db17537 251 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 376:cb4d9db17537 252 * frequency of the crystal used. Otherwise, this function may
mbed_official 376:cb4d9db17537 253 * have wrong result.
mbed_official 376:cb4d9db17537 254 *
mbed_official 376:cb4d9db17537 255 * - The result of this function could be not correct when using fractional
mbed_official 376:cb4d9db17537 256 * value for HSE crystal.
mbed_official 376:cb4d9db17537 257 * @param None
mbed_official 376:cb4d9db17537 258 * @retval None
mbed_official 376:cb4d9db17537 259 */
mbed_official 376:cb4d9db17537 260 void SystemCoreClockUpdate (void)
mbed_official 376:cb4d9db17537 261 {
mbed_official 376:cb4d9db17537 262 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official 376:cb4d9db17537 263
mbed_official 376:cb4d9db17537 264 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 376:cb4d9db17537 265 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 376:cb4d9db17537 266
mbed_official 376:cb4d9db17537 267 switch (tmp)
mbed_official 376:cb4d9db17537 268 {
mbed_official 376:cb4d9db17537 269 case 0x00: /* MSI used as system clock */
mbed_official 376:cb4d9db17537 270 SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000);
mbed_official 376:cb4d9db17537 271 break;
mbed_official 376:cb4d9db17537 272 case 0x04: /* HSI used as system clock */
mbed_official 376:cb4d9db17537 273 SystemCoreClock = HSI_VALUE;
mbed_official 376:cb4d9db17537 274 break;
mbed_official 376:cb4d9db17537 275 case 0x08: /* HSE used as system clock */
mbed_official 376:cb4d9db17537 276 SystemCoreClock = HSE_VALUE;
mbed_official 376:cb4d9db17537 277 break;
mbed_official 376:cb4d9db17537 278 case 0x0C: /* PLL used as system clock */
mbed_official 376:cb4d9db17537 279 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 376:cb4d9db17537 280 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 376:cb4d9db17537 281 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 376:cb4d9db17537 282 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 376:cb4d9db17537 283 plldiv = (plldiv >> 22) + 1;
mbed_official 376:cb4d9db17537 284
mbed_official 376:cb4d9db17537 285 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 376:cb4d9db17537 286
mbed_official 376:cb4d9db17537 287 if (pllsource == 0x00)
mbed_official 376:cb4d9db17537 288 {
mbed_official 376:cb4d9db17537 289 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 376:cb4d9db17537 290 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 376:cb4d9db17537 291 }
mbed_official 376:cb4d9db17537 292 else
mbed_official 376:cb4d9db17537 293 {
mbed_official 376:cb4d9db17537 294 /* HSE selected as PLL clock entry */
mbed_official 376:cb4d9db17537 295 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 376:cb4d9db17537 296 }
mbed_official 376:cb4d9db17537 297 break;
mbed_official 376:cb4d9db17537 298 default: /* MSI used as system clock */
mbed_official 376:cb4d9db17537 299 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 376:cb4d9db17537 300 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 376:cb4d9db17537 301 break;
mbed_official 376:cb4d9db17537 302 }
mbed_official 376:cb4d9db17537 303 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 376:cb4d9db17537 304 /* Get HCLK prescaler */
mbed_official 376:cb4d9db17537 305 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 376:cb4d9db17537 306 /* HCLK clock frequency */
mbed_official 376:cb4d9db17537 307 SystemCoreClock >>= tmp;
mbed_official 376:cb4d9db17537 308 }
mbed_official 376:cb4d9db17537 309
mbed_official 376:cb4d9db17537 310 /**
mbed_official 376:cb4d9db17537 311 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 376:cb4d9db17537 312 * AHB/APBx prescalers and Flash settings
mbed_official 376:cb4d9db17537 313 * @note This function should be called only once the RCC clock configuration
mbed_official 376:cb4d9db17537 314 * is reset to the default reset state (done in SystemInit() function).
mbed_official 376:cb4d9db17537 315 * @param None
mbed_official 376:cb4d9db17537 316 * @retval None
mbed_official 376:cb4d9db17537 317 */
mbed_official 376:cb4d9db17537 318 void SetSysClock(void)
mbed_official 376:cb4d9db17537 319 {
mbed_official 376:cb4d9db17537 320 /* 1- Try to start with HSE and external clock */
mbed_official 376:cb4d9db17537 321 #if USE_PLL_HSE_EXTC != 0
mbed_official 376:cb4d9db17537 322 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 376:cb4d9db17537 323 #endif
mbed_official 376:cb4d9db17537 324 {
mbed_official 376:cb4d9db17537 325 /* 2- If fail try to start with HSE and external xtal */
mbed_official 376:cb4d9db17537 326 #if USE_PLL_HSE_XTAL != 0
mbed_official 376:cb4d9db17537 327 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 376:cb4d9db17537 328 #endif
mbed_official 376:cb4d9db17537 329 {
mbed_official 376:cb4d9db17537 330 /* 3- If fail start with HSI clock */
mbed_official 376:cb4d9db17537 331 if (SetSysClock_PLL_HSI() == 0)
mbed_official 376:cb4d9db17537 332 {
mbed_official 376:cb4d9db17537 333 while(1)
mbed_official 376:cb4d9db17537 334 {
mbed_official 376:cb4d9db17537 335 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 376:cb4d9db17537 336 }
mbed_official 376:cb4d9db17537 337 }
mbed_official 376:cb4d9db17537 338 }
mbed_official 376:cb4d9db17537 339 }
mbed_official 376:cb4d9db17537 340
mbed_official 376:cb4d9db17537 341 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 376:cb4d9db17537 342 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official 376:cb4d9db17537 343 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
mbed_official 376:cb4d9db17537 344 }
mbed_official 376:cb4d9db17537 345
mbed_official 376:cb4d9db17537 346 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 376:cb4d9db17537 347 /******************************************************************************/
mbed_official 376:cb4d9db17537 348 /* PLL (clocked by HSE) used as System clock source */
mbed_official 376:cb4d9db17537 349 /******************************************************************************/
mbed_official 376:cb4d9db17537 350 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 376:cb4d9db17537 351 {
mbed_official 376:cb4d9db17537 352 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 376:cb4d9db17537 353 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 376:cb4d9db17537 354
mbed_official 376:cb4d9db17537 355 /* Used to gain time after DeepSleep in case HSI is used */
mbed_official 376:cb4d9db17537 356 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 376:cb4d9db17537 357 {
mbed_official 376:cb4d9db17537 358 return 0;
mbed_official 376:cb4d9db17537 359 }
mbed_official 376:cb4d9db17537 360
mbed_official 376:cb4d9db17537 361 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 376:cb4d9db17537 362 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 376:cb4d9db17537 363 regarding system frequency refer to product datasheet. */
mbed_official 376:cb4d9db17537 364 __PWR_CLK_ENABLE();
mbed_official 376:cb4d9db17537 365 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 376:cb4d9db17537 366
mbed_official 376:cb4d9db17537 367 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official 376:cb4d9db17537 368 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
mbed_official 376:cb4d9db17537 369 if (bypass == 0)
mbed_official 376:cb4d9db17537 370 {
mbed_official 376:cb4d9db17537 371 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 376:cb4d9db17537 372 }
mbed_official 376:cb4d9db17537 373 else
mbed_official 376:cb4d9db17537 374 {
mbed_official 376:cb4d9db17537 375 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 376:cb4d9db17537 376 }
mbed_official 376:cb4d9db17537 377 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official 376:cb4d9db17537 378 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 376:cb4d9db17537 379 // PLLCLK = (8 MHz * 8)/2 = 32 MHz
mbed_official 376:cb4d9db17537 380 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 376:cb4d9db17537 381 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 376:cb4d9db17537 382 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8;
mbed_official 376:cb4d9db17537 383 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 376:cb4d9db17537 384 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 376:cb4d9db17537 385 {
mbed_official 376:cb4d9db17537 386 return 0; // FAIL
mbed_official 376:cb4d9db17537 387 }
mbed_official 376:cb4d9db17537 388
mbed_official 376:cb4d9db17537 389 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 376:cb4d9db17537 390 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 376:cb4d9db17537 391 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 376:cb4d9db17537 392 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 393 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 394 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 395 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 376:cb4d9db17537 396 {
mbed_official 376:cb4d9db17537 397 return 0; // FAIL
mbed_official 376:cb4d9db17537 398 }
mbed_official 376:cb4d9db17537 399
mbed_official 376:cb4d9db17537 400 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 376:cb4d9db17537 401 //if (bypass == 0)
mbed_official 376:cb4d9db17537 402 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official 376:cb4d9db17537 403 //else
mbed_official 376:cb4d9db17537 404 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official 376:cb4d9db17537 405
mbed_official 376:cb4d9db17537 406 return 1; // OK
mbed_official 376:cb4d9db17537 407 }
mbed_official 376:cb4d9db17537 408 #endif
mbed_official 376:cb4d9db17537 409
mbed_official 376:cb4d9db17537 410 /******************************************************************************/
mbed_official 376:cb4d9db17537 411 /* PLL (clocked by HSI) used as System clock source */
mbed_official 376:cb4d9db17537 412 /******************************************************************************/
mbed_official 376:cb4d9db17537 413 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 376:cb4d9db17537 414 {
mbed_official 376:cb4d9db17537 415 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 376:cb4d9db17537 416 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 376:cb4d9db17537 417
mbed_official 376:cb4d9db17537 418 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 376:cb4d9db17537 419 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 376:cb4d9db17537 420 regarding system frequency refer to product datasheet. */
mbed_official 376:cb4d9db17537 421 __PWR_CLK_ENABLE();
mbed_official 376:cb4d9db17537 422 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official 376:cb4d9db17537 423
mbed_official 376:cb4d9db17537 424 /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
mbed_official 376:cb4d9db17537 425 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 376:cb4d9db17537 426 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 376:cb4d9db17537 427 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 376:cb4d9db17537 428 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
mbed_official 376:cb4d9db17537 429 // PLLCLK = (16 MHz * 4)/2 = 32 MHz
mbed_official 376:cb4d9db17537 430 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 376:cb4d9db17537 431 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 376:cb4d9db17537 432 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
mbed_official 376:cb4d9db17537 433 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
mbed_official 376:cb4d9db17537 434 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 376:cb4d9db17537 435 {
mbed_official 376:cb4d9db17537 436 return 0; // FAIL
mbed_official 376:cb4d9db17537 437 }
mbed_official 376:cb4d9db17537 438
mbed_official 376:cb4d9db17537 439 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 376:cb4d9db17537 440 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 376:cb4d9db17537 441 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official 376:cb4d9db17537 442 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 443 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 444 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official 376:cb4d9db17537 445 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official 376:cb4d9db17537 446 {
mbed_official 376:cb4d9db17537 447 return 0; // FAIL
mbed_official 376:cb4d9db17537 448 }
mbed_official 376:cb4d9db17537 449
mbed_official 376:cb4d9db17537 450 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 376:cb4d9db17537 451 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 376:cb4d9db17537 452
mbed_official 376:cb4d9db17537 453 return 1; // OK
mbed_official 376:cb4d9db17537 454 }
mbed_official 376:cb4d9db17537 455
mbed_official 376:cb4d9db17537 456 /**
mbed_official 376:cb4d9db17537 457 * @}
mbed_official 376:cb4d9db17537 458 */
mbed_official 376:cb4d9db17537 459
mbed_official 376:cb4d9db17537 460 /**
mbed_official 376:cb4d9db17537 461 * @}
mbed_official 376:cb4d9db17537 462 */
mbed_official 376:cb4d9db17537 463
mbed_official 376:cb4d9db17537 464 /**
mbed_official 376:cb4d9db17537 465 * @}
mbed_official 376:cb4d9db17537 466 */
mbed_official 376:cb4d9db17537 467
mbed_official 376:cb4d9db17537 468 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/