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targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/stm32f303xe.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:
moirans2
Date:
Wed Jan 14 20:53:08 2015 +0000
Revision:
445:9a3ffe6cfa19
Parent:
423:560d1a9f3083 
internal clock stm32L051

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UserRevisionLine numberNew contents of line
mbed_official 423:560d1a9f3083 1 /**
mbed_official 423:560d1a9f3083 2 ******************************************************************************
mbed_official 423:560d1a9f3083 3 * @file stm32f303xe.h
mbed_official 423:560d1a9f3083 4 * @author MCD Application Team
mbed_official 423:560d1a9f3083 5 * @version V2.1.0
mbed_official 423:560d1a9f3083 6 * @date 12-Sept-2014
mbed_official 423:560d1a9f3083 7 * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
mbed_official 423:560d1a9f3083 8 *
mbed_official 423:560d1a9f3083 9 * This file contains:
mbed_official 423:560d1a9f3083 10 * - Data structures and the address mapping for all peripherals
mbed_official 423:560d1a9f3083 11 * - Peripheral's registers declarations and bits definition
mbed_official 423:560d1a9f3083 12 * - Macros to access peripheral’s registers hardware
mbed_official 423:560d1a9f3083 13 *
mbed_official 423:560d1a9f3083 14 ******************************************************************************
mbed_official 423:560d1a9f3083 15 * @attention
mbed_official 423:560d1a9f3083 16 *
mbed_official 423:560d1a9f3083 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 423:560d1a9f3083 18 *
mbed_official 423:560d1a9f3083 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 423:560d1a9f3083 20 * are permitted provided that the following conditions are met:
mbed_official 423:560d1a9f3083 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 423:560d1a9f3083 22 * this list of conditions and the following disclaimer.
mbed_official 423:560d1a9f3083 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 423:560d1a9f3083 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 423:560d1a9f3083 25 * and/or other materials provided with the distribution.
mbed_official 423:560d1a9f3083 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 423:560d1a9f3083 27 * may be used to endorse or promote products derived from this software
mbed_official 423:560d1a9f3083 28 * without specific prior written permission.
mbed_official 423:560d1a9f3083 29 *
mbed_official 423:560d1a9f3083 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 423:560d1a9f3083 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 423:560d1a9f3083 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 423:560d1a9f3083 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 423:560d1a9f3083 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 423:560d1a9f3083 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 423:560d1a9f3083 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 423:560d1a9f3083 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 423:560d1a9f3083 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 423:560d1a9f3083 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 423:560d1a9f3083 40 *
mbed_official 423:560d1a9f3083 41 ******************************************************************************
mbed_official 423:560d1a9f3083 42 */
mbed_official 423:560d1a9f3083 43
mbed_official 423:560d1a9f3083 44 /** @addtogroup CMSIS_Device
mbed_official 423:560d1a9f3083 45 * @{
mbed_official 423:560d1a9f3083 46 */
mbed_official 423:560d1a9f3083 47
mbed_official 423:560d1a9f3083 48 /** @addtogroup stm32f303xe
mbed_official 423:560d1a9f3083 49 * @{
mbed_official 423:560d1a9f3083 50 */
mbed_official 423:560d1a9f3083 51
mbed_official 423:560d1a9f3083 52 #ifndef __STM32F303xE_H
mbed_official 423:560d1a9f3083 53 #define __STM32F303xE_H
mbed_official 423:560d1a9f3083 54
mbed_official 423:560d1a9f3083 55 #ifdef __cplusplus
mbed_official 423:560d1a9f3083 56 extern "C" {
mbed_official 423:560d1a9f3083 57 #endif /* __cplusplus */
mbed_official 423:560d1a9f3083 58
mbed_official 423:560d1a9f3083 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 423:560d1a9f3083 60 * @{
mbed_official 423:560d1a9f3083 61 */
mbed_official 423:560d1a9f3083 62
mbed_official 423:560d1a9f3083 63 /**
mbed_official 423:560d1a9f3083 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 423:560d1a9f3083 65 */
mbed_official 423:560d1a9f3083 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 423:560d1a9f3083 67 #define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */
mbed_official 423:560d1a9f3083 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
mbed_official 423:560d1a9f3083 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 423:560d1a9f3083 70 #define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */
mbed_official 423:560d1a9f3083 71
mbed_official 423:560d1a9f3083 72 /**
mbed_official 423:560d1a9f3083 73 * @}
mbed_official 423:560d1a9f3083 74 */
mbed_official 423:560d1a9f3083 75
mbed_official 423:560d1a9f3083 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 423:560d1a9f3083 77 * @{
mbed_official 423:560d1a9f3083 78 */
mbed_official 423:560d1a9f3083 79
mbed_official 423:560d1a9f3083 80 /**
mbed_official 423:560d1a9f3083 81 * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
mbed_official 423:560d1a9f3083 82 * in @ref Library_configuration_section
mbed_official 423:560d1a9f3083 83 */
mbed_official 423:560d1a9f3083 84 typedef enum
mbed_official 423:560d1a9f3083 85 {
mbed_official 423:560d1a9f3083 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 423:560d1a9f3083 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 423:560d1a9f3083 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 423:560d1a9f3083 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 423:560d1a9f3083 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 423:560d1a9f3083 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 423:560d1a9f3083 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 423:560d1a9f3083 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 423:560d1a9f3083 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 423:560d1a9f3083 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 423:560d1a9f3083 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 423:560d1a9f3083 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 423:560d1a9f3083 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
mbed_official 423:560d1a9f3083 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
mbed_official 423:560d1a9f3083 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 423:560d1a9f3083 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 423:560d1a9f3083 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 423:560d1a9f3083 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 423:560d1a9f3083 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
mbed_official 423:560d1a9f3083 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 423:560d1a9f3083 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 423:560d1a9f3083 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 423:560d1a9f3083 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 423:560d1a9f3083 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 423:560d1a9f3083 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 423:560d1a9f3083 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 423:560d1a9f3083 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 423:560d1a9f3083 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 423:560d1a9f3083 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
mbed_official 423:560d1a9f3083 115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
mbed_official 423:560d1a9f3083 116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
mbed_official 423:560d1a9f3083 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
mbed_official 423:560d1a9f3083 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
mbed_official 423:560d1a9f3083 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 423:560d1a9f3083 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 423:560d1a9f3083 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 423:560d1a9f3083 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 423:560d1a9f3083 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 423:560d1a9f3083 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 423:560d1a9f3083 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 423:560d1a9f3083 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 423:560d1a9f3083 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 423:560d1a9f3083 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 423:560d1a9f3083 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
mbed_official 423:560d1a9f3083 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 423:560d1a9f3083 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 423:560d1a9f3083 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 423:560d1a9f3083 133 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 423:560d1a9f3083 134 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 423:560d1a9f3083 135 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
mbed_official 423:560d1a9f3083 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 423:560d1a9f3083 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
mbed_official 423:560d1a9f3083 138 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
mbed_official 423:560d1a9f3083 139 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
mbed_official 423:560d1a9f3083 140 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
mbed_official 423:560d1a9f3083 141 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
mbed_official 423:560d1a9f3083 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 423:560d1a9f3083 143 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
mbed_official 423:560d1a9f3083 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
mbed_official 423:560d1a9f3083 145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 423:560d1a9f3083 146 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
mbed_official 423:560d1a9f3083 147 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
mbed_official 423:560d1a9f3083 148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
mbed_official 423:560d1a9f3083 149 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
mbed_official 423:560d1a9f3083 150 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 423:560d1a9f3083 151 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 423:560d1a9f3083 152 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 423:560d1a9f3083 153 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 423:560d1a9f3083 154 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 423:560d1a9f3083 155 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
mbed_official 423:560d1a9f3083 156 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
mbed_official 423:560d1a9f3083 157 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
mbed_official 423:560d1a9f3083 158 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
mbed_official 423:560d1a9f3083 159 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 423:560d1a9f3083 160 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 423:560d1a9f3083 161 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
mbed_official 423:560d1a9f3083 162 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
mbed_official 423:560d1a9f3083 163 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
mbed_official 423:560d1a9f3083 164 TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
mbed_official 423:560d1a9f3083 165 TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
mbed_official 423:560d1a9f3083 166 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
mbed_official 423:560d1a9f3083 167 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
mbed_official 423:560d1a9f3083 168 FPU_IRQn = 81, /*!< Floating point Interrupt */
mbed_official 423:560d1a9f3083 169 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 423:560d1a9f3083 170 } IRQn_Type;
mbed_official 423:560d1a9f3083 171
mbed_official 423:560d1a9f3083 172 /**
mbed_official 423:560d1a9f3083 173 * @}
mbed_official 423:560d1a9f3083 174 */
mbed_official 423:560d1a9f3083 175
mbed_official 423:560d1a9f3083 176 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 423:560d1a9f3083 177 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
mbed_official 423:560d1a9f3083 178 #include <stdint.h>
mbed_official 423:560d1a9f3083 179
mbed_official 423:560d1a9f3083 180 /** @addtogroup Peripheral_registers_structures
mbed_official 423:560d1a9f3083 181 * @{
mbed_official 423:560d1a9f3083 182 */
mbed_official 423:560d1a9f3083 183
mbed_official 423:560d1a9f3083 184 /**
mbed_official 423:560d1a9f3083 185 * @brief Analog to Digital Converter
mbed_official 423:560d1a9f3083 186 */
mbed_official 423:560d1a9f3083 187
mbed_official 423:560d1a9f3083 188 typedef struct
mbed_official 423:560d1a9f3083 189 {
mbed_official 423:560d1a9f3083 190 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 191 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 192 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 193 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 194 uint32_t RESERVED0; /*!< Reserved, 0x010 */
mbed_official 423:560d1a9f3083 195 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 196 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 197 uint32_t RESERVED1; /*!< Reserved, 0x01C */
mbed_official 423:560d1a9f3083 198 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 199 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 200 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 201 uint32_t RESERVED2; /*!< Reserved, 0x02C */
mbed_official 423:560d1a9f3083 202 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 203 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 423:560d1a9f3083 204 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 423:560d1a9f3083 205 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 423:560d1a9f3083 206 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
mbed_official 423:560d1a9f3083 207 uint32_t RESERVED3; /*!< Reserved, 0x044 */
mbed_official 423:560d1a9f3083 208 uint32_t RESERVED4; /*!< Reserved, 0x048 */
mbed_official 423:560d1a9f3083 209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
mbed_official 423:560d1a9f3083 210 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
mbed_official 423:560d1a9f3083 211 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
mbed_official 423:560d1a9f3083 212 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
mbed_official 423:560d1a9f3083 213 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
mbed_official 423:560d1a9f3083 214 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
mbed_official 423:560d1a9f3083 215 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
mbed_official 423:560d1a9f3083 216 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
mbed_official 423:560d1a9f3083 217 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
mbed_official 423:560d1a9f3083 218 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
mbed_official 423:560d1a9f3083 219 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
mbed_official 423:560d1a9f3083 220 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
mbed_official 423:560d1a9f3083 221 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
mbed_official 423:560d1a9f3083 222 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
mbed_official 423:560d1a9f3083 223 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
mbed_official 423:560d1a9f3083 224 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
mbed_official 423:560d1a9f3083 225 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
mbed_official 423:560d1a9f3083 226 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
mbed_official 423:560d1a9f3083 227
mbed_official 423:560d1a9f3083 228 } ADC_TypeDef;
mbed_official 423:560d1a9f3083 229
mbed_official 423:560d1a9f3083 230 typedef struct
mbed_official 423:560d1a9f3083 231 {
mbed_official 423:560d1a9f3083 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
mbed_official 423:560d1a9f3083 233 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
mbed_official 423:560d1a9f3083 234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
mbed_official 423:560d1a9f3083 235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 423:560d1a9f3083 236 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
mbed_official 423:560d1a9f3083 237 } ADC_Common_TypeDef;
mbed_official 423:560d1a9f3083 238
mbed_official 423:560d1a9f3083 239 /**
mbed_official 423:560d1a9f3083 240 * @brief Controller Area Network TxMailBox
mbed_official 423:560d1a9f3083 241 */
mbed_official 423:560d1a9f3083 242 typedef struct
mbed_official 423:560d1a9f3083 243 {
mbed_official 423:560d1a9f3083 244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 423:560d1a9f3083 245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 423:560d1a9f3083 246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 423:560d1a9f3083 247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 423:560d1a9f3083 248 } CAN_TxMailBox_TypeDef;
mbed_official 423:560d1a9f3083 249
mbed_official 423:560d1a9f3083 250 /**
mbed_official 423:560d1a9f3083 251 * @brief Controller Area Network FIFOMailBox
mbed_official 423:560d1a9f3083 252 */
mbed_official 423:560d1a9f3083 253 typedef struct
mbed_official 423:560d1a9f3083 254 {
mbed_official 423:560d1a9f3083 255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 423:560d1a9f3083 256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 423:560d1a9f3083 257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 423:560d1a9f3083 258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 423:560d1a9f3083 259 } CAN_FIFOMailBox_TypeDef;
mbed_official 423:560d1a9f3083 260
mbed_official 423:560d1a9f3083 261 /**
mbed_official 423:560d1a9f3083 262 * @brief Controller Area Network FilterRegister
mbed_official 423:560d1a9f3083 263 */
mbed_official 423:560d1a9f3083 264 typedef struct
mbed_official 423:560d1a9f3083 265 {
mbed_official 423:560d1a9f3083 266 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 423:560d1a9f3083 267 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 423:560d1a9f3083 268 } CAN_FilterRegister_TypeDef;
mbed_official 423:560d1a9f3083 269
mbed_official 423:560d1a9f3083 270 /**
mbed_official 423:560d1a9f3083 271 * @brief Controller Area Network
mbed_official 423:560d1a9f3083 272 */
mbed_official 423:560d1a9f3083 273 typedef struct
mbed_official 423:560d1a9f3083 274 {
mbed_official 423:560d1a9f3083 275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 423:560d1a9f3083 284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 423:560d1a9f3083 285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 423:560d1a9f3083 286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 423:560d1a9f3083 287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 423:560d1a9f3083 288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 423:560d1a9f3083 289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 423:560d1a9f3083 290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 423:560d1a9f3083 291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 423:560d1a9f3083 292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 423:560d1a9f3083 293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 423:560d1a9f3083 294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 423:560d1a9f3083 295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 423:560d1a9f3083 296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 423:560d1a9f3083 297 } CAN_TypeDef;
mbed_official 423:560d1a9f3083 298
mbed_official 423:560d1a9f3083 299 /**
mbed_official 423:560d1a9f3083 300 * @brief Analog Comparators
mbed_official 423:560d1a9f3083 301 */
mbed_official 423:560d1a9f3083 302
mbed_official 423:560d1a9f3083 303 typedef struct
mbed_official 423:560d1a9f3083 304 {
mbed_official 423:560d1a9f3083 305 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 306 } COMP_TypeDef;
mbed_official 423:560d1a9f3083 307
mbed_official 423:560d1a9f3083 308 /**
mbed_official 423:560d1a9f3083 309 * @brief CRC calculation unit
mbed_official 423:560d1a9f3083 310 */
mbed_official 423:560d1a9f3083 311
mbed_official 423:560d1a9f3083 312 typedef struct
mbed_official 423:560d1a9f3083 313 {
mbed_official 423:560d1a9f3083 314 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 315 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 316 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 423:560d1a9f3083 317 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 423:560d1a9f3083 318 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 319 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 423:560d1a9f3083 320 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 321 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 322 } CRC_TypeDef;
mbed_official 423:560d1a9f3083 323
mbed_official 423:560d1a9f3083 324 /**
mbed_official 423:560d1a9f3083 325 * @brief Digital to Analog Converter
mbed_official 423:560d1a9f3083 326 */
mbed_official 423:560d1a9f3083 327
mbed_official 423:560d1a9f3083 328 typedef struct
mbed_official 423:560d1a9f3083 329 {
mbed_official 423:560d1a9f3083 330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 423:560d1a9f3083 344 } DAC_TypeDef;
mbed_official 423:560d1a9f3083 345
mbed_official 423:560d1a9f3083 346 /**
mbed_official 423:560d1a9f3083 347 * @brief Debug MCU
mbed_official 423:560d1a9f3083 348 */
mbed_official 423:560d1a9f3083 349
mbed_official 423:560d1a9f3083 350 typedef struct
mbed_official 423:560d1a9f3083 351 {
mbed_official 423:560d1a9f3083 352 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 353 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 354 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 355 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 356 }DBGMCU_TypeDef;
mbed_official 423:560d1a9f3083 357
mbed_official 423:560d1a9f3083 358 /**
mbed_official 423:560d1a9f3083 359 * @brief DMA Controller
mbed_official 423:560d1a9f3083 360 */
mbed_official 423:560d1a9f3083 361
mbed_official 423:560d1a9f3083 362 typedef struct
mbed_official 423:560d1a9f3083 363 {
mbed_official 423:560d1a9f3083 364 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 423:560d1a9f3083 365 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 423:560d1a9f3083 366 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 423:560d1a9f3083 367 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 423:560d1a9f3083 368 } DMA_Channel_TypeDef;
mbed_official 423:560d1a9f3083 369
mbed_official 423:560d1a9f3083 370 typedef struct
mbed_official 423:560d1a9f3083 371 {
mbed_official 423:560d1a9f3083 372 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 373 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 374 } DMA_TypeDef;
mbed_official 423:560d1a9f3083 375
mbed_official 423:560d1a9f3083 376 /**
mbed_official 423:560d1a9f3083 377 * @brief External Interrupt/Event Controller
mbed_official 423:560d1a9f3083 378 */
mbed_official 423:560d1a9f3083 379
mbed_official 423:560d1a9f3083 380 typedef struct
mbed_official 423:560d1a9f3083 381 {
mbed_official 423:560d1a9f3083 382 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 383 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 384 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 385 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 386 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 387 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 388 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 423:560d1a9f3083 389 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 423:560d1a9f3083 390 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 391 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 392 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 393 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 394 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 395 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
mbed_official 423:560d1a9f3083 396 }EXTI_TypeDef;
mbed_official 423:560d1a9f3083 397
mbed_official 423:560d1a9f3083 398 /**
mbed_official 423:560d1a9f3083 399 * @brief FLASH Registers
mbed_official 423:560d1a9f3083 400 */
mbed_official 423:560d1a9f3083 401
mbed_official 423:560d1a9f3083 402 typedef struct
mbed_official 423:560d1a9f3083 403 {
mbed_official 423:560d1a9f3083 404 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 405 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 406 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 407 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 408 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 409 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 410 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 423:560d1a9f3083 411 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 412 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 413
mbed_official 423:560d1a9f3083 414 } FLASH_TypeDef;
mbed_official 423:560d1a9f3083 415
mbed_official 423:560d1a9f3083 416 /**
mbed_official 423:560d1a9f3083 417 * @brief Flexible Memory Controller
mbed_official 423:560d1a9f3083 418 */
mbed_official 423:560d1a9f3083 419
mbed_official 423:560d1a9f3083 420 typedef struct
mbed_official 423:560d1a9f3083 421 {
mbed_official 423:560d1a9f3083 422 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 423:560d1a9f3083 423 } FMC_Bank1_TypeDef;
mbed_official 423:560d1a9f3083 424
mbed_official 423:560d1a9f3083 425 /**
mbed_official 423:560d1a9f3083 426 * @brief Flexible Memory Controller Bank1E
mbed_official 423:560d1a9f3083 427 */
mbed_official 423:560d1a9f3083 428
mbed_official 423:560d1a9f3083 429 typedef struct
mbed_official 423:560d1a9f3083 430 {
mbed_official 423:560d1a9f3083 431 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 423:560d1a9f3083 432 } FMC_Bank1E_TypeDef;
mbed_official 423:560d1a9f3083 433
mbed_official 423:560d1a9f3083 434 /**
mbed_official 423:560d1a9f3083 435 * @brief Flexible Memory Controller Bank2
mbed_official 423:560d1a9f3083 436 */
mbed_official 423:560d1a9f3083 437
mbed_official 423:560d1a9f3083 438 typedef struct
mbed_official 423:560d1a9f3083 439 {
mbed_official 423:560d1a9f3083 440 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
mbed_official 423:560d1a9f3083 441 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
mbed_official 423:560d1a9f3083 442 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
mbed_official 423:560d1a9f3083 443 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
mbed_official 423:560d1a9f3083 444 uint32_t RESERVED0; /*!< Reserved, 0x70 */
mbed_official 423:560d1a9f3083 445 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
mbed_official 423:560d1a9f3083 446 uint32_t RESERVED1; /*!< Reserved, 0x78 */
mbed_official 423:560d1a9f3083 447 uint32_t RESERVED2; /*!< Reserved, 0x7C */
mbed_official 423:560d1a9f3083 448 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
mbed_official 423:560d1a9f3083 449 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
mbed_official 423:560d1a9f3083 450 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
mbed_official 423:560d1a9f3083 451 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
mbed_official 423:560d1a9f3083 452 uint32_t RESERVED3; /*!< Reserved, 0x90 */
mbed_official 423:560d1a9f3083 453 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
mbed_official 423:560d1a9f3083 454 } FMC_Bank2_3_TypeDef;
mbed_official 423:560d1a9f3083 455
mbed_official 423:560d1a9f3083 456 /**
mbed_official 423:560d1a9f3083 457 * @brief Flexible Memory Controller Bank4
mbed_official 423:560d1a9f3083 458 */
mbed_official 423:560d1a9f3083 459
mbed_official 423:560d1a9f3083 460 typedef struct
mbed_official 423:560d1a9f3083 461 {
mbed_official 423:560d1a9f3083 462 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
mbed_official 423:560d1a9f3083 463 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
mbed_official 423:560d1a9f3083 464 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
mbed_official 423:560d1a9f3083 465 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
mbed_official 423:560d1a9f3083 466 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
mbed_official 423:560d1a9f3083 467 } FMC_Bank4_TypeDef;
mbed_official 423:560d1a9f3083 468
mbed_official 423:560d1a9f3083 469 /**
mbed_official 423:560d1a9f3083 470 * @brief Option Bytes Registers
mbed_official 423:560d1a9f3083 471 */
mbed_official 423:560d1a9f3083 472 typedef struct
mbed_official 423:560d1a9f3083 473 {
mbed_official 423:560d1a9f3083 474 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 475 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
mbed_official 423:560d1a9f3083 476 uint16_t RESERVED0; /*!< Reserved, 0x04 */
mbed_official 423:560d1a9f3083 477 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 423:560d1a9f3083 478 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 479 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 480 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 481 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
mbed_official 423:560d1a9f3083 482 } OB_TypeDef;
mbed_official 423:560d1a9f3083 483
mbed_official 423:560d1a9f3083 484 /**
mbed_official 423:560d1a9f3083 485 * @brief General Purpose I/O
mbed_official 423:560d1a9f3083 486 */
mbed_official 423:560d1a9f3083 487
mbed_official 423:560d1a9f3083 488 typedef struct
mbed_official 423:560d1a9f3083 489 {
mbed_official 423:560d1a9f3083 490 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 491 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 492 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 493 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 494 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 495 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 496 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 497 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
mbed_official 423:560d1a9f3083 498 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 499 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 423:560d1a9f3083 500 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 501 }GPIO_TypeDef;
mbed_official 423:560d1a9f3083 502
mbed_official 423:560d1a9f3083 503 /**
mbed_official 423:560d1a9f3083 504 * @brief Operational Amplifier (OPAMP)
mbed_official 423:560d1a9f3083 505 */
mbed_official 423:560d1a9f3083 506
mbed_official 423:560d1a9f3083 507 typedef struct
mbed_official 423:560d1a9f3083 508 {
mbed_official 423:560d1a9f3083 509 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 510 } OPAMP_TypeDef;
mbed_official 423:560d1a9f3083 511
mbed_official 423:560d1a9f3083 512 /**
mbed_official 423:560d1a9f3083 513 * @brief System configuration controller
mbed_official 423:560d1a9f3083 514 */
mbed_official 423:560d1a9f3083 515
mbed_official 423:560d1a9f3083 516 typedef struct
mbed_official 423:560d1a9f3083 517 {
mbed_official 423:560d1a9f3083 518 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 519 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 520 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
mbed_official 423:560d1a9f3083 521 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 522 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 423:560d1a9f3083 523 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
mbed_official 423:560d1a9f3083 524 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
mbed_official 423:560d1a9f3083 525 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
mbed_official 423:560d1a9f3083 526 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
mbed_official 423:560d1a9f3083 527 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
mbed_official 423:560d1a9f3083 528 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
mbed_official 423:560d1a9f3083 529 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
mbed_official 423:560d1a9f3083 530 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
mbed_official 423:560d1a9f3083 531 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
mbed_official 423:560d1a9f3083 532 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
mbed_official 423:560d1a9f3083 533 __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
mbed_official 423:560d1a9f3083 534 __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
mbed_official 423:560d1a9f3083 535 __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
mbed_official 423:560d1a9f3083 536 } SYSCFG_TypeDef;
mbed_official 423:560d1a9f3083 537
mbed_official 423:560d1a9f3083 538 /**
mbed_official 423:560d1a9f3083 539 * @brief Inter-integrated Circuit Interface
mbed_official 423:560d1a9f3083 540 */
mbed_official 423:560d1a9f3083 541
mbed_official 423:560d1a9f3083 542 typedef struct
mbed_official 423:560d1a9f3083 543 {
mbed_official 423:560d1a9f3083 544 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 545 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 546 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 547 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 548 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 549 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 550 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 551 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 552 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 553 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 554 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 555 }I2C_TypeDef;
mbed_official 423:560d1a9f3083 556
mbed_official 423:560d1a9f3083 557 /**
mbed_official 423:560d1a9f3083 558 * @brief Independent WATCHDOG
mbed_official 423:560d1a9f3083 559 */
mbed_official 423:560d1a9f3083 560
mbed_official 423:560d1a9f3083 561 typedef struct
mbed_official 423:560d1a9f3083 562 {
mbed_official 423:560d1a9f3083 563 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 564 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 565 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 566 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 567 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 568 } IWDG_TypeDef;
mbed_official 423:560d1a9f3083 569
mbed_official 423:560d1a9f3083 570 /**
mbed_official 423:560d1a9f3083 571 * @brief Power Control
mbed_official 423:560d1a9f3083 572 */
mbed_official 423:560d1a9f3083 573
mbed_official 423:560d1a9f3083 574 typedef struct
mbed_official 423:560d1a9f3083 575 {
mbed_official 423:560d1a9f3083 576 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 577 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 578 } PWR_TypeDef;
mbed_official 423:560d1a9f3083 579
mbed_official 423:560d1a9f3083 580 /**
mbed_official 423:560d1a9f3083 581 * @brief Reset and Clock Control
mbed_official 423:560d1a9f3083 582 */
mbed_official 423:560d1a9f3083 583 typedef struct
mbed_official 423:560d1a9f3083 584 {
mbed_official 423:560d1a9f3083 585 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 586 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 587 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 588 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 589 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 590 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 591 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 592 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 593 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 594 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 595 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 596 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 597 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 598 } RCC_TypeDef;
mbed_official 423:560d1a9f3083 599
mbed_official 423:560d1a9f3083 600 /**
mbed_official 423:560d1a9f3083 601 * @brief Real-Time Clock
mbed_official 423:560d1a9f3083 602 */
mbed_official 423:560d1a9f3083 603
mbed_official 423:560d1a9f3083 604 typedef struct
mbed_official 423:560d1a9f3083 605 {
mbed_official 423:560d1a9f3083 606 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 607 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 608 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 609 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 610 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 611 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 612 uint32_t RESERVED0; /*!< Reserved, 0x18 */
mbed_official 423:560d1a9f3083 613 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 614 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 615 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 616 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 617 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 618 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 619 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 423:560d1a9f3083 620 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 423:560d1a9f3083 621 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 423:560d1a9f3083 622 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 423:560d1a9f3083 623 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 423:560d1a9f3083 624 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 423:560d1a9f3083 625 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 423:560d1a9f3083 626 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 423:560d1a9f3083 627 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 423:560d1a9f3083 628 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 423:560d1a9f3083 629 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 423:560d1a9f3083 630 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 423:560d1a9f3083 631 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 423:560d1a9f3083 632 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 423:560d1a9f3083 633 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 423:560d1a9f3083 634 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 423:560d1a9f3083 635 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 423:560d1a9f3083 636 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 423:560d1a9f3083 637 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 423:560d1a9f3083 638 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 423:560d1a9f3083 639 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 423:560d1a9f3083 640 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 423:560d1a9f3083 641 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 423:560d1a9f3083 642 } RTC_TypeDef;
mbed_official 423:560d1a9f3083 643
mbed_official 423:560d1a9f3083 644
mbed_official 423:560d1a9f3083 645 /**
mbed_official 423:560d1a9f3083 646 * @brief Serial Peripheral Interface
mbed_official 423:560d1a9f3083 647 */
mbed_official 423:560d1a9f3083 648
mbed_official 423:560d1a9f3083 649 typedef struct
mbed_official 423:560d1a9f3083 650 {
mbed_official 423:560d1a9f3083 651 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 423:560d1a9f3083 652 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 653 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 654 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 655 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 423:560d1a9f3083 656 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 423:560d1a9f3083 657 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 423:560d1a9f3083 658 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 659 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 660 } SPI_TypeDef;
mbed_official 423:560d1a9f3083 661
mbed_official 423:560d1a9f3083 662 /**
mbed_official 423:560d1a9f3083 663 * @brief TIM
mbed_official 423:560d1a9f3083 664 */
mbed_official 423:560d1a9f3083 665 typedef struct
mbed_official 423:560d1a9f3083 666 {
mbed_official 423:560d1a9f3083 667 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 668 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 669 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 670 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 671 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 672 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 673 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 674 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 675 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 676 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 677 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 678 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 679 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 680 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 423:560d1a9f3083 681 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 423:560d1a9f3083 682 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 423:560d1a9f3083 683 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 423:560d1a9f3083 684 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 423:560d1a9f3083 685 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 423:560d1a9f3083 686 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 423:560d1a9f3083 687 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 423:560d1a9f3083 688 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 423:560d1a9f3083 689 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
mbed_official 423:560d1a9f3083 690 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
mbed_official 423:560d1a9f3083 691 } TIM_TypeDef;
mbed_official 423:560d1a9f3083 692
mbed_official 423:560d1a9f3083 693 /**
mbed_official 423:560d1a9f3083 694 * @brief Touch Sensing Controller (TSC)
mbed_official 423:560d1a9f3083 695 */
mbed_official 423:560d1a9f3083 696 typedef struct
mbed_official 423:560d1a9f3083 697 {
mbed_official 423:560d1a9f3083 698 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 699 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 700 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 701 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 702 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 703 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 704 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 705 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 706 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 707 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 708 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 709 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 423:560d1a9f3083 710 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 423:560d1a9f3083 711 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 423:560d1a9f3083 712 } TSC_TypeDef;
mbed_official 423:560d1a9f3083 713
mbed_official 423:560d1a9f3083 714 /**
mbed_official 423:560d1a9f3083 715 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 423:560d1a9f3083 716 */
mbed_official 423:560d1a9f3083 717
mbed_official 423:560d1a9f3083 718 typedef struct
mbed_official 423:560d1a9f3083 719 {
mbed_official 423:560d1a9f3083 720 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 721 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 722 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 723 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 724 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 725 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 726 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 727 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 728 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 423:560d1a9f3083 729 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 423:560d1a9f3083 730 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 423:560d1a9f3083 731 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 423:560d1a9f3083 732 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 423:560d1a9f3083 733 } USART_TypeDef;
mbed_official 423:560d1a9f3083 734
mbed_official 423:560d1a9f3083 735 /**
mbed_official 423:560d1a9f3083 736 * @brief Universal Serial Bus Full Speed Device
mbed_official 423:560d1a9f3083 737 */
mbed_official 423:560d1a9f3083 738
mbed_official 423:560d1a9f3083 739 typedef struct
mbed_official 423:560d1a9f3083 740 {
mbed_official 423:560d1a9f3083 741 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 742 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 423:560d1a9f3083 743 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 744 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 423:560d1a9f3083 745 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 746 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 423:560d1a9f3083 747 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 423:560d1a9f3083 748 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 423:560d1a9f3083 749 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 423:560d1a9f3083 750 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 423:560d1a9f3083 751 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 423:560d1a9f3083 752 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 423:560d1a9f3083 753 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 423:560d1a9f3083 754 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 423:560d1a9f3083 755 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 423:560d1a9f3083 756 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 423:560d1a9f3083 757 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 423:560d1a9f3083 758 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 423:560d1a9f3083 759 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 423:560d1a9f3083 760 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 423:560d1a9f3083 761 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 423:560d1a9f3083 762 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 423:560d1a9f3083 763 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 423:560d1a9f3083 764 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 423:560d1a9f3083 765 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 423:560d1a9f3083 766 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 423:560d1a9f3083 767 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
mbed_official 423:560d1a9f3083 768 __IO uint16_t RESERVEDD; /*!< Reserved */
mbed_official 423:560d1a9f3083 769 } USB_TypeDef;
mbed_official 423:560d1a9f3083 770
mbed_official 423:560d1a9f3083 771 /**
mbed_official 423:560d1a9f3083 772 * @brief Window WATCHDOG
mbed_official 423:560d1a9f3083 773 */
mbed_official 423:560d1a9f3083 774 typedef struct
mbed_official 423:560d1a9f3083 775 {
mbed_official 423:560d1a9f3083 776 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 423:560d1a9f3083 777 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 423:560d1a9f3083 778 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 423:560d1a9f3083 779 } WWDG_TypeDef;
mbed_official 423:560d1a9f3083 780
mbed_official 423:560d1a9f3083 781 /** @addtogroup Peripheral_memory_map
mbed_official 423:560d1a9f3083 782 * @{
mbed_official 423:560d1a9f3083 783 */
mbed_official 423:560d1a9f3083 784
mbed_official 423:560d1a9f3083 785 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(512KB) base address in the alias region */
mbed_official 423:560d1a9f3083 786 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the alias region */
mbed_official 423:560d1a9f3083 787 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(64KB) base address in the alias region */
mbed_official 423:560d1a9f3083 788 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 423:560d1a9f3083 789 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
mbed_official 423:560d1a9f3083 790
mbed_official 423:560d1a9f3083 791 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the bit-band region */
mbed_official 423:560d1a9f3083 792 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(64KB) base address in the bit-band region */
mbed_official 423:560d1a9f3083 793 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 423:560d1a9f3083 794
mbed_official 423:560d1a9f3083 795
mbed_official 423:560d1a9f3083 796 /*!< Peripheral memory map */
mbed_official 423:560d1a9f3083 797 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 423:560d1a9f3083 798 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 423:560d1a9f3083 799 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 423:560d1a9f3083 800 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 423:560d1a9f3083 801 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 423:560d1a9f3083 802
mbed_official 423:560d1a9f3083 803 /*!< APB1 peripherals */
mbed_official 423:560d1a9f3083 804 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 423:560d1a9f3083 805 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 423:560d1a9f3083 806 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
mbed_official 423:560d1a9f3083 807 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 423:560d1a9f3083 808 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 423:560d1a9f3083 809 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 423:560d1a9f3083 810 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 423:560d1a9f3083 811 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 423:560d1a9f3083 812 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
mbed_official 423:560d1a9f3083 813 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
mbed_official 423:560d1a9f3083 814 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
mbed_official 423:560d1a9f3083 815 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
mbed_official 423:560d1a9f3083 816 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 423:560d1a9f3083 817 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 423:560d1a9f3083 818 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
mbed_official 423:560d1a9f3083 819 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
mbed_official 423:560d1a9f3083 820 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 423:560d1a9f3083 821 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
mbed_official 423:560d1a9f3083 822 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 423:560d1a9f3083 823 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 423:560d1a9f3083 824 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
mbed_official 423:560d1a9f3083 825 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 423:560d1a9f3083 826 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 423:560d1a9f3083 827 #define DAC_BASE DAC1_BASE
mbed_official 423:560d1a9f3083 828 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
mbed_official 423:560d1a9f3083 829
mbed_official 423:560d1a9f3083 830 /*!< APB2 peripherals */
mbed_official 423:560d1a9f3083 831 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 423:560d1a9f3083 832 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
mbed_official 423:560d1a9f3083 833 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
mbed_official 423:560d1a9f3083 834 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
mbed_official 423:560d1a9f3083 835 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
mbed_official 423:560d1a9f3083 836 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
mbed_official 423:560d1a9f3083 837 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
mbed_official 423:560d1a9f3083 838 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
mbed_official 423:560d1a9f3083 839 #define COMP_BASE COMP1_BASE
mbed_official 423:560d1a9f3083 840 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
mbed_official 423:560d1a9f3083 841 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
mbed_official 423:560d1a9f3083 842 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
mbed_official 423:560d1a9f3083 843 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
mbed_official 423:560d1a9f3083 844 #define OPAMP_BASE OPAMP1_BASE
mbed_official 423:560d1a9f3083 845 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 423:560d1a9f3083 846 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
mbed_official 423:560d1a9f3083 847 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 423:560d1a9f3083 848 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
mbed_official 423:560d1a9f3083 849 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 423:560d1a9f3083 850 #define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
mbed_official 423:560d1a9f3083 851 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
mbed_official 423:560d1a9f3083 852 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
mbed_official 423:560d1a9f3083 853 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
mbed_official 423:560d1a9f3083 854 #define TIM20_BASE (APB2PERIPH_BASE + 0x00005000)
mbed_official 423:560d1a9f3083 855
mbed_official 423:560d1a9f3083 856 /*!< AHB1 peripherals */
mbed_official 423:560d1a9f3083 857 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
mbed_official 423:560d1a9f3083 858 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
mbed_official 423:560d1a9f3083 859 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
mbed_official 423:560d1a9f3083 860 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
mbed_official 423:560d1a9f3083 861 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
mbed_official 423:560d1a9f3083 862 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
mbed_official 423:560d1a9f3083 863 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
mbed_official 423:560d1a9f3083 864 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
mbed_official 423:560d1a9f3083 865 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
mbed_official 423:560d1a9f3083 866 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
mbed_official 423:560d1a9f3083 867 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
mbed_official 423:560d1a9f3083 868 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
mbed_official 423:560d1a9f3083 869 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
mbed_official 423:560d1a9f3083 870 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
mbed_official 423:560d1a9f3083 871 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
mbed_official 423:560d1a9f3083 872 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
mbed_official 423:560d1a9f3083 873 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
mbed_official 423:560d1a9f3083 874 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
mbed_official 423:560d1a9f3083 875 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
mbed_official 423:560d1a9f3083 876
mbed_official 423:560d1a9f3083 877 /*!< AHB2 peripherals */
mbed_official 423:560d1a9f3083 878 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 423:560d1a9f3083 879 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 423:560d1a9f3083 880 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 423:560d1a9f3083 881 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 423:560d1a9f3083 882 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 423:560d1a9f3083 883 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 423:560d1a9f3083 884 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
mbed_official 423:560d1a9f3083 885 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
mbed_official 423:560d1a9f3083 886
mbed_official 423:560d1a9f3083 887 /*!< AHB3 peripherals */
mbed_official 423:560d1a9f3083 888 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
mbed_official 423:560d1a9f3083 889 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
mbed_official 423:560d1a9f3083 890 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
mbed_official 423:560d1a9f3083 891 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
mbed_official 423:560d1a9f3083 892 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
mbed_official 423:560d1a9f3083 893 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
mbed_official 423:560d1a9f3083 894
mbed_official 423:560d1a9f3083 895 /*!< FMC Bankx registers base address */
mbed_official 423:560d1a9f3083 896 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
mbed_official 423:560d1a9f3083 897 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
mbed_official 423:560d1a9f3083 898 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
mbed_official 423:560d1a9f3083 899 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
mbed_official 423:560d1a9f3083 900
mbed_official 423:560d1a9f3083 901 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 423:560d1a9f3083 902 /**
mbed_official 423:560d1a9f3083 903 * @}
mbed_official 423:560d1a9f3083 904 */
mbed_official 423:560d1a9f3083 905
mbed_official 423:560d1a9f3083 906 /** @addtogroup Peripheral_declaration
mbed_official 423:560d1a9f3083 907 * @{
mbed_official 423:560d1a9f3083 908 */
mbed_official 423:560d1a9f3083 909 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 423:560d1a9f3083 910 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 423:560d1a9f3083 911 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 423:560d1a9f3083 912 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 423:560d1a9f3083 913 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 423:560d1a9f3083 914 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 423:560d1a9f3083 915 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 423:560d1a9f3083 916 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 423:560d1a9f3083 917 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 423:560d1a9f3083 918 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 423:560d1a9f3083 919 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 423:560d1a9f3083 920 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 423:560d1a9f3083 921 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 423:560d1a9f3083 922 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 423:560d1a9f3083 923 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 423:560d1a9f3083 924 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 423:560d1a9f3083 925 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 423:560d1a9f3083 926 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 423:560d1a9f3083 927 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 423:560d1a9f3083 928 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 423:560d1a9f3083 929 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 423:560d1a9f3083 930 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
mbed_official 423:560d1a9f3083 931 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 423:560d1a9f3083 932 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 423:560d1a9f3083 933 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 423:560d1a9f3083 934 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
mbed_official 423:560d1a9f3083 935 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official 423:560d1a9f3083 936 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
mbed_official 423:560d1a9f3083 937 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
mbed_official 423:560d1a9f3083 938 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
mbed_official 423:560d1a9f3083 939 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
mbed_official 423:560d1a9f3083 940 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
mbed_official 423:560d1a9f3083 941 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 423:560d1a9f3083 942 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
mbed_official 423:560d1a9f3083 943 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
mbed_official 423:560d1a9f3083 944 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
mbed_official 423:560d1a9f3083 945 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
mbed_official 423:560d1a9f3083 946 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 423:560d1a9f3083 947 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 423:560d1a9f3083 948 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 423:560d1a9f3083 949 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 423:560d1a9f3083 950 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 423:560d1a9f3083 951 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 423:560d1a9f3083 952 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 423:560d1a9f3083 953 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 423:560d1a9f3083 954 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 423:560d1a9f3083 955 #define TIM20 ((TIM_TypeDef *) TIM20_BASE)
mbed_official 423:560d1a9f3083 956 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 423:560d1a9f3083 957 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 423:560d1a9f3083 958 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 423:560d1a9f3083 959 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 423:560d1a9f3083 960 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 423:560d1a9f3083 961 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 423:560d1a9f3083 962 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 423:560d1a9f3083 963 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 423:560d1a9f3083 964 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 423:560d1a9f3083 965 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 423:560d1a9f3083 966 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 423:560d1a9f3083 967 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 423:560d1a9f3083 968 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 423:560d1a9f3083 969 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 423:560d1a9f3083 970 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 423:560d1a9f3083 971 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 423:560d1a9f3083 972 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 423:560d1a9f3083 973 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 423:560d1a9f3083 974 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 423:560d1a9f3083 975 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 423:560d1a9f3083 976 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 423:560d1a9f3083 977 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 423:560d1a9f3083 978 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 423:560d1a9f3083 979 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 423:560d1a9f3083 980 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 423:560d1a9f3083 981 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 423:560d1a9f3083 982 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 423:560d1a9f3083 983 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 423:560d1a9f3083 984 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 423:560d1a9f3083 985 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 423:560d1a9f3083 986 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 423:560d1a9f3083 987 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
mbed_official 423:560d1a9f3083 988 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
mbed_official 423:560d1a9f3083 989 #define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
mbed_official 423:560d1a9f3083 990 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 423:560d1a9f3083 991 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
mbed_official 423:560d1a9f3083 992 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
mbed_official 423:560d1a9f3083 993 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
mbed_official 423:560d1a9f3083 994 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
mbed_official 423:560d1a9f3083 995
mbed_official 423:560d1a9f3083 996 /**
mbed_official 423:560d1a9f3083 997 * @}
mbed_official 423:560d1a9f3083 998 */
mbed_official 423:560d1a9f3083 999
mbed_official 423:560d1a9f3083 1000 /** @addtogroup Exported_constants
mbed_official 423:560d1a9f3083 1001 * @{
mbed_official 423:560d1a9f3083 1002 */
mbed_official 423:560d1a9f3083 1003
mbed_official 423:560d1a9f3083 1004 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 423:560d1a9f3083 1005 * @{
mbed_official 423:560d1a9f3083 1006 */
mbed_official 423:560d1a9f3083 1007
mbed_official 423:560d1a9f3083 1008 /******************************************************************************/
mbed_official 423:560d1a9f3083 1009 /* Peripheral Registers_Bits_Definition */
mbed_official 423:560d1a9f3083 1010 /******************************************************************************/
mbed_official 423:560d1a9f3083 1011
mbed_official 423:560d1a9f3083 1012 /******************************************************************************/
mbed_official 423:560d1a9f3083 1013 /* */
mbed_official 423:560d1a9f3083 1014 /* Analog to Digital Converter SAR (ADC) */
mbed_official 423:560d1a9f3083 1015 /* */
mbed_official 423:560d1a9f3083 1016 /******************************************************************************/
mbed_official 423:560d1a9f3083 1017 /******************** Bit definition for ADC_ISR register ********************/
mbed_official 423:560d1a9f3083 1018 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
mbed_official 423:560d1a9f3083 1019 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
mbed_official 423:560d1a9f3083 1020 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
mbed_official 423:560d1a9f3083 1021 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
mbed_official 423:560d1a9f3083 1022 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
mbed_official 423:560d1a9f3083 1023 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
mbed_official 423:560d1a9f3083 1024 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
mbed_official 423:560d1a9f3083 1025 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
mbed_official 423:560d1a9f3083 1026 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
mbed_official 423:560d1a9f3083 1027 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
mbed_official 423:560d1a9f3083 1028 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
mbed_official 423:560d1a9f3083 1029
mbed_official 423:560d1a9f3083 1030 /******************** Bit definition for ADC_IER register ********************/
mbed_official 423:560d1a9f3083 1031 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
mbed_official 423:560d1a9f3083 1032 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
mbed_official 423:560d1a9f3083 1033 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
mbed_official 423:560d1a9f3083 1034 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
mbed_official 423:560d1a9f3083 1035 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
mbed_official 423:560d1a9f3083 1036 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
mbed_official 423:560d1a9f3083 1037 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
mbed_official 423:560d1a9f3083 1038 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
mbed_official 423:560d1a9f3083 1039 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
mbed_official 423:560d1a9f3083 1040 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
mbed_official 423:560d1a9f3083 1041 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
mbed_official 423:560d1a9f3083 1042
mbed_official 423:560d1a9f3083 1043 /******************** Bit definition for ADC_CR register ********************/
mbed_official 423:560d1a9f3083 1044 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
mbed_official 423:560d1a9f3083 1045 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
mbed_official 423:560d1a9f3083 1046 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
mbed_official 423:560d1a9f3083 1047 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
mbed_official 423:560d1a9f3083 1048 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
mbed_official 423:560d1a9f3083 1049 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
mbed_official 423:560d1a9f3083 1050 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
mbed_official 423:560d1a9f3083 1051 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
mbed_official 423:560d1a9f3083 1052 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
mbed_official 423:560d1a9f3083 1053 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
mbed_official 423:560d1a9f3083 1054 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
mbed_official 423:560d1a9f3083 1055
mbed_official 423:560d1a9f3083 1056 /******************** Bit definition for ADC_CFGR register ********************/
mbed_official 423:560d1a9f3083 1057 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
mbed_official 423:560d1a9f3083 1058 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
mbed_official 423:560d1a9f3083 1059
mbed_official 423:560d1a9f3083 1060 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
mbed_official 423:560d1a9f3083 1061 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
mbed_official 423:560d1a9f3083 1062 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
mbed_official 423:560d1a9f3083 1063
mbed_official 423:560d1a9f3083 1064 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
mbed_official 423:560d1a9f3083 1065
mbed_official 423:560d1a9f3083 1066 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
mbed_official 423:560d1a9f3083 1067 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
mbed_official 423:560d1a9f3083 1068 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
mbed_official 423:560d1a9f3083 1069 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
mbed_official 423:560d1a9f3083 1070 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
mbed_official 423:560d1a9f3083 1071
mbed_official 423:560d1a9f3083 1072 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
mbed_official 423:560d1a9f3083 1073 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
mbed_official 423:560d1a9f3083 1074 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
mbed_official 423:560d1a9f3083 1075
mbed_official 423:560d1a9f3083 1076 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
mbed_official 423:560d1a9f3083 1077 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
mbed_official 423:560d1a9f3083 1078 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
mbed_official 423:560d1a9f3083 1079 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
mbed_official 423:560d1a9f3083 1080 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
mbed_official 423:560d1a9f3083 1081
mbed_official 423:560d1a9f3083 1082 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
mbed_official 423:560d1a9f3083 1083 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
mbed_official 423:560d1a9f3083 1084 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
mbed_official 423:560d1a9f3083 1085 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
mbed_official 423:560d1a9f3083 1086
mbed_official 423:560d1a9f3083 1087 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
mbed_official 423:560d1a9f3083 1088 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
mbed_official 423:560d1a9f3083 1089 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
mbed_official 423:560d1a9f3083 1090 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
mbed_official 423:560d1a9f3083 1091 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
mbed_official 423:560d1a9f3083 1092 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
mbed_official 423:560d1a9f3083 1093
mbed_official 423:560d1a9f3083 1094 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
mbed_official 423:560d1a9f3083 1095 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
mbed_official 423:560d1a9f3083 1096 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
mbed_official 423:560d1a9f3083 1097 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
mbed_official 423:560d1a9f3083 1098 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
mbed_official 423:560d1a9f3083 1099 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
mbed_official 423:560d1a9f3083 1100
mbed_official 423:560d1a9f3083 1101 /******************** Bit definition for ADC_SMPR1 register ********************/
mbed_official 423:560d1a9f3083 1102 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
mbed_official 423:560d1a9f3083 1103 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
mbed_official 423:560d1a9f3083 1104 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
mbed_official 423:560d1a9f3083 1105 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
mbed_official 423:560d1a9f3083 1106
mbed_official 423:560d1a9f3083 1107 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
mbed_official 423:560d1a9f3083 1108 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
mbed_official 423:560d1a9f3083 1109 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
mbed_official 423:560d1a9f3083 1110 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
mbed_official 423:560d1a9f3083 1111
mbed_official 423:560d1a9f3083 1112 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
mbed_official 423:560d1a9f3083 1113 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
mbed_official 423:560d1a9f3083 1114 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
mbed_official 423:560d1a9f3083 1115 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
mbed_official 423:560d1a9f3083 1116
mbed_official 423:560d1a9f3083 1117 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
mbed_official 423:560d1a9f3083 1118 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
mbed_official 423:560d1a9f3083 1119 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
mbed_official 423:560d1a9f3083 1120 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
mbed_official 423:560d1a9f3083 1121
mbed_official 423:560d1a9f3083 1122 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
mbed_official 423:560d1a9f3083 1123 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
mbed_official 423:560d1a9f3083 1124 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
mbed_official 423:560d1a9f3083 1125 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
mbed_official 423:560d1a9f3083 1126
mbed_official 423:560d1a9f3083 1127 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
mbed_official 423:560d1a9f3083 1128 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
mbed_official 423:560d1a9f3083 1129 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
mbed_official 423:560d1a9f3083 1130 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
mbed_official 423:560d1a9f3083 1131
mbed_official 423:560d1a9f3083 1132 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
mbed_official 423:560d1a9f3083 1133 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
mbed_official 423:560d1a9f3083 1134 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
mbed_official 423:560d1a9f3083 1135 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
mbed_official 423:560d1a9f3083 1136
mbed_official 423:560d1a9f3083 1137 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
mbed_official 423:560d1a9f3083 1138 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
mbed_official 423:560d1a9f3083 1139 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
mbed_official 423:560d1a9f3083 1140 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
mbed_official 423:560d1a9f3083 1141
mbed_official 423:560d1a9f3083 1142 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
mbed_official 423:560d1a9f3083 1143 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
mbed_official 423:560d1a9f3083 1144 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
mbed_official 423:560d1a9f3083 1145 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
mbed_official 423:560d1a9f3083 1146
mbed_official 423:560d1a9f3083 1147 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
mbed_official 423:560d1a9f3083 1148 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
mbed_official 423:560d1a9f3083 1149 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
mbed_official 423:560d1a9f3083 1150 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
mbed_official 423:560d1a9f3083 1151
mbed_official 423:560d1a9f3083 1152 /******************** Bit definition for ADC_SMPR2 register ********************/
mbed_official 423:560d1a9f3083 1153 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
mbed_official 423:560d1a9f3083 1154 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
mbed_official 423:560d1a9f3083 1155 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
mbed_official 423:560d1a9f3083 1156 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
mbed_official 423:560d1a9f3083 1157
mbed_official 423:560d1a9f3083 1158 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
mbed_official 423:560d1a9f3083 1159 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
mbed_official 423:560d1a9f3083 1160 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
mbed_official 423:560d1a9f3083 1161 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
mbed_official 423:560d1a9f3083 1162
mbed_official 423:560d1a9f3083 1163 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
mbed_official 423:560d1a9f3083 1164 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
mbed_official 423:560d1a9f3083 1165 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
mbed_official 423:560d1a9f3083 1166 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
mbed_official 423:560d1a9f3083 1167
mbed_official 423:560d1a9f3083 1168 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
mbed_official 423:560d1a9f3083 1169 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
mbed_official 423:560d1a9f3083 1170 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
mbed_official 423:560d1a9f3083 1171 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
mbed_official 423:560d1a9f3083 1172
mbed_official 423:560d1a9f3083 1173 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
mbed_official 423:560d1a9f3083 1174 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
mbed_official 423:560d1a9f3083 1175 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
mbed_official 423:560d1a9f3083 1176 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
mbed_official 423:560d1a9f3083 1177
mbed_official 423:560d1a9f3083 1178 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
mbed_official 423:560d1a9f3083 1179 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
mbed_official 423:560d1a9f3083 1180 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
mbed_official 423:560d1a9f3083 1181 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
mbed_official 423:560d1a9f3083 1182
mbed_official 423:560d1a9f3083 1183 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
mbed_official 423:560d1a9f3083 1184 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
mbed_official 423:560d1a9f3083 1185 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
mbed_official 423:560d1a9f3083 1186 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
mbed_official 423:560d1a9f3083 1187
mbed_official 423:560d1a9f3083 1188 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
mbed_official 423:560d1a9f3083 1189 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
mbed_official 423:560d1a9f3083 1190 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
mbed_official 423:560d1a9f3083 1191 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
mbed_official 423:560d1a9f3083 1192
mbed_official 423:560d1a9f3083 1193 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
mbed_official 423:560d1a9f3083 1194 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
mbed_official 423:560d1a9f3083 1195 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
mbed_official 423:560d1a9f3083 1196 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
mbed_official 423:560d1a9f3083 1197
mbed_official 423:560d1a9f3083 1198 /******************** Bit definition for ADC_TR1 register ********************/
mbed_official 423:560d1a9f3083 1199 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
mbed_official 423:560d1a9f3083 1200 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
mbed_official 423:560d1a9f3083 1201 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
mbed_official 423:560d1a9f3083 1202 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
mbed_official 423:560d1a9f3083 1203 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
mbed_official 423:560d1a9f3083 1204 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
mbed_official 423:560d1a9f3083 1205 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
mbed_official 423:560d1a9f3083 1206 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
mbed_official 423:560d1a9f3083 1207 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
mbed_official 423:560d1a9f3083 1208 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
mbed_official 423:560d1a9f3083 1209 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
mbed_official 423:560d1a9f3083 1210 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
mbed_official 423:560d1a9f3083 1211 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
mbed_official 423:560d1a9f3083 1212
mbed_official 423:560d1a9f3083 1213 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
mbed_official 423:560d1a9f3083 1214 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
mbed_official 423:560d1a9f3083 1215 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
mbed_official 423:560d1a9f3083 1216 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
mbed_official 423:560d1a9f3083 1217 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
mbed_official 423:560d1a9f3083 1218 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
mbed_official 423:560d1a9f3083 1219 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
mbed_official 423:560d1a9f3083 1220 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
mbed_official 423:560d1a9f3083 1221 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
mbed_official 423:560d1a9f3083 1222 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
mbed_official 423:560d1a9f3083 1223 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
mbed_official 423:560d1a9f3083 1224 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
mbed_official 423:560d1a9f3083 1225 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
mbed_official 423:560d1a9f3083 1226
mbed_official 423:560d1a9f3083 1227 /******************** Bit definition for ADC_TR2 register ********************/
mbed_official 423:560d1a9f3083 1228 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
mbed_official 423:560d1a9f3083 1229 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
mbed_official 423:560d1a9f3083 1230 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
mbed_official 423:560d1a9f3083 1231 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
mbed_official 423:560d1a9f3083 1232 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
mbed_official 423:560d1a9f3083 1233 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
mbed_official 423:560d1a9f3083 1234 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
mbed_official 423:560d1a9f3083 1235 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
mbed_official 423:560d1a9f3083 1236 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
mbed_official 423:560d1a9f3083 1237
mbed_official 423:560d1a9f3083 1238 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
mbed_official 423:560d1a9f3083 1239 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
mbed_official 423:560d1a9f3083 1240 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
mbed_official 423:560d1a9f3083 1241 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
mbed_official 423:560d1a9f3083 1242 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
mbed_official 423:560d1a9f3083 1243 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
mbed_official 423:560d1a9f3083 1244 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
mbed_official 423:560d1a9f3083 1245 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
mbed_official 423:560d1a9f3083 1246 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
mbed_official 423:560d1a9f3083 1247
mbed_official 423:560d1a9f3083 1248 /******************** Bit definition for ADC_TR3 register ********************/
mbed_official 423:560d1a9f3083 1249 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
mbed_official 423:560d1a9f3083 1250 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
mbed_official 423:560d1a9f3083 1251 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
mbed_official 423:560d1a9f3083 1252 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
mbed_official 423:560d1a9f3083 1253 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
mbed_official 423:560d1a9f3083 1254 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
mbed_official 423:560d1a9f3083 1255 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
mbed_official 423:560d1a9f3083 1256 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
mbed_official 423:560d1a9f3083 1257 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
mbed_official 423:560d1a9f3083 1258
mbed_official 423:560d1a9f3083 1259 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
mbed_official 423:560d1a9f3083 1260 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
mbed_official 423:560d1a9f3083 1261 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
mbed_official 423:560d1a9f3083 1262 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
mbed_official 423:560d1a9f3083 1263 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
mbed_official 423:560d1a9f3083 1264 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
mbed_official 423:560d1a9f3083 1265 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
mbed_official 423:560d1a9f3083 1266 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
mbed_official 423:560d1a9f3083 1267 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
mbed_official 423:560d1a9f3083 1268
mbed_official 423:560d1a9f3083 1269 /******************** Bit definition for ADC_SQR1 register ********************/
mbed_official 423:560d1a9f3083 1270 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
mbed_official 423:560d1a9f3083 1271 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
mbed_official 423:560d1a9f3083 1272 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
mbed_official 423:560d1a9f3083 1273 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
mbed_official 423:560d1a9f3083 1274 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
mbed_official 423:560d1a9f3083 1275
mbed_official 423:560d1a9f3083 1276 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
mbed_official 423:560d1a9f3083 1277 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
mbed_official 423:560d1a9f3083 1278 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
mbed_official 423:560d1a9f3083 1279 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
mbed_official 423:560d1a9f3083 1280 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
mbed_official 423:560d1a9f3083 1281 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
mbed_official 423:560d1a9f3083 1282
mbed_official 423:560d1a9f3083 1283 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
mbed_official 423:560d1a9f3083 1284 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
mbed_official 423:560d1a9f3083 1285 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
mbed_official 423:560d1a9f3083 1286 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
mbed_official 423:560d1a9f3083 1287 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
mbed_official 423:560d1a9f3083 1288 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
mbed_official 423:560d1a9f3083 1289
mbed_official 423:560d1a9f3083 1290 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
mbed_official 423:560d1a9f3083 1291 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
mbed_official 423:560d1a9f3083 1292 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
mbed_official 423:560d1a9f3083 1293 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
mbed_official 423:560d1a9f3083 1294 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
mbed_official 423:560d1a9f3083 1295 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
mbed_official 423:560d1a9f3083 1296
mbed_official 423:560d1a9f3083 1297 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1298 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
mbed_official 423:560d1a9f3083 1299 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
mbed_official 423:560d1a9f3083 1300 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
mbed_official 423:560d1a9f3083 1301 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
mbed_official 423:560d1a9f3083 1302 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
mbed_official 423:560d1a9f3083 1303
mbed_official 423:560d1a9f3083 1304 /******************** Bit definition for ADC_SQR2 register ********************/
mbed_official 423:560d1a9f3083 1305 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1306 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
mbed_official 423:560d1a9f3083 1307 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
mbed_official 423:560d1a9f3083 1308 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
mbed_official 423:560d1a9f3083 1309 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
mbed_official 423:560d1a9f3083 1310 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
mbed_official 423:560d1a9f3083 1311
mbed_official 423:560d1a9f3083 1312 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1313 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
mbed_official 423:560d1a9f3083 1314 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
mbed_official 423:560d1a9f3083 1315 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
mbed_official 423:560d1a9f3083 1316 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
mbed_official 423:560d1a9f3083 1317 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
mbed_official 423:560d1a9f3083 1318
mbed_official 423:560d1a9f3083 1319 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1320 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
mbed_official 423:560d1a9f3083 1321 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
mbed_official 423:560d1a9f3083 1322 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
mbed_official 423:560d1a9f3083 1323 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
mbed_official 423:560d1a9f3083 1324 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
mbed_official 423:560d1a9f3083 1325
mbed_official 423:560d1a9f3083 1326 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1327 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
mbed_official 423:560d1a9f3083 1328 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
mbed_official 423:560d1a9f3083 1329 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
mbed_official 423:560d1a9f3083 1330 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
mbed_official 423:560d1a9f3083 1331 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
mbed_official 423:560d1a9f3083 1332
mbed_official 423:560d1a9f3083 1333 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1334 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
mbed_official 423:560d1a9f3083 1335 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
mbed_official 423:560d1a9f3083 1336 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
mbed_official 423:560d1a9f3083 1337 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
mbed_official 423:560d1a9f3083 1338 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
mbed_official 423:560d1a9f3083 1339
mbed_official 423:560d1a9f3083 1340 /******************** Bit definition for ADC_SQR3 register ********************/
mbed_official 423:560d1a9f3083 1341 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1342 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
mbed_official 423:560d1a9f3083 1343 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
mbed_official 423:560d1a9f3083 1344 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
mbed_official 423:560d1a9f3083 1345 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
mbed_official 423:560d1a9f3083 1346 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
mbed_official 423:560d1a9f3083 1347
mbed_official 423:560d1a9f3083 1348 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1349 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
mbed_official 423:560d1a9f3083 1350 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
mbed_official 423:560d1a9f3083 1351 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
mbed_official 423:560d1a9f3083 1352 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
mbed_official 423:560d1a9f3083 1353 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
mbed_official 423:560d1a9f3083 1354
mbed_official 423:560d1a9f3083 1355 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1356 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
mbed_official 423:560d1a9f3083 1357 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
mbed_official 423:560d1a9f3083 1358 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
mbed_official 423:560d1a9f3083 1359 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
mbed_official 423:560d1a9f3083 1360 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
mbed_official 423:560d1a9f3083 1361
mbed_official 423:560d1a9f3083 1362 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1363 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
mbed_official 423:560d1a9f3083 1364 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
mbed_official 423:560d1a9f3083 1365 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
mbed_official 423:560d1a9f3083 1366 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
mbed_official 423:560d1a9f3083 1367 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
mbed_official 423:560d1a9f3083 1368
mbed_official 423:560d1a9f3083 1369 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1370 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
mbed_official 423:560d1a9f3083 1371 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
mbed_official 423:560d1a9f3083 1372 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
mbed_official 423:560d1a9f3083 1373 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
mbed_official 423:560d1a9f3083 1374 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
mbed_official 423:560d1a9f3083 1375
mbed_official 423:560d1a9f3083 1376 /******************** Bit definition for ADC_SQR4 register ********************/
mbed_official 423:560d1a9f3083 1377 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1378 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
mbed_official 423:560d1a9f3083 1379 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
mbed_official 423:560d1a9f3083 1380 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
mbed_official 423:560d1a9f3083 1381 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
mbed_official 423:560d1a9f3083 1382 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
mbed_official 423:560d1a9f3083 1383
mbed_official 423:560d1a9f3083 1384 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
mbed_official 423:560d1a9f3083 1385 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
mbed_official 423:560d1a9f3083 1386 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
mbed_official 423:560d1a9f3083 1387 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
mbed_official 423:560d1a9f3083 1388 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
mbed_official 423:560d1a9f3083 1389 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
mbed_official 423:560d1a9f3083 1390 /******************** Bit definition for ADC_DR register ********************/
mbed_official 423:560d1a9f3083 1391 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
mbed_official 423:560d1a9f3083 1392 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
mbed_official 423:560d1a9f3083 1393 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
mbed_official 423:560d1a9f3083 1394 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
mbed_official 423:560d1a9f3083 1395 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
mbed_official 423:560d1a9f3083 1396 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
mbed_official 423:560d1a9f3083 1397 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
mbed_official 423:560d1a9f3083 1398 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
mbed_official 423:560d1a9f3083 1399 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
mbed_official 423:560d1a9f3083 1400 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
mbed_official 423:560d1a9f3083 1401 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
mbed_official 423:560d1a9f3083 1402 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
mbed_official 423:560d1a9f3083 1403 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
mbed_official 423:560d1a9f3083 1404 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
mbed_official 423:560d1a9f3083 1405 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
mbed_official 423:560d1a9f3083 1406 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
mbed_official 423:560d1a9f3083 1407 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
mbed_official 423:560d1a9f3083 1408
mbed_official 423:560d1a9f3083 1409 /******************** Bit definition for ADC_JSQR register ********************/
mbed_official 423:560d1a9f3083 1410 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
mbed_official 423:560d1a9f3083 1411 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
mbed_official 423:560d1a9f3083 1412 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
mbed_official 423:560d1a9f3083 1413
mbed_official 423:560d1a9f3083 1414 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
mbed_official 423:560d1a9f3083 1415 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
mbed_official 423:560d1a9f3083 1416 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
mbed_official 423:560d1a9f3083 1417 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
mbed_official 423:560d1a9f3083 1418 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
mbed_official 423:560d1a9f3083 1419
mbed_official 423:560d1a9f3083 1420 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
mbed_official 423:560d1a9f3083 1421 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
mbed_official 423:560d1a9f3083 1422 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
mbed_official 423:560d1a9f3083 1423
mbed_official 423:560d1a9f3083 1424 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
mbed_official 423:560d1a9f3083 1425 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
mbed_official 423:560d1a9f3083 1426 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
mbed_official 423:560d1a9f3083 1427 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
mbed_official 423:560d1a9f3083 1428 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
mbed_official 423:560d1a9f3083 1429 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
mbed_official 423:560d1a9f3083 1430
mbed_official 423:560d1a9f3083 1431 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
mbed_official 423:560d1a9f3083 1432 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
mbed_official 423:560d1a9f3083 1433 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
mbed_official 423:560d1a9f3083 1434 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
mbed_official 423:560d1a9f3083 1435 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
mbed_official 423:560d1a9f3083 1436 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
mbed_official 423:560d1a9f3083 1437
mbed_official 423:560d1a9f3083 1438 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
mbed_official 423:560d1a9f3083 1439 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
mbed_official 423:560d1a9f3083 1440 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
mbed_official 423:560d1a9f3083 1441 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
mbed_official 423:560d1a9f3083 1442 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
mbed_official 423:560d1a9f3083 1443 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
mbed_official 423:560d1a9f3083 1444
mbed_official 423:560d1a9f3083 1445 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
mbed_official 423:560d1a9f3083 1446 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
mbed_official 423:560d1a9f3083 1447 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
mbed_official 423:560d1a9f3083 1448 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
mbed_official 423:560d1a9f3083 1449 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
mbed_official 423:560d1a9f3083 1450 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
mbed_official 423:560d1a9f3083 1451
mbed_official 423:560d1a9f3083 1452 /******************** Bit definition for ADC_OFR1 register ********************/
mbed_official 423:560d1a9f3083 1453 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
mbed_official 423:560d1a9f3083 1454 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
mbed_official 423:560d1a9f3083 1455 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
mbed_official 423:560d1a9f3083 1456 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
mbed_official 423:560d1a9f3083 1457 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
mbed_official 423:560d1a9f3083 1458 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
mbed_official 423:560d1a9f3083 1459 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
mbed_official 423:560d1a9f3083 1460 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
mbed_official 423:560d1a9f3083 1461 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
mbed_official 423:560d1a9f3083 1462 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
mbed_official 423:560d1a9f3083 1463 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
mbed_official 423:560d1a9f3083 1464 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
mbed_official 423:560d1a9f3083 1465 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
mbed_official 423:560d1a9f3083 1466
mbed_official 423:560d1a9f3083 1467 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
mbed_official 423:560d1a9f3083 1468 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
mbed_official 423:560d1a9f3083 1469 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
mbed_official 423:560d1a9f3083 1470 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
mbed_official 423:560d1a9f3083 1471 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
mbed_official 423:560d1a9f3083 1472 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
mbed_official 423:560d1a9f3083 1473
mbed_official 423:560d1a9f3083 1474 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
mbed_official 423:560d1a9f3083 1475
mbed_official 423:560d1a9f3083 1476 /******************** Bit definition for ADC_OFR2 register ********************/
mbed_official 423:560d1a9f3083 1477 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
mbed_official 423:560d1a9f3083 1478 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
mbed_official 423:560d1a9f3083 1479 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
mbed_official 423:560d1a9f3083 1480 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
mbed_official 423:560d1a9f3083 1481 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
mbed_official 423:560d1a9f3083 1482 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
mbed_official 423:560d1a9f3083 1483 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
mbed_official 423:560d1a9f3083 1484 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
mbed_official 423:560d1a9f3083 1485 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
mbed_official 423:560d1a9f3083 1486 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
mbed_official 423:560d1a9f3083 1487 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
mbed_official 423:560d1a9f3083 1488 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
mbed_official 423:560d1a9f3083 1489 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
mbed_official 423:560d1a9f3083 1490
mbed_official 423:560d1a9f3083 1491 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
mbed_official 423:560d1a9f3083 1492 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
mbed_official 423:560d1a9f3083 1493 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
mbed_official 423:560d1a9f3083 1494 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
mbed_official 423:560d1a9f3083 1495 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
mbed_official 423:560d1a9f3083 1496 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
mbed_official 423:560d1a9f3083 1497
mbed_official 423:560d1a9f3083 1498 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
mbed_official 423:560d1a9f3083 1499
mbed_official 423:560d1a9f3083 1500 /******************** Bit definition for ADC_OFR3 register ********************/
mbed_official 423:560d1a9f3083 1501 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
mbed_official 423:560d1a9f3083 1502 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
mbed_official 423:560d1a9f3083 1503 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
mbed_official 423:560d1a9f3083 1504 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
mbed_official 423:560d1a9f3083 1505 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
mbed_official 423:560d1a9f3083 1506 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
mbed_official 423:560d1a9f3083 1507 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
mbed_official 423:560d1a9f3083 1508 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
mbed_official 423:560d1a9f3083 1509 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
mbed_official 423:560d1a9f3083 1510 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
mbed_official 423:560d1a9f3083 1511 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
mbed_official 423:560d1a9f3083 1512 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
mbed_official 423:560d1a9f3083 1513 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
mbed_official 423:560d1a9f3083 1514
mbed_official 423:560d1a9f3083 1515 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
mbed_official 423:560d1a9f3083 1516 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
mbed_official 423:560d1a9f3083 1517 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
mbed_official 423:560d1a9f3083 1518 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
mbed_official 423:560d1a9f3083 1519 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
mbed_official 423:560d1a9f3083 1520 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
mbed_official 423:560d1a9f3083 1521
mbed_official 423:560d1a9f3083 1522 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
mbed_official 423:560d1a9f3083 1523
mbed_official 423:560d1a9f3083 1524 /******************** Bit definition for ADC_OFR4 register ********************/
mbed_official 423:560d1a9f3083 1525 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
mbed_official 423:560d1a9f3083 1526 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
mbed_official 423:560d1a9f3083 1527 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
mbed_official 423:560d1a9f3083 1528 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
mbed_official 423:560d1a9f3083 1529 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
mbed_official 423:560d1a9f3083 1530 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
mbed_official 423:560d1a9f3083 1531 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
mbed_official 423:560d1a9f3083 1532 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
mbed_official 423:560d1a9f3083 1533 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
mbed_official 423:560d1a9f3083 1534 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
mbed_official 423:560d1a9f3083 1535 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
mbed_official 423:560d1a9f3083 1536 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
mbed_official 423:560d1a9f3083 1537 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
mbed_official 423:560d1a9f3083 1538
mbed_official 423:560d1a9f3083 1539 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
mbed_official 423:560d1a9f3083 1540 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
mbed_official 423:560d1a9f3083 1541 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
mbed_official 423:560d1a9f3083 1542 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
mbed_official 423:560d1a9f3083 1543 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
mbed_official 423:560d1a9f3083 1544 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
mbed_official 423:560d1a9f3083 1545
mbed_official 423:560d1a9f3083 1546 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
mbed_official 423:560d1a9f3083 1547
mbed_official 423:560d1a9f3083 1548 /******************** Bit definition for ADC_JDR1 register ********************/
mbed_official 423:560d1a9f3083 1549 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 423:560d1a9f3083 1550 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 423:560d1a9f3083 1551 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 423:560d1a9f3083 1552 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 423:560d1a9f3083 1553 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 423:560d1a9f3083 1554 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 423:560d1a9f3083 1555 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 423:560d1a9f3083 1556 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 423:560d1a9f3083 1557 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 423:560d1a9f3083 1558 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 423:560d1a9f3083 1559 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 423:560d1a9f3083 1560 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 423:560d1a9f3083 1561 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 423:560d1a9f3083 1562 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 423:560d1a9f3083 1563 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 423:560d1a9f3083 1564 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 423:560d1a9f3083 1565 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 423:560d1a9f3083 1566
mbed_official 423:560d1a9f3083 1567 /******************** Bit definition for ADC_JDR2 register ********************/
mbed_official 423:560d1a9f3083 1568 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 423:560d1a9f3083 1569 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 423:560d1a9f3083 1570 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 423:560d1a9f3083 1571 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 423:560d1a9f3083 1572 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 423:560d1a9f3083 1573 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 423:560d1a9f3083 1574 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 423:560d1a9f3083 1575 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 423:560d1a9f3083 1576 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 423:560d1a9f3083 1577 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 423:560d1a9f3083 1578 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 423:560d1a9f3083 1579 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 423:560d1a9f3083 1580 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 423:560d1a9f3083 1581 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 423:560d1a9f3083 1582 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 423:560d1a9f3083 1583 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 423:560d1a9f3083 1584 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 423:560d1a9f3083 1585
mbed_official 423:560d1a9f3083 1586 /******************** Bit definition for ADC_JDR3 register ********************/
mbed_official 423:560d1a9f3083 1587 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 423:560d1a9f3083 1588 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 423:560d1a9f3083 1589 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 423:560d1a9f3083 1590 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 423:560d1a9f3083 1591 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 423:560d1a9f3083 1592 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 423:560d1a9f3083 1593 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 423:560d1a9f3083 1594 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 423:560d1a9f3083 1595 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 423:560d1a9f3083 1596 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 423:560d1a9f3083 1597 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 423:560d1a9f3083 1598 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 423:560d1a9f3083 1599 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 423:560d1a9f3083 1600 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 423:560d1a9f3083 1601 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 423:560d1a9f3083 1602 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 423:560d1a9f3083 1603 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 423:560d1a9f3083 1604
mbed_official 423:560d1a9f3083 1605 /******************** Bit definition for ADC_JDR4 register ********************/
mbed_official 423:560d1a9f3083 1606 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 423:560d1a9f3083 1607 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 423:560d1a9f3083 1608 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 423:560d1a9f3083 1609 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 423:560d1a9f3083 1610 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 423:560d1a9f3083 1611 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 423:560d1a9f3083 1612 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 423:560d1a9f3083 1613 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 423:560d1a9f3083 1614 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 423:560d1a9f3083 1615 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 423:560d1a9f3083 1616 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 423:560d1a9f3083 1617 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 423:560d1a9f3083 1618 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 423:560d1a9f3083 1619 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 423:560d1a9f3083 1620 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 423:560d1a9f3083 1621 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 423:560d1a9f3083 1622 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 423:560d1a9f3083 1623
mbed_official 423:560d1a9f3083 1624 /******************** Bit definition for ADC_AWD2CR register ********************/
mbed_official 423:560d1a9f3083 1625 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 423:560d1a9f3083 1626 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
mbed_official 423:560d1a9f3083 1627 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
mbed_official 423:560d1a9f3083 1628 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
mbed_official 423:560d1a9f3083 1629 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
mbed_official 423:560d1a9f3083 1630 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
mbed_official 423:560d1a9f3083 1631 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
mbed_official 423:560d1a9f3083 1632 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
mbed_official 423:560d1a9f3083 1633 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
mbed_official 423:560d1a9f3083 1634 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
mbed_official 423:560d1a9f3083 1635 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
mbed_official 423:560d1a9f3083 1636 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
mbed_official 423:560d1a9f3083 1637 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
mbed_official 423:560d1a9f3083 1638 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
mbed_official 423:560d1a9f3083 1639 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
mbed_official 423:560d1a9f3083 1640 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
mbed_official 423:560d1a9f3083 1641 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
mbed_official 423:560d1a9f3083 1642 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
mbed_official 423:560d1a9f3083 1643 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
mbed_official 423:560d1a9f3083 1644
mbed_official 423:560d1a9f3083 1645 /******************** Bit definition for ADC_AWD3CR register ********************/
mbed_official 423:560d1a9f3083 1646 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 423:560d1a9f3083 1647 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
mbed_official 423:560d1a9f3083 1648 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
mbed_official 423:560d1a9f3083 1649 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
mbed_official 423:560d1a9f3083 1650 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
mbed_official 423:560d1a9f3083 1651 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
mbed_official 423:560d1a9f3083 1652 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
mbed_official 423:560d1a9f3083 1653 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
mbed_official 423:560d1a9f3083 1654 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
mbed_official 423:560d1a9f3083 1655 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
mbed_official 423:560d1a9f3083 1656 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
mbed_official 423:560d1a9f3083 1657 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
mbed_official 423:560d1a9f3083 1658 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
mbed_official 423:560d1a9f3083 1659 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
mbed_official 423:560d1a9f3083 1660 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
mbed_official 423:560d1a9f3083 1661 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
mbed_official 423:560d1a9f3083 1662 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
mbed_official 423:560d1a9f3083 1663 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
mbed_official 423:560d1a9f3083 1664 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
mbed_official 423:560d1a9f3083 1665
mbed_official 423:560d1a9f3083 1666 /******************** Bit definition for ADC_DIFSEL register ********************/
mbed_official 423:560d1a9f3083 1667 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
mbed_official 423:560d1a9f3083 1668 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
mbed_official 423:560d1a9f3083 1669 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
mbed_official 423:560d1a9f3083 1670 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
mbed_official 423:560d1a9f3083 1671 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
mbed_official 423:560d1a9f3083 1672 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
mbed_official 423:560d1a9f3083 1673 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
mbed_official 423:560d1a9f3083 1674 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
mbed_official 423:560d1a9f3083 1675 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
mbed_official 423:560d1a9f3083 1676 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
mbed_official 423:560d1a9f3083 1677 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
mbed_official 423:560d1a9f3083 1678 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
mbed_official 423:560d1a9f3083 1679 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
mbed_official 423:560d1a9f3083 1680 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
mbed_official 423:560d1a9f3083 1681 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
mbed_official 423:560d1a9f3083 1682 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
mbed_official 423:560d1a9f3083 1683 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
mbed_official 423:560d1a9f3083 1684 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
mbed_official 423:560d1a9f3083 1685 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
mbed_official 423:560d1a9f3083 1686
mbed_official 423:560d1a9f3083 1687 /******************** Bit definition for ADC_CALFACT register ********************/
mbed_official 423:560d1a9f3083 1688 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
mbed_official 423:560d1a9f3083 1689 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
mbed_official 423:560d1a9f3083 1690 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
mbed_official 423:560d1a9f3083 1691 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
mbed_official 423:560d1a9f3083 1692 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
mbed_official 423:560d1a9f3083 1693 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
mbed_official 423:560d1a9f3083 1694 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
mbed_official 423:560d1a9f3083 1695 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
mbed_official 423:560d1a9f3083 1696 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
mbed_official 423:560d1a9f3083 1697 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
mbed_official 423:560d1a9f3083 1698 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
mbed_official 423:560d1a9f3083 1699 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
mbed_official 423:560d1a9f3083 1700 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
mbed_official 423:560d1a9f3083 1701 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
mbed_official 423:560d1a9f3083 1702 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
mbed_official 423:560d1a9f3083 1703 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
mbed_official 423:560d1a9f3083 1704
mbed_official 423:560d1a9f3083 1705 /************************* ADC Common registers *****************************/
mbed_official 423:560d1a9f3083 1706 /******************** Bit definition for ADC12_CSR register ********************/
mbed_official 423:560d1a9f3083 1707 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 423:560d1a9f3083 1708 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 423:560d1a9f3083 1709 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 423:560d1a9f3083 1710 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 423:560d1a9f3083 1711 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 423:560d1a9f3083 1712 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 423:560d1a9f3083 1713 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 423:560d1a9f3083 1714 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 423:560d1a9f3083 1715 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 423:560d1a9f3083 1716 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 423:560d1a9f3083 1717 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 423:560d1a9f3083 1718 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 423:560d1a9f3083 1719 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 423:560d1a9f3083 1720 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 423:560d1a9f3083 1721 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 423:560d1a9f3083 1722 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 423:560d1a9f3083 1723 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 423:560d1a9f3083 1724 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 423:560d1a9f3083 1725 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1726 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1727 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1728 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 423:560d1a9f3083 1729
mbed_official 423:560d1a9f3083 1730 /******************** Bit definition for ADC34_CSR register ********************/
mbed_official 423:560d1a9f3083 1731 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 423:560d1a9f3083 1732 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 423:560d1a9f3083 1733 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 423:560d1a9f3083 1734 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 423:560d1a9f3083 1735 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 423:560d1a9f3083 1736 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 423:560d1a9f3083 1737 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 423:560d1a9f3083 1738 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 423:560d1a9f3083 1739 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 423:560d1a9f3083 1740 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 423:560d1a9f3083 1741 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 423:560d1a9f3083 1742 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 423:560d1a9f3083 1743 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 423:560d1a9f3083 1744 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 423:560d1a9f3083 1745 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 423:560d1a9f3083 1746 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 423:560d1a9f3083 1747 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 423:560d1a9f3083 1748 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 423:560d1a9f3083 1749 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1750 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1751 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 423:560d1a9f3083 1752 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 423:560d1a9f3083 1753
mbed_official 423:560d1a9f3083 1754 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 423:560d1a9f3083 1755 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 423:560d1a9f3083 1756 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 423:560d1a9f3083 1757 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 423:560d1a9f3083 1758 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 423:560d1a9f3083 1759 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 423:560d1a9f3083 1760 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 423:560d1a9f3083 1761 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 423:560d1a9f3083 1762 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 423:560d1a9f3083 1763 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 423:560d1a9f3083 1764 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 423:560d1a9f3083 1765 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 423:560d1a9f3083 1766 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 423:560d1a9f3083 1767 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 423:560d1a9f3083 1768 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 423:560d1a9f3083 1769 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 423:560d1a9f3083 1770 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 423:560d1a9f3083 1771 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 423:560d1a9f3083 1772 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 423:560d1a9f3083 1773 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 423:560d1a9f3083 1774 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 423:560d1a9f3083 1775 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 423:560d1a9f3083 1776
mbed_official 423:560d1a9f3083 1777 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 423:560d1a9f3083 1778 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 423:560d1a9f3083 1779 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 423:560d1a9f3083 1780 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 423:560d1a9f3083 1781 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 423:560d1a9f3083 1782 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 423:560d1a9f3083 1783 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 423:560d1a9f3083 1784
mbed_official 423:560d1a9f3083 1785 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 423:560d1a9f3083 1786 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 423:560d1a9f3083 1787 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 423:560d1a9f3083 1788 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 423:560d1a9f3083 1789 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 423:560d1a9f3083 1790
mbed_official 423:560d1a9f3083 1791 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 423:560d1a9f3083 1792 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 423:560d1a9f3083 1793 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 423:560d1a9f3083 1794 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 423:560d1a9f3083 1795
mbed_official 423:560d1a9f3083 1796 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 423:560d1a9f3083 1797 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 423:560d1a9f3083 1798 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 423:560d1a9f3083 1799
mbed_official 423:560d1a9f3083 1800 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 423:560d1a9f3083 1801 #define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 423:560d1a9f3083 1802 #define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 423:560d1a9f3083 1803
mbed_official 423:560d1a9f3083 1804 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 423:560d1a9f3083 1805 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 423:560d1a9f3083 1806 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 423:560d1a9f3083 1807 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 423:560d1a9f3083 1808 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 423:560d1a9f3083 1809 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 423:560d1a9f3083 1810 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 423:560d1a9f3083 1811 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 423:560d1a9f3083 1812 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 423:560d1a9f3083 1813 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 423:560d1a9f3083 1814 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 423:560d1a9f3083 1815 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 423:560d1a9f3083 1816 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 423:560d1a9f3083 1817 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 423:560d1a9f3083 1818 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 423:560d1a9f3083 1819 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 423:560d1a9f3083 1820 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 423:560d1a9f3083 1821 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 423:560d1a9f3083 1822
mbed_official 423:560d1a9f3083 1823 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 423:560d1a9f3083 1824 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 423:560d1a9f3083 1825 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 423:560d1a9f3083 1826 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 423:560d1a9f3083 1827 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 423:560d1a9f3083 1828 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 423:560d1a9f3083 1829 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 423:560d1a9f3083 1830 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 423:560d1a9f3083 1831 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 423:560d1a9f3083 1832 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 423:560d1a9f3083 1833 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 423:560d1a9f3083 1834 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 423:560d1a9f3083 1835 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 423:560d1a9f3083 1836 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 423:560d1a9f3083 1837 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 423:560d1a9f3083 1838 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 423:560d1a9f3083 1839 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 423:560d1a9f3083 1840
mbed_official 423:560d1a9f3083 1841 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 423:560d1a9f3083 1842 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 423:560d1a9f3083 1843 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 423:560d1a9f3083 1844 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 423:560d1a9f3083 1845 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 423:560d1a9f3083 1846 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 423:560d1a9f3083 1847 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 423:560d1a9f3083 1848 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 423:560d1a9f3083 1849 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 423:560d1a9f3083 1850 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 423:560d1a9f3083 1851 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 423:560d1a9f3083 1852 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 423:560d1a9f3083 1853 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 423:560d1a9f3083 1854 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 423:560d1a9f3083 1855 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 423:560d1a9f3083 1856 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 423:560d1a9f3083 1857 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 423:560d1a9f3083 1858 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 423:560d1a9f3083 1859
mbed_official 423:560d1a9f3083 1860 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 423:560d1a9f3083 1861 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 423:560d1a9f3083 1862 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 423:560d1a9f3083 1863 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 423:560d1a9f3083 1864 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 423:560d1a9f3083 1865 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 423:560d1a9f3083 1866 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 423:560d1a9f3083 1867 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 423:560d1a9f3083 1868 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 423:560d1a9f3083 1869 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 423:560d1a9f3083 1870 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 423:560d1a9f3083 1871 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 423:560d1a9f3083 1872 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 423:560d1a9f3083 1873 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 423:560d1a9f3083 1874 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 423:560d1a9f3083 1875 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 423:560d1a9f3083 1876 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 423:560d1a9f3083 1877
mbed_official 423:560d1a9f3083 1878 /******************************************************************************/
mbed_official 423:560d1a9f3083 1879 /* */
mbed_official 423:560d1a9f3083 1880 /* Analog Comparators (COMP) */
mbed_official 423:560d1a9f3083 1881 /* */
mbed_official 423:560d1a9f3083 1882 /******************************************************************************/
mbed_official 423:560d1a9f3083 1883 /********************** Bit definition for COMP1_CSR register ***************/
mbed_official 423:560d1a9f3083 1884 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 423:560d1a9f3083 1885 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
mbed_official 423:560d1a9f3083 1886 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 423:560d1a9f3083 1887 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1888 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1889 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1890 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
mbed_official 423:560d1a9f3083 1891 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
mbed_official 423:560d1a9f3083 1892 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
mbed_official 423:560d1a9f3083 1893 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
mbed_official 423:560d1a9f3083 1894 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
mbed_official 423:560d1a9f3083 1895 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
mbed_official 423:560d1a9f3083 1896 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
mbed_official 423:560d1a9f3083 1897 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
mbed_official 423:560d1a9f3083 1898 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
mbed_official 423:560d1a9f3083 1899 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
mbed_official 423:560d1a9f3083 1900 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
mbed_official 423:560d1a9f3083 1901 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
mbed_official 423:560d1a9f3083 1902
mbed_official 423:560d1a9f3083 1903 /********************** Bit definition for COMP2_CSR register ***************/
mbed_official 423:560d1a9f3083 1904 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
mbed_official 423:560d1a9f3083 1905 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
mbed_official 423:560d1a9f3083 1906 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1907 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1908 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1909 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
mbed_official 423:560d1a9f3083 1910 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
mbed_official 423:560d1a9f3083 1911 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
mbed_official 423:560d1a9f3083 1912 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
mbed_official 423:560d1a9f3083 1913 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
mbed_official 423:560d1a9f3083 1914 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
mbed_official 423:560d1a9f3083 1915 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
mbed_official 423:560d1a9f3083 1916 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
mbed_official 423:560d1a9f3083 1917 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
mbed_official 423:560d1a9f3083 1918 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
mbed_official 423:560d1a9f3083 1919 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
mbed_official 423:560d1a9f3083 1920 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 423:560d1a9f3083 1921 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 423:560d1a9f3083 1922
mbed_official 423:560d1a9f3083 1923 /********************** Bit definition for COMP3_CSR register ***************/
mbed_official 423:560d1a9f3083 1924 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
mbed_official 423:560d1a9f3083 1925 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
mbed_official 423:560d1a9f3083 1926 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1927 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1928 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1929 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
mbed_official 423:560d1a9f3083 1930 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
mbed_official 423:560d1a9f3083 1931 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
mbed_official 423:560d1a9f3083 1932 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
mbed_official 423:560d1a9f3083 1933 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
mbed_official 423:560d1a9f3083 1934 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
mbed_official 423:560d1a9f3083 1935 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
mbed_official 423:560d1a9f3083 1936 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
mbed_official 423:560d1a9f3083 1937 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
mbed_official 423:560d1a9f3083 1938 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
mbed_official 423:560d1a9f3083 1939 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
mbed_official 423:560d1a9f3083 1940 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
mbed_official 423:560d1a9f3083 1941
mbed_official 423:560d1a9f3083 1942 /********************** Bit definition for COMP4_CSR register ***************/
mbed_official 423:560d1a9f3083 1943 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
mbed_official 423:560d1a9f3083 1944 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
mbed_official 423:560d1a9f3083 1945 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1946 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1947 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1948 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
mbed_official 423:560d1a9f3083 1949 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
mbed_official 423:560d1a9f3083 1950 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
mbed_official 423:560d1a9f3083 1951 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
mbed_official 423:560d1a9f3083 1952 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
mbed_official 423:560d1a9f3083 1953 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
mbed_official 423:560d1a9f3083 1954 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
mbed_official 423:560d1a9f3083 1955 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
mbed_official 423:560d1a9f3083 1956 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
mbed_official 423:560d1a9f3083 1957 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
mbed_official 423:560d1a9f3083 1958 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
mbed_official 423:560d1a9f3083 1959 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
mbed_official 423:560d1a9f3083 1960 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
mbed_official 423:560d1a9f3083 1961
mbed_official 423:560d1a9f3083 1962 /********************** Bit definition for COMP5_CSR register ***************/
mbed_official 423:560d1a9f3083 1963 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
mbed_official 423:560d1a9f3083 1964 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
mbed_official 423:560d1a9f3083 1965 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1966 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1967 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1968 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
mbed_official 423:560d1a9f3083 1969 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
mbed_official 423:560d1a9f3083 1970 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
mbed_official 423:560d1a9f3083 1971 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
mbed_official 423:560d1a9f3083 1972 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
mbed_official 423:560d1a9f3083 1973 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
mbed_official 423:560d1a9f3083 1974 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
mbed_official 423:560d1a9f3083 1975 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
mbed_official 423:560d1a9f3083 1976 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
mbed_official 423:560d1a9f3083 1977 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
mbed_official 423:560d1a9f3083 1978 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
mbed_official 423:560d1a9f3083 1979 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
mbed_official 423:560d1a9f3083 1980
mbed_official 423:560d1a9f3083 1981 /********************** Bit definition for COMP6_CSR register ***************/
mbed_official 423:560d1a9f3083 1982 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
mbed_official 423:560d1a9f3083 1983 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
mbed_official 423:560d1a9f3083 1984 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 1985 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 1986 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 1987 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
mbed_official 423:560d1a9f3083 1988 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
mbed_official 423:560d1a9f3083 1989 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
mbed_official 423:560d1a9f3083 1990 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
mbed_official 423:560d1a9f3083 1991 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
mbed_official 423:560d1a9f3083 1992 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
mbed_official 423:560d1a9f3083 1993 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
mbed_official 423:560d1a9f3083 1994 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
mbed_official 423:560d1a9f3083 1995 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
mbed_official 423:560d1a9f3083 1996 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
mbed_official 423:560d1a9f3083 1997 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
mbed_official 423:560d1a9f3083 1998 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
mbed_official 423:560d1a9f3083 1999 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
mbed_official 423:560d1a9f3083 2000
mbed_official 423:560d1a9f3083 2001 /********************** Bit definition for COMP7_CSR register ***************/
mbed_official 423:560d1a9f3083 2002 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
mbed_official 423:560d1a9f3083 2003 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
mbed_official 423:560d1a9f3083 2004 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
mbed_official 423:560d1a9f3083 2005 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
mbed_official 423:560d1a9f3083 2006 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
mbed_official 423:560d1a9f3083 2007 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
mbed_official 423:560d1a9f3083 2008 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
mbed_official 423:560d1a9f3083 2009 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
mbed_official 423:560d1a9f3083 2010 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
mbed_official 423:560d1a9f3083 2011 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
mbed_official 423:560d1a9f3083 2012 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
mbed_official 423:560d1a9f3083 2013 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
mbed_official 423:560d1a9f3083 2014 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
mbed_official 423:560d1a9f3083 2015 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
mbed_official 423:560d1a9f3083 2016 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
mbed_official 423:560d1a9f3083 2017 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
mbed_official 423:560d1a9f3083 2018 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
mbed_official 423:560d1a9f3083 2019
mbed_official 423:560d1a9f3083 2020 /********************** Bit definition for COMP_CSR register ****************/
mbed_official 423:560d1a9f3083 2021 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 423:560d1a9f3083 2022 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
mbed_official 423:560d1a9f3083 2023 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 423:560d1a9f3083 2024 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 423:560d1a9f3083 2025 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 423:560d1a9f3083 2026 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
mbed_official 423:560d1a9f3083 2027 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
mbed_official 423:560d1a9f3083 2028 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
mbed_official 423:560d1a9f3083 2029 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
mbed_official 423:560d1a9f3083 2030 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
mbed_official 423:560d1a9f3083 2031 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
mbed_official 423:560d1a9f3083 2032 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
mbed_official 423:560d1a9f3083 2033 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
mbed_official 423:560d1a9f3083 2034 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
mbed_official 423:560d1a9f3083 2035 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
mbed_official 423:560d1a9f3083 2036 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
mbed_official 423:560d1a9f3083 2037 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
mbed_official 423:560d1a9f3083 2038 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
mbed_official 423:560d1a9f3083 2039
mbed_official 423:560d1a9f3083 2040 /******************************************************************************/
mbed_official 423:560d1a9f3083 2041 /* */
mbed_official 423:560d1a9f3083 2042 /* Operational Amplifier (OPAMP) */
mbed_official 423:560d1a9f3083 2043 /* */
mbed_official 423:560d1a9f3083 2044 /******************************************************************************/
mbed_official 423:560d1a9f3083 2045 /********************* Bit definition for OPAMP1_CSR register ***************/
mbed_official 423:560d1a9f3083 2046 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
mbed_official 423:560d1a9f3083 2047 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 423:560d1a9f3083 2048 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 423:560d1a9f3083 2049 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2050 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2051 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 423:560d1a9f3083 2052 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2053 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2054 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 423:560d1a9f3083 2055 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 423:560d1a9f3083 2056 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 423:560d1a9f3083 2057 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2058 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2059 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 423:560d1a9f3083 2060 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 423:560d1a9f3083 2061 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2062 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2063 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 423:560d1a9f3083 2064 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2065 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2066 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 2067 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 2068 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 423:560d1a9f3083 2069 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 423:560d1a9f3083 2070 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 423:560d1a9f3083 2071 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 423:560d1a9f3083 2072 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 423:560d1a9f3083 2073 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 423:560d1a9f3083 2074
mbed_official 423:560d1a9f3083 2075 /********************* Bit definition for OPAMP2_CSR register ***************/
mbed_official 423:560d1a9f3083 2076 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
mbed_official 423:560d1a9f3083 2077 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 423:560d1a9f3083 2078 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 423:560d1a9f3083 2079 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2080 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2081 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 423:560d1a9f3083 2082 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2083 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2084 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 423:560d1a9f3083 2085 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 423:560d1a9f3083 2086 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 423:560d1a9f3083 2087 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2088 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2089 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 423:560d1a9f3083 2090 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 423:560d1a9f3083 2091 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2092 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2093 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 423:560d1a9f3083 2094 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2095 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2096 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 2097 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 2098 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 423:560d1a9f3083 2099 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 423:560d1a9f3083 2100 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 423:560d1a9f3083 2101 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 423:560d1a9f3083 2102 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 423:560d1a9f3083 2103 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 423:560d1a9f3083 2104
mbed_official 423:560d1a9f3083 2105 /********************* Bit definition for OPAMP3_CSR register ***************/
mbed_official 423:560d1a9f3083 2106 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
mbed_official 423:560d1a9f3083 2107 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 423:560d1a9f3083 2108 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 423:560d1a9f3083 2109 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2110 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2111 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 423:560d1a9f3083 2112 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2113 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2114 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 423:560d1a9f3083 2115 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 423:560d1a9f3083 2116 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 423:560d1a9f3083 2117 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2118 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2119 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 423:560d1a9f3083 2120 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 423:560d1a9f3083 2121 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2122 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2123 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 423:560d1a9f3083 2124 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2125 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2126 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 2127 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 2128 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 423:560d1a9f3083 2129 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 423:560d1a9f3083 2130 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 423:560d1a9f3083 2131 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 423:560d1a9f3083 2132 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 423:560d1a9f3083 2133 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 423:560d1a9f3083 2134
mbed_official 423:560d1a9f3083 2135 /********************* Bit definition for OPAMP4_CSR register ***************/
mbed_official 423:560d1a9f3083 2136 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
mbed_official 423:560d1a9f3083 2137 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 423:560d1a9f3083 2138 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 423:560d1a9f3083 2139 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2140 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2141 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 423:560d1a9f3083 2142 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2143 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2144 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 423:560d1a9f3083 2145 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 423:560d1a9f3083 2146 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 423:560d1a9f3083 2147 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2148 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2149 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 423:560d1a9f3083 2150 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 423:560d1a9f3083 2151 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2152 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2153 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 423:560d1a9f3083 2154 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2155 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2156 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 2157 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 2158 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 423:560d1a9f3083 2159 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 423:560d1a9f3083 2160 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 423:560d1a9f3083 2161 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 423:560d1a9f3083 2162 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 423:560d1a9f3083 2163 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 423:560d1a9f3083 2164
mbed_official 423:560d1a9f3083 2165 /********************* Bit definition for OPAMPx_CSR register ***************/
mbed_official 423:560d1a9f3083 2166 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
mbed_official 423:560d1a9f3083 2167 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 423:560d1a9f3083 2168 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 423:560d1a9f3083 2169 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2170 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2171 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 423:560d1a9f3083 2172 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2173 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2174 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 423:560d1a9f3083 2175 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 423:560d1a9f3083 2176 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 423:560d1a9f3083 2177 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2178 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2179 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 423:560d1a9f3083 2180 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 423:560d1a9f3083 2181 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2182 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2183 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 423:560d1a9f3083 2184 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 2185 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 2186 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 2187 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 2188 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 423:560d1a9f3083 2189 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 423:560d1a9f3083 2190 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 423:560d1a9f3083 2191 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 423:560d1a9f3083 2192 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 423:560d1a9f3083 2193 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 423:560d1a9f3083 2194
mbed_official 423:560d1a9f3083 2195 /******************************************************************************/
mbed_official 423:560d1a9f3083 2196 /* */
mbed_official 423:560d1a9f3083 2197 /* Controller Area Network (CAN ) */
mbed_official 423:560d1a9f3083 2198 /* */
mbed_official 423:560d1a9f3083 2199 /******************************************************************************/
mbed_official 423:560d1a9f3083 2200 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 423:560d1a9f3083 2201 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 423:560d1a9f3083 2202 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 423:560d1a9f3083 2203 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 423:560d1a9f3083 2204 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 423:560d1a9f3083 2205 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 423:560d1a9f3083 2206 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 423:560d1a9f3083 2207 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 423:560d1a9f3083 2208 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 423:560d1a9f3083 2209 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 423:560d1a9f3083 2210
mbed_official 423:560d1a9f3083 2211 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 423:560d1a9f3083 2212 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 423:560d1a9f3083 2213 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 423:560d1a9f3083 2214 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 423:560d1a9f3083 2215 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 423:560d1a9f3083 2216 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 423:560d1a9f3083 2217 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 423:560d1a9f3083 2218 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 423:560d1a9f3083 2219 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 423:560d1a9f3083 2220 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 423:560d1a9f3083 2221
mbed_official 423:560d1a9f3083 2222 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 423:560d1a9f3083 2223 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 423:560d1a9f3083 2224 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 423:560d1a9f3083 2225 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 423:560d1a9f3083 2226 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 423:560d1a9f3083 2227 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 423:560d1a9f3083 2228 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 423:560d1a9f3083 2229 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 423:560d1a9f3083 2230 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 423:560d1a9f3083 2231 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 423:560d1a9f3083 2232 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 423:560d1a9f3083 2233 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 423:560d1a9f3083 2234 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 423:560d1a9f3083 2235 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 423:560d1a9f3083 2236 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 423:560d1a9f3083 2237 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 423:560d1a9f3083 2238 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 423:560d1a9f3083 2239
mbed_official 423:560d1a9f3083 2240 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 423:560d1a9f3083 2241 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 423:560d1a9f3083 2242 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 423:560d1a9f3083 2243 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 423:560d1a9f3083 2244
mbed_official 423:560d1a9f3083 2245 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 423:560d1a9f3083 2246 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 423:560d1a9f3083 2247 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 423:560d1a9f3083 2248 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 423:560d1a9f3083 2249
mbed_official 423:560d1a9f3083 2250 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 423:560d1a9f3083 2251 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 423:560d1a9f3083 2252 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 423:560d1a9f3083 2253 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 423:560d1a9f3083 2254 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 423:560d1a9f3083 2255
mbed_official 423:560d1a9f3083 2256 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 423:560d1a9f3083 2257 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 423:560d1a9f3083 2258 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 423:560d1a9f3083 2259 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 423:560d1a9f3083 2260 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 423:560d1a9f3083 2261
mbed_official 423:560d1a9f3083 2262 /******************** Bit definition for CAN_IER register *******************/
mbed_official 423:560d1a9f3083 2263 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 423:560d1a9f3083 2264 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 423:560d1a9f3083 2265 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 423:560d1a9f3083 2266 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 423:560d1a9f3083 2267 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 423:560d1a9f3083 2268 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 423:560d1a9f3083 2269 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 423:560d1a9f3083 2270 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 423:560d1a9f3083 2271 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 423:560d1a9f3083 2272 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 423:560d1a9f3083 2273 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 423:560d1a9f3083 2274 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 423:560d1a9f3083 2275 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 423:560d1a9f3083 2276 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 423:560d1a9f3083 2277
mbed_official 423:560d1a9f3083 2278 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 423:560d1a9f3083 2279 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 423:560d1a9f3083 2280 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 423:560d1a9f3083 2281 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 423:560d1a9f3083 2282
mbed_official 423:560d1a9f3083 2283 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 423:560d1a9f3083 2284 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 2285 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 2286 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 2287
mbed_official 423:560d1a9f3083 2288 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 423:560d1a9f3083 2289 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 423:560d1a9f3083 2290
mbed_official 423:560d1a9f3083 2291 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 423:560d1a9f3083 2292 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 423:560d1a9f3083 2293 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 423:560d1a9f3083 2294 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 423:560d1a9f3083 2295 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 423:560d1a9f3083 2296 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 423:560d1a9f3083 2297 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 423:560d1a9f3083 2298 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 423:560d1a9f3083 2299 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 423:560d1a9f3083 2300 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 423:560d1a9f3083 2301 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 423:560d1a9f3083 2302 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 423:560d1a9f3083 2303 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 423:560d1a9f3083 2304 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 423:560d1a9f3083 2305 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 423:560d1a9f3083 2306 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 423:560d1a9f3083 2307
mbed_official 423:560d1a9f3083 2308 /*!<Mailbox registers */
mbed_official 423:560d1a9f3083 2309 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 423:560d1a9f3083 2310 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 423:560d1a9f3083 2311 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 423:560d1a9f3083 2312 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 423:560d1a9f3083 2313 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 423:560d1a9f3083 2314 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 423:560d1a9f3083 2315
mbed_official 423:560d1a9f3083 2316 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 423:560d1a9f3083 2317 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 423:560d1a9f3083 2318 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 423:560d1a9f3083 2319 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 423:560d1a9f3083 2320
mbed_official 423:560d1a9f3083 2321 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 423:560d1a9f3083 2322 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 423:560d1a9f3083 2323 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 423:560d1a9f3083 2324 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 423:560d1a9f3083 2325 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 423:560d1a9f3083 2326
mbed_official 423:560d1a9f3083 2327 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 423:560d1a9f3083 2328 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 423:560d1a9f3083 2329 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 423:560d1a9f3083 2330 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 423:560d1a9f3083 2331 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 423:560d1a9f3083 2332
mbed_official 423:560d1a9f3083 2333 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 423:560d1a9f3083 2334 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 423:560d1a9f3083 2335 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 423:560d1a9f3083 2336 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 423:560d1a9f3083 2337 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 423:560d1a9f3083 2338 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 423:560d1a9f3083 2339
mbed_official 423:560d1a9f3083 2340 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 423:560d1a9f3083 2341 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 423:560d1a9f3083 2342 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 423:560d1a9f3083 2343 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 423:560d1a9f3083 2344
mbed_official 423:560d1a9f3083 2345 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 423:560d1a9f3083 2346 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 423:560d1a9f3083 2347 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 423:560d1a9f3083 2348 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 423:560d1a9f3083 2349 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 423:560d1a9f3083 2350
mbed_official 423:560d1a9f3083 2351 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 423:560d1a9f3083 2352 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 423:560d1a9f3083 2353 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 423:560d1a9f3083 2354 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 423:560d1a9f3083 2355 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 423:560d1a9f3083 2356
mbed_official 423:560d1a9f3083 2357 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 423:560d1a9f3083 2358 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 423:560d1a9f3083 2359 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 423:560d1a9f3083 2360 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 423:560d1a9f3083 2361 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 423:560d1a9f3083 2362 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 423:560d1a9f3083 2363
mbed_official 423:560d1a9f3083 2364 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 423:560d1a9f3083 2365 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 423:560d1a9f3083 2366 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 423:560d1a9f3083 2367 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 423:560d1a9f3083 2368
mbed_official 423:560d1a9f3083 2369 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 423:560d1a9f3083 2370 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 423:560d1a9f3083 2371 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 423:560d1a9f3083 2372 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 423:560d1a9f3083 2373 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 423:560d1a9f3083 2374
mbed_official 423:560d1a9f3083 2375 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 423:560d1a9f3083 2376 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 423:560d1a9f3083 2377 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 423:560d1a9f3083 2378 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 423:560d1a9f3083 2379 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 423:560d1a9f3083 2380
mbed_official 423:560d1a9f3083 2381 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 423:560d1a9f3083 2382 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 423:560d1a9f3083 2383 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 423:560d1a9f3083 2384 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 423:560d1a9f3083 2385 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 423:560d1a9f3083 2386
mbed_official 423:560d1a9f3083 2387 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 423:560d1a9f3083 2388 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 423:560d1a9f3083 2389 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 423:560d1a9f3083 2390 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 423:560d1a9f3083 2391
mbed_official 423:560d1a9f3083 2392 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 423:560d1a9f3083 2393 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 423:560d1a9f3083 2394 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 423:560d1a9f3083 2395 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 423:560d1a9f3083 2396 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 423:560d1a9f3083 2397
mbed_official 423:560d1a9f3083 2398 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 423:560d1a9f3083 2399 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 423:560d1a9f3083 2400 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 423:560d1a9f3083 2401 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 423:560d1a9f3083 2402 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 423:560d1a9f3083 2403
mbed_official 423:560d1a9f3083 2404 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 423:560d1a9f3083 2405 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 423:560d1a9f3083 2406 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 423:560d1a9f3083 2407 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 423:560d1a9f3083 2408 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 423:560d1a9f3083 2409
mbed_official 423:560d1a9f3083 2410 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 423:560d1a9f3083 2411 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 423:560d1a9f3083 2412 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 423:560d1a9f3083 2413 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 423:560d1a9f3083 2414
mbed_official 423:560d1a9f3083 2415 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 423:560d1a9f3083 2416 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 423:560d1a9f3083 2417 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 423:560d1a9f3083 2418 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 423:560d1a9f3083 2419 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 423:560d1a9f3083 2420
mbed_official 423:560d1a9f3083 2421 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 423:560d1a9f3083 2422 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 423:560d1a9f3083 2423 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 423:560d1a9f3083 2424 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 423:560d1a9f3083 2425 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 423:560d1a9f3083 2426
mbed_official 423:560d1a9f3083 2427 /*!<CAN filter registers */
mbed_official 423:560d1a9f3083 2428 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 423:560d1a9f3083 2429 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
mbed_official 423:560d1a9f3083 2430
mbed_official 423:560d1a9f3083 2431 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 423:560d1a9f3083 2432 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
mbed_official 423:560d1a9f3083 2433 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 423:560d1a9f3083 2434 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 423:560d1a9f3083 2435 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 423:560d1a9f3083 2436 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 423:560d1a9f3083 2437 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 423:560d1a9f3083 2438 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 423:560d1a9f3083 2439 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 423:560d1a9f3083 2440 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 423:560d1a9f3083 2441 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 423:560d1a9f3083 2442 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 423:560d1a9f3083 2443 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 423:560d1a9f3083 2444 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 423:560d1a9f3083 2445 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 423:560d1a9f3083 2446 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 423:560d1a9f3083 2447
mbed_official 423:560d1a9f3083 2448 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 423:560d1a9f3083 2449 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
mbed_official 423:560d1a9f3083 2450 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 423:560d1a9f3083 2451 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 423:560d1a9f3083 2452 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 423:560d1a9f3083 2453 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 423:560d1a9f3083 2454 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 423:560d1a9f3083 2455 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 423:560d1a9f3083 2456 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 423:560d1a9f3083 2457 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 423:560d1a9f3083 2458 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 423:560d1a9f3083 2459 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 423:560d1a9f3083 2460 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 423:560d1a9f3083 2461 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 423:560d1a9f3083 2462 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 423:560d1a9f3083 2463 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 423:560d1a9f3083 2464
mbed_official 423:560d1a9f3083 2465 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 423:560d1a9f3083 2466 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
mbed_official 423:560d1a9f3083 2467 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 423:560d1a9f3083 2468 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 423:560d1a9f3083 2469 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 423:560d1a9f3083 2470 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 423:560d1a9f3083 2471 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 423:560d1a9f3083 2472 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 423:560d1a9f3083 2473 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 423:560d1a9f3083 2474 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 423:560d1a9f3083 2475 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 423:560d1a9f3083 2476 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 423:560d1a9f3083 2477 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 423:560d1a9f3083 2478 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 423:560d1a9f3083 2479 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 423:560d1a9f3083 2480 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 423:560d1a9f3083 2481
mbed_official 423:560d1a9f3083 2482 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 423:560d1a9f3083 2483 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
mbed_official 423:560d1a9f3083 2484 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
mbed_official 423:560d1a9f3083 2485 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
mbed_official 423:560d1a9f3083 2486 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
mbed_official 423:560d1a9f3083 2487 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
mbed_official 423:560d1a9f3083 2488 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
mbed_official 423:560d1a9f3083 2489 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
mbed_official 423:560d1a9f3083 2490 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
mbed_official 423:560d1a9f3083 2491 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
mbed_official 423:560d1a9f3083 2492 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
mbed_official 423:560d1a9f3083 2493 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
mbed_official 423:560d1a9f3083 2494 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
mbed_official 423:560d1a9f3083 2495 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
mbed_official 423:560d1a9f3083 2496 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
mbed_official 423:560d1a9f3083 2497 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
mbed_official 423:560d1a9f3083 2498
mbed_official 423:560d1a9f3083 2499 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 423:560d1a9f3083 2500 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2501 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2502 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2503 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2504 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2505 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2506 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2507 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2508 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2509 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2510 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2511 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2512 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2513 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2514 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2515 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2516 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2517 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2518 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2519 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2520 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2521 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2522 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2523 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2524 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2525 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2526 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2527 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2528 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2529 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2530 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2531 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2532
mbed_official 423:560d1a9f3083 2533 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 423:560d1a9f3083 2534 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2535 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2536 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2537 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2538 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2539 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2540 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2541 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2542 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2543 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2544 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2545 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2546 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2547 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2548 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2549 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2550 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2551 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2552 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2553 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2554 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2555 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2556 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2557 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2558 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2559 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2560 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2561 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2562 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2563 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2564 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2565 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2566
mbed_official 423:560d1a9f3083 2567 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 423:560d1a9f3083 2568 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2569 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2570 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2571 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2572 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2573 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2574 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2575 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2576 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2577 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2578 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2579 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2580 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2581 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2582 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2583 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2584 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2585 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2586 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2587 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2588 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2589 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2590 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2591 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2592 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2593 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2594 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2595 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2596 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2597 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2598 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2599 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2600
mbed_official 423:560d1a9f3083 2601 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 423:560d1a9f3083 2602 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2603 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2604 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2605 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2606 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2607 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2608 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2609 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2610 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2611 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2612 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2613 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2614 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2615 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2616 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2617 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2618 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2619 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2620 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2621 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2622 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2623 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2624 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2625 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2626 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2627 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2628 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2629 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2630 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2631 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2632 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2633 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2634
mbed_official 423:560d1a9f3083 2635 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 423:560d1a9f3083 2636 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2637 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2638 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2639 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2640 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2641 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2642 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2643 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2644 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2645 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2646 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2647 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2648 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2649 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2650 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2651 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2652 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2653 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2654 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2655 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2656 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2657 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2658 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2659 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2660 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2661 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2662 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2663 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2664 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2665 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2666 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2667 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2668
mbed_official 423:560d1a9f3083 2669 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 423:560d1a9f3083 2670 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2671 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2672 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2673 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2674 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2675 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2676 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2677 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2678 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2679 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2680 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2681 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2682 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2683 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2684 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2685 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2686 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2687 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2688 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2689 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2690 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2691 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2692 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2693 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2694 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2695 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2696 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2697 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2698 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2699 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2700 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2701 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2702
mbed_official 423:560d1a9f3083 2703 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 423:560d1a9f3083 2704 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2705 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2706 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2707 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2708 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2709 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2710 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2711 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2712 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2713 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2714 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2715 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2716 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2717 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2718 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2719 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2720 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2721 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2722 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2723 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2724 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2725 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2726 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2727 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2728 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2729 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2730 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2731 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2732 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2733 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2734 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2735 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2736
mbed_official 423:560d1a9f3083 2737 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 423:560d1a9f3083 2738 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2739 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2740 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2741 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2742 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2743 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2744 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2745 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2746 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2747 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2748 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2749 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2750 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2751 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2752 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2753 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2754 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2755 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2756 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2757 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2758 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2759 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2760 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2761 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2762 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2763 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2764 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2765 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2766 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2767 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2768 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2769 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2770
mbed_official 423:560d1a9f3083 2771 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 423:560d1a9f3083 2772 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2773 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2774 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2775 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2776 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2777 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2778 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2779 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2780 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2781 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2782 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2783 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2784 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2785 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2786 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2787 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2788 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2789 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2790 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2791 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2792 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2793 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2794 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2795 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2796 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2797 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2798 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2799 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2800 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2801 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2802 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2803 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2804
mbed_official 423:560d1a9f3083 2805 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 423:560d1a9f3083 2806 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2807 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2808 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2809 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2810 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2811 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2812 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2813 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2814 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2815 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2816 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2817 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2818 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2819 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2820 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2821 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2822 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2823 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2824 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2825 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2826 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2827 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2828 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2829 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2830 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2831 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2832 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2833 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2834 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2835 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2836 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2837 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2838
mbed_official 423:560d1a9f3083 2839 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 423:560d1a9f3083 2840 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2841 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2842 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2843 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2844 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2845 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2846 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2847 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2848 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2849 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2850 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2851 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2852 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2853 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2854 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2855 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2856 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2857 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2858 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2859 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2860 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2861 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2862 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2863 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2864 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2865 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2866 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2867 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2868 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2869 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2870 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2871 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2872
mbed_official 423:560d1a9f3083 2873 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 423:560d1a9f3083 2874 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2875 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2876 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2877 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2878 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2879 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2880 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2881 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2882 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2883 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2884 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2885 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2886 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2887 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2888 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2889 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2890 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2891 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2892 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2893 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2894 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2895 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2896 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2897 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2898 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2899 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2900 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2901 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2902 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2903 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2904 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2905 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2906
mbed_official 423:560d1a9f3083 2907 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 423:560d1a9f3083 2908 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2909 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2910 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2911 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2912 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2913 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2914 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2915 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2916 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2917 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2918 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2919 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2920 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2921 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2922 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2923 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2924 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2925 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2926 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2927 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2928 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2929 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2930 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2931 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2932 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2933 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2934 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2935 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2936 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2937 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2938 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2939 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2940
mbed_official 423:560d1a9f3083 2941 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 423:560d1a9f3083 2942 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2943 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2944 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2945 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2946 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2947 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2948 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2949 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2950 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2951 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2952 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2953 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2954 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2955 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2956 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2957 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2958 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2959 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2960 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2961 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2962 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2963 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2964 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2965 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 2966 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 2967 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 2968 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 2969 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 2970 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 2971 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 2972 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 2973 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 2974
mbed_official 423:560d1a9f3083 2975 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 423:560d1a9f3083 2976 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 2977 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 2978 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 2979 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 2980 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 2981 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 2982 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 2983 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 2984 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 2985 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 2986 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 2987 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 2988 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 2989 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 2990 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 2991 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 2992 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 2993 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 2994 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 2995 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 2996 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 2997 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 2998 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 2999 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3000 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3001 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3002 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3003 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3004 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3005 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3006 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3007 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3008
mbed_official 423:560d1a9f3083 3009 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 423:560d1a9f3083 3010 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3011 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3012 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3013 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3014 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3015 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3016 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3017 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3018 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3019 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3020 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3021 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3022 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3023 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3024 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3025 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3026 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3027 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3028 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3029 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3030 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3031 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3032 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3033 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3034 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3035 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3036 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3037 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3038 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3039 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3040 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3041 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3042
mbed_official 423:560d1a9f3083 3043 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 423:560d1a9f3083 3044 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3045 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3046 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3047 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3048 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3049 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3050 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3051 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3052 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3053 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3054 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3055 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3056 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3057 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3058 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3059 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3060 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3061 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3062 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3063 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3064 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3065 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3066 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3067 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3068 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3069 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3070 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3071 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3072 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3073 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3074 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3075 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3076
mbed_official 423:560d1a9f3083 3077 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 423:560d1a9f3083 3078 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3079 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3080 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3081 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3082 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3083 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3084 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3085 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3086 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3087 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3088 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3089 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3090 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3091 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3092 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3093 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3094 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3095 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3096 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3097 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3098 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3099 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3100 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3101 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3102 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3103 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3104 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3105 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3106 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3107 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3108 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3109 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3110
mbed_official 423:560d1a9f3083 3111 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 423:560d1a9f3083 3112 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3113 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3114 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3115 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3116 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3117 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3118 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3119 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3120 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3121 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3122 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3123 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3124 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3125 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3126 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3127 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3128 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3129 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3130 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3131 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3132 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3133 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3134 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3135 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3136 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3137 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3138 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3139 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3140 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3141 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3142 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3143 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3144
mbed_official 423:560d1a9f3083 3145 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 423:560d1a9f3083 3146 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3147 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3148 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3149 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3150 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3151 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3152 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3153 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3154 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3155 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3156 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3157 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3158 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3159 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3160 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3161 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3162 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3163 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3164 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3165 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3166 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3167 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3168 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3169 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3170 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3171 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3172 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3173 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3174 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3175 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3176 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3177 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3178
mbed_official 423:560d1a9f3083 3179 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 423:560d1a9f3083 3180 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3181 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3182 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3183 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3184 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3185 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3186 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3187 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3188 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3189 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3190 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3191 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3192 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3193 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3194 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3195 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3196 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3197 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3198 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3199 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3200 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3201 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3202 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3203 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3204 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3205 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3206 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3207 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3208 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3209 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3210 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3211 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3212
mbed_official 423:560d1a9f3083 3213 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 423:560d1a9f3083 3214 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3215 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3216 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3217 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3218 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3219 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3220 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3221 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3222 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3223 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3224 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3225 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3226 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3227 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3228 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3229 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3230 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3231 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3232 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3233 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3234 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3235 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3236 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3237 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3238 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3239 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3240 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3241 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3242 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3243 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3244 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3245 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3246
mbed_official 423:560d1a9f3083 3247 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 423:560d1a9f3083 3248 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3249 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3250 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3251 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3252 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3253 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3254 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3255 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3256 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3257 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3258 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3259 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3260 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3261 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3262 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3263 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3264 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3265 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3266 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3267 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3268 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3269 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3270 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3271 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3272 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3273 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3274 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3275 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3276 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3277 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3278 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3279 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3280
mbed_official 423:560d1a9f3083 3281 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 423:560d1a9f3083 3282 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3283 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3284 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3285 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3286 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3287 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3288 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3289 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3290 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3291 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3292 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3293 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3294 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3295 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3296 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3297 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3298 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3299 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3300 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3301 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3302 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3303 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3304 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3305 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3306 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3307 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3308 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3309 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3310 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3311 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3312 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3313 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3314
mbed_official 423:560d1a9f3083 3315 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 423:560d1a9f3083 3316 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3317 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3318 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3319 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3320 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3321 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3322 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3323 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3324 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3325 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3326 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3327 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3328 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3329 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3330 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3331 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3332 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3333 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3334 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3335 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3336 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3337 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3338 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3339 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3340 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3341 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3342 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3343 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3344 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3345 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3346 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3347 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3348
mbed_official 423:560d1a9f3083 3349 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 423:560d1a9f3083 3350 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3351 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3352 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3353 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3354 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3355 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3356 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3357 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3358 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3359 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3360 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3361 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3362 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3363 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3364 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3365 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3366 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3367 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3368 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3369 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3370 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3371 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3372 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3373 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3374 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3375 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3376 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3377 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3378 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3379 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3380 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3381 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3382
mbed_official 423:560d1a9f3083 3383 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 423:560d1a9f3083 3384 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3385 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3386 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3387 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3388 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3389 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3390 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3391 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3392 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3393 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3394 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3395 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3396 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3397 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3398 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3399 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3400 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3401 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3402 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3403 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3404 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3405 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3406 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3407 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3408 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3409 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3410 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3411 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3412 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3413 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3414 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3415 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3416
mbed_official 423:560d1a9f3083 3417 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 423:560d1a9f3083 3418 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 423:560d1a9f3083 3419 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 423:560d1a9f3083 3420 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 423:560d1a9f3083 3421 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 423:560d1a9f3083 3422 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 423:560d1a9f3083 3423 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 423:560d1a9f3083 3424 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 423:560d1a9f3083 3425 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 423:560d1a9f3083 3426 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 423:560d1a9f3083 3427 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 423:560d1a9f3083 3428 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 423:560d1a9f3083 3429 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 423:560d1a9f3083 3430 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 423:560d1a9f3083 3431 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 423:560d1a9f3083 3432 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 423:560d1a9f3083 3433 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 423:560d1a9f3083 3434 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 423:560d1a9f3083 3435 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 423:560d1a9f3083 3436 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 423:560d1a9f3083 3437 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 423:560d1a9f3083 3438 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 423:560d1a9f3083 3439 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 423:560d1a9f3083 3440 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 423:560d1a9f3083 3441 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 423:560d1a9f3083 3442 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 423:560d1a9f3083 3443 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 423:560d1a9f3083 3444 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 423:560d1a9f3083 3445 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 423:560d1a9f3083 3446 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 423:560d1a9f3083 3447 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 423:560d1a9f3083 3448 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 423:560d1a9f3083 3449 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 423:560d1a9f3083 3450
mbed_official 423:560d1a9f3083 3451 /******************************************************************************/
mbed_official 423:560d1a9f3083 3452 /* */
mbed_official 423:560d1a9f3083 3453 /* CRC calculation unit (CRC) */
mbed_official 423:560d1a9f3083 3454 /* */
mbed_official 423:560d1a9f3083 3455 /******************************************************************************/
mbed_official 423:560d1a9f3083 3456 /******************* Bit definition for CRC_DR register *********************/
mbed_official 423:560d1a9f3083 3457 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 423:560d1a9f3083 3458
mbed_official 423:560d1a9f3083 3459 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 423:560d1a9f3083 3460 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 423:560d1a9f3083 3461
mbed_official 423:560d1a9f3083 3462 /******************** Bit definition for CRC_CR register ********************/
mbed_official 423:560d1a9f3083 3463 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 423:560d1a9f3083 3464 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 423:560d1a9f3083 3465 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 423:560d1a9f3083 3466 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 423:560d1a9f3083 3467 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 423:560d1a9f3083 3468 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3469 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3470 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 423:560d1a9f3083 3471
mbed_official 423:560d1a9f3083 3472 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 423:560d1a9f3083 3473 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 423:560d1a9f3083 3474
mbed_official 423:560d1a9f3083 3475 /******************* Bit definition for CRC_POL register ********************/
mbed_official 423:560d1a9f3083 3476 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 423:560d1a9f3083 3477
mbed_official 423:560d1a9f3083 3478 /******************************************************************************/
mbed_official 423:560d1a9f3083 3479 /* */
mbed_official 423:560d1a9f3083 3480 /* Digital to Analog Converter (DAC) */
mbed_official 423:560d1a9f3083 3481 /* */
mbed_official 423:560d1a9f3083 3482 /******************************************************************************/
mbed_official 423:560d1a9f3083 3483 /******************** Bit definition for DAC_CR register ********************/
mbed_official 423:560d1a9f3083 3484 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 423:560d1a9f3083 3485 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 423:560d1a9f3083 3486 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 423:560d1a9f3083 3487
mbed_official 423:560d1a9f3083 3488 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 423:560d1a9f3083 3489 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3490 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3491 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 3492
mbed_official 423:560d1a9f3083 3493 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 423:560d1a9f3083 3494 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3495 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3496
mbed_official 423:560d1a9f3083 3497 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 423:560d1a9f3083 3498 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3499 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3500 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 3501 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 3502
mbed_official 423:560d1a9f3083 3503 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 423:560d1a9f3083 3504 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
mbed_official 423:560d1a9f3083 3505 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 423:560d1a9f3083 3506 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 423:560d1a9f3083 3507 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 423:560d1a9f3083 3508
mbed_official 423:560d1a9f3083 3509 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 423:560d1a9f3083 3510 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3511 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3512 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 3513
mbed_official 423:560d1a9f3083 3514 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 423:560d1a9f3083 3515 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3516 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3517
mbed_official 423:560d1a9f3083 3518 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 423:560d1a9f3083 3519 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3520 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3521 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 3522 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 3523
mbed_official 423:560d1a9f3083 3524 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 423:560d1a9f3083 3525 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
mbed_official 423:560d1a9f3083 3526
mbed_official 423:560d1a9f3083 3527 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 423:560d1a9f3083 3528 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 423:560d1a9f3083 3529 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 423:560d1a9f3083 3530
mbed_official 423:560d1a9f3083 3531 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 423:560d1a9f3083 3532 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 423:560d1a9f3083 3533
mbed_official 423:560d1a9f3083 3534 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 423:560d1a9f3083 3535 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 423:560d1a9f3083 3536
mbed_official 423:560d1a9f3083 3537 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 423:560d1a9f3083 3538 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 423:560d1a9f3083 3539
mbed_official 423:560d1a9f3083 3540 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 423:560d1a9f3083 3541 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 423:560d1a9f3083 3542
mbed_official 423:560d1a9f3083 3543 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 423:560d1a9f3083 3544 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 423:560d1a9f3083 3545
mbed_official 423:560d1a9f3083 3546 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 423:560d1a9f3083 3547 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 423:560d1a9f3083 3548
mbed_official 423:560d1a9f3083 3549 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 423:560d1a9f3083 3550 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 423:560d1a9f3083 3551 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 423:560d1a9f3083 3552
mbed_official 423:560d1a9f3083 3553 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 423:560d1a9f3083 3554 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 423:560d1a9f3083 3555 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 423:560d1a9f3083 3556
mbed_official 423:560d1a9f3083 3557 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 423:560d1a9f3083 3558 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 423:560d1a9f3083 3559 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 423:560d1a9f3083 3560
mbed_official 423:560d1a9f3083 3561 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 423:560d1a9f3083 3562 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 423:560d1a9f3083 3563
mbed_official 423:560d1a9f3083 3564 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 423:560d1a9f3083 3565 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 423:560d1a9f3083 3566
mbed_official 423:560d1a9f3083 3567 /******************** Bit definition for DAC_SR register ********************/
mbed_official 423:560d1a9f3083 3568 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 423:560d1a9f3083 3569 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 423:560d1a9f3083 3570
mbed_official 423:560d1a9f3083 3571 /******************************************************************************/
mbed_official 423:560d1a9f3083 3572 /* */
mbed_official 423:560d1a9f3083 3573 /* Debug MCU (DBGMCU) */
mbed_official 423:560d1a9f3083 3574 /* */
mbed_official 423:560d1a9f3083 3575 /******************************************************************************/
mbed_official 423:560d1a9f3083 3576 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 423:560d1a9f3083 3577 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 423:560d1a9f3083 3578 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 423:560d1a9f3083 3579
mbed_official 423:560d1a9f3083 3580 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 423:560d1a9f3083 3581 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 3582 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 3583 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 3584 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 3585
mbed_official 423:560d1a9f3083 3586 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 423:560d1a9f3083 3587 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 423:560d1a9f3083 3588 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 423:560d1a9f3083 3589
mbed_official 423:560d1a9f3083 3590 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 423:560d1a9f3083 3591 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 3592 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 3593 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 3594 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 3595 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 3596 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 3597 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 3598 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 3599 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 3600 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 3601 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 3602 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 3603
mbed_official 423:560d1a9f3083 3604 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 423:560d1a9f3083 3605 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 3606 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 3607 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 3608 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 3609 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 3610 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 3611
mbed_official 423:560d1a9f3083 3612 /******************************************************************************/
mbed_official 423:560d1a9f3083 3613 /* */
mbed_official 423:560d1a9f3083 3614 /* DMA Controller (DMA) */
mbed_official 423:560d1a9f3083 3615 /* */
mbed_official 423:560d1a9f3083 3616 /******************************************************************************/
mbed_official 423:560d1a9f3083 3617 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 423:560d1a9f3083 3618 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 423:560d1a9f3083 3619 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3620 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 423:560d1a9f3083 3621 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 423:560d1a9f3083 3622 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 423:560d1a9f3083 3623 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3624 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 423:560d1a9f3083 3625 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 423:560d1a9f3083 3626 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 423:560d1a9f3083 3627 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3628 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 423:560d1a9f3083 3629 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 423:560d1a9f3083 3630 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 423:560d1a9f3083 3631 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3632 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 423:560d1a9f3083 3633 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 423:560d1a9f3083 3634 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 423:560d1a9f3083 3635 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3636 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 423:560d1a9f3083 3637 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 423:560d1a9f3083 3638 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 423:560d1a9f3083 3639 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3640 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 423:560d1a9f3083 3641 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 423:560d1a9f3083 3642 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 423:560d1a9f3083 3643 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 423:560d1a9f3083 3644 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 423:560d1a9f3083 3645 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 423:560d1a9f3083 3646
mbed_official 423:560d1a9f3083 3647 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 423:560d1a9f3083 3648 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 423:560d1a9f3083 3649 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3650 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 423:560d1a9f3083 3651 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 423:560d1a9f3083 3652 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 423:560d1a9f3083 3653 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3654 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 423:560d1a9f3083 3655 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 423:560d1a9f3083 3656 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 423:560d1a9f3083 3657 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3658 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 423:560d1a9f3083 3659 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 423:560d1a9f3083 3660 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 423:560d1a9f3083 3661 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3662 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 423:560d1a9f3083 3663 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 423:560d1a9f3083 3664 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 423:560d1a9f3083 3665 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3666 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 423:560d1a9f3083 3667 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 423:560d1a9f3083 3668 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 423:560d1a9f3083 3669 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3670 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 423:560d1a9f3083 3671 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 423:560d1a9f3083 3672 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 423:560d1a9f3083 3673 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 423:560d1a9f3083 3674 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 423:560d1a9f3083 3675 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 423:560d1a9f3083 3676
mbed_official 423:560d1a9f3083 3677 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 423:560d1a9f3083 3678 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 423:560d1a9f3083 3679 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 423:560d1a9f3083 3680 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 423:560d1a9f3083 3681 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 423:560d1a9f3083 3682 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 423:560d1a9f3083 3683 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 423:560d1a9f3083 3684 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 423:560d1a9f3083 3685 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 423:560d1a9f3083 3686
mbed_official 423:560d1a9f3083 3687 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 423:560d1a9f3083 3688 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3689 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3690
mbed_official 423:560d1a9f3083 3691 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 423:560d1a9f3083 3692 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3693 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3694
mbed_official 423:560d1a9f3083 3695 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 423:560d1a9f3083 3696 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3697 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3698
mbed_official 423:560d1a9f3083 3699 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 423:560d1a9f3083 3700
mbed_official 423:560d1a9f3083 3701 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 423:560d1a9f3083 3702 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 423:560d1a9f3083 3703
mbed_official 423:560d1a9f3083 3704 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 423:560d1a9f3083 3705 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 423:560d1a9f3083 3706
mbed_official 423:560d1a9f3083 3707 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 423:560d1a9f3083 3708 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 423:560d1a9f3083 3709
mbed_official 423:560d1a9f3083 3710 /******************************************************************************/
mbed_official 423:560d1a9f3083 3711 /* */
mbed_official 423:560d1a9f3083 3712 /* External Interrupt/Event Controller (EXTI) */
mbed_official 423:560d1a9f3083 3713 /* */
mbed_official 423:560d1a9f3083 3714 /******************************************************************************/
mbed_official 423:560d1a9f3083 3715 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
mbed_official 423:560d1a9f3083 3716 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 423:560d1a9f3083 3717 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 423:560d1a9f3083 3718 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 423:560d1a9f3083 3719 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 423:560d1a9f3083 3720 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 423:560d1a9f3083 3721 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 423:560d1a9f3083 3722 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 423:560d1a9f3083 3723 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 423:560d1a9f3083 3724 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 423:560d1a9f3083 3725 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 423:560d1a9f3083 3726 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 423:560d1a9f3083 3727 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 423:560d1a9f3083 3728 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 423:560d1a9f3083 3729 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 423:560d1a9f3083 3730 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 423:560d1a9f3083 3731 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 423:560d1a9f3083 3732 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 423:560d1a9f3083 3733 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 423:560d1a9f3083 3734 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 423:560d1a9f3083 3735 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 423:560d1a9f3083 3736 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 423:560d1a9f3083 3737 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 423:560d1a9f3083 3738 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 423:560d1a9f3083 3739 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 423:560d1a9f3083 3740 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
mbed_official 423:560d1a9f3083 3741 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 423:560d1a9f3083 3742 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 423:560d1a9f3083 3743 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 423:560d1a9f3083 3744 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 423:560d1a9f3083 3745
mbed_official 423:560d1a9f3083 3746 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
mbed_official 423:560d1a9f3083 3747 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 423:560d1a9f3083 3748 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 423:560d1a9f3083 3749 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 423:560d1a9f3083 3750 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 423:560d1a9f3083 3751 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 423:560d1a9f3083 3752 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 423:560d1a9f3083 3753 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 423:560d1a9f3083 3754 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 423:560d1a9f3083 3755 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 423:560d1a9f3083 3756 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 423:560d1a9f3083 3757 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 423:560d1a9f3083 3758 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 423:560d1a9f3083 3759 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 423:560d1a9f3083 3760 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 423:560d1a9f3083 3761 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 423:560d1a9f3083 3762 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 423:560d1a9f3083 3763 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 423:560d1a9f3083 3764 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 423:560d1a9f3083 3765 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 423:560d1a9f3083 3766 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 423:560d1a9f3083 3767 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 423:560d1a9f3083 3768 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 423:560d1a9f3083 3769 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 423:560d1a9f3083 3770 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 423:560d1a9f3083 3771 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
mbed_official 423:560d1a9f3083 3772 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 423:560d1a9f3083 3773 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 423:560d1a9f3083 3774 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 423:560d1a9f3083 3775 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 423:560d1a9f3083 3776
mbed_official 423:560d1a9f3083 3777 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
mbed_official 423:560d1a9f3083 3778 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 423:560d1a9f3083 3779 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 423:560d1a9f3083 3780 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 423:560d1a9f3083 3781 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 423:560d1a9f3083 3782 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 423:560d1a9f3083 3783 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 423:560d1a9f3083 3784 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 423:560d1a9f3083 3785 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 423:560d1a9f3083 3786 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 423:560d1a9f3083 3787 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 423:560d1a9f3083 3788 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 423:560d1a9f3083 3789 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 423:560d1a9f3083 3790 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 423:560d1a9f3083 3791 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 423:560d1a9f3083 3792 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 423:560d1a9f3083 3793 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 423:560d1a9f3083 3794 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 423:560d1a9f3083 3795 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 423:560d1a9f3083 3796 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 423:560d1a9f3083 3797 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 423:560d1a9f3083 3798 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 423:560d1a9f3083 3799 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 423:560d1a9f3083 3800 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 423:560d1a9f3083 3801 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 423:560d1a9f3083 3802 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
mbed_official 423:560d1a9f3083 3803 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
mbed_official 423:560d1a9f3083 3804 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
mbed_official 423:560d1a9f3083 3805 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
mbed_official 423:560d1a9f3083 3806 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
mbed_official 423:560d1a9f3083 3807
mbed_official 423:560d1a9f3083 3808 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
mbed_official 423:560d1a9f3083 3809 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 423:560d1a9f3083 3810 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 423:560d1a9f3083 3811 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 423:560d1a9f3083 3812 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 423:560d1a9f3083 3813 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 423:560d1a9f3083 3814 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 423:560d1a9f3083 3815 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 423:560d1a9f3083 3816 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 423:560d1a9f3083 3817 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 423:560d1a9f3083 3818 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 423:560d1a9f3083 3819 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 423:560d1a9f3083 3820 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 423:560d1a9f3083 3821 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 423:560d1a9f3083 3822 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 423:560d1a9f3083 3823 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 423:560d1a9f3083 3824 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 423:560d1a9f3083 3825 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 423:560d1a9f3083 3826 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 423:560d1a9f3083 3827 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 423:560d1a9f3083 3828 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 423:560d1a9f3083 3829 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 423:560d1a9f3083 3830 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 423:560d1a9f3083 3831 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 423:560d1a9f3083 3832 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 423:560d1a9f3083 3833 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
mbed_official 423:560d1a9f3083 3834 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
mbed_official 423:560d1a9f3083 3835 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
mbed_official 423:560d1a9f3083 3836 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
mbed_official 423:560d1a9f3083 3837 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
mbed_official 423:560d1a9f3083 3838
mbed_official 423:560d1a9f3083 3839 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
mbed_official 423:560d1a9f3083 3840 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 423:560d1a9f3083 3841 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 423:560d1a9f3083 3842 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 423:560d1a9f3083 3843 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 423:560d1a9f3083 3844 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 423:560d1a9f3083 3845 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 423:560d1a9f3083 3846 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 423:560d1a9f3083 3847 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 423:560d1a9f3083 3848 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 423:560d1a9f3083 3849 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 423:560d1a9f3083 3850 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 423:560d1a9f3083 3851 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 423:560d1a9f3083 3852 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 423:560d1a9f3083 3853 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 423:560d1a9f3083 3854 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 423:560d1a9f3083 3855 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 423:560d1a9f3083 3856 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 423:560d1a9f3083 3857 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 423:560d1a9f3083 3858 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 423:560d1a9f3083 3859 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 423:560d1a9f3083 3860 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 423:560d1a9f3083 3861 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 423:560d1a9f3083 3862 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 423:560d1a9f3083 3863 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 423:560d1a9f3083 3864 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
mbed_official 423:560d1a9f3083 3865 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
mbed_official 423:560d1a9f3083 3866 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
mbed_official 423:560d1a9f3083 3867 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
mbed_official 423:560d1a9f3083 3868 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
mbed_official 423:560d1a9f3083 3869
mbed_official 423:560d1a9f3083 3870 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
mbed_official 423:560d1a9f3083 3871 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 423:560d1a9f3083 3872 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 423:560d1a9f3083 3873 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 423:560d1a9f3083 3874 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 423:560d1a9f3083 3875 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 423:560d1a9f3083 3876 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 423:560d1a9f3083 3877 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 423:560d1a9f3083 3878 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 423:560d1a9f3083 3879 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 423:560d1a9f3083 3880 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 423:560d1a9f3083 3881 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 423:560d1a9f3083 3882 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 423:560d1a9f3083 3883 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 423:560d1a9f3083 3884 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 423:560d1a9f3083 3885 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 423:560d1a9f3083 3886 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 423:560d1a9f3083 3887 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 423:560d1a9f3083 3888 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 423:560d1a9f3083 3889 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 423:560d1a9f3083 3890 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 423:560d1a9f3083 3891 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 423:560d1a9f3083 3892 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 423:560d1a9f3083 3893 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 423:560d1a9f3083 3894 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 423:560d1a9f3083 3895 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
mbed_official 423:560d1a9f3083 3896 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
mbed_official 423:560d1a9f3083 3897 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
mbed_official 423:560d1a9f3083 3898 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
mbed_official 423:560d1a9f3083 3899 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
mbed_official 423:560d1a9f3083 3900
mbed_official 423:560d1a9f3083 3901 /******************************************************************************/
mbed_official 423:560d1a9f3083 3902 /* */
mbed_official 423:560d1a9f3083 3903 /* FLASH */
mbed_official 423:560d1a9f3083 3904 /* */
mbed_official 423:560d1a9f3083 3905 /******************************************************************************/
mbed_official 423:560d1a9f3083 3906 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 423:560d1a9f3083 3907 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
mbed_official 423:560d1a9f3083 3908 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 3909 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 3910 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 3911
mbed_official 423:560d1a9f3083 3912 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
mbed_official 423:560d1a9f3083 3913 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 423:560d1a9f3083 3914 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 423:560d1a9f3083 3915
mbed_official 423:560d1a9f3083 3916 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 423:560d1a9f3083 3917 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 423:560d1a9f3083 3918
mbed_official 423:560d1a9f3083 3919 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
mbed_official 423:560d1a9f3083 3920 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
mbed_official 423:560d1a9f3083 3921 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
mbed_official 423:560d1a9f3083 3922
mbed_official 423:560d1a9f3083 3923 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 423:560d1a9f3083 3924 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 423:560d1a9f3083 3925
mbed_official 423:560d1a9f3083 3926 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
mbed_official 423:560d1a9f3083 3927 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
mbed_official 423:560d1a9f3083 3928
mbed_official 423:560d1a9f3083 3929 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 423:560d1a9f3083 3930 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 423:560d1a9f3083 3931 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 423:560d1a9f3083 3932 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 423:560d1a9f3083 3933 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 423:560d1a9f3083 3934
mbed_official 423:560d1a9f3083 3935 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 423:560d1a9f3083 3936 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 423:560d1a9f3083 3937 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 423:560d1a9f3083 3938 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 423:560d1a9f3083 3939 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 423:560d1a9f3083 3940 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 423:560d1a9f3083 3941 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 423:560d1a9f3083 3942 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 423:560d1a9f3083 3943 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 423:560d1a9f3083 3944 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 423:560d1a9f3083 3945 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 423:560d1a9f3083 3946 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
mbed_official 423:560d1a9f3083 3947
mbed_official 423:560d1a9f3083 3948 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 423:560d1a9f3083 3949 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 423:560d1a9f3083 3950
mbed_official 423:560d1a9f3083 3951 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 423:560d1a9f3083 3952 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 423:560d1a9f3083 3953 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
mbed_official 423:560d1a9f3083 3954 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 423:560d1a9f3083 3955 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
mbed_official 423:560d1a9f3083 3956
mbed_official 423:560d1a9f3083 3957 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
mbed_official 423:560d1a9f3083 3958 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 423:560d1a9f3083 3959 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 423:560d1a9f3083 3960 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 423:560d1a9f3083 3961 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 423:560d1a9f3083 3962 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
mbed_official 423:560d1a9f3083 3963 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
mbed_official 423:560d1a9f3083 3964
mbed_official 423:560d1a9f3083 3965 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 423:560d1a9f3083 3966 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 423:560d1a9f3083 3967
mbed_official 423:560d1a9f3083 3968 /*----------------------------------------------------------------------------*/
mbed_official 423:560d1a9f3083 3969
mbed_official 423:560d1a9f3083 3970 /****************** Bit definition for OB_RDP register **********************/
mbed_official 423:560d1a9f3083 3971 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 423:560d1a9f3083 3972 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 423:560d1a9f3083 3973
mbed_official 423:560d1a9f3083 3974 /****************** Bit definition for OB_USER register *********************/
mbed_official 423:560d1a9f3083 3975 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 423:560d1a9f3083 3976 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 423:560d1a9f3083 3977
mbed_official 423:560d1a9f3083 3978 /****************** Bit definition for FLASH_WRP0 register ******************/
mbed_official 423:560d1a9f3083 3979 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 423:560d1a9f3083 3980 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 423:560d1a9f3083 3981
mbed_official 423:560d1a9f3083 3982 /****************** Bit definition for FLASH_WRP1 register ******************/
mbed_official 423:560d1a9f3083 3983 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 423:560d1a9f3083 3984 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 423:560d1a9f3083 3985
mbed_official 423:560d1a9f3083 3986 /****************** Bit definition for FLASH_WRP2 register ******************/
mbed_official 423:560d1a9f3083 3987 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 423:560d1a9f3083 3988 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 423:560d1a9f3083 3989
mbed_official 423:560d1a9f3083 3990 /****************** Bit definition for FLASH_WRP3 register ******************/
mbed_official 423:560d1a9f3083 3991 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 423:560d1a9f3083 3992 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 423:560d1a9f3083 3993
mbed_official 423:560d1a9f3083 3994
mbed_official 423:560d1a9f3083 3995 /******************************************************************************/
mbed_official 423:560d1a9f3083 3996 /* */
mbed_official 423:560d1a9f3083 3997 /* Flexible Memory Controller */
mbed_official 423:560d1a9f3083 3998 /* */
mbed_official 423:560d1a9f3083 3999 /******************************************************************************/
mbed_official 423:560d1a9f3083 4000 /****************** Bit definition for FMC_BCR1 register *******************/
mbed_official 423:560d1a9f3083 4001 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 423:560d1a9f3083 4002 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 423:560d1a9f3083 4003
mbed_official 423:560d1a9f3083 4004 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 423:560d1a9f3083 4005 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4006 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4007
mbed_official 423:560d1a9f3083 4008 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 423:560d1a9f3083 4009 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4010 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4011
mbed_official 423:560d1a9f3083 4012 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 423:560d1a9f3083 4013 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 423:560d1a9f3083 4014 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 423:560d1a9f3083 4015 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 423:560d1a9f3083 4016 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 423:560d1a9f3083 4017 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 423:560d1a9f3083 4018 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 423:560d1a9f3083 4019 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 423:560d1a9f3083 4020 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 423:560d1a9f3083 4021 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 423:560d1a9f3083 4022 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
mbed_official 423:560d1a9f3083 4023
mbed_official 423:560d1a9f3083 4024 /****************** Bit definition for FMC_BCR2 register *******************/
mbed_official 423:560d1a9f3083 4025 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 423:560d1a9f3083 4026 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 423:560d1a9f3083 4027
mbed_official 423:560d1a9f3083 4028 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 423:560d1a9f3083 4029 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4030 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4031
mbed_official 423:560d1a9f3083 4032 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 423:560d1a9f3083 4033 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4034 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4035
mbed_official 423:560d1a9f3083 4036 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 423:560d1a9f3083 4037 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 423:560d1a9f3083 4038 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 423:560d1a9f3083 4039 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 423:560d1a9f3083 4040 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 423:560d1a9f3083 4041 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 423:560d1a9f3083 4042 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 423:560d1a9f3083 4043 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 423:560d1a9f3083 4044 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 423:560d1a9f3083 4045 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 423:560d1a9f3083 4046
mbed_official 423:560d1a9f3083 4047 /****************** Bit definition for FMC_BCR3 register *******************/
mbed_official 423:560d1a9f3083 4048 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 423:560d1a9f3083 4049 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 423:560d1a9f3083 4050
mbed_official 423:560d1a9f3083 4051 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 423:560d1a9f3083 4052 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4053 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4054
mbed_official 423:560d1a9f3083 4055 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 423:560d1a9f3083 4056 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4057 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4058
mbed_official 423:560d1a9f3083 4059 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 423:560d1a9f3083 4060 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 423:560d1a9f3083 4061 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 423:560d1a9f3083 4062 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 423:560d1a9f3083 4063 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 423:560d1a9f3083 4064 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 423:560d1a9f3083 4065 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 423:560d1a9f3083 4066 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 423:560d1a9f3083 4067 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 423:560d1a9f3083 4068 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 423:560d1a9f3083 4069
mbed_official 423:560d1a9f3083 4070 /****************** Bit definition for FMC_BCR4 register *******************/
mbed_official 423:560d1a9f3083 4071 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 423:560d1a9f3083 4072 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 423:560d1a9f3083 4073
mbed_official 423:560d1a9f3083 4074 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 423:560d1a9f3083 4075 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4076 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4077
mbed_official 423:560d1a9f3083 4078 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 423:560d1a9f3083 4079 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4080 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4081
mbed_official 423:560d1a9f3083 4082 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 423:560d1a9f3083 4083 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 423:560d1a9f3083 4084 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 423:560d1a9f3083 4085 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 423:560d1a9f3083 4086 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 423:560d1a9f3083 4087 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 423:560d1a9f3083 4088 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 423:560d1a9f3083 4089 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 423:560d1a9f3083 4090 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 423:560d1a9f3083 4091 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 423:560d1a9f3083 4092
mbed_official 423:560d1a9f3083 4093 /****************** Bit definition for FMC_BTR1 register ******************/
mbed_official 423:560d1a9f3083 4094 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4095 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4096 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4097 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4098 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4099
mbed_official 423:560d1a9f3083 4100 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4101 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4102 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4103 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4104 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4105
mbed_official 423:560d1a9f3083 4106 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4107 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4108 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4109 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4110 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4111 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4112 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4113 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4114 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4115
mbed_official 423:560d1a9f3083 4116 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 423:560d1a9f3083 4117 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4118 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4119 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4120 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4121
mbed_official 423:560d1a9f3083 4122 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4123 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4124 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4125 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4126 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4127
mbed_official 423:560d1a9f3083 4128 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4129 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4130 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4131 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4132 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4133
mbed_official 423:560d1a9f3083 4134 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4135 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4136 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4137
mbed_official 423:560d1a9f3083 4138 /****************** Bit definition for FMC_BTR2 register *******************/
mbed_official 423:560d1a9f3083 4139 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4140 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4141 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4142 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4143 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4144
mbed_official 423:560d1a9f3083 4145 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4146 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4147 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4148 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4149 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4150
mbed_official 423:560d1a9f3083 4151 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4152 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4153 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4154 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4155 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4156 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4157 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4158 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4159 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4160
mbed_official 423:560d1a9f3083 4161 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 423:560d1a9f3083 4162 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4163 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4164 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4165 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4166
mbed_official 423:560d1a9f3083 4167 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4168 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4169 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4170 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4171 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4172
mbed_official 423:560d1a9f3083 4173 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4174 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4175 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4176 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4177 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4178
mbed_official 423:560d1a9f3083 4179 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4180 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4181 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4182
mbed_official 423:560d1a9f3083 4183 /******************* Bit definition for FMC_BTR3 register *******************/
mbed_official 423:560d1a9f3083 4184 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4185 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4186 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4187 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4188 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4189
mbed_official 423:560d1a9f3083 4190 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4191 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4192 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4193 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4194 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4195
mbed_official 423:560d1a9f3083 4196 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4197 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4198 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4199 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4200 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4201 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4202 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4203 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4204 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4205
mbed_official 423:560d1a9f3083 4206 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 423:560d1a9f3083 4207 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4208 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4209 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4210 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4211
mbed_official 423:560d1a9f3083 4212 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4213 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4214 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4215 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4216 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4217
mbed_official 423:560d1a9f3083 4218 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4219 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4220 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4221 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4222 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4223
mbed_official 423:560d1a9f3083 4224 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4225 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4226 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4227
mbed_official 423:560d1a9f3083 4228 /****************** Bit definition for FMC_BTR4 register *******************/
mbed_official 423:560d1a9f3083 4229 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4230 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4231 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4232 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4233 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4234
mbed_official 423:560d1a9f3083 4235 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4236 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4237 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4238 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4239 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4240
mbed_official 423:560d1a9f3083 4241 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4242 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4243 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4244 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4245 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4246 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4247 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4248 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4249 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4250
mbed_official 423:560d1a9f3083 4251 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 423:560d1a9f3083 4252 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4253 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4254 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4255 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4256
mbed_official 423:560d1a9f3083 4257 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4258 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4259 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4260 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4261 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4262
mbed_official 423:560d1a9f3083 4263 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4264 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4265 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4266 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4267 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4268
mbed_official 423:560d1a9f3083 4269 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4270 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4271 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4272
mbed_official 423:560d1a9f3083 4273 /****************** Bit definition for FMC_BWTR1 register ******************/
mbed_official 423:560d1a9f3083 4274 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4275 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4276 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4277 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4278 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4279
mbed_official 423:560d1a9f3083 4280 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4281 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4282 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4283 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4284 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4285
mbed_official 423:560d1a9f3083 4286 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4287 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4288 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4289 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4290 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4291 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4292 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4293 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4294 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4295
mbed_official 423:560d1a9f3083 4296 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4297 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4298 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4299 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4300 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4301
mbed_official 423:560d1a9f3083 4302 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4303 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4304 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4305 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4306 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4307
mbed_official 423:560d1a9f3083 4308 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4309 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4310 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4311
mbed_official 423:560d1a9f3083 4312 /****************** Bit definition for FMC_BWTR2 register ******************/
mbed_official 423:560d1a9f3083 4313 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4314 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4315 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4316 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4317 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4318
mbed_official 423:560d1a9f3083 4319 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4320 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4321 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4322 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4323 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4324
mbed_official 423:560d1a9f3083 4325 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4326 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4327 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4328 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4329 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4330 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4331 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4332 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4333 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4334
mbed_official 423:560d1a9f3083 4335 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4336 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4337 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
mbed_official 423:560d1a9f3083 4338 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4339 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4340
mbed_official 423:560d1a9f3083 4341 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4342 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4343 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4344 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4345 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4346
mbed_official 423:560d1a9f3083 4347 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4348 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4349 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4350
mbed_official 423:560d1a9f3083 4351 /****************** Bit definition for FMC_BWTR3 register ******************/
mbed_official 423:560d1a9f3083 4352 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4353 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4354 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4355 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4356 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4357
mbed_official 423:560d1a9f3083 4358 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4359 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4360 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4361 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4362 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4363
mbed_official 423:560d1a9f3083 4364 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4365 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4366 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4367 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4368 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4369 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4370 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4371 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4372 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4373
mbed_official 423:560d1a9f3083 4374 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4375 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4376 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4377 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4378 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4379
mbed_official 423:560d1a9f3083 4380 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4381 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4382 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4383 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4384 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4385
mbed_official 423:560d1a9f3083 4386 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4387 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4388 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4389
mbed_official 423:560d1a9f3083 4390 /****************** Bit definition for FMC_BWTR4 register ******************/
mbed_official 423:560d1a9f3083 4391 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 423:560d1a9f3083 4392 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4393 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4394 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4395 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4396
mbed_official 423:560d1a9f3083 4397 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 423:560d1a9f3083 4398 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4399 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4400 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4401 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4402
mbed_official 423:560d1a9f3083 4403 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 423:560d1a9f3083 4404 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4405 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4406 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4407 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4408 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4409 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4410 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4411 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4412
mbed_official 423:560d1a9f3083 4413 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 423:560d1a9f3083 4414 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4415 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4416 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4417 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4418
mbed_official 423:560d1a9f3083 4419 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 423:560d1a9f3083 4420 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4421 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4422 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4423 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4424
mbed_official 423:560d1a9f3083 4425 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 423:560d1a9f3083 4426 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4427 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4428
mbed_official 423:560d1a9f3083 4429 /****************** Bit definition for FMC_PCR2 register *******************/
mbed_official 423:560d1a9f3083 4430 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 423:560d1a9f3083 4431 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 423:560d1a9f3083 4432 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 423:560d1a9f3083 4433
mbed_official 423:560d1a9f3083 4434 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 423:560d1a9f3083 4435 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4436 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4437
mbed_official 423:560d1a9f3083 4438 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 423:560d1a9f3083 4439
mbed_official 423:560d1a9f3083 4440 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 423:560d1a9f3083 4441 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4442 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4443 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4444 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4445
mbed_official 423:560d1a9f3083 4446 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 423:560d1a9f3083 4447 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4448 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4449 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4450 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4451
mbed_official 423:560d1a9f3083 4452 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
mbed_official 423:560d1a9f3083 4453 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4454 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4455 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4456
mbed_official 423:560d1a9f3083 4457 /****************** Bit definition for FMC_PCR3 register *******************/
mbed_official 423:560d1a9f3083 4458 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 423:560d1a9f3083 4459 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 423:560d1a9f3083 4460 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 423:560d1a9f3083 4461
mbed_official 423:560d1a9f3083 4462 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 423:560d1a9f3083 4463 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4464 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4465
mbed_official 423:560d1a9f3083 4466 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 423:560d1a9f3083 4467
mbed_official 423:560d1a9f3083 4468 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 423:560d1a9f3083 4469 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4470 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4471 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4472 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4473
mbed_official 423:560d1a9f3083 4474 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 423:560d1a9f3083 4475 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4476 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4477 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4478 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4479
mbed_official 423:560d1a9f3083 4480 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 423:560d1a9f3083 4481 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4482 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4483 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4484
mbed_official 423:560d1a9f3083 4485 /****************** Bit definition for FMC_PCR4 register *******************/
mbed_official 423:560d1a9f3083 4486 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 423:560d1a9f3083 4487 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 423:560d1a9f3083 4488 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 423:560d1a9f3083 4489
mbed_official 423:560d1a9f3083 4490 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 423:560d1a9f3083 4491 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4492 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4493
mbed_official 423:560d1a9f3083 4494 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 423:560d1a9f3083 4495
mbed_official 423:560d1a9f3083 4496 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 423:560d1a9f3083 4497 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4498 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4499 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4500 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4501
mbed_official 423:560d1a9f3083 4502 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 423:560d1a9f3083 4503 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4504 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4505 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4506 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4507
mbed_official 423:560d1a9f3083 4508 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 423:560d1a9f3083 4509 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4510 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4511 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4512
mbed_official 423:560d1a9f3083 4513 /******************* Bit definition for FMC_SR2 register *******************/
mbed_official 423:560d1a9f3083 4514 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 423:560d1a9f3083 4515 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 423:560d1a9f3083 4516 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 423:560d1a9f3083 4517 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4518 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 423:560d1a9f3083 4519 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4520 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 423:560d1a9f3083 4521
mbed_official 423:560d1a9f3083 4522 /******************* Bit definition for FMC_SR3 register *******************/
mbed_official 423:560d1a9f3083 4523 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 423:560d1a9f3083 4524 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 423:560d1a9f3083 4525 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 423:560d1a9f3083 4526 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4527 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 423:560d1a9f3083 4528 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4529 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 423:560d1a9f3083 4530
mbed_official 423:560d1a9f3083 4531 /******************* Bit definition for FMC_SR4 register *******************/
mbed_official 423:560d1a9f3083 4532 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 423:560d1a9f3083 4533 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 423:560d1a9f3083 4534 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 423:560d1a9f3083 4535 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4536 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 423:560d1a9f3083 4537 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 423:560d1a9f3083 4538 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 423:560d1a9f3083 4539
mbed_official 423:560d1a9f3083 4540 /****************** Bit definition for FMC_PMEM2 register ******************/
mbed_official 423:560d1a9f3083 4541 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
mbed_official 423:560d1a9f3083 4542 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4543 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4544 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4545 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4546 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4547 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4548 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4549 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4550
mbed_official 423:560d1a9f3083 4551 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
mbed_official 423:560d1a9f3083 4552 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4553 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4554 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4555 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4556 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4557 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4558 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4559 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4560
mbed_official 423:560d1a9f3083 4561 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
mbed_official 423:560d1a9f3083 4562 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4563 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4564 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4565 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4566 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4567 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4568 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4569 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4570
mbed_official 423:560d1a9f3083 4571 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
mbed_official 423:560d1a9f3083 4572 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4573 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4574 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4575 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4576 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4577 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4578 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4579 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4580
mbed_official 423:560d1a9f3083 4581 /****************** Bit definition for FMC_PMEM3 register ******************/
mbed_official 423:560d1a9f3083 4582 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
mbed_official 423:560d1a9f3083 4583 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4584 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4585 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4586 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4587 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4588 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4589 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4590 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4591
mbed_official 423:560d1a9f3083 4592 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
mbed_official 423:560d1a9f3083 4593 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4594 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4595 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4596 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4597 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4598 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4599 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4600 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4601
mbed_official 423:560d1a9f3083 4602 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
mbed_official 423:560d1a9f3083 4603 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4604 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4605 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4606 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4607 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4608 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4609 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4610 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4611
mbed_official 423:560d1a9f3083 4612 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
mbed_official 423:560d1a9f3083 4613 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4614 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4615 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4616 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4617 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4618 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4619 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4620 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4621
mbed_official 423:560d1a9f3083 4622 /****************** Bit definition for FMC_PMEM4 register ******************/
mbed_official 423:560d1a9f3083 4623 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
mbed_official 423:560d1a9f3083 4624 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4625 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4626 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4627 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4628 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4629 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4630 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4631 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4632
mbed_official 423:560d1a9f3083 4633 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
mbed_official 423:560d1a9f3083 4634 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4635 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4636 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4637 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4638 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4639 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4640 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4641 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4642
mbed_official 423:560d1a9f3083 4643 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
mbed_official 423:560d1a9f3083 4644 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4645 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4646 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4647 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4648 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4649 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4650 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4651 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4652
mbed_official 423:560d1a9f3083 4653 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
mbed_official 423:560d1a9f3083 4654 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4655 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4656 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4657 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4658 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4659 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4660 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4661 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4662
mbed_official 423:560d1a9f3083 4663 /****************** Bit definition for FMC_PATT2 register ******************/
mbed_official 423:560d1a9f3083 4664 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
mbed_official 423:560d1a9f3083 4665 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4666 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4667 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4668 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4669 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4670 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4671 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4672 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4673
mbed_official 423:560d1a9f3083 4674 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
mbed_official 423:560d1a9f3083 4675 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4676 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4677 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4678 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4679 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4680 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4681 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4682 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4683
mbed_official 423:560d1a9f3083 4684 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
mbed_official 423:560d1a9f3083 4685 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4686 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4687 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4688 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4689 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4690 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4691 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4692 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4693
mbed_official 423:560d1a9f3083 4694 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
mbed_official 423:560d1a9f3083 4695 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4696 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4697 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4698 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4699 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4700 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4701 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4702 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4703
mbed_official 423:560d1a9f3083 4704 /****************** Bit definition for FMC_PATT3 register ******************/
mbed_official 423:560d1a9f3083 4705 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
mbed_official 423:560d1a9f3083 4706 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4707 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4708 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4709 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4710 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4711 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4712 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4713 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4714
mbed_official 423:560d1a9f3083 4715 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
mbed_official 423:560d1a9f3083 4716 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4717 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4718 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4719 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4720 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4721 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4722 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4723 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4724
mbed_official 423:560d1a9f3083 4725 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
mbed_official 423:560d1a9f3083 4726 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4727 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4728 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4729 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4730 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4731 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4732 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4733 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4734
mbed_official 423:560d1a9f3083 4735 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
mbed_official 423:560d1a9f3083 4736 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4737 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4738 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4739 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4740 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4741 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4742 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4743 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4744
mbed_official 423:560d1a9f3083 4745 /****************** Bit definition for FMC_PATT4 register ******************/
mbed_official 423:560d1a9f3083 4746 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
mbed_official 423:560d1a9f3083 4747 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4748 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4749 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4750 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4751 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4752 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4753 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4754 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4755
mbed_official 423:560d1a9f3083 4756 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
mbed_official 423:560d1a9f3083 4757 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4758 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4759 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4760 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4761 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4762 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4763 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4764 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4765
mbed_official 423:560d1a9f3083 4766 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
mbed_official 423:560d1a9f3083 4767 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4768 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4769 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4770 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4771 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4772 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4773 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4774 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4775
mbed_official 423:560d1a9f3083 4776 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
mbed_official 423:560d1a9f3083 4777 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4778 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4779 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4780 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4781 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4782 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4783 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4784 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4785
mbed_official 423:560d1a9f3083 4786 /****************** Bit definition for FMC_PIO4 register *******************/
mbed_official 423:560d1a9f3083 4787 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
mbed_official 423:560d1a9f3083 4788 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4789 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4790 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4791 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4792 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4793 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4794 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4795 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4796
mbed_official 423:560d1a9f3083 4797 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
mbed_official 423:560d1a9f3083 4798 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4799 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4800 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4801 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4802 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4803 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4804 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4805 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4806
mbed_official 423:560d1a9f3083 4807 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
mbed_official 423:560d1a9f3083 4808 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4809 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4810 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4811 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4812 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4813 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4814 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4815 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4816
mbed_official 423:560d1a9f3083 4817 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
mbed_official 423:560d1a9f3083 4818 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4819 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4820 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4821 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4822 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 4823 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 4824 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 4825 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 4826
mbed_official 423:560d1a9f3083 4827 /****************** Bit definition for FMC_ECCR2 register ******************/
mbed_official 423:560d1a9f3083 4828 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 423:560d1a9f3083 4829
mbed_official 423:560d1a9f3083 4830 /****************** Bit definition for FMC_ECCR3 register ******************/
mbed_official 423:560d1a9f3083 4831 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 423:560d1a9f3083 4832
mbed_official 423:560d1a9f3083 4833 /****************** Bit definition for FMC_SDCR1 register ******************/
mbed_official 423:560d1a9f3083 4834 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 423:560d1a9f3083 4835 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4836 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4837
mbed_official 423:560d1a9f3083 4838 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 423:560d1a9f3083 4839 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4840 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4841
mbed_official 423:560d1a9f3083 4842 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 423:560d1a9f3083 4843 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4844 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4845
mbed_official 423:560d1a9f3083 4846 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 423:560d1a9f3083 4847
mbed_official 423:560d1a9f3083 4848 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 423:560d1a9f3083 4849 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4850 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4851
mbed_official 423:560d1a9f3083 4852 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 423:560d1a9f3083 4853
mbed_official 423:560d1a9f3083 4854 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
mbed_official 423:560d1a9f3083 4855 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4856 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4857
mbed_official 423:560d1a9f3083 4858 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 423:560d1a9f3083 4859
mbed_official 423:560d1a9f3083 4860 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
mbed_official 423:560d1a9f3083 4861 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4862 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4863
mbed_official 423:560d1a9f3083 4864 /****************** Bit definition for FMC_SDCR2 register ******************/
mbed_official 423:560d1a9f3083 4865 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 423:560d1a9f3083 4866 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4867 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4868
mbed_official 423:560d1a9f3083 4869 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 423:560d1a9f3083 4870 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4871 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4872
mbed_official 423:560d1a9f3083 4873 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 423:560d1a9f3083 4874 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4875 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4876
mbed_official 423:560d1a9f3083 4877 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 423:560d1a9f3083 4878
mbed_official 423:560d1a9f3083 4879 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 423:560d1a9f3083 4880 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4881 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4882
mbed_official 423:560d1a9f3083 4883 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 423:560d1a9f3083 4884
mbed_official 423:560d1a9f3083 4885 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
mbed_official 423:560d1a9f3083 4886 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4887 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4888
mbed_official 423:560d1a9f3083 4889 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 423:560d1a9f3083 4890
mbed_official 423:560d1a9f3083 4891 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
mbed_official 423:560d1a9f3083 4892 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4893 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4894
mbed_official 423:560d1a9f3083 4895 /****************** Bit definition for FMC_SDTR1 register ******************/
mbed_official 423:560d1a9f3083 4896 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 423:560d1a9f3083 4897 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4898 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4899 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4900 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4901
mbed_official 423:560d1a9f3083 4902 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 423:560d1a9f3083 4903 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4904 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4905 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4906 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4907
mbed_official 423:560d1a9f3083 4908 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 423:560d1a9f3083 4909 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4910 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4911 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4912 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4913
mbed_official 423:560d1a9f3083 4914 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 423:560d1a9f3083 4915 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4916 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4917 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4918
mbed_official 423:560d1a9f3083 4919 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 423:560d1a9f3083 4920 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4921 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4922 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4923
mbed_official 423:560d1a9f3083 4924 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 423:560d1a9f3083 4925 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4926 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4927 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4928
mbed_official 423:560d1a9f3083 4929 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 423:560d1a9f3083 4930 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4931 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4932 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4933
mbed_official 423:560d1a9f3083 4934 /****************** Bit definition for FMC_SDTR2 register ******************/
mbed_official 423:560d1a9f3083 4935 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 423:560d1a9f3083 4936 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4937 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4938 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4939 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4940
mbed_official 423:560d1a9f3083 4941 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 423:560d1a9f3083 4942 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4943 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4944 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4945 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4946
mbed_official 423:560d1a9f3083 4947 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 423:560d1a9f3083 4948 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4949 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4950 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4951 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4952
mbed_official 423:560d1a9f3083 4953 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 423:560d1a9f3083 4954 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4955 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4956 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4957
mbed_official 423:560d1a9f3083 4958 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 423:560d1a9f3083 4959 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4960 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4961 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4962
mbed_official 423:560d1a9f3083 4963 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 423:560d1a9f3083 4964 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4965 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4966 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4967
mbed_official 423:560d1a9f3083 4968 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 423:560d1a9f3083 4969 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4970 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4971 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4972
mbed_official 423:560d1a9f3083 4973 /****************** Bit definition for FMC_SDCMR register ******************/
mbed_official 423:560d1a9f3083 4974 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
mbed_official 423:560d1a9f3083 4975 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4976 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4977 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4978
mbed_official 423:560d1a9f3083 4979 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
mbed_official 423:560d1a9f3083 4980
mbed_official 423:560d1a9f3083 4981 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
mbed_official 423:560d1a9f3083 4982
mbed_official 423:560d1a9f3083 4983 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
mbed_official 423:560d1a9f3083 4984 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 4985 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 4986 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 4987 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 4988
mbed_official 423:560d1a9f3083 4989 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
mbed_official 423:560d1a9f3083 4990
mbed_official 423:560d1a9f3083 4991 /****************** Bit definition for FMC_SDRTR register ******************/
mbed_official 423:560d1a9f3083 4992 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
mbed_official 423:560d1a9f3083 4993
mbed_official 423:560d1a9f3083 4994 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
mbed_official 423:560d1a9f3083 4995
mbed_official 423:560d1a9f3083 4996 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
mbed_official 423:560d1a9f3083 4997
mbed_official 423:560d1a9f3083 4998 /****************** Bit definition for FMC_SDSR register ******************/
mbed_official 423:560d1a9f3083 4999 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
mbed_official 423:560d1a9f3083 5000
mbed_official 423:560d1a9f3083 5001 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
mbed_official 423:560d1a9f3083 5002 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 5003 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 5004
mbed_official 423:560d1a9f3083 5005 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
mbed_official 423:560d1a9f3083 5006 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 5007 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 5008 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
mbed_official 423:560d1a9f3083 5009
mbed_official 423:560d1a9f3083 5010
mbed_official 423:560d1a9f3083 5011
mbed_official 423:560d1a9f3083 5012 /******************************************************************************/
mbed_official 423:560d1a9f3083 5013 /* */
mbed_official 423:560d1a9f3083 5014 /* General Purpose I/O (GPIO) */
mbed_official 423:560d1a9f3083 5015 /* */
mbed_official 423:560d1a9f3083 5016 /******************************************************************************/
mbed_official 423:560d1a9f3083 5017 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 423:560d1a9f3083 5018 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 423:560d1a9f3083 5019 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5020 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5021 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 423:560d1a9f3083 5022 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5023 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5024 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 423:560d1a9f3083 5025 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5026 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5027 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 423:560d1a9f3083 5028 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5029 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5030 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 423:560d1a9f3083 5031 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5032 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5033 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 423:560d1a9f3083 5034 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5035 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5036 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 423:560d1a9f3083 5037 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5038 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5039 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 423:560d1a9f3083 5040 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5041 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5042 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 423:560d1a9f3083 5043 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5044 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5045 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 423:560d1a9f3083 5046 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5047 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5048 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 5049 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5050 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5051 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 423:560d1a9f3083 5052 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5053 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 5054 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 423:560d1a9f3083 5055 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 5056 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 5057 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 423:560d1a9f3083 5058 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 5059 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 5060 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 423:560d1a9f3083 5061 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 5062 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 5063 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 423:560d1a9f3083 5064 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 5065 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 5066
mbed_official 423:560d1a9f3083 5067 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 423:560d1a9f3083 5068 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5069 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5070 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5071 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5072 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5073 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5074 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5075 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5076 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5077 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5078 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5079 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5080 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5081 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5082 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5083 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5084
mbed_official 423:560d1a9f3083 5085 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 423:560d1a9f3083 5086 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 423:560d1a9f3083 5087 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5088 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5089 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 423:560d1a9f3083 5090 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5091 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5092 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 423:560d1a9f3083 5093 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5094 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5095 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 423:560d1a9f3083 5096 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5097 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5098 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 423:560d1a9f3083 5099 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5100 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5101 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 423:560d1a9f3083 5102 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5103 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5104 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 423:560d1a9f3083 5105 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5106 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5107 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 423:560d1a9f3083 5108 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5109 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5110 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 423:560d1a9f3083 5111 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5112 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5113 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 423:560d1a9f3083 5114 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5115 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5116 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 5117 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5118 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5119 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 423:560d1a9f3083 5120 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5121 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 5122 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 423:560d1a9f3083 5123 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 5124 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 5125 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 423:560d1a9f3083 5126 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 5127 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 5128 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 423:560d1a9f3083 5129 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 5130 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 5131 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 423:560d1a9f3083 5132 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 5133 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 5134
mbed_official 423:560d1a9f3083 5135 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 423:560d1a9f3083 5136 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 423:560d1a9f3083 5137 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5138 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5139 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 423:560d1a9f3083 5140 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5141 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5142 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 423:560d1a9f3083 5143 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5144 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5145 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 423:560d1a9f3083 5146 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5147 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5148 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 423:560d1a9f3083 5149 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5150 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5151 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 423:560d1a9f3083 5152 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5153 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5154 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 423:560d1a9f3083 5155 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5156 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5157 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 423:560d1a9f3083 5158 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5159 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5160 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 423:560d1a9f3083 5161 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5162 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5163 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 423:560d1a9f3083 5164 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5165 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5166 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 5167 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5168 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5169 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 423:560d1a9f3083 5170 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5171 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 5172 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 423:560d1a9f3083 5173 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 5174 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 5175 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 423:560d1a9f3083 5176 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 5177 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 5178 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 423:560d1a9f3083 5179 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 5180 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 5181 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 423:560d1a9f3083 5182 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 5183 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 5184
mbed_official 423:560d1a9f3083 5185 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 423:560d1a9f3083 5186 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5187 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5188 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5189 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5190 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5191 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5192 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5193 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5194 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5195 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5196 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5197 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5198 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5199 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5200 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5201 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5202
mbed_official 423:560d1a9f3083 5203 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 423:560d1a9f3083 5204 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5205 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5206 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5207 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5208 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5209 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5210 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5211 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5212 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5213 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5214 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5215 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5216 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5217 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5218 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5219 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5220
mbed_official 423:560d1a9f3083 5221 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 423:560d1a9f3083 5222 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5223 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5224 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5225 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5226 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5227 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5228 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5229 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5230 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5231 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5232 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5233 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5234 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5235 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5236 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5237 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5238 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5239 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5240 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5241 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5242 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5243 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5244 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5245 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 5246 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 5247 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 5248 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 5249 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 5250 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 5251 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 5252 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 5253 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 5254
mbed_official 423:560d1a9f3083 5255 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 423:560d1a9f3083 5256 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5257 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5258 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5259 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5260 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5261 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5262 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5263 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5264 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5265 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5266 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5267 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5268 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5269 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5270 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5271 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5272 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5273
mbed_official 423:560d1a9f3083 5274 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 423:560d1a9f3083 5275 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 5276 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 423:560d1a9f3083 5277 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 5278 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 423:560d1a9f3083 5279 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 5280 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 423:560d1a9f3083 5281 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 5282 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 423:560d1a9f3083 5283
mbed_official 423:560d1a9f3083 5284 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 423:560d1a9f3083 5285 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 5286 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 423:560d1a9f3083 5287 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 5288 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 423:560d1a9f3083 5289 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 5290 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 423:560d1a9f3083 5291 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 5292 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 423:560d1a9f3083 5293
mbed_official 423:560d1a9f3083 5294 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 423:560d1a9f3083 5295 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5296 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5297 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5298 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5299 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5300 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5301 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5302 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 5303 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5304 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5305 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5306 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5307 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5308 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5309 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5310 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 5311
mbed_official 423:560d1a9f3083 5312 /******************************************************************************/
mbed_official 423:560d1a9f3083 5313 /* */
mbed_official 423:560d1a9f3083 5314 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 423:560d1a9f3083 5315 /* */
mbed_official 423:560d1a9f3083 5316 /******************************************************************************/
mbed_official 423:560d1a9f3083 5317 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 423:560d1a9f3083 5318 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 423:560d1a9f3083 5319 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 423:560d1a9f3083 5320 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 423:560d1a9f3083 5321 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 423:560d1a9f3083 5322 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 423:560d1a9f3083 5323 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 423:560d1a9f3083 5324 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 423:560d1a9f3083 5325 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 423:560d1a9f3083 5326 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 423:560d1a9f3083 5327 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 423:560d1a9f3083 5328 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 423:560d1a9f3083 5329 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 423:560d1a9f3083 5330 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 423:560d1a9f3083 5331 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 423:560d1a9f3083 5332 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 423:560d1a9f3083 5333 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 423:560d1a9f3083 5334 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 423:560d1a9f3083 5335 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 423:560d1a9f3083 5336 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 423:560d1a9f3083 5337 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 423:560d1a9f3083 5338 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 423:560d1a9f3083 5339
mbed_official 423:560d1a9f3083 5340 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 423:560d1a9f3083 5341 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 423:560d1a9f3083 5342 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 423:560d1a9f3083 5343 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 423:560d1a9f3083 5344 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 423:560d1a9f3083 5345 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 423:560d1a9f3083 5346 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 423:560d1a9f3083 5347 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 423:560d1a9f3083 5348 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 423:560d1a9f3083 5349 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 423:560d1a9f3083 5350 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 423:560d1a9f3083 5351 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 423:560d1a9f3083 5352
mbed_official 423:560d1a9f3083 5353 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 423:560d1a9f3083 5354 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 423:560d1a9f3083 5355 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 423:560d1a9f3083 5356 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 423:560d1a9f3083 5357
mbed_official 423:560d1a9f3083 5358 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 423:560d1a9f3083 5359 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 423:560d1a9f3083 5360 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 423:560d1a9f3083 5361 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 423:560d1a9f3083 5362
mbed_official 423:560d1a9f3083 5363 /******************* Bit definition for I2C_TIMINGR register *****************/
mbed_official 423:560d1a9f3083 5364 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 423:560d1a9f3083 5365 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 423:560d1a9f3083 5366 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 423:560d1a9f3083 5367 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 423:560d1a9f3083 5368 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 423:560d1a9f3083 5369
mbed_official 423:560d1a9f3083 5370 /******************* Bit definition for I2C_TIMEOUTR register *****************/
mbed_official 423:560d1a9f3083 5371 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 423:560d1a9f3083 5372 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 423:560d1a9f3083 5373 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 423:560d1a9f3083 5374 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 423:560d1a9f3083 5375 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 423:560d1a9f3083 5376
mbed_official 423:560d1a9f3083 5377 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 423:560d1a9f3083 5378 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 423:560d1a9f3083 5379 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 423:560d1a9f3083 5380 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 423:560d1a9f3083 5381 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 423:560d1a9f3083 5382 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 423:560d1a9f3083 5383 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 423:560d1a9f3083 5384 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 423:560d1a9f3083 5385 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 423:560d1a9f3083 5386 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 423:560d1a9f3083 5387 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 423:560d1a9f3083 5388 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 423:560d1a9f3083 5389 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 423:560d1a9f3083 5390 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 423:560d1a9f3083 5391 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 423:560d1a9f3083 5392 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 423:560d1a9f3083 5393 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 423:560d1a9f3083 5394 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 423:560d1a9f3083 5395
mbed_official 423:560d1a9f3083 5396 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 423:560d1a9f3083 5397 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 423:560d1a9f3083 5398 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 423:560d1a9f3083 5399 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 423:560d1a9f3083 5400 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 423:560d1a9f3083 5401 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 423:560d1a9f3083 5402 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 423:560d1a9f3083 5403 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 423:560d1a9f3083 5404 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 423:560d1a9f3083 5405 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 423:560d1a9f3083 5406
mbed_official 423:560d1a9f3083 5407 /****************** Bit definition for I2C_PECR register ********************/
mbed_official 423:560d1a9f3083 5408 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 423:560d1a9f3083 5409
mbed_official 423:560d1a9f3083 5410 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 423:560d1a9f3083 5411 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 423:560d1a9f3083 5412
mbed_official 423:560d1a9f3083 5413 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 423:560d1a9f3083 5414 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 423:560d1a9f3083 5415
mbed_official 423:560d1a9f3083 5416
mbed_official 423:560d1a9f3083 5417 /******************************************************************************/
mbed_official 423:560d1a9f3083 5418 /* */
mbed_official 423:560d1a9f3083 5419 /* Independent WATCHDOG (IWDG) */
mbed_official 423:560d1a9f3083 5420 /* */
mbed_official 423:560d1a9f3083 5421 /******************************************************************************/
mbed_official 423:560d1a9f3083 5422 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 423:560d1a9f3083 5423 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 423:560d1a9f3083 5424
mbed_official 423:560d1a9f3083 5425 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 423:560d1a9f3083 5426 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 423:560d1a9f3083 5427 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5428 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5429 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5430
mbed_official 423:560d1a9f3083 5431 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 423:560d1a9f3083 5432 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 423:560d1a9f3083 5433
mbed_official 423:560d1a9f3083 5434 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 423:560d1a9f3083 5435 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 423:560d1a9f3083 5436 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 423:560d1a9f3083 5437 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
mbed_official 423:560d1a9f3083 5438
mbed_official 423:560d1a9f3083 5439 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 423:560d1a9f3083 5440 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
mbed_official 423:560d1a9f3083 5441
mbed_official 423:560d1a9f3083 5442 /******************************************************************************/
mbed_official 423:560d1a9f3083 5443 /* */
mbed_official 423:560d1a9f3083 5444 /* Power Control */
mbed_official 423:560d1a9f3083 5445 /* */
mbed_official 423:560d1a9f3083 5446 /******************************************************************************/
mbed_official 423:560d1a9f3083 5447 /******************** Bit definition for PWR_CR register ********************/
mbed_official 423:560d1a9f3083 5448 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 423:560d1a9f3083 5449 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 423:560d1a9f3083 5450 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 423:560d1a9f3083 5451 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 423:560d1a9f3083 5452 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 423:560d1a9f3083 5453
mbed_official 423:560d1a9f3083 5454 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 423:560d1a9f3083 5455 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5456 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5457 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5458
mbed_official 423:560d1a9f3083 5459 /*!< PVD level configuration */
mbed_official 423:560d1a9f3083 5460 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 423:560d1a9f3083 5461 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 423:560d1a9f3083 5462 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 423:560d1a9f3083 5463 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 423:560d1a9f3083 5464 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 423:560d1a9f3083 5465 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 423:560d1a9f3083 5466 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 423:560d1a9f3083 5467 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 423:560d1a9f3083 5468
mbed_official 423:560d1a9f3083 5469 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 423:560d1a9f3083 5470
mbed_official 423:560d1a9f3083 5471 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 423:560d1a9f3083 5472 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 423:560d1a9f3083 5473 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 423:560d1a9f3083 5474 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 423:560d1a9f3083 5475 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 423:560d1a9f3083 5476
mbed_official 423:560d1a9f3083 5477 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 423:560d1a9f3083 5478 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 423:560d1a9f3083 5479 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 423:560d1a9f3083 5480
mbed_official 423:560d1a9f3083 5481 /******************************************************************************/
mbed_official 423:560d1a9f3083 5482 /* */
mbed_official 423:560d1a9f3083 5483 /* Reset and Clock Control */
mbed_official 423:560d1a9f3083 5484 /* */
mbed_official 423:560d1a9f3083 5485 /******************************************************************************/
mbed_official 423:560d1a9f3083 5486 /******************** Bit definition for RCC_CR register ********************/
mbed_official 423:560d1a9f3083 5487 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5488 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5489
mbed_official 423:560d1a9f3083 5490 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 423:560d1a9f3083 5491 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 423:560d1a9f3083 5492 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 423:560d1a9f3083 5493 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 423:560d1a9f3083 5494 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 423:560d1a9f3083 5495 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 423:560d1a9f3083 5496
mbed_official 423:560d1a9f3083 5497 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 423:560d1a9f3083 5498 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 423:560d1a9f3083 5499 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 423:560d1a9f3083 5500 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 423:560d1a9f3083 5501 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 423:560d1a9f3083 5502 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 423:560d1a9f3083 5503 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 423:560d1a9f3083 5504 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 423:560d1a9f3083 5505 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 423:560d1a9f3083 5506
mbed_official 423:560d1a9f3083 5507 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5508 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5509 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5510 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5511 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 5512 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 5513
mbed_official 423:560d1a9f3083 5514 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 423:560d1a9f3083 5515 /*!< SW configuration */
mbed_official 423:560d1a9f3083 5516 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 423:560d1a9f3083 5517 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5518 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5519
mbed_official 423:560d1a9f3083 5520 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 423:560d1a9f3083 5521 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 423:560d1a9f3083 5522 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 423:560d1a9f3083 5523
mbed_official 423:560d1a9f3083 5524 /*!< SWS configuration */
mbed_official 423:560d1a9f3083 5525 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 423:560d1a9f3083 5526 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5527 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5528
mbed_official 423:560d1a9f3083 5529 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 423:560d1a9f3083 5530 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 423:560d1a9f3083 5531 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 423:560d1a9f3083 5532
mbed_official 423:560d1a9f3083 5533 /*!< HPRE configuration */
mbed_official 423:560d1a9f3083 5534 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 423:560d1a9f3083 5535 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5536 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5537 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5538 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 5539
mbed_official 423:560d1a9f3083 5540 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 423:560d1a9f3083 5541 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 423:560d1a9f3083 5542 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 423:560d1a9f3083 5543 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 423:560d1a9f3083 5544 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 423:560d1a9f3083 5545 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 423:560d1a9f3083 5546 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 423:560d1a9f3083 5547 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 423:560d1a9f3083 5548 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 423:560d1a9f3083 5549
mbed_official 423:560d1a9f3083 5550 /*!< PPRE1 configuration */
mbed_official 423:560d1a9f3083 5551 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 423:560d1a9f3083 5552 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5553 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5554 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5555
mbed_official 423:560d1a9f3083 5556 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 423:560d1a9f3083 5557 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 423:560d1a9f3083 5558 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 423:560d1a9f3083 5559 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 423:560d1a9f3083 5560 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 423:560d1a9f3083 5561
mbed_official 423:560d1a9f3083 5562 /*!< PPRE2 configuration */
mbed_official 423:560d1a9f3083 5563 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 423:560d1a9f3083 5564 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5565 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5566 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5567
mbed_official 423:560d1a9f3083 5568 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 423:560d1a9f3083 5569 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 423:560d1a9f3083 5570 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 423:560d1a9f3083 5571 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 423:560d1a9f3083 5572 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 423:560d1a9f3083 5573
mbed_official 423:560d1a9f3083 5574 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
mbed_official 423:560d1a9f3083 5575 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
mbed_official 423:560d1a9f3083 5576 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 423:560d1a9f3083 5577
mbed_official 423:560d1a9f3083 5578 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 423:560d1a9f3083 5579 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 423:560d1a9f3083 5580 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 423:560d1a9f3083 5581
mbed_official 423:560d1a9f3083 5582 /*!< PLLMUL configuration */
mbed_official 423:560d1a9f3083 5583 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 423:560d1a9f3083 5584 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5585 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5586 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5587 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 5588
mbed_official 423:560d1a9f3083 5589 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 423:560d1a9f3083 5590 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 423:560d1a9f3083 5591 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 423:560d1a9f3083 5592 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 423:560d1a9f3083 5593 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 423:560d1a9f3083 5594 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 423:560d1a9f3083 5595 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 423:560d1a9f3083 5596 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 423:560d1a9f3083 5597 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 423:560d1a9f3083 5598 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 423:560d1a9f3083 5599 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 423:560d1a9f3083 5600 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 423:560d1a9f3083 5601 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 423:560d1a9f3083 5602 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 423:560d1a9f3083 5603 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 423:560d1a9f3083 5604
mbed_official 423:560d1a9f3083 5605 /*!< USB configuration */
mbed_official 423:560d1a9f3083 5606 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
mbed_official 423:560d1a9f3083 5607
mbed_official 423:560d1a9f3083 5608 #define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
mbed_official 423:560d1a9f3083 5609 #define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
mbed_official 423:560d1a9f3083 5610
mbed_official 423:560d1a9f3083 5611 /*!< I2S configuration */
mbed_official 423:560d1a9f3083 5612 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
mbed_official 423:560d1a9f3083 5613
mbed_official 423:560d1a9f3083 5614 #define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
mbed_official 423:560d1a9f3083 5615 #define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
mbed_official 423:560d1a9f3083 5616
mbed_official 423:560d1a9f3083 5617 /*!< MCO configuration */
mbed_official 423:560d1a9f3083 5618 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 423:560d1a9f3083 5619 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5620 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5621 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5622
mbed_official 423:560d1a9f3083 5623 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 423:560d1a9f3083 5624 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 423:560d1a9f3083 5625 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 423:560d1a9f3083 5626 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 423:560d1a9f3083 5627 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 423:560d1a9f3083 5628 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 423:560d1a9f3083 5629 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 423:560d1a9f3083 5630
mbed_official 423:560d1a9f3083 5631 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
mbed_official 423:560d1a9f3083 5632
mbed_official 423:560d1a9f3083 5633 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
mbed_official 423:560d1a9f3083 5634 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5635 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5636 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5637
mbed_official 423:560d1a9f3083 5638 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 423:560d1a9f3083 5639
mbed_official 423:560d1a9f3083 5640 /********************* Bit definition for RCC_CIR register ********************/
mbed_official 423:560d1a9f3083 5641 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 423:560d1a9f3083 5642 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 423:560d1a9f3083 5643 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 423:560d1a9f3083 5644 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 423:560d1a9f3083 5645 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 423:560d1a9f3083 5646 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 423:560d1a9f3083 5647 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 423:560d1a9f3083 5648 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 423:560d1a9f3083 5649 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 423:560d1a9f3083 5650 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 423:560d1a9f3083 5651 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 423:560d1a9f3083 5652 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 423:560d1a9f3083 5653 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 423:560d1a9f3083 5654 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 423:560d1a9f3083 5655 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 423:560d1a9f3083 5656 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 423:560d1a9f3083 5657 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 423:560d1a9f3083 5658
mbed_official 423:560d1a9f3083 5659 /****************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 423:560d1a9f3083 5660 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
mbed_official 423:560d1a9f3083 5661 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
mbed_official 423:560d1a9f3083 5662 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 423:560d1a9f3083 5663 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
mbed_official 423:560d1a9f3083 5664 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 423:560d1a9f3083 5665 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
mbed_official 423:560d1a9f3083 5666 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
mbed_official 423:560d1a9f3083 5667 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
mbed_official 423:560d1a9f3083 5668 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
mbed_official 423:560d1a9f3083 5669 #define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */
mbed_official 423:560d1a9f3083 5670
mbed_official 423:560d1a9f3083 5671 /****************** Bit definition for RCC_APB1RSTR register ******************/
mbed_official 423:560d1a9f3083 5672 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 423:560d1a9f3083 5673 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 423:560d1a9f3083 5674 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 423:560d1a9f3083 5675 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 423:560d1a9f3083 5676 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 423:560d1a9f3083 5677 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 423:560d1a9f3083 5678 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
mbed_official 423:560d1a9f3083 5679 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
mbed_official 423:560d1a9f3083 5680 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 423:560d1a9f3083 5681 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 423:560d1a9f3083 5682 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
mbed_official 423:560d1a9f3083 5683 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
mbed_official 423:560d1a9f3083 5684 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 423:560d1a9f3083 5685 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 423:560d1a9f3083 5686 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
mbed_official 423:560d1a9f3083 5687 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
mbed_official 423:560d1a9f3083 5688 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
mbed_official 423:560d1a9f3083 5689 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
mbed_official 423:560d1a9f3083 5690 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
mbed_official 423:560d1a9f3083 5691
mbed_official 423:560d1a9f3083 5692 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 423:560d1a9f3083 5693 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 423:560d1a9f3083 5694 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
mbed_official 423:560d1a9f3083 5695 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 423:560d1a9f3083 5696 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 423:560d1a9f3083 5697 #define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
mbed_official 423:560d1a9f3083 5698 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 423:560d1a9f3083 5699 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
mbed_official 423:560d1a9f3083 5700 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 423:560d1a9f3083 5701 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 423:560d1a9f3083 5702 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 423:560d1a9f3083 5703 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 423:560d1a9f3083 5704 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 423:560d1a9f3083 5705 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 423:560d1a9f3083 5706 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
mbed_official 423:560d1a9f3083 5707 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
mbed_official 423:560d1a9f3083 5708 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
mbed_official 423:560d1a9f3083 5709 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
mbed_official 423:560d1a9f3083 5710
mbed_official 423:560d1a9f3083 5711 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 423:560d1a9f3083 5712 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
mbed_official 423:560d1a9f3083 5713 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 423:560d1a9f3083 5714 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 423:560d1a9f3083 5715 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
mbed_official 423:560d1a9f3083 5716 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 423:560d1a9f3083 5717 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
mbed_official 423:560d1a9f3083 5718 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 423:560d1a9f3083 5719 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 423:560d1a9f3083 5720 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 423:560d1a9f3083 5721 #define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */
mbed_official 423:560d1a9f3083 5722
mbed_official 423:560d1a9f3083 5723 /****************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 423:560d1a9f3083 5724 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 423:560d1a9f3083 5725 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 423:560d1a9f3083 5726 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 423:560d1a9f3083 5727 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 423:560d1a9f3083 5728 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 423:560d1a9f3083 5729 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 423:560d1a9f3083 5730 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 423:560d1a9f3083 5731 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
mbed_official 423:560d1a9f3083 5732 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 423:560d1a9f3083 5733 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 423:560d1a9f3083 5734 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
mbed_official 423:560d1a9f3083 5735 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
mbed_official 423:560d1a9f3083 5736 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 423:560d1a9f3083 5737 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 423:560d1a9f3083 5738 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 423:560d1a9f3083 5739 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 423:560d1a9f3083 5740 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 423:560d1a9f3083 5741 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
mbed_official 423:560d1a9f3083 5742 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
mbed_official 423:560d1a9f3083 5743
mbed_official 423:560d1a9f3083 5744 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 423:560d1a9f3083 5745 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
mbed_official 423:560d1a9f3083 5746 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 423:560d1a9f3083 5747 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 423:560d1a9f3083 5748 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 423:560d1a9f3083 5749
mbed_official 423:560d1a9f3083 5750 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 423:560d1a9f3083 5751 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5752 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5753
mbed_official 423:560d1a9f3083 5754 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 423:560d1a9f3083 5755 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5756 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5757
mbed_official 423:560d1a9f3083 5758 /*!< RTC configuration */
mbed_official 423:560d1a9f3083 5759 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 423:560d1a9f3083 5760 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 423:560d1a9f3083 5761 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 423:560d1a9f3083 5762 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
mbed_official 423:560d1a9f3083 5763
mbed_official 423:560d1a9f3083 5764 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 423:560d1a9f3083 5765 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 423:560d1a9f3083 5766
mbed_official 423:560d1a9f3083 5767 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 423:560d1a9f3083 5768 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 423:560d1a9f3083 5769 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 423:560d1a9f3083 5770 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 423:560d1a9f3083 5771 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 423:560d1a9f3083 5772 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 423:560d1a9f3083 5773 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 423:560d1a9f3083 5774 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 423:560d1a9f3083 5775 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 423:560d1a9f3083 5776 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 423:560d1a9f3083 5777 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 423:560d1a9f3083 5778
mbed_official 423:560d1a9f3083 5779 /******************* Bit definition for RCC_AHBRSTR register ****************/
mbed_official 423:560d1a9f3083 5780 #define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
mbed_official 423:560d1a9f3083 5781 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
mbed_official 423:560d1a9f3083 5782 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
mbed_official 423:560d1a9f3083 5783 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
mbed_official 423:560d1a9f3083 5784 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
mbed_official 423:560d1a9f3083 5785 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
mbed_official 423:560d1a9f3083 5786 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
mbed_official 423:560d1a9f3083 5787 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
mbed_official 423:560d1a9f3083 5788 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
mbed_official 423:560d1a9f3083 5789 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
mbed_official 423:560d1a9f3083 5790 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
mbed_official 423:560d1a9f3083 5791 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
mbed_official 423:560d1a9f3083 5792
mbed_official 423:560d1a9f3083 5793 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 423:560d1a9f3083 5794 /*!< PREDIV configuration */
mbed_official 423:560d1a9f3083 5795 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 423:560d1a9f3083 5796 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5797 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5798 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5799 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 5800
mbed_official 423:560d1a9f3083 5801 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 423:560d1a9f3083 5802 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 423:560d1a9f3083 5803 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 423:560d1a9f3083 5804 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 423:560d1a9f3083 5805 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 423:560d1a9f3083 5806 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 423:560d1a9f3083 5807 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 423:560d1a9f3083 5808 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 423:560d1a9f3083 5809 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 423:560d1a9f3083 5810 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 423:560d1a9f3083 5811 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 423:560d1a9f3083 5812 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 423:560d1a9f3083 5813 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 423:560d1a9f3083 5814 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 423:560d1a9f3083 5815 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 423:560d1a9f3083 5816 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 423:560d1a9f3083 5817
mbed_official 423:560d1a9f3083 5818 /*!< ADCPRE12 configuration */
mbed_official 423:560d1a9f3083 5819 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
mbed_official 423:560d1a9f3083 5820 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5821 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5822 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5823 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 5824 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
mbed_official 423:560d1a9f3083 5825
mbed_official 423:560d1a9f3083 5826 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
mbed_official 423:560d1a9f3083 5827 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
mbed_official 423:560d1a9f3083 5828 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
mbed_official 423:560d1a9f3083 5829 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
mbed_official 423:560d1a9f3083 5830 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
mbed_official 423:560d1a9f3083 5831 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
mbed_official 423:560d1a9f3083 5832 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
mbed_official 423:560d1a9f3083 5833 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
mbed_official 423:560d1a9f3083 5834 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
mbed_official 423:560d1a9f3083 5835 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
mbed_official 423:560d1a9f3083 5836 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
mbed_official 423:560d1a9f3083 5837 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
mbed_official 423:560d1a9f3083 5838 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
mbed_official 423:560d1a9f3083 5839
mbed_official 423:560d1a9f3083 5840 /*!< ADCPRE34 configuration */
mbed_official 423:560d1a9f3083 5841 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
mbed_official 423:560d1a9f3083 5842 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5843 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5844 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 5845 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 5846 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
mbed_official 423:560d1a9f3083 5847
mbed_official 423:560d1a9f3083 5848 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
mbed_official 423:560d1a9f3083 5849 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
mbed_official 423:560d1a9f3083 5850 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
mbed_official 423:560d1a9f3083 5851 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
mbed_official 423:560d1a9f3083 5852 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
mbed_official 423:560d1a9f3083 5853 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
mbed_official 423:560d1a9f3083 5854 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
mbed_official 423:560d1a9f3083 5855 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
mbed_official 423:560d1a9f3083 5856 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
mbed_official 423:560d1a9f3083 5857 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
mbed_official 423:560d1a9f3083 5858 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
mbed_official 423:560d1a9f3083 5859 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
mbed_official 423:560d1a9f3083 5860 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
mbed_official 423:560d1a9f3083 5861
mbed_official 423:560d1a9f3083 5862 /******************* Bit definition for RCC_CFGR3 register ******************/
mbed_official 423:560d1a9f3083 5863 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 423:560d1a9f3083 5864 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5865 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5866
mbed_official 423:560d1a9f3083 5867 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
mbed_official 423:560d1a9f3083 5868 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 423:560d1a9f3083 5869 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 423:560d1a9f3083 5870 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 423:560d1a9f3083 5871
mbed_official 423:560d1a9f3083 5872 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
mbed_official 423:560d1a9f3083 5873 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 423:560d1a9f3083 5874 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
mbed_official 423:560d1a9f3083 5875 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
mbed_official 423:560d1a9f3083 5876
mbed_official 423:560d1a9f3083 5877 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 423:560d1a9f3083 5878 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 423:560d1a9f3083 5879 #define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
mbed_official 423:560d1a9f3083 5880 #define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
mbed_official 423:560d1a9f3083 5881 #define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
mbed_official 423:560d1a9f3083 5882 #define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
mbed_official 423:560d1a9f3083 5883
mbed_official 423:560d1a9f3083 5884 #define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
mbed_official 423:560d1a9f3083 5885 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
mbed_official 423:560d1a9f3083 5886 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
mbed_official 423:560d1a9f3083 5887 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
mbed_official 423:560d1a9f3083 5888 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
mbed_official 423:560d1a9f3083 5889 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
mbed_official 423:560d1a9f3083 5890 #define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */
mbed_official 423:560d1a9f3083 5891 #define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
mbed_official 423:560d1a9f3083 5892 #define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
mbed_official 423:560d1a9f3083 5893
mbed_official 423:560d1a9f3083 5894 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
mbed_official 423:560d1a9f3083 5895 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
mbed_official 423:560d1a9f3083 5896
mbed_official 423:560d1a9f3083 5897 #define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
mbed_official 423:560d1a9f3083 5898 #define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
mbed_official 423:560d1a9f3083 5899
mbed_official 423:560d1a9f3083 5900 #define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
mbed_official 423:560d1a9f3083 5901 #define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
mbed_official 423:560d1a9f3083 5902
mbed_official 423:560d1a9f3083 5903 #define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
mbed_official 423:560d1a9f3083 5904 #define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
mbed_official 423:560d1a9f3083 5905
mbed_official 423:560d1a9f3083 5906 #define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
mbed_official 423:560d1a9f3083 5907 #define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
mbed_official 423:560d1a9f3083 5908
mbed_official 423:560d1a9f3083 5909 #define RCC_CFGR3_TIM20SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM20 clock source */
mbed_official 423:560d1a9f3083 5910 #define RCC_CFGR3_TIM20SW_PLL ((uint32_t)0x00008000) /*!< PLL clock used as TIM20 clock source */
mbed_official 423:560d1a9f3083 5911
mbed_official 423:560d1a9f3083 5912 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 423:560d1a9f3083 5913 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5914 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5915
mbed_official 423:560d1a9f3083 5916 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
mbed_official 423:560d1a9f3083 5917 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 423:560d1a9f3083 5918 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 423:560d1a9f3083 5919 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 423:560d1a9f3083 5920
mbed_official 423:560d1a9f3083 5921 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
mbed_official 423:560d1a9f3083 5922 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5923 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5924
mbed_official 423:560d1a9f3083 5925 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
mbed_official 423:560d1a9f3083 5926 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
mbed_official 423:560d1a9f3083 5927 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
mbed_official 423:560d1a9f3083 5928 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
mbed_official 423:560d1a9f3083 5929
mbed_official 423:560d1a9f3083 5930 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
mbed_official 423:560d1a9f3083 5931 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5932 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5933
mbed_official 423:560d1a9f3083 5934 #define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
mbed_official 423:560d1a9f3083 5935 #define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
mbed_official 423:560d1a9f3083 5936 #define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
mbed_official 423:560d1a9f3083 5937 #define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
mbed_official 423:560d1a9f3083 5938
mbed_official 423:560d1a9f3083 5939 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
mbed_official 423:560d1a9f3083 5940 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 5941 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 5942
mbed_official 423:560d1a9f3083 5943 #define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
mbed_official 423:560d1a9f3083 5944 #define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
mbed_official 423:560d1a9f3083 5945 #define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
mbed_official 423:560d1a9f3083 5946 #define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
mbed_official 423:560d1a9f3083 5947
mbed_official 423:560d1a9f3083 5948 #define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
mbed_official 423:560d1a9f3083 5949 #define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
mbed_official 423:560d1a9f3083 5950
mbed_official 423:560d1a9f3083 5951 #define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
mbed_official 423:560d1a9f3083 5952 #define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
mbed_official 423:560d1a9f3083 5953
mbed_official 423:560d1a9f3083 5954 /******************************************************************************/
mbed_official 423:560d1a9f3083 5955 /* */
mbed_official 423:560d1a9f3083 5956 /* Real-Time Clock (RTC) */
mbed_official 423:560d1a9f3083 5957 /* */
mbed_official 423:560d1a9f3083 5958 /******************************************************************************/
mbed_official 423:560d1a9f3083 5959 /******************** Bits definition for RTC_TR register *******************/
mbed_official 423:560d1a9f3083 5960 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5961 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 5962 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5963 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5964 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 5965 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5966 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5967 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5968 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5969 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 423:560d1a9f3083 5970 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 5971 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 5972 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 5973 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 5974 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 5975 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 5976 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 5977 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 5978 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 423:560d1a9f3083 5979 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 5980 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 5981 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 5982 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 5983 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 5984 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 5985 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 5986 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 5987
mbed_official 423:560d1a9f3083 5988 /******************** Bits definition for RTC_DR register *******************/
mbed_official 423:560d1a9f3083 5989 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 423:560d1a9f3083 5990 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 5991 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 5992 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 5993 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 5994 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 5995 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 5996 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 5997 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 5998 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 5999 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 423:560d1a9f3083 6000 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6001 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6002 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6003 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6004 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 6005 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6006 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6007 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6008 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6009 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 423:560d1a9f3083 6010 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6011 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6012 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 6013 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6014 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6015 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6016 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6017
mbed_official 423:560d1a9f3083 6018 /******************** Bits definition for RTC_CR register *******************/
mbed_official 423:560d1a9f3083 6019 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 6020 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 423:560d1a9f3083 6021 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 6022 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 6023 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 6024 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 6025 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 6026 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 6027 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 6028 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6029 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6030 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6031 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6032 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6033 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6034 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6035 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6036 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6037 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6038 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6039 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6040 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 423:560d1a9f3083 6041 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6042 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6043 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6044
mbed_official 423:560d1a9f3083 6045 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 423:560d1a9f3083 6046 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 6047 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6048 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6049 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6050 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6051 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6052 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6053 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6054 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6055 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 6056 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6057 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6058 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6059 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6060 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6061 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6062 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6063
mbed_official 423:560d1a9f3083 6064 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 423:560d1a9f3083 6065 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 423:560d1a9f3083 6066 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 423:560d1a9f3083 6067
mbed_official 423:560d1a9f3083 6068 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 423:560d1a9f3083 6069 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 423:560d1a9f3083 6070
mbed_official 423:560d1a9f3083 6071 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 423:560d1a9f3083 6072 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 6073 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 6074 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 423:560d1a9f3083 6075 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 6076 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 6077 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 6078 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 6079 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 6080 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 6081 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 6082 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 6083 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 6084 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 6085 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 6086 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 6087 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 6088 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 6089 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 6090 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 6091 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 6092 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6093 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 423:560d1a9f3083 6094 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6095 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6096 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6097 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 6098 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6099 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6100 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6101 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6102 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 6103 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 423:560d1a9f3083 6104 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6105 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6106 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6107 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 6108 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6109 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6110 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6111 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6112
mbed_official 423:560d1a9f3083 6113 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 423:560d1a9f3083 6114 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 6115 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 423:560d1a9f3083 6116 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 423:560d1a9f3083 6117 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 423:560d1a9f3083 6118 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 423:560d1a9f3083 6119 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 6120 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 6121 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 6122 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 6123 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 6124 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 423:560d1a9f3083 6125 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 6126 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 6127 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 6128 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 6129 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 6130 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 6131 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 6132 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 6133 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 6134 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6135 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 423:560d1a9f3083 6136 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6137 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6138 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6139 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 6140 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6141 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6142 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6143 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6144 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 6145 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 423:560d1a9f3083 6146 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6147 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6148 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6149 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 6150 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6151 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6152 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6153 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6154
mbed_official 423:560d1a9f3083 6155 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 423:560d1a9f3083 6156 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 423:560d1a9f3083 6157
mbed_official 423:560d1a9f3083 6158 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 423:560d1a9f3083 6159 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 423:560d1a9f3083 6160
mbed_official 423:560d1a9f3083 6161 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 423:560d1a9f3083 6162 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 423:560d1a9f3083 6163 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 423:560d1a9f3083 6164
mbed_official 423:560d1a9f3083 6165 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 423:560d1a9f3083 6166 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 423:560d1a9f3083 6167 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 423:560d1a9f3083 6168 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 423:560d1a9f3083 6169 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 423:560d1a9f3083 6170 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 423:560d1a9f3083 6171 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 423:560d1a9f3083 6172 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 423:560d1a9f3083 6173 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 6174 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 423:560d1a9f3083 6175 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 423:560d1a9f3083 6176 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6177 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6178 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6179 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 6180 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6181 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6182 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6183 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6184 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 423:560d1a9f3083 6185 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6186 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6187 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6188 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 6189 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6190 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6191 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6192 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6193
mbed_official 423:560d1a9f3083 6194 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 423:560d1a9f3083 6195 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 423:560d1a9f3083 6196 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6197 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6198 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6199 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6200 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 423:560d1a9f3083 6201 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6202 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6203 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6204 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6205 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 423:560d1a9f3083 6206 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6207 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6208 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 423:560d1a9f3083 6209 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6210 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6211 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6212 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6213
mbed_official 423:560d1a9f3083 6214 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 423:560d1a9f3083 6215 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 423:560d1a9f3083 6216
mbed_official 423:560d1a9f3083 6217 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 423:560d1a9f3083 6218 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6219 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6220 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6221 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 423:560d1a9f3083 6222 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6223 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6224 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6225 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6226 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6227 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6228 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6229 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 6230 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6231
mbed_official 423:560d1a9f3083 6232 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 423:560d1a9f3083 6233 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 423:560d1a9f3083 6234 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 423:560d1a9f3083 6235 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 423:560d1a9f3083 6236 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 423:560d1a9f3083 6237 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 423:560d1a9f3083 6238 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 423:560d1a9f3083 6239 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 423:560d1a9f3083 6240 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 423:560d1a9f3083 6241 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 423:560d1a9f3083 6242 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 423:560d1a9f3083 6243 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 423:560d1a9f3083 6244 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 423:560d1a9f3083 6245 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 423:560d1a9f3083 6246 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 423:560d1a9f3083 6247 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 423:560d1a9f3083 6248 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6249 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 423:560d1a9f3083 6250 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 423:560d1a9f3083 6251 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 423:560d1a9f3083 6252 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 423:560d1a9f3083 6253
mbed_official 423:560d1a9f3083 6254 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 423:560d1a9f3083 6255 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 6256 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 6257 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 6258 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 6259 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 6260 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 423:560d1a9f3083 6261
mbed_official 423:560d1a9f3083 6262 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 423:560d1a9f3083 6263 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 423:560d1a9f3083 6264 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 423:560d1a9f3083 6265 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 423:560d1a9f3083 6266 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 423:560d1a9f3083 6267 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 423:560d1a9f3083 6268 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 423:560d1a9f3083 6269
mbed_official 423:560d1a9f3083 6270 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 423:560d1a9f3083 6271 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6272
mbed_official 423:560d1a9f3083 6273 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 423:560d1a9f3083 6274 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6275
mbed_official 423:560d1a9f3083 6276 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 423:560d1a9f3083 6277 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6278
mbed_official 423:560d1a9f3083 6279 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 423:560d1a9f3083 6280 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6281
mbed_official 423:560d1a9f3083 6282 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 423:560d1a9f3083 6283 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6284
mbed_official 423:560d1a9f3083 6285 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 423:560d1a9f3083 6286 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6287
mbed_official 423:560d1a9f3083 6288 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 423:560d1a9f3083 6289 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6290
mbed_official 423:560d1a9f3083 6291 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 423:560d1a9f3083 6292 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6293
mbed_official 423:560d1a9f3083 6294 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 423:560d1a9f3083 6295 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6296
mbed_official 423:560d1a9f3083 6297 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 423:560d1a9f3083 6298 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6299
mbed_official 423:560d1a9f3083 6300 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 423:560d1a9f3083 6301 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6302
mbed_official 423:560d1a9f3083 6303 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 423:560d1a9f3083 6304 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6305
mbed_official 423:560d1a9f3083 6306 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 423:560d1a9f3083 6307 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6308
mbed_official 423:560d1a9f3083 6309 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 423:560d1a9f3083 6310 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6311
mbed_official 423:560d1a9f3083 6312 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 423:560d1a9f3083 6313 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6314
mbed_official 423:560d1a9f3083 6315 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 423:560d1a9f3083 6316 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 423:560d1a9f3083 6317
mbed_official 423:560d1a9f3083 6318 /******************** Number of backup registers ******************************/
mbed_official 423:560d1a9f3083 6319 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
mbed_official 423:560d1a9f3083 6320
mbed_official 423:560d1a9f3083 6321 /******************************************************************************/
mbed_official 423:560d1a9f3083 6322 /* */
mbed_official 423:560d1a9f3083 6323 /* Serial Peripheral Interface (SPI) */
mbed_official 423:560d1a9f3083 6324 /* */
mbed_official 423:560d1a9f3083 6325 /******************************************************************************/
mbed_official 423:560d1a9f3083 6326 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 423:560d1a9f3083 6327 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 423:560d1a9f3083 6328 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 423:560d1a9f3083 6329 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 423:560d1a9f3083 6330 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 423:560d1a9f3083 6331 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 6332 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6333 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 6334 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 423:560d1a9f3083 6335 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 423:560d1a9f3083 6336 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 423:560d1a9f3083 6337 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 423:560d1a9f3083 6338 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 423:560d1a9f3083 6339 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 423:560d1a9f3083 6340 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 423:560d1a9f3083 6341 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 423:560d1a9f3083 6342 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 423:560d1a9f3083 6343 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 423:560d1a9f3083 6344
mbed_official 423:560d1a9f3083 6345 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 423:560d1a9f3083 6346 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 423:560d1a9f3083 6347 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 423:560d1a9f3083 6348 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 423:560d1a9f3083 6349 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 423:560d1a9f3083 6350 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 423:560d1a9f3083 6351 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 423:560d1a9f3083 6352 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 423:560d1a9f3083 6353 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 423:560d1a9f3083 6354 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 423:560d1a9f3083 6355 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 6356 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6357 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 6358 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 6359 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 423:560d1a9f3083 6360 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 423:560d1a9f3083 6361 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 423:560d1a9f3083 6362
mbed_official 423:560d1a9f3083 6363 /******************** Bit definition for SPI_SR register ********************/
mbed_official 423:560d1a9f3083 6364 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 423:560d1a9f3083 6365 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 423:560d1a9f3083 6366 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 423:560d1a9f3083 6367 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 423:560d1a9f3083 6368 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 423:560d1a9f3083 6369 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 423:560d1a9f3083 6370 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 423:560d1a9f3083 6371 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 423:560d1a9f3083 6372 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 423:560d1a9f3083 6373 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 423:560d1a9f3083 6374 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 6375 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6376 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 423:560d1a9f3083 6377 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 6378 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6379
mbed_official 423:560d1a9f3083 6380 /******************** Bit definition for SPI_DR register ********************/
mbed_official 423:560d1a9f3083 6381 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 423:560d1a9f3083 6382
mbed_official 423:560d1a9f3083 6383 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 423:560d1a9f3083 6384 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 423:560d1a9f3083 6385
mbed_official 423:560d1a9f3083 6386 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 423:560d1a9f3083 6387 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 423:560d1a9f3083 6388
mbed_official 423:560d1a9f3083 6389 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 423:560d1a9f3083 6390 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 423:560d1a9f3083 6391
mbed_official 423:560d1a9f3083 6392 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 423:560d1a9f3083 6393 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 423:560d1a9f3083 6394 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 423:560d1a9f3083 6395 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6396 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6397 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 423:560d1a9f3083 6398 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 423:560d1a9f3083 6399 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6400 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6401 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 423:560d1a9f3083 6402 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 423:560d1a9f3083 6403 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6404 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6405 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 423:560d1a9f3083 6406 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 423:560d1a9f3083 6407
mbed_official 423:560d1a9f3083 6408 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 423:560d1a9f3083 6409 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 423:560d1a9f3083 6410 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 423:560d1a9f3083 6411 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 423:560d1a9f3083 6412
mbed_official 423:560d1a9f3083 6413 /******************************************************************************/
mbed_official 423:560d1a9f3083 6414 /* */
mbed_official 423:560d1a9f3083 6415 /* System Configuration(SYSCFG) */
mbed_official 423:560d1a9f3083 6416 /* */
mbed_official 423:560d1a9f3083 6417 /******************************************************************************/
mbed_official 423:560d1a9f3083 6418 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
mbed_official 423:560d1a9f3083 6419 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 423:560d1a9f3083 6420 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 6421 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6422 #define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 6423 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
mbed_official 423:560d1a9f3083 6424 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
mbed_official 423:560d1a9f3083 6425 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
mbed_official 423:560d1a9f3083 6426 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
mbed_official 423:560d1a9f3083 6427 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
mbed_official 423:560d1a9f3083 6428 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 423:560d1a9f3083 6429 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 423:560d1a9f3083 6430 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
mbed_official 423:560d1a9f3083 6431 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
mbed_official 423:560d1a9f3083 6432 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 423:560d1a9f3083 6433 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 423:560d1a9f3083 6434 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 423:560d1a9f3083 6435 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 423:560d1a9f3083 6436 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
mbed_official 423:560d1a9f3083 6437 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
mbed_official 423:560d1a9f3083 6438 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
mbed_official 423:560d1a9f3083 6439 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
mbed_official 423:560d1a9f3083 6440 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
mbed_official 423:560d1a9f3083 6441 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
mbed_official 423:560d1a9f3083 6442 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
mbed_official 423:560d1a9f3083 6443 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
mbed_official 423:560d1a9f3083 6444 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
mbed_official 423:560d1a9f3083 6445 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
mbed_official 423:560d1a9f3083 6446 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
mbed_official 423:560d1a9f3083 6447 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
mbed_official 423:560d1a9f3083 6448 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
mbed_official 423:560d1a9f3083 6449
mbed_official 423:560d1a9f3083 6450 /***************** Bit definition for SYSCFG_RCR register *******************/
mbed_official 423:560d1a9f3083 6451 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
mbed_official 423:560d1a9f3083 6452 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
mbed_official 423:560d1a9f3083 6453 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
mbed_official 423:560d1a9f3083 6454 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
mbed_official 423:560d1a9f3083 6455 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
mbed_official 423:560d1a9f3083 6456 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
mbed_official 423:560d1a9f3083 6457 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
mbed_official 423:560d1a9f3083 6458 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
mbed_official 423:560d1a9f3083 6459 #define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */
mbed_official 423:560d1a9f3083 6460 #define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */
mbed_official 423:560d1a9f3083 6461 #define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */
mbed_official 423:560d1a9f3083 6462 #define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */
mbed_official 423:560d1a9f3083 6463 #define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */
mbed_official 423:560d1a9f3083 6464 #define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */
mbed_official 423:560d1a9f3083 6465 #define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */
mbed_official 423:560d1a9f3083 6466 #define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */
mbed_official 423:560d1a9f3083 6467
mbed_official 423:560d1a9f3083 6468 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 423:560d1a9f3083 6469 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 423:560d1a9f3083 6470 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 423:560d1a9f3083 6471 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 423:560d1a9f3083 6472 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 423:560d1a9f3083 6473
mbed_official 423:560d1a9f3083 6474 /*!<*
mbed_official 423:560d1a9f3083 6475 * @brief EXTI0 configuration
mbed_official 423:560d1a9f3083 6476 */
mbed_official 423:560d1a9f3083 6477 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 423:560d1a9f3083 6478 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 423:560d1a9f3083 6479 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 423:560d1a9f3083 6480 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 423:560d1a9f3083 6481 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 423:560d1a9f3083 6482 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 423:560d1a9f3083 6483 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
mbed_official 423:560d1a9f3083 6484 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
mbed_official 423:560d1a9f3083 6485
mbed_official 423:560d1a9f3083 6486 /*!<*
mbed_official 423:560d1a9f3083 6487 * @brief EXTI1 configuration
mbed_official 423:560d1a9f3083 6488 */
mbed_official 423:560d1a9f3083 6489 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 423:560d1a9f3083 6490 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 423:560d1a9f3083 6491 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 423:560d1a9f3083 6492 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 423:560d1a9f3083 6493 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 423:560d1a9f3083 6494 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 423:560d1a9f3083 6495 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
mbed_official 423:560d1a9f3083 6496 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
mbed_official 423:560d1a9f3083 6497
mbed_official 423:560d1a9f3083 6498 /*!<*
mbed_official 423:560d1a9f3083 6499 * @brief EXTI2 configuration
mbed_official 423:560d1a9f3083 6500 */
mbed_official 423:560d1a9f3083 6501 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 423:560d1a9f3083 6502 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 423:560d1a9f3083 6503 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 423:560d1a9f3083 6504 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 423:560d1a9f3083 6505 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 423:560d1a9f3083 6506 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 423:560d1a9f3083 6507 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
mbed_official 423:560d1a9f3083 6508
mbed_official 423:560d1a9f3083 6509 /*!<*
mbed_official 423:560d1a9f3083 6510 * @brief EXTI3 configuration
mbed_official 423:560d1a9f3083 6511 */
mbed_official 423:560d1a9f3083 6512 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 423:560d1a9f3083 6513 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 423:560d1a9f3083 6514 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 423:560d1a9f3083 6515 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 423:560d1a9f3083 6516 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 423:560d1a9f3083 6517 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
mbed_official 423:560d1a9f3083 6518 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
mbed_official 423:560d1a9f3083 6519
mbed_official 423:560d1a9f3083 6520 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 423:560d1a9f3083 6521 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 423:560d1a9f3083 6522 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 423:560d1a9f3083 6523 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 423:560d1a9f3083 6524 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 423:560d1a9f3083 6525
mbed_official 423:560d1a9f3083 6526 /*!<*
mbed_official 423:560d1a9f3083 6527 * @brief EXTI4 configuration
mbed_official 423:560d1a9f3083 6528 */
mbed_official 423:560d1a9f3083 6529 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 423:560d1a9f3083 6530 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 423:560d1a9f3083 6531 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 423:560d1a9f3083 6532 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 423:560d1a9f3083 6533 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 423:560d1a9f3083 6534 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 423:560d1a9f3083 6535 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
mbed_official 423:560d1a9f3083 6536 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
mbed_official 423:560d1a9f3083 6537
mbed_official 423:560d1a9f3083 6538 /*!<*
mbed_official 423:560d1a9f3083 6539 * @brief EXTI5 configuration
mbed_official 423:560d1a9f3083 6540 */
mbed_official 423:560d1a9f3083 6541 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 423:560d1a9f3083 6542 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 423:560d1a9f3083 6543 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 423:560d1a9f3083 6544 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 423:560d1a9f3083 6545 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 423:560d1a9f3083 6546 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 423:560d1a9f3083 6547 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
mbed_official 423:560d1a9f3083 6548
mbed_official 423:560d1a9f3083 6549 /*!<*
mbed_official 423:560d1a9f3083 6550 * @brief EXTI6 configuration
mbed_official 423:560d1a9f3083 6551 */
mbed_official 423:560d1a9f3083 6552 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 423:560d1a9f3083 6553 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 423:560d1a9f3083 6554 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 423:560d1a9f3083 6555 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 423:560d1a9f3083 6556 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 423:560d1a9f3083 6557 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 423:560d1a9f3083 6558 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
mbed_official 423:560d1a9f3083 6559
mbed_official 423:560d1a9f3083 6560 /*!<*
mbed_official 423:560d1a9f3083 6561 * @brief EXTI7 configuration
mbed_official 423:560d1a9f3083 6562 */
mbed_official 423:560d1a9f3083 6563 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 423:560d1a9f3083 6564 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 423:560d1a9f3083 6565 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 423:560d1a9f3083 6566 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 423:560d1a9f3083 6567 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 423:560d1a9f3083 6568 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
mbed_official 423:560d1a9f3083 6569 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
mbed_official 423:560d1a9f3083 6570
mbed_official 423:560d1a9f3083 6571 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 423:560d1a9f3083 6572 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 423:560d1a9f3083 6573 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 423:560d1a9f3083 6574 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 423:560d1a9f3083 6575 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 423:560d1a9f3083 6576
mbed_official 423:560d1a9f3083 6577 /*!<*
mbed_official 423:560d1a9f3083 6578 * @brief EXTI8 configuration
mbed_official 423:560d1a9f3083 6579 */
mbed_official 423:560d1a9f3083 6580 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 423:560d1a9f3083 6581 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 423:560d1a9f3083 6582 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 423:560d1a9f3083 6583 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 423:560d1a9f3083 6584 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 423:560d1a9f3083 6585 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
mbed_official 423:560d1a9f3083 6586 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
mbed_official 423:560d1a9f3083 6587
mbed_official 423:560d1a9f3083 6588 /*!<*
mbed_official 423:560d1a9f3083 6589 * @brief EXTI9 configuration
mbed_official 423:560d1a9f3083 6590 */
mbed_official 423:560d1a9f3083 6591 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 423:560d1a9f3083 6592 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 423:560d1a9f3083 6593 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 423:560d1a9f3083 6594 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 423:560d1a9f3083 6595 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 423:560d1a9f3083 6596 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 423:560d1a9f3083 6597 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
mbed_official 423:560d1a9f3083 6598
mbed_official 423:560d1a9f3083 6599 /*!<*
mbed_official 423:560d1a9f3083 6600 * @brief EXTI10 configuration
mbed_official 423:560d1a9f3083 6601 */
mbed_official 423:560d1a9f3083 6602 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 423:560d1a9f3083 6603 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 423:560d1a9f3083 6604 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 423:560d1a9f3083 6605 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 423:560d1a9f3083 6606 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 423:560d1a9f3083 6607 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 423:560d1a9f3083 6608 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
mbed_official 423:560d1a9f3083 6609
mbed_official 423:560d1a9f3083 6610 /*!<*
mbed_official 423:560d1a9f3083 6611 * @brief EXTI11 configuration
mbed_official 423:560d1a9f3083 6612 */
mbed_official 423:560d1a9f3083 6613 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 423:560d1a9f3083 6614 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 423:560d1a9f3083 6615 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 423:560d1a9f3083 6616 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 423:560d1a9f3083 6617 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 423:560d1a9f3083 6618 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
mbed_official 423:560d1a9f3083 6619 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
mbed_official 423:560d1a9f3083 6620
mbed_official 423:560d1a9f3083 6621 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 423:560d1a9f3083 6622 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 423:560d1a9f3083 6623 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 423:560d1a9f3083 6624 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 423:560d1a9f3083 6625 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 423:560d1a9f3083 6626
mbed_official 423:560d1a9f3083 6627 /*!<*
mbed_official 423:560d1a9f3083 6628 * @brief EXTI12 configuration
mbed_official 423:560d1a9f3083 6629 */
mbed_official 423:560d1a9f3083 6630 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 423:560d1a9f3083 6631 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 423:560d1a9f3083 6632 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 423:560d1a9f3083 6633 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 423:560d1a9f3083 6634 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 423:560d1a9f3083 6635 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
mbed_official 423:560d1a9f3083 6636 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
mbed_official 423:560d1a9f3083 6637
mbed_official 423:560d1a9f3083 6638 /*!<*
mbed_official 423:560d1a9f3083 6639 * @brief EXTI13 configuration
mbed_official 423:560d1a9f3083 6640 */
mbed_official 423:560d1a9f3083 6641 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 423:560d1a9f3083 6642 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 423:560d1a9f3083 6643 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 423:560d1a9f3083 6644 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 423:560d1a9f3083 6645 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 423:560d1a9f3083 6646 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
mbed_official 423:560d1a9f3083 6647 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
mbed_official 423:560d1a9f3083 6648
mbed_official 423:560d1a9f3083 6649 /*!<*
mbed_official 423:560d1a9f3083 6650 * @brief EXTI14 configuration
mbed_official 423:560d1a9f3083 6651 */
mbed_official 423:560d1a9f3083 6652 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 423:560d1a9f3083 6653 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 423:560d1a9f3083 6654 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 423:560d1a9f3083 6655 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 423:560d1a9f3083 6656 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 423:560d1a9f3083 6657 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
mbed_official 423:560d1a9f3083 6658 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
mbed_official 423:560d1a9f3083 6659
mbed_official 423:560d1a9f3083 6660 /*!<*
mbed_official 423:560d1a9f3083 6661 * @brief EXTI15 configuration
mbed_official 423:560d1a9f3083 6662 */
mbed_official 423:560d1a9f3083 6663 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 423:560d1a9f3083 6664 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 423:560d1a9f3083 6665 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 423:560d1a9f3083 6666 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 423:560d1a9f3083 6667 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 423:560d1a9f3083 6668 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
mbed_official 423:560d1a9f3083 6669 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
mbed_official 423:560d1a9f3083 6670
mbed_official 423:560d1a9f3083 6671 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
mbed_official 423:560d1a9f3083 6672 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
mbed_official 423:560d1a9f3083 6673 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
mbed_official 423:560d1a9f3083 6674 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
mbed_official 423:560d1a9f3083 6675 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
mbed_official 423:560d1a9f3083 6676 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 423:560d1a9f3083 6677
mbed_official 423:560d1a9f3083 6678 /***************** Bit definition for SYSCFG_CFGR4 register *****************/
mbed_official 423:560d1a9f3083 6679 #define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */
mbed_official 423:560d1a9f3083 6680 #define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */
mbed_official 423:560d1a9f3083 6681 #define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */
mbed_official 423:560d1a9f3083 6682 #define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */
mbed_official 423:560d1a9f3083 6683 #define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */
mbed_official 423:560d1a9f3083 6684 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */
mbed_official 423:560d1a9f3083 6685 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */
mbed_official 423:560d1a9f3083 6686 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */
mbed_official 423:560d1a9f3083 6687 #define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */
mbed_official 423:560d1a9f3083 6688 #define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */
mbed_official 423:560d1a9f3083 6689 #define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */
mbed_official 423:560d1a9f3083 6690 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */
mbed_official 423:560d1a9f3083 6691 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */
mbed_official 423:560d1a9f3083 6692 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */
mbed_official 423:560d1a9f3083 6693
mbed_official 423:560d1a9f3083 6694 /******************************************************************************/
mbed_official 423:560d1a9f3083 6695 /* */
mbed_official 423:560d1a9f3083 6696 /* TIM */
mbed_official 423:560d1a9f3083 6697 /* */
mbed_official 423:560d1a9f3083 6698 /******************************************************************************/
mbed_official 423:560d1a9f3083 6699 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 423:560d1a9f3083 6700 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 423:560d1a9f3083 6701 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 423:560d1a9f3083 6702 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 423:560d1a9f3083 6703 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 423:560d1a9f3083 6704 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 423:560d1a9f3083 6705
mbed_official 423:560d1a9f3083 6706 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 423:560d1a9f3083 6707 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6708 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6709
mbed_official 423:560d1a9f3083 6710 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 423:560d1a9f3083 6711
mbed_official 423:560d1a9f3083 6712 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 423:560d1a9f3083 6713 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6714 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6715
mbed_official 423:560d1a9f3083 6716 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
mbed_official 423:560d1a9f3083 6717
mbed_official 423:560d1a9f3083 6718 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 423:560d1a9f3083 6719 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 423:560d1a9f3083 6720 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 423:560d1a9f3083 6721 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 423:560d1a9f3083 6722
mbed_official 423:560d1a9f3083 6723 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 423:560d1a9f3083 6724 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6725 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6726 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6727
mbed_official 423:560d1a9f3083 6728 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 423:560d1a9f3083 6729 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 423:560d1a9f3083 6730 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 423:560d1a9f3083 6731 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 423:560d1a9f3083 6732 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 423:560d1a9f3083 6733 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 423:560d1a9f3083 6734 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 423:560d1a9f3083 6735 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 423:560d1a9f3083 6736 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 423:560d1a9f3083 6737 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 423:560d1a9f3083 6738
mbed_official 423:560d1a9f3083 6739 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 423:560d1a9f3083 6740 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6741 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6742 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6743 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6744
mbed_official 423:560d1a9f3083 6745 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 423:560d1a9f3083 6746 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 423:560d1a9f3083 6747 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6748 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6749 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6750 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6751
mbed_official 423:560d1a9f3083 6752 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 423:560d1a9f3083 6753
mbed_official 423:560d1a9f3083 6754 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 423:560d1a9f3083 6755 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6756 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6757 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6758
mbed_official 423:560d1a9f3083 6759 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 423:560d1a9f3083 6760
mbed_official 423:560d1a9f3083 6761 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 423:560d1a9f3083 6762 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6763 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6764 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6765 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6766
mbed_official 423:560d1a9f3083 6767 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 423:560d1a9f3083 6768 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6769 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6770
mbed_official 423:560d1a9f3083 6771 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 423:560d1a9f3083 6772 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 423:560d1a9f3083 6773
mbed_official 423:560d1a9f3083 6774 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 423:560d1a9f3083 6775 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 423:560d1a9f3083 6776 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 423:560d1a9f3083 6777 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 423:560d1a9f3083 6778 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 423:560d1a9f3083 6779 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 423:560d1a9f3083 6780 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 423:560d1a9f3083 6781 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 423:560d1a9f3083 6782 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 423:560d1a9f3083 6783 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 423:560d1a9f3083 6784 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 423:560d1a9f3083 6785 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 423:560d1a9f3083 6786 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 423:560d1a9f3083 6787 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 423:560d1a9f3083 6788 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 423:560d1a9f3083 6789 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 423:560d1a9f3083 6790
mbed_official 423:560d1a9f3083 6791 /******************** Bit definition for TIM_SR register ********************/
mbed_official 423:560d1a9f3083 6792 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 423:560d1a9f3083 6793 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 423:560d1a9f3083 6794 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 423:560d1a9f3083 6795 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 423:560d1a9f3083 6796 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 423:560d1a9f3083 6797 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 423:560d1a9f3083 6798 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 423:560d1a9f3083 6799 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 423:560d1a9f3083 6800 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
mbed_official 423:560d1a9f3083 6801 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 423:560d1a9f3083 6802 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 423:560d1a9f3083 6803 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 423:560d1a9f3083 6804 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 423:560d1a9f3083 6805 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
mbed_official 423:560d1a9f3083 6806 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
mbed_official 423:560d1a9f3083 6807
mbed_official 423:560d1a9f3083 6808 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 423:560d1a9f3083 6809 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 423:560d1a9f3083 6810 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 423:560d1a9f3083 6811 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 423:560d1a9f3083 6812 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 423:560d1a9f3083 6813 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 423:560d1a9f3083 6814 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 423:560d1a9f3083 6815 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 423:560d1a9f3083 6816 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 423:560d1a9f3083 6817 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
mbed_official 423:560d1a9f3083 6818
mbed_official 423:560d1a9f3083 6819 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 423:560d1a9f3083 6820 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 423:560d1a9f3083 6821 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6822 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6823
mbed_official 423:560d1a9f3083 6824 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 423:560d1a9f3083 6825 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 423:560d1a9f3083 6826
mbed_official 423:560d1a9f3083 6827 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 423:560d1a9f3083 6828 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6829 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6830 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6831 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6832
mbed_official 423:560d1a9f3083 6833 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 423:560d1a9f3083 6834
mbed_official 423:560d1a9f3083 6835 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 423:560d1a9f3083 6836 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6837 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6838
mbed_official 423:560d1a9f3083 6839 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 423:560d1a9f3083 6840 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 423:560d1a9f3083 6841
mbed_official 423:560d1a9f3083 6842 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 423:560d1a9f3083 6843 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6844 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6845 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6846 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6847
mbed_official 423:560d1a9f3083 6848 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 423:560d1a9f3083 6849
mbed_official 423:560d1a9f3083 6850 /*----------------------------------------------------------------------------*/
mbed_official 423:560d1a9f3083 6851
mbed_official 423:560d1a9f3083 6852 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 423:560d1a9f3083 6853 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6854 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6855
mbed_official 423:560d1a9f3083 6856 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 423:560d1a9f3083 6857 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6858 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6859 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6860 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6861
mbed_official 423:560d1a9f3083 6862 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 423:560d1a9f3083 6863 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6864 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6865
mbed_official 423:560d1a9f3083 6866 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 423:560d1a9f3083 6867 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6868 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6869 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6870 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6871
mbed_official 423:560d1a9f3083 6872 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 423:560d1a9f3083 6873 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 423:560d1a9f3083 6874 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6875 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6876
mbed_official 423:560d1a9f3083 6877 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 423:560d1a9f3083 6878 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 423:560d1a9f3083 6879
mbed_official 423:560d1a9f3083 6880 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 423:560d1a9f3083 6881 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6882 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6883 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6884 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6885
mbed_official 423:560d1a9f3083 6886 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 423:560d1a9f3083 6887
mbed_official 423:560d1a9f3083 6888 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 423:560d1a9f3083 6889 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6890 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6891
mbed_official 423:560d1a9f3083 6892 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 423:560d1a9f3083 6893 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 423:560d1a9f3083 6894
mbed_official 423:560d1a9f3083 6895 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 423:560d1a9f3083 6896 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6897 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6898 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6899 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6900
mbed_official 423:560d1a9f3083 6901 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 423:560d1a9f3083 6902
mbed_official 423:560d1a9f3083 6903 /*----------------------------------------------------------------------------*/
mbed_official 423:560d1a9f3083 6904
mbed_official 423:560d1a9f3083 6905 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 423:560d1a9f3083 6906 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6907 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6908
mbed_official 423:560d1a9f3083 6909 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 423:560d1a9f3083 6910 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6911 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6912 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6913 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6914
mbed_official 423:560d1a9f3083 6915 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 423:560d1a9f3083 6916 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6917 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6918
mbed_official 423:560d1a9f3083 6919 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 423:560d1a9f3083 6920 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6921 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6922 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6923 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6924
mbed_official 423:560d1a9f3083 6925 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 423:560d1a9f3083 6926 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 423:560d1a9f3083 6927 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 423:560d1a9f3083 6928 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 423:560d1a9f3083 6929 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 423:560d1a9f3083 6930 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 423:560d1a9f3083 6931 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 423:560d1a9f3083 6932 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 423:560d1a9f3083 6933 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 423:560d1a9f3083 6934 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 423:560d1a9f3083 6935 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 423:560d1a9f3083 6936 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 423:560d1a9f3083 6937 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 423:560d1a9f3083 6938 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 423:560d1a9f3083 6939 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 423:560d1a9f3083 6940 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 423:560d1a9f3083 6941 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
mbed_official 423:560d1a9f3083 6942 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
mbed_official 423:560d1a9f3083 6943 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
mbed_official 423:560d1a9f3083 6944 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
mbed_official 423:560d1a9f3083 6945
mbed_official 423:560d1a9f3083 6946 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 423:560d1a9f3083 6947 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 423:560d1a9f3083 6948 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
mbed_official 423:560d1a9f3083 6949
mbed_official 423:560d1a9f3083 6950 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 423:560d1a9f3083 6951 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 423:560d1a9f3083 6952
mbed_official 423:560d1a9f3083 6953 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 423:560d1a9f3083 6954 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 423:560d1a9f3083 6955
mbed_official 423:560d1a9f3083 6956 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 423:560d1a9f3083 6957 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 423:560d1a9f3083 6958
mbed_official 423:560d1a9f3083 6959 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 423:560d1a9f3083 6960 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 423:560d1a9f3083 6961
mbed_official 423:560d1a9f3083 6962 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 423:560d1a9f3083 6963 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 423:560d1a9f3083 6964
mbed_official 423:560d1a9f3083 6965 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 423:560d1a9f3083 6966 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 423:560d1a9f3083 6967
mbed_official 423:560d1a9f3083 6968 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 423:560d1a9f3083 6969 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 423:560d1a9f3083 6970
mbed_official 423:560d1a9f3083 6971 /******************* Bit definition for TIM_CCR5 register *******************/
mbed_official 423:560d1a9f3083 6972 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
mbed_official 423:560d1a9f3083 6973 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
mbed_official 423:560d1a9f3083 6974 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
mbed_official 423:560d1a9f3083 6975 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
mbed_official 423:560d1a9f3083 6976
mbed_official 423:560d1a9f3083 6977 /******************* Bit definition for TIM_CCR6 register *******************/
mbed_official 423:560d1a9f3083 6978 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
mbed_official 423:560d1a9f3083 6979
mbed_official 423:560d1a9f3083 6980 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 423:560d1a9f3083 6981 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 423:560d1a9f3083 6982 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6983 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6984 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 6985 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 6986 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 6987 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 6988 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 6989 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 423:560d1a9f3083 6990
mbed_official 423:560d1a9f3083 6991 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 423:560d1a9f3083 6992 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 6993 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 6994
mbed_official 423:560d1a9f3083 6995 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 423:560d1a9f3083 6996 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 423:560d1a9f3083 6997 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
mbed_official 423:560d1a9f3083 6998 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
mbed_official 423:560d1a9f3083 6999 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 423:560d1a9f3083 7000 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 423:560d1a9f3083 7001
mbed_official 423:560d1a9f3083 7002 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
mbed_official 423:560d1a9f3083 7003 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
mbed_official 423:560d1a9f3083 7004
mbed_official 423:560d1a9f3083 7005 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
mbed_official 423:560d1a9f3083 7006 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
mbed_official 423:560d1a9f3083 7007
mbed_official 423:560d1a9f3083 7008 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 423:560d1a9f3083 7009 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 423:560d1a9f3083 7010 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7011 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7012 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7013 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7014 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 7015
mbed_official 423:560d1a9f3083 7016 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 423:560d1a9f3083 7017 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7018 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7019 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7020 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7021 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 7022
mbed_official 423:560d1a9f3083 7023 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 423:560d1a9f3083 7024 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 423:560d1a9f3083 7025
mbed_official 423:560d1a9f3083 7026 /******************* Bit definition for TIM16_OR register ********************/
mbed_official 423:560d1a9f3083 7027 #define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
mbed_official 423:560d1a9f3083 7028 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7029 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7030
mbed_official 423:560d1a9f3083 7031 /******************* Bit definition for TIM1_OR register ********************/
mbed_official 423:560d1a9f3083 7032 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
mbed_official 423:560d1a9f3083 7033 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7034 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7035 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7036 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7037
mbed_official 423:560d1a9f3083 7038 /******************* Bit definition for TIM8_OR register ********************/
mbed_official 423:560d1a9f3083 7039 #define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
mbed_official 423:560d1a9f3083 7040 #define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7041 #define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7042 #define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7043 #define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7044
mbed_official 423:560d1a9f3083 7045 /******************* Bit definition for TIM20_OR register *******************/
mbed_official 423:560d1a9f3083 7046 #define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
mbed_official 423:560d1a9f3083 7047 #define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7048 #define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7049 #define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7050 #define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7051
mbed_official 423:560d1a9f3083 7052 /****************** Bit definition for TIM_CCMR3 register *******************/
mbed_official 423:560d1a9f3083 7053 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
mbed_official 423:560d1a9f3083 7054 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
mbed_official 423:560d1a9f3083 7055
mbed_official 423:560d1a9f3083 7056 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
mbed_official 423:560d1a9f3083 7057 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7058 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7059 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7060 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7061
mbed_official 423:560d1a9f3083 7062 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
mbed_official 423:560d1a9f3083 7063
mbed_official 423:560d1a9f3083 7064 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
mbed_official 423:560d1a9f3083 7065 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
mbed_official 423:560d1a9f3083 7066
mbed_official 423:560d1a9f3083 7067 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
mbed_official 423:560d1a9f3083 7068 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7069 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7070 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7071 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7072
mbed_official 423:560d1a9f3083 7073 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
mbed_official 423:560d1a9f3083 7074
mbed_official 423:560d1a9f3083 7075 /******************************************************************************/
mbed_official 423:560d1a9f3083 7076 /* */
mbed_official 423:560d1a9f3083 7077 /* Touch Sensing Controller (TSC) */
mbed_official 423:560d1a9f3083 7078 /* */
mbed_official 423:560d1a9f3083 7079 /******************************************************************************/
mbed_official 423:560d1a9f3083 7080 /******************* Bit definition for TSC_CR register *********************/
mbed_official 423:560d1a9f3083 7081 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 423:560d1a9f3083 7082 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 423:560d1a9f3083 7083 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 423:560d1a9f3083 7084 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 423:560d1a9f3083 7085 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 423:560d1a9f3083 7086
mbed_official 423:560d1a9f3083 7087 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 423:560d1a9f3083 7088 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7089 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7090 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7091
mbed_official 423:560d1a9f3083 7092 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 423:560d1a9f3083 7093 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7094 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7095 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7096
mbed_official 423:560d1a9f3083 7097 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 423:560d1a9f3083 7098 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 423:560d1a9f3083 7099
mbed_official 423:560d1a9f3083 7100 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 423:560d1a9f3083 7101 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7102 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7103 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7104 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7105 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 7106 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 7107 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 7108
mbed_official 423:560d1a9f3083 7109 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 423:560d1a9f3083 7110 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7111 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7112 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7113 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7114
mbed_official 423:560d1a9f3083 7115 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 423:560d1a9f3083 7116 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7117 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7118 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7119 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7120
mbed_official 423:560d1a9f3083 7121 /******************* Bit definition for TSC_IER register ********************/
mbed_official 423:560d1a9f3083 7122 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 423:560d1a9f3083 7123 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 423:560d1a9f3083 7124
mbed_official 423:560d1a9f3083 7125 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 423:560d1a9f3083 7126 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 423:560d1a9f3083 7127 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 423:560d1a9f3083 7128
mbed_official 423:560d1a9f3083 7129 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 423:560d1a9f3083 7130 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 423:560d1a9f3083 7131 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 423:560d1a9f3083 7132
mbed_official 423:560d1a9f3083 7133 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 423:560d1a9f3083 7134 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7135 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7136 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7137 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7138 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7139 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7140 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7141 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7142 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7143 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7144 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7145 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7146 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7147 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7148 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7149 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7150 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7151 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7152 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7153 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7154 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7155 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7156 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7157 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7158 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7159 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7160 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7161 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7162 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7163 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7164 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7165 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 423:560d1a9f3083 7166
mbed_official 423:560d1a9f3083 7167 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 423:560d1a9f3083 7168 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7169 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7170 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7171 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7172 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7173 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7174 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7175 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7176 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7177 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7178 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7179 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7180 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7181 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7182 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7183 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7184 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7185 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7186 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7187 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7188 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7189 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7190 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7191 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7192 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7193 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7194 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7195 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7196 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 423:560d1a9f3083 7197 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 423:560d1a9f3083 7198 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 423:560d1a9f3083 7199 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 423:560d1a9f3083 7200
mbed_official 423:560d1a9f3083 7201 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 423:560d1a9f3083 7202 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7203 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7204 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7205 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7206 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7207 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7208 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7209 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7210 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7211 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7212 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7213 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7214 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7215 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7216 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7217 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7218 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7219 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7220 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7221 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7222 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7223 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7224 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7225 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7226 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7227 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7228 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7229 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7230 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 423:560d1a9f3083 7231 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 423:560d1a9f3083 7232 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 423:560d1a9f3083 7233 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 423:560d1a9f3083 7234
mbed_official 423:560d1a9f3083 7235 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 423:560d1a9f3083 7236 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 423:560d1a9f3083 7237 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 423:560d1a9f3083 7238 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 423:560d1a9f3083 7239 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 423:560d1a9f3083 7240 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 423:560d1a9f3083 7241 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 423:560d1a9f3083 7242 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 423:560d1a9f3083 7243 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 423:560d1a9f3083 7244 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 423:560d1a9f3083 7245 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 423:560d1a9f3083 7246 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 423:560d1a9f3083 7247 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 423:560d1a9f3083 7248 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 423:560d1a9f3083 7249 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 423:560d1a9f3083 7250 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 423:560d1a9f3083 7251 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 423:560d1a9f3083 7252 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 423:560d1a9f3083 7253 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 423:560d1a9f3083 7254 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 423:560d1a9f3083 7255 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 423:560d1a9f3083 7256 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 423:560d1a9f3083 7257 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 423:560d1a9f3083 7258 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 423:560d1a9f3083 7259 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 423:560d1a9f3083 7260 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 423:560d1a9f3083 7261 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 423:560d1a9f3083 7262 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 423:560d1a9f3083 7263 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 423:560d1a9f3083 7264 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 423:560d1a9f3083 7265 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 423:560d1a9f3083 7266 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 423:560d1a9f3083 7267 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 423:560d1a9f3083 7268
mbed_official 423:560d1a9f3083 7269 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 423:560d1a9f3083 7270 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 423:560d1a9f3083 7271 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 423:560d1a9f3083 7272 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 423:560d1a9f3083 7273 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 423:560d1a9f3083 7274 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 423:560d1a9f3083 7275 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 423:560d1a9f3083 7276 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 423:560d1a9f3083 7277 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 423:560d1a9f3083 7278 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 423:560d1a9f3083 7279 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 423:560d1a9f3083 7280 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 423:560d1a9f3083 7281 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 423:560d1a9f3083 7282 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 423:560d1a9f3083 7283 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 423:560d1a9f3083 7284 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 423:560d1a9f3083 7285 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 423:560d1a9f3083 7286
mbed_official 423:560d1a9f3083 7287 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 423:560d1a9f3083 7288 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 423:560d1a9f3083 7289
mbed_official 423:560d1a9f3083 7290 /******************************************************************************/
mbed_official 423:560d1a9f3083 7291 /* */
mbed_official 423:560d1a9f3083 7292 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 423:560d1a9f3083 7293 /* */
mbed_official 423:560d1a9f3083 7294 /******************************************************************************/
mbed_official 423:560d1a9f3083 7295 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 423:560d1a9f3083 7296 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 423:560d1a9f3083 7297 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 423:560d1a9f3083 7298 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 423:560d1a9f3083 7299 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 423:560d1a9f3083 7300 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 423:560d1a9f3083 7301 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 423:560d1a9f3083 7302 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 423:560d1a9f3083 7303 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 423:560d1a9f3083 7304 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 423:560d1a9f3083 7305 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 423:560d1a9f3083 7306 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 423:560d1a9f3083 7307 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 423:560d1a9f3083 7308 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 423:560d1a9f3083 7309 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 423:560d1a9f3083 7310 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 423:560d1a9f3083 7311 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 423:560d1a9f3083 7312 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 423:560d1a9f3083 7313 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7314 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7315 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 7316 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 7317 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 423:560d1a9f3083 7318 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 423:560d1a9f3083 7319 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7320 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7321 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 7322 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 423:560d1a9f3083 7323 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 423:560d1a9f3083 7324 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 423:560d1a9f3083 7325 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 423:560d1a9f3083 7326 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
mbed_official 423:560d1a9f3083 7327 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
mbed_official 423:560d1a9f3083 7328
mbed_official 423:560d1a9f3083 7329 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 423:560d1a9f3083 7330 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 423:560d1a9f3083 7331 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 423:560d1a9f3083 7332 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 423:560d1a9f3083 7333 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 423:560d1a9f3083 7334 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 423:560d1a9f3083 7335 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 423:560d1a9f3083 7336 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 423:560d1a9f3083 7337 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 423:560d1a9f3083 7338 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7339 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7340 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 423:560d1a9f3083 7341 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 423:560d1a9f3083 7342 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 423:560d1a9f3083 7343 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 423:560d1a9f3083 7344 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 423:560d1a9f3083 7345 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 423:560d1a9f3083 7346 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 423:560d1a9f3083 7347 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 423:560d1a9f3083 7348 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7349 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7350 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 423:560d1a9f3083 7351 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 423:560d1a9f3083 7352
mbed_official 423:560d1a9f3083 7353 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 423:560d1a9f3083 7354 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 423:560d1a9f3083 7355 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 423:560d1a9f3083 7356 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 423:560d1a9f3083 7357 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 423:560d1a9f3083 7358 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 423:560d1a9f3083 7359 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 423:560d1a9f3083 7360 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 423:560d1a9f3083 7361 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 423:560d1a9f3083 7362 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 423:560d1a9f3083 7363 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 423:560d1a9f3083 7364 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 423:560d1a9f3083 7365 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 423:560d1a9f3083 7366 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 423:560d1a9f3083 7367 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 423:560d1a9f3083 7368 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 423:560d1a9f3083 7369 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 423:560d1a9f3083 7370 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 423:560d1a9f3083 7371 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7372 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7373 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 423:560d1a9f3083 7374 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 423:560d1a9f3083 7375 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 423:560d1a9f3083 7376 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 423:560d1a9f3083 7377 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 423:560d1a9f3083 7378
mbed_official 423:560d1a9f3083 7379 /****************** Bit definition for USART_BRR register *******************/
mbed_official 423:560d1a9f3083 7380 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 423:560d1a9f3083 7381 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 423:560d1a9f3083 7382
mbed_official 423:560d1a9f3083 7383 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 423:560d1a9f3083 7384 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 423:560d1a9f3083 7385 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 423:560d1a9f3083 7386
mbed_official 423:560d1a9f3083 7387
mbed_official 423:560d1a9f3083 7388 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 423:560d1a9f3083 7389 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 423:560d1a9f3083 7390 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 423:560d1a9f3083 7391
mbed_official 423:560d1a9f3083 7392 /******************* Bit definition for USART_RQR register ******************/
mbed_official 423:560d1a9f3083 7393 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 423:560d1a9f3083 7394 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 423:560d1a9f3083 7395 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 423:560d1a9f3083 7396 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 423:560d1a9f3083 7397 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 423:560d1a9f3083 7398
mbed_official 423:560d1a9f3083 7399 /******************* Bit definition for USART_ISR register ******************/
mbed_official 423:560d1a9f3083 7400 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 423:560d1a9f3083 7401 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 423:560d1a9f3083 7402 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 423:560d1a9f3083 7403 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 423:560d1a9f3083 7404 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 423:560d1a9f3083 7405 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 423:560d1a9f3083 7406 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 423:560d1a9f3083 7407 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 423:560d1a9f3083 7408 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 423:560d1a9f3083 7409 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 423:560d1a9f3083 7410 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 423:560d1a9f3083 7411 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 423:560d1a9f3083 7412 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 423:560d1a9f3083 7413 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 423:560d1a9f3083 7414 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 423:560d1a9f3083 7415 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 423:560d1a9f3083 7416 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 423:560d1a9f3083 7417 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 423:560d1a9f3083 7418 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 423:560d1a9f3083 7419 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 423:560d1a9f3083 7420 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 423:560d1a9f3083 7421 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 423:560d1a9f3083 7422
mbed_official 423:560d1a9f3083 7423 /******************* Bit definition for USART_ICR register ******************/
mbed_official 423:560d1a9f3083 7424 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 423:560d1a9f3083 7425 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 423:560d1a9f3083 7426 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 423:560d1a9f3083 7427 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 423:560d1a9f3083 7428 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 423:560d1a9f3083 7429 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 423:560d1a9f3083 7430 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 423:560d1a9f3083 7431 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 423:560d1a9f3083 7432 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 423:560d1a9f3083 7433 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 423:560d1a9f3083 7434 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 423:560d1a9f3083 7435 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 423:560d1a9f3083 7436
mbed_official 423:560d1a9f3083 7437 /******************* Bit definition for USART_RDR register ******************/
mbed_official 423:560d1a9f3083 7438 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 423:560d1a9f3083 7439
mbed_official 423:560d1a9f3083 7440 /******************* Bit definition for USART_TDR register ******************/
mbed_official 423:560d1a9f3083 7441 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 423:560d1a9f3083 7442
mbed_official 423:560d1a9f3083 7443 /******************************************************************************/
mbed_official 423:560d1a9f3083 7444 /* */
mbed_official 423:560d1a9f3083 7445 /* USB Device General registers */
mbed_official 423:560d1a9f3083 7446 /* */
mbed_official 423:560d1a9f3083 7447 /******************************************************************************/
mbed_official 423:560d1a9f3083 7448 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
mbed_official 423:560d1a9f3083 7449 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
mbed_official 423:560d1a9f3083 7450 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
mbed_official 423:560d1a9f3083 7451 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
mbed_official 423:560d1a9f3083 7452 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
mbed_official 423:560d1a9f3083 7453 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
mbed_official 423:560d1a9f3083 7454
mbed_official 423:560d1a9f3083 7455 /**************************** ISTR interrupt events *************************/
mbed_official 423:560d1a9f3083 7456 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
mbed_official 423:560d1a9f3083 7457 #define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
mbed_official 423:560d1a9f3083 7458 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
mbed_official 423:560d1a9f3083 7459 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
mbed_official 423:560d1a9f3083 7460 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
mbed_official 423:560d1a9f3083 7461 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
mbed_official 423:560d1a9f3083 7462 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
mbed_official 423:560d1a9f3083 7463 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
mbed_official 423:560d1a9f3083 7464 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
mbed_official 423:560d1a9f3083 7465 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
mbed_official 423:560d1a9f3083 7466 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
mbed_official 423:560d1a9f3083 7467
mbed_official 423:560d1a9f3083 7468 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 423:560d1a9f3083 7469 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 423:560d1a9f3083 7470 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 423:560d1a9f3083 7471 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 423:560d1a9f3083 7472 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 423:560d1a9f3083 7473 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 423:560d1a9f3083 7474 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 423:560d1a9f3083 7475 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 423:560d1a9f3083 7476 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
mbed_official 423:560d1a9f3083 7477
mbed_official 423:560d1a9f3083 7478 /************************* CNTR control register bits definitions ***********/
mbed_official 423:560d1a9f3083 7479 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
mbed_official 423:560d1a9f3083 7480 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
mbed_official 423:560d1a9f3083 7481 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
mbed_official 423:560d1a9f3083 7482 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
mbed_official 423:560d1a9f3083 7483 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
mbed_official 423:560d1a9f3083 7484 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
mbed_official 423:560d1a9f3083 7485 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
mbed_official 423:560d1a9f3083 7486 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
mbed_official 423:560d1a9f3083 7487 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
mbed_official 423:560d1a9f3083 7488 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
mbed_official 423:560d1a9f3083 7489 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
mbed_official 423:560d1a9f3083 7490 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
mbed_official 423:560d1a9f3083 7491 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
mbed_official 423:560d1a9f3083 7492 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
mbed_official 423:560d1a9f3083 7493 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
mbed_official 423:560d1a9f3083 7494
mbed_official 423:560d1a9f3083 7495 /*************************** LPM register bits definitions ******************/
mbed_official 423:560d1a9f3083 7496 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
mbed_official 423:560d1a9f3083 7497 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 423:560d1a9f3083 7498 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
mbed_official 423:560d1a9f3083 7499 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
mbed_official 423:560d1a9f3083 7500
mbed_official 423:560d1a9f3083 7501 /******************** FNR Frame Number Register bit definitions ************/
mbed_official 423:560d1a9f3083 7502 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
mbed_official 423:560d1a9f3083 7503 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
mbed_official 423:560d1a9f3083 7504 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
mbed_official 423:560d1a9f3083 7505 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
mbed_official 423:560d1a9f3083 7506 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
mbed_official 423:560d1a9f3083 7507
mbed_official 423:560d1a9f3083 7508 /******************** DADDR Device ADDRess bit definitions ****************/
mbed_official 423:560d1a9f3083 7509 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
mbed_official 423:560d1a9f3083 7510 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
mbed_official 423:560d1a9f3083 7511
mbed_official 423:560d1a9f3083 7512 /****************************** Endpoint register *************************/
mbed_official 423:560d1a9f3083 7513 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 423:560d1a9f3083 7514 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
mbed_official 423:560d1a9f3083 7515 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
mbed_official 423:560d1a9f3083 7516 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
mbed_official 423:560d1a9f3083 7517 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
mbed_official 423:560d1a9f3083 7518 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
mbed_official 423:560d1a9f3083 7519 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
mbed_official 423:560d1a9f3083 7520 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
mbed_official 423:560d1a9f3083 7521 /* bit positions */
mbed_official 423:560d1a9f3083 7522 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
mbed_official 423:560d1a9f3083 7523 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
mbed_official 423:560d1a9f3083 7524 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
mbed_official 423:560d1a9f3083 7525 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
mbed_official 423:560d1a9f3083 7526 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
mbed_official 423:560d1a9f3083 7527 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
mbed_official 423:560d1a9f3083 7528 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
mbed_official 423:560d1a9f3083 7529 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
mbed_official 423:560d1a9f3083 7530 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
mbed_official 423:560d1a9f3083 7531 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
mbed_official 423:560d1a9f3083 7532
mbed_official 423:560d1a9f3083 7533 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 423:560d1a9f3083 7534 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 423:560d1a9f3083 7535 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 423:560d1a9f3083 7536 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
mbed_official 423:560d1a9f3083 7537 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
mbed_official 423:560d1a9f3083 7538 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
mbed_official 423:560d1a9f3083 7539 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
mbed_official 423:560d1a9f3083 7540 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
mbed_official 423:560d1a9f3083 7541 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 423:560d1a9f3083 7542
mbed_official 423:560d1a9f3083 7543 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 423:560d1a9f3083 7544 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 423:560d1a9f3083 7545 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
mbed_official 423:560d1a9f3083 7546 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
mbed_official 423:560d1a9f3083 7547 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
mbed_official 423:560d1a9f3083 7548 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
mbed_official 423:560d1a9f3083 7549 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 423:560d1a9f3083 7550 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 423:560d1a9f3083 7551 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 423:560d1a9f3083 7552 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 423:560d1a9f3083 7553 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
mbed_official 423:560d1a9f3083 7554 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
mbed_official 423:560d1a9f3083 7555 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
mbed_official 423:560d1a9f3083 7556 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
mbed_official 423:560d1a9f3083 7557 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 423:560d1a9f3083 7558 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 423:560d1a9f3083 7559 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 423:560d1a9f3083 7560
mbed_official 423:560d1a9f3083 7561 /******************************************************************************/
mbed_official 423:560d1a9f3083 7562 /* */
mbed_official 423:560d1a9f3083 7563 /* Window WATCHDOG */
mbed_official 423:560d1a9f3083 7564 /* */
mbed_official 423:560d1a9f3083 7565 /******************************************************************************/
mbed_official 423:560d1a9f3083 7566 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 423:560d1a9f3083 7567 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 423:560d1a9f3083 7568 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7569 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7570 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7571 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7572 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 7573 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 7574 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 7575
mbed_official 423:560d1a9f3083 7576 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
mbed_official 423:560d1a9f3083 7577
mbed_official 423:560d1a9f3083 7578 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 423:560d1a9f3083 7579 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 423:560d1a9f3083 7580 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7581 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7582 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 423:560d1a9f3083 7583 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 423:560d1a9f3083 7584 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 423:560d1a9f3083 7585 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 423:560d1a9f3083 7586 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 423:560d1a9f3083 7587
mbed_official 423:560d1a9f3083 7588 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 423:560d1a9f3083 7589 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 423:560d1a9f3083 7590 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 423:560d1a9f3083 7591
mbed_official 423:560d1a9f3083 7592 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
mbed_official 423:560d1a9f3083 7593
mbed_official 423:560d1a9f3083 7594 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 423:560d1a9f3083 7595 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
mbed_official 423:560d1a9f3083 7596
mbed_official 423:560d1a9f3083 7597 /**
mbed_official 423:560d1a9f3083 7598 * @}
mbed_official 423:560d1a9f3083 7599 */
mbed_official 423:560d1a9f3083 7600
mbed_official 423:560d1a9f3083 7601 /**
mbed_official 423:560d1a9f3083 7602 * @}
mbed_official 423:560d1a9f3083 7603 */
mbed_official 423:560d1a9f3083 7604
mbed_official 423:560d1a9f3083 7605 /** @addtogroup Exported_macros
mbed_official 423:560d1a9f3083 7606 * @{
mbed_official 423:560d1a9f3083 7607 */
mbed_official 423:560d1a9f3083 7608
mbed_official 423:560d1a9f3083 7609 /****************************** ADC Instances *********************************/
mbed_official 423:560d1a9f3083 7610 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 423:560d1a9f3083 7611 ((INSTANCE) == ADC2) || \
mbed_official 423:560d1a9f3083 7612 ((INSTANCE) == ADC3) || \
mbed_official 423:560d1a9f3083 7613 ((INSTANCE) == ADC4))
mbed_official 423:560d1a9f3083 7614
mbed_official 423:560d1a9f3083 7615 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 423:560d1a9f3083 7616 ((INSTANCE) == ADC3))
mbed_official 423:560d1a9f3083 7617
mbed_official 423:560d1a9f3083 7618 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
mbed_official 423:560d1a9f3083 7619 ((INSTANCE) == ADC3_4_COMMON))
mbed_official 423:560d1a9f3083 7620
mbed_official 423:560d1a9f3083 7621 /****************************** CAN Instances *********************************/
mbed_official 423:560d1a9f3083 7622 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 423:560d1a9f3083 7623
mbed_official 423:560d1a9f3083 7624 /****************************** COMP Instances ********************************/
mbed_official 423:560d1a9f3083 7625 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 423:560d1a9f3083 7626 ((INSTANCE) == COMP2) || \
mbed_official 423:560d1a9f3083 7627 ((INSTANCE) == COMP3) || \
mbed_official 423:560d1a9f3083 7628 ((INSTANCE) == COMP4) || \
mbed_official 423:560d1a9f3083 7629 ((INSTANCE) == COMP5) || \
mbed_official 423:560d1a9f3083 7630 ((INSTANCE) == COMP6) || \
mbed_official 423:560d1a9f3083 7631 ((INSTANCE) == COMP7))
mbed_official 423:560d1a9f3083 7632
mbed_official 423:560d1a9f3083 7633 /******************** COMP Instances with window mode capability **************/
mbed_official 423:560d1a9f3083 7634 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
mbed_official 423:560d1a9f3083 7635 ((INSTANCE) == COMP4) || \
mbed_official 423:560d1a9f3083 7636 ((INSTANCE) == COMP6))
mbed_official 423:560d1a9f3083 7637
mbed_official 423:560d1a9f3083 7638 /****************************** CRC Instances *********************************/
mbed_official 423:560d1a9f3083 7639 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 423:560d1a9f3083 7640
mbed_official 423:560d1a9f3083 7641 /****************************** DAC Instances *********************************/
mbed_official 423:560d1a9f3083 7642 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
mbed_official 423:560d1a9f3083 7643
mbed_official 423:560d1a9f3083 7644 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 423:560d1a9f3083 7645 (((INSTANCE) == DAC1) && \
mbed_official 423:560d1a9f3083 7646 (((CHANNEL) == DAC_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7647 ((CHANNEL) == DAC_CHANNEL_2)))
mbed_official 423:560d1a9f3083 7648
mbed_official 423:560d1a9f3083 7649 /****************************** DMA Instances *********************************/
mbed_official 423:560d1a9f3083 7650 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 423:560d1a9f3083 7651 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 423:560d1a9f3083 7652 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 423:560d1a9f3083 7653 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 423:560d1a9f3083 7654 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 423:560d1a9f3083 7655 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 423:560d1a9f3083 7656 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 423:560d1a9f3083 7657 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 423:560d1a9f3083 7658 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 423:560d1a9f3083 7659 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 423:560d1a9f3083 7660 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 423:560d1a9f3083 7661 ((INSTANCE) == DMA2_Channel5))
mbed_official 423:560d1a9f3083 7662
mbed_official 423:560d1a9f3083 7663 /****************************** GPIO Instances ********************************/
mbed_official 423:560d1a9f3083 7664 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 423:560d1a9f3083 7665 ((INSTANCE) == GPIOB) || \
mbed_official 423:560d1a9f3083 7666 ((INSTANCE) == GPIOC) || \
mbed_official 423:560d1a9f3083 7667 ((INSTANCE) == GPIOD) || \
mbed_official 423:560d1a9f3083 7668 ((INSTANCE) == GPIOE) || \
mbed_official 423:560d1a9f3083 7669 ((INSTANCE) == GPIOF) || \
mbed_official 423:560d1a9f3083 7670 ((INSTANCE) == GPIOG) || \
mbed_official 423:560d1a9f3083 7671 ((INSTANCE) == GPIOH))
mbed_official 423:560d1a9f3083 7672
mbed_official 423:560d1a9f3083 7673 /****************************** I2C Instances *********************************/
mbed_official 423:560d1a9f3083 7674 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 423:560d1a9f3083 7675 ((INSTANCE) == I2C2) || \
mbed_official 423:560d1a9f3083 7676 ((INSTANCE) == I2C3))
mbed_official 423:560d1a9f3083 7677
mbed_official 423:560d1a9f3083 7678 /****************************** I2S Instances *********************************/
mbed_official 423:560d1a9f3083 7679 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 423:560d1a9f3083 7680 ((INSTANCE) == SPI3))
mbed_official 423:560d1a9f3083 7681
mbed_official 423:560d1a9f3083 7682 /****************************** IWDG Instances ********************************/
mbed_official 423:560d1a9f3083 7683 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 423:560d1a9f3083 7684
mbed_official 423:560d1a9f3083 7685 /****************************** OPAMP Instances *******************************/
mbed_official 423:560d1a9f3083 7686 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
mbed_official 423:560d1a9f3083 7687 ((INSTANCE) == OPAMP2) || \
mbed_official 423:560d1a9f3083 7688 ((INSTANCE) == OPAMP3) || \
mbed_official 423:560d1a9f3083 7689 ((INSTANCE) == OPAMP4))
mbed_official 423:560d1a9f3083 7690
mbed_official 423:560d1a9f3083 7691 /****************************** RTC Instances *********************************/
mbed_official 423:560d1a9f3083 7692 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 423:560d1a9f3083 7693
mbed_official 423:560d1a9f3083 7694 /****************************** SMBUS Instances *******************************/
mbed_official 423:560d1a9f3083 7695 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 423:560d1a9f3083 7696 ((INSTANCE) == I2C2) || \
mbed_official 423:560d1a9f3083 7697 ((INSTANCE) == I2C3))
mbed_official 423:560d1a9f3083 7698
mbed_official 423:560d1a9f3083 7699 /****************************** SPI Instances *********************************/
mbed_official 423:560d1a9f3083 7700 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 423:560d1a9f3083 7701 ((INSTANCE) == SPI2) || \
mbed_official 423:560d1a9f3083 7702 ((INSTANCE) == SPI3) || \
mbed_official 423:560d1a9f3083 7703 ((INSTANCE) == SPI4))
mbed_official 423:560d1a9f3083 7704
mbed_official 423:560d1a9f3083 7705 /******************* TIM Instances : All supported instances ******************/
mbed_official 423:560d1a9f3083 7706 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7707 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7708 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7709 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7710 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7711 ((INSTANCE) == TIM6) || \
mbed_official 423:560d1a9f3083 7712 ((INSTANCE) == TIM7) || \
mbed_official 423:560d1a9f3083 7713 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7714 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7715 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 7716 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 7717 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7718
mbed_official 423:560d1a9f3083 7719 /******************* TIM Instances : at least 1 capture/compare channel *******/
mbed_official 423:560d1a9f3083 7720 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7721 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7722 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7723 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7724 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7725 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7726 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7727 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 7728 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 7729 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7730
mbed_official 423:560d1a9f3083 7731 /****************** TIM Instances : at least 2 capture/compare channels *******/
mbed_official 423:560d1a9f3083 7732 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7733 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7734 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7735 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7736 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7737 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7738 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7739 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7740
mbed_official 423:560d1a9f3083 7741 /****************** TIM Instances : at least 3 capture/compare channels *******/
mbed_official 423:560d1a9f3083 7742 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7743 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7744 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7745 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7746 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7747 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7748 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7749
mbed_official 423:560d1a9f3083 7750 /****************** TIM Instances : at least 4 capture/compare channels *******/
mbed_official 423:560d1a9f3083 7751 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7752 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7753 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7754 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7755 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7756 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7757 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7758
mbed_official 423:560d1a9f3083 7759 /****************** TIM Instances : at least 5 capture/compare channels *******/
mbed_official 423:560d1a9f3083 7760 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7761 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7762 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7763 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7764
mbed_official 423:560d1a9f3083 7765 /****************** TIM Instances : at least 6 capture/compare channels *******/
mbed_official 423:560d1a9f3083 7766 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7767 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7768 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7769 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7770
mbed_official 423:560d1a9f3083 7771 /************************** TIM Instances : Advanced-control timers ***********/
mbed_official 423:560d1a9f3083 7772
mbed_official 423:560d1a9f3083 7773 /****************** TIM Instances : supporting clock selection ****************/
mbed_official 423:560d1a9f3083 7774 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7775 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7776 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7777 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7778 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7779 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7780 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7781 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7782
mbed_official 423:560d1a9f3083 7783 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
mbed_official 423:560d1a9f3083 7784 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7785 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7786 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7787 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7788 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7789 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7790 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7791
mbed_official 423:560d1a9f3083 7792 /****************** TIM Instances : supporting external clock mode 2 **********/
mbed_official 423:560d1a9f3083 7793 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7794 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7795 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7796 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7797 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7798 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7799 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7800
mbed_official 423:560d1a9f3083 7801 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 423:560d1a9f3083 7802 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7803 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7804 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7805 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7806 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7807 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7808 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7809 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7810
mbed_official 423:560d1a9f3083 7811 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 423:560d1a9f3083 7812 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7813 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7814 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7815 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7816 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7817 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7818 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7819 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7820
mbed_official 423:560d1a9f3083 7821 /****************** TIM Instances : supporting OCxREF clear *******************/
mbed_official 423:560d1a9f3083 7822 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7823 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7824 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7825 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7826 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7827 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7828 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7829
mbed_official 423:560d1a9f3083 7830 /****************** TIM Instances : supporting encoder interface **************/
mbed_official 423:560d1a9f3083 7831 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7832 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7833 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7834 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7835 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7836 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7837 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7838
mbed_official 423:560d1a9f3083 7839 /****************** TIM Instances : supporting Hall interface *****************/
mbed_official 423:560d1a9f3083 7840 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7841 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7842 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7843 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7844
mbed_official 423:560d1a9f3083 7845 /****************** TIM Instances : supporting input XOR function *************/
mbed_official 423:560d1a9f3083 7846 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7847 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7848 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7849 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7850 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7851 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7852 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7853 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7854
mbed_official 423:560d1a9f3083 7855 /****************** TIM Instances : supporting master mode ********************/
mbed_official 423:560d1a9f3083 7856 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7857 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7858 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7859 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7860 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7861 ((INSTANCE) == TIM6) || \
mbed_official 423:560d1a9f3083 7862 ((INSTANCE) == TIM7) || \
mbed_official 423:560d1a9f3083 7863 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7864 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7865 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7866
mbed_official 423:560d1a9f3083 7867 /****************** TIM Instances : supporting slave mode *********************/
mbed_official 423:560d1a9f3083 7868 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7869 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7870 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7871 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7872 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7873 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7874 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7875 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7876
mbed_official 423:560d1a9f3083 7877 /****************** TIM Instances : supporting synchronization ****************/
mbed_official 423:560d1a9f3083 7878 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7879 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7880 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7881 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7882 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7883 ((INSTANCE) == TIM6) || \
mbed_official 423:560d1a9f3083 7884 ((INSTANCE) == TIM7) || \
mbed_official 423:560d1a9f3083 7885 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7886 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7887 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7888
mbed_official 423:560d1a9f3083 7889 /****************** TIM Instances : supporting 32 bits counter ****************/
mbed_official 423:560d1a9f3083 7890 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7891 ((INSTANCE) == TIM2)
mbed_official 423:560d1a9f3083 7892
mbed_official 423:560d1a9f3083 7893 /****************** TIM Instances : supporting DMA burst **********************/
mbed_official 423:560d1a9f3083 7894 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7895 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7896 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7897 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7898 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 7899 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7900 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7901 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 7902 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 7903 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7904
mbed_official 423:560d1a9f3083 7905 /****************** TIM Instances : supporting the break function *************/
mbed_official 423:560d1a9f3083 7906 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7907 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7908 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 7909 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 7910 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 7911 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 7912 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 7913
mbed_official 423:560d1a9f3083 7914 /****************** TIM Instances : supporting input/output channel(s) ********/
mbed_official 423:560d1a9f3083 7915 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 423:560d1a9f3083 7916 ((((INSTANCE) == TIM1) && \
mbed_official 423:560d1a9f3083 7917 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7918 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7919 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7920 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 423:560d1a9f3083 7921 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 423:560d1a9f3083 7922 ((CHANNEL) == TIM_CHANNEL_6))) \
mbed_official 423:560d1a9f3083 7923 || \
mbed_official 423:560d1a9f3083 7924 (((INSTANCE) == TIM2) && \
mbed_official 423:560d1a9f3083 7925 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7926 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7927 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7928 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 423:560d1a9f3083 7929 || \
mbed_official 423:560d1a9f3083 7930 (((INSTANCE) == TIM3) && \
mbed_official 423:560d1a9f3083 7931 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7932 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7933 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7934 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 423:560d1a9f3083 7935 || \
mbed_official 423:560d1a9f3083 7936 (((INSTANCE) == TIM4) && \
mbed_official 423:560d1a9f3083 7937 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7938 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7939 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7940 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 423:560d1a9f3083 7941 || \
mbed_official 423:560d1a9f3083 7942 (((INSTANCE) == TIM8) && \
mbed_official 423:560d1a9f3083 7943 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7944 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7945 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7946 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 423:560d1a9f3083 7947 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 423:560d1a9f3083 7948 ((CHANNEL) == TIM_CHANNEL_6))) \
mbed_official 423:560d1a9f3083 7949 || \
mbed_official 423:560d1a9f3083 7950 (((INSTANCE) == TIM15) && \
mbed_official 423:560d1a9f3083 7951 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7952 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 423:560d1a9f3083 7953 || \
mbed_official 423:560d1a9f3083 7954 (((INSTANCE) == TIM16) && \
mbed_official 423:560d1a9f3083 7955 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 423:560d1a9f3083 7956 || \
mbed_official 423:560d1a9f3083 7957 (((INSTANCE) == TIM17) && \
mbed_official 423:560d1a9f3083 7958 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 423:560d1a9f3083 7959 || \
mbed_official 423:560d1a9f3083 7960 (((INSTANCE) == TIM20) && \
mbed_official 423:560d1a9f3083 7961 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7962 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7963 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 423:560d1a9f3083 7964 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 423:560d1a9f3083 7965 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 423:560d1a9f3083 7966 ((CHANNEL) == TIM_CHANNEL_6))))
mbed_official 423:560d1a9f3083 7967
mbed_official 423:560d1a9f3083 7968 /****************** TIM Instances : supporting complementary output(s) ********/
mbed_official 423:560d1a9f3083 7969 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 423:560d1a9f3083 7970 ((((INSTANCE) == TIM1) && \
mbed_official 423:560d1a9f3083 7971 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7972 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7973 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 423:560d1a9f3083 7974 || \
mbed_official 423:560d1a9f3083 7975 (((INSTANCE) == TIM8) && \
mbed_official 423:560d1a9f3083 7976 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7977 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7978 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 423:560d1a9f3083 7979 || \
mbed_official 423:560d1a9f3083 7980 (((INSTANCE) == TIM15) && \
mbed_official 423:560d1a9f3083 7981 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 423:560d1a9f3083 7982 || \
mbed_official 423:560d1a9f3083 7983 (((INSTANCE) == TIM16) && \
mbed_official 423:560d1a9f3083 7984 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 423:560d1a9f3083 7985 || \
mbed_official 423:560d1a9f3083 7986 (((INSTANCE) == TIM17) && \
mbed_official 423:560d1a9f3083 7987 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 423:560d1a9f3083 7988 || \
mbed_official 423:560d1a9f3083 7989 (((INSTANCE) == TIM20) && \
mbed_official 423:560d1a9f3083 7990 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 423:560d1a9f3083 7991 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 423:560d1a9f3083 7992 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 423:560d1a9f3083 7993
mbed_official 423:560d1a9f3083 7994 /****************** TIM Instances : supporting counting mode selection ********/
mbed_official 423:560d1a9f3083 7995 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 7996 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 7997 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 7998 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 7999 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 8000 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8001 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8002
mbed_official 423:560d1a9f3083 8003 /****************** TIM Instances : supporting repetition counter *************/
mbed_official 423:560d1a9f3083 8004 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8005 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8006 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8007 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 8008 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8009 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 8010 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8011
mbed_official 423:560d1a9f3083 8012 /****************** TIM Instances : supporting clock division *****************/
mbed_official 423:560d1a9f3083 8013 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8014 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8015 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 8016 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 8017 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 8018 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8019 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 8020 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8021 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 8022 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8023
mbed_official 423:560d1a9f3083 8024 /****************** TIM Instances : supporting 2 break inputs *****************/
mbed_official 423:560d1a9f3083 8025 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8026 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8027 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8028 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8029
mbed_official 423:560d1a9f3083 8030 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
mbed_official 423:560d1a9f3083 8031 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8032 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8033 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8034 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8035
mbed_official 423:560d1a9f3083 8036 /****************** TIM Instances : supporting DMA generation on Update events*/
mbed_official 423:560d1a9f3083 8037 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8038 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8039 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 8040 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 8041 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 8042 ((INSTANCE) == TIM6) || \
mbed_official 423:560d1a9f3083 8043 ((INSTANCE) == TIM7) || \
mbed_official 423:560d1a9f3083 8044 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8045 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 8046 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8047 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 8048 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8049
mbed_official 423:560d1a9f3083 8050 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
mbed_official 423:560d1a9f3083 8051 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8052 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8053 ((INSTANCE) == TIM2) || \
mbed_official 423:560d1a9f3083 8054 ((INSTANCE) == TIM3) || \
mbed_official 423:560d1a9f3083 8055 ((INSTANCE) == TIM4) || \
mbed_official 423:560d1a9f3083 8056 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8057 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 8058 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8059 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 8060 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8061
mbed_official 423:560d1a9f3083 8062 /****************** TIM Instances : supporting commutation event generation ***/
mbed_official 423:560d1a9f3083 8063 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8064 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8065 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8066 ((INSTANCE) == TIM15) || \
mbed_official 423:560d1a9f3083 8067 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8068 ((INSTANCE) == TIM17) || \
mbed_official 423:560d1a9f3083 8069 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8070
mbed_official 423:560d1a9f3083 8071 /****************** TIM Instances : supporting remapping capability ***********/
mbed_official 423:560d1a9f3083 8072 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 423:560d1a9f3083 8073 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8074 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8075 ((INSTANCE) == TIM16) || \
mbed_official 423:560d1a9f3083 8076 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8077
mbed_official 423:560d1a9f3083 8078 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
mbed_official 423:560d1a9f3083 8079 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
mbed_official 423:560d1a9f3083 8080 (((INSTANCE) == TIM1) || \
mbed_official 423:560d1a9f3083 8081 ((INSTANCE) == TIM8) || \
mbed_official 423:560d1a9f3083 8082 ((INSTANCE) == TIM20))
mbed_official 423:560d1a9f3083 8083
mbed_official 423:560d1a9f3083 8084 /****************************** TSC Instances *********************************/
mbed_official 423:560d1a9f3083 8085 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 423:560d1a9f3083 8086
mbed_official 423:560d1a9f3083 8087 /******************** USART Instances : Synchronous mode **********************/
mbed_official 423:560d1a9f3083 8088 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8089 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8090 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8091
mbed_official 423:560d1a9f3083 8092 /****************** USART Instances : Auto Baud Rate detection ****************/
mbed_official 423:560d1a9f3083 8093 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8094 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8095 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8096
mbed_official 423:560d1a9f3083 8097 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 423:560d1a9f3083 8098 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8099 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8100 ((INSTANCE) == USART3) || \
mbed_official 423:560d1a9f3083 8101 ((INSTANCE) == UART4) || \
mbed_official 423:560d1a9f3083 8102 ((INSTANCE) == UART5))
mbed_official 423:560d1a9f3083 8103
mbed_official 423:560d1a9f3083 8104 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 423:560d1a9f3083 8105 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8106 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8107 ((INSTANCE) == USART3) || \
mbed_official 423:560d1a9f3083 8108 ((INSTANCE) == UART4) || \
mbed_official 423:560d1a9f3083 8109 ((INSTANCE) == UART5))
mbed_official 423:560d1a9f3083 8110
mbed_official 423:560d1a9f3083 8111 /******************** UART Instances : LIN mode **********************/
mbed_official 423:560d1a9f3083 8112 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8113 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8114 ((INSTANCE) == USART3) || \
mbed_official 423:560d1a9f3083 8115 ((INSTANCE) == UART4) || \
mbed_official 423:560d1a9f3083 8116 ((INSTANCE) == UART5))
mbed_official 423:560d1a9f3083 8117
mbed_official 423:560d1a9f3083 8118 /******************** UART Instances : Wake-up from Stop mode **********************/
mbed_official 423:560d1a9f3083 8119 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8120 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8121 ((INSTANCE) == USART3) || \
mbed_official 423:560d1a9f3083 8122 ((INSTANCE) == UART4) || \
mbed_official 423:560d1a9f3083 8123 ((INSTANCE) == UART5))
mbed_official 423:560d1a9f3083 8124
mbed_official 423:560d1a9f3083 8125 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 423:560d1a9f3083 8126 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8127 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8128 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8129
mbed_official 423:560d1a9f3083 8130 /****************** UART Instances : Auto Baud Rate detection *****************/
mbed_official 423:560d1a9f3083 8131 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8132 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8133 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8134
mbed_official 423:560d1a9f3083 8135 /****************** UART Instances : Driver Enable ****************************/
mbed_official 423:560d1a9f3083 8136 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8137 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8138 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8139
mbed_official 423:560d1a9f3083 8140 /********************* UART Instances : Smard card mode ***********************/
mbed_official 423:560d1a9f3083 8141 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8142 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8143 ((INSTANCE) == USART3))
mbed_official 423:560d1a9f3083 8144
mbed_official 423:560d1a9f3083 8145 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 423:560d1a9f3083 8146 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 423:560d1a9f3083 8147 ((INSTANCE) == USART2) || \
mbed_official 423:560d1a9f3083 8148 ((INSTANCE) == USART3) || \
mbed_official 423:560d1a9f3083 8149 ((INSTANCE) == UART4) || \
mbed_official 423:560d1a9f3083 8150 ((INSTANCE) == UART5))
mbed_official 423:560d1a9f3083 8151
mbed_official 423:560d1a9f3083 8152 /****************************** USB Instances *********************************/
mbed_official 423:560d1a9f3083 8153 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 423:560d1a9f3083 8154
mbed_official 423:560d1a9f3083 8155 /****************************** WWDG Instances ********************************/
mbed_official 423:560d1a9f3083 8156 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 423:560d1a9f3083 8157
mbed_official 423:560d1a9f3083 8158 /**
mbed_official 423:560d1a9f3083 8159 * @}
mbed_official 423:560d1a9f3083 8160 */
mbed_official 423:560d1a9f3083 8161
mbed_official 423:560d1a9f3083 8162
mbed_official 423:560d1a9f3083 8163 /******************************************************************************/
mbed_official 423:560d1a9f3083 8164 /* For a painless codes migration between the STM32F3xx device product */
mbed_official 423:560d1a9f3083 8165 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 423:560d1a9f3083 8166 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 423:560d1a9f3083 8167 /* No need to update developed interrupt code when moving across */
mbed_official 423:560d1a9f3083 8168 /* product lines within the same STM32F3 Family */
mbed_official 423:560d1a9f3083 8169 /******************************************************************************/
mbed_official 423:560d1a9f3083 8170
mbed_official 423:560d1a9f3083 8171 /* Aliases for __IRQn */
mbed_official 423:560d1a9f3083 8172
mbed_official 423:560d1a9f3083 8173 #define ADC1_IRQn ADC1_2_IRQn
mbed_official 423:560d1a9f3083 8174 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
mbed_official 423:560d1a9f3083 8175 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
mbed_official 423:560d1a9f3083 8176 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 423:560d1a9f3083 8177 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
mbed_official 423:560d1a9f3083 8178 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 423:560d1a9f3083 8179 #define COMP_IRQn COMP1_2_3_IRQn
mbed_official 423:560d1a9f3083 8180 #define COMP2_IRQn COMP1_2_3_IRQn
mbed_official 423:560d1a9f3083 8181 #define COMP1_2_IRQn COMP1_2_3_IRQn
mbed_official 423:560d1a9f3083 8182 #define COMP4_6_IRQn COMP4_5_6_IRQn
mbed_official 423:560d1a9f3083 8183 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
mbed_official 423:560d1a9f3083 8184
mbed_official 423:560d1a9f3083 8185 /* Aliases for __IRQHandler */
mbed_official 423:560d1a9f3083 8186 #define ADC1_IRQHandler ADC1_2_IRQHandler
mbed_official 423:560d1a9f3083 8187 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
mbed_official 423:560d1a9f3083 8188 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
mbed_official 423:560d1a9f3083 8189 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 423:560d1a9f3083 8190 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 423:560d1a9f3083 8191 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 423:560d1a9f3083 8192 #define COMP_IRQHandler COMP1_2_3_IRQHandler
mbed_official 423:560d1a9f3083 8193 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
mbed_official 423:560d1a9f3083 8194 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
mbed_official 423:560d1a9f3083 8195 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
mbed_official 423:560d1a9f3083 8196 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
mbed_official 423:560d1a9f3083 8197
mbed_official 423:560d1a9f3083 8198 #ifdef __cplusplus
mbed_official 423:560d1a9f3083 8199 }
mbed_official 423:560d1a9f3083 8200 #endif /* __cplusplus */
mbed_official 423:560d1a9f3083 8201
mbed_official 423:560d1a9f3083 8202 #endif /* __STM32F303xE_H */
mbed_official 423:560d1a9f3083 8203
mbed_official 423:560d1a9f3083 8204 /**
mbed_official 423:560d1a9f3083 8205 * @}
mbed_official 423:560d1a9f3083 8206 */
mbed_official 423:560d1a9f3083 8207
mbed_official 423:560d1a9f3083 8208 /**
mbed_official 423:560d1a9f3083 8209 * @}
mbed_official 423:560d1a9f3083 8210 */
mbed_official 423:560d1a9f3083 8211
mbed_official 423:560d1a9f3083 8212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/