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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:: moirans2
Date:: Wed Jan 14 20:53:08 2015 +0000
Revision:: 445:9a3ffe6cfa19
Parent:: 441:d2c15dda23c1

internal clock stm32L051

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_tim.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	441:d2c15dda23c1	5	* @version V1.2.0
mbed_official	441:d2c15dda23c1	6	* @date 11-December-2014
mbed_official	340:28d1f895c6fe	7	* @brief Header file of TIM HAL module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	340:28d1f895c6fe	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_TIM_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_TIM_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup TIM
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	340:28d1f895c6fe	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	340:28d1f895c6fe	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	340:28d1f895c6fe	59	* @{
mbed_official	340:28d1f895c6fe	60	*/
mbed_official	340:28d1f895c6fe	61
mbed_official	340:28d1f895c6fe	62	/**
mbed_official	340:28d1f895c6fe	63	* @brief TIM Time base Configuration Structure definition
mbed_official	340:28d1f895c6fe	64	*/
mbed_official	340:28d1f895c6fe	65	typedef struct
mbed_official	340:28d1f895c6fe	66	{
mbed_official	340:28d1f895c6fe	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	340:28d1f895c6fe	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	69
mbed_official	340:28d1f895c6fe	70	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	340:28d1f895c6fe	71	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	340:28d1f895c6fe	72
mbed_official	340:28d1f895c6fe	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	340:28d1f895c6fe	74	Auto-Reload Register at the next update event.
mbed_official	340:28d1f895c6fe	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	340:28d1f895c6fe	76
mbed_official	340:28d1f895c6fe	77	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	340:28d1f895c6fe	78	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	340:28d1f895c6fe	79
mbed_official	340:28d1f895c6fe	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	340:28d1f895c6fe	81	reaches zero, an update event is generated and counting restarts
mbed_official	340:28d1f895c6fe	82	from the RCR value (N).
mbed_official	340:28d1f895c6fe	83	This means in PWM mode that (N+1) corresponds to:
mbed_official	340:28d1f895c6fe	84	- the number of PWM periods in edge-aligned mode
mbed_official	340:28d1f895c6fe	85	- the number of half PWM period in center-aligned mode
mbed_official	340:28d1f895c6fe	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	340:28d1f895c6fe	87	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	88	} TIM_Base_InitTypeDef;
mbed_official	340:28d1f895c6fe	89
mbed_official	340:28d1f895c6fe	90	/**
mbed_official	340:28d1f895c6fe	91	* @brief TIM Output Compare Configuration Structure definition
mbed_official	340:28d1f895c6fe	92	*/
mbed_official	340:28d1f895c6fe	93	typedef struct
mbed_official	340:28d1f895c6fe	94	{
mbed_official	340:28d1f895c6fe	95	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	340:28d1f895c6fe	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	340:28d1f895c6fe	97
mbed_official	340:28d1f895c6fe	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	340:28d1f895c6fe	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	100
mbed_official	340:28d1f895c6fe	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	340:28d1f895c6fe	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	340:28d1f895c6fe	103
mbed_official	340:28d1f895c6fe	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	340:28d1f895c6fe	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	340:28d1f895c6fe	106	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	107
mbed_official	340:28d1f895c6fe	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	340:28d1f895c6fe	109	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	340:28d1f895c6fe	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	340:28d1f895c6fe	111
mbed_official	340:28d1f895c6fe	112
mbed_official	340:28d1f895c6fe	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	340:28d1f895c6fe	115	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	116
mbed_official	340:28d1f895c6fe	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	340:28d1f895c6fe	119	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	120	} TIM_OC_InitTypeDef;
mbed_official	340:28d1f895c6fe	121
mbed_official	340:28d1f895c6fe	122	/**
mbed_official	340:28d1f895c6fe	123	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	340:28d1f895c6fe	124	*/
mbed_official	340:28d1f895c6fe	125	typedef struct
mbed_official	340:28d1f895c6fe	126	{
mbed_official	340:28d1f895c6fe	127	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	340:28d1f895c6fe	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	340:28d1f895c6fe	129
mbed_official	340:28d1f895c6fe	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	340:28d1f895c6fe	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	340:28d1f895c6fe	132
mbed_official	340:28d1f895c6fe	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	340:28d1f895c6fe	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	340:28d1f895c6fe	135
mbed_official	340:28d1f895c6fe	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	340:28d1f895c6fe	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	340:28d1f895c6fe	138	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	139
mbed_official	340:28d1f895c6fe	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	340:28d1f895c6fe	142	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	143
mbed_official	340:28d1f895c6fe	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	340:28d1f895c6fe	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	340:28d1f895c6fe	146	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	340:28d1f895c6fe	147
mbed_official	340:28d1f895c6fe	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	150
mbed_official	340:28d1f895c6fe	151	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	153
mbed_official	340:28d1f895c6fe	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	156	} TIM_OnePulse_InitTypeDef;
mbed_official	340:28d1f895c6fe	157
mbed_official	340:28d1f895c6fe	158
mbed_official	340:28d1f895c6fe	159	/**
mbed_official	340:28d1f895c6fe	160	* @brief TIM Input Capture Configuration Structure definition
mbed_official	340:28d1f895c6fe	161	*/
mbed_official	340:28d1f895c6fe	162	typedef struct
mbed_official	340:28d1f895c6fe	163	{
mbed_official	340:28d1f895c6fe	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	166
mbed_official	340:28d1f895c6fe	167	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	169
mbed_official	340:28d1f895c6fe	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	172
mbed_official	340:28d1f895c6fe	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	175	} TIM_IC_InitTypeDef;
mbed_official	340:28d1f895c6fe	176
mbed_official	340:28d1f895c6fe	177	/**
mbed_official	340:28d1f895c6fe	178	* @brief TIM Encoder Configuration Structure definition
mbed_official	340:28d1f895c6fe	179	*/
mbed_official	340:28d1f895c6fe	180	typedef struct
mbed_official	340:28d1f895c6fe	181	{
mbed_official	340:28d1f895c6fe	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	183	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	340:28d1f895c6fe	184
mbed_official	340:28d1f895c6fe	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	187
mbed_official	340:28d1f895c6fe	188	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	190
mbed_official	340:28d1f895c6fe	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	193
mbed_official	340:28d1f895c6fe	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	196
mbed_official	340:28d1f895c6fe	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	340:28d1f895c6fe	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	340:28d1f895c6fe	199
mbed_official	340:28d1f895c6fe	200	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	340:28d1f895c6fe	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	340:28d1f895c6fe	202
mbed_official	340:28d1f895c6fe	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	340:28d1f895c6fe	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	340:28d1f895c6fe	205
mbed_official	340:28d1f895c6fe	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	340:28d1f895c6fe	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	340:28d1f895c6fe	208	} TIM_Encoder_InitTypeDef;
mbed_official	340:28d1f895c6fe	209
mbed_official	340:28d1f895c6fe	210
mbed_official	340:28d1f895c6fe	211	/**
mbed_official	340:28d1f895c6fe	212	* @brief Clock Configuration Handle Structure definition
mbed_official	340:28d1f895c6fe	213	*/
mbed_official	340:28d1f895c6fe	214	typedef struct
mbed_official	340:28d1f895c6fe	215	{
mbed_official	340:28d1f895c6fe	216	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	340:28d1f895c6fe	217	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	340:28d1f895c6fe	218	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	340:28d1f895c6fe	219	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	340:28d1f895c6fe	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	340:28d1f895c6fe	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	340:28d1f895c6fe	222	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	340:28d1f895c6fe	223	This parameter can be a value of @ref TIM_Clock_Filter */
mbed_official	340:28d1f895c6fe	224	}TIM_ClockConfigTypeDef;
mbed_official	340:28d1f895c6fe	225
mbed_official	340:28d1f895c6fe	226	/**
mbed_official	340:28d1f895c6fe	227	* @brief Clear Input Configuration Handle Structure definition
mbed_official	340:28d1f895c6fe	228	*/
mbed_official	340:28d1f895c6fe	229	typedef struct
mbed_official	340:28d1f895c6fe	230	{
mbed_official	340:28d1f895c6fe	231	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	340:28d1f895c6fe	232	This parameter can be ENABLE or DISABLE */
mbed_official	340:28d1f895c6fe	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	340:28d1f895c6fe	234	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	340:28d1f895c6fe	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	340:28d1f895c6fe	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	340:28d1f895c6fe	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	340:28d1f895c6fe	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	340:28d1f895c6fe	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	340:28d1f895c6fe	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
mbed_official	340:28d1f895c6fe	241	}TIM_ClearInputConfigTypeDef;
mbed_official	340:28d1f895c6fe	242
mbed_official	340:28d1f895c6fe	243	/**
mbed_official	340:28d1f895c6fe	244	* @brief TIM Slave configuration Structure definition
mbed_official	340:28d1f895c6fe	245	*/
mbed_official	340:28d1f895c6fe	246	typedef struct {
mbed_official	340:28d1f895c6fe	247	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	340:28d1f895c6fe	248	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	340:28d1f895c6fe	249	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	340:28d1f895c6fe	250	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	340:28d1f895c6fe	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	340:28d1f895c6fe	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	340:28d1f895c6fe	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	340:28d1f895c6fe	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	340:28d1f895c6fe	255	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	340:28d1f895c6fe	256	This parameter can be a value of @ref TIM_Trigger_Filter */
mbed_official	340:28d1f895c6fe	257
mbed_official	340:28d1f895c6fe	258	}TIM_SlaveConfigTypeDef;
mbed_official	340:28d1f895c6fe	259
mbed_official	340:28d1f895c6fe	260	/**
mbed_official	340:28d1f895c6fe	261	* @brief HAL State structures definition
mbed_official	340:28d1f895c6fe	262	*/
mbed_official	340:28d1f895c6fe	263	typedef enum
mbed_official	340:28d1f895c6fe	264	{
mbed_official	340:28d1f895c6fe	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	340:28d1f895c6fe	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	340:28d1f895c6fe	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	340:28d1f895c6fe	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	340:28d1f895c6fe	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	340:28d1f895c6fe	270	}HAL_TIM_StateTypeDef;
mbed_official	340:28d1f895c6fe	271
mbed_official	340:28d1f895c6fe	272	/**
mbed_official	340:28d1f895c6fe	273	* @brief HAL Active channel structures definition
mbed_official	340:28d1f895c6fe	274	*/
mbed_official	340:28d1f895c6fe	275	typedef enum
mbed_official	340:28d1f895c6fe	276	{
mbed_official	340:28d1f895c6fe	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	340:28d1f895c6fe	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	340:28d1f895c6fe	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	340:28d1f895c6fe	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	340:28d1f895c6fe	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	340:28d1f895c6fe	282	}HAL_TIM_ActiveChannel;
mbed_official	340:28d1f895c6fe	283
mbed_official	340:28d1f895c6fe	284	/**
mbed_official	340:28d1f895c6fe	285	* @brief TIM Time Base Handle Structure definition
mbed_official	340:28d1f895c6fe	286	*/
mbed_official	340:28d1f895c6fe	287	typedef struct
mbed_official	340:28d1f895c6fe	288	{
mbed_official	340:28d1f895c6fe	289	TIM_TypeDef Instance; /!< Register base address */
mbed_official	340:28d1f895c6fe	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	340:28d1f895c6fe	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	340:28d1f895c6fe	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	441:d2c15dda23c1	293	This array is accessed by a @ref TIM_DMA_Handle_index */
mbed_official	340:28d1f895c6fe	294	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	340:28d1f895c6fe	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	340:28d1f895c6fe	296	}TIM_HandleTypeDef;
mbed_official	340:28d1f895c6fe	297
mbed_official	340:28d1f895c6fe	298	/**
mbed_official	340:28d1f895c6fe	299	* @}
mbed_official	340:28d1f895c6fe	300	*/
mbed_official	340:28d1f895c6fe	301
mbed_official	340:28d1f895c6fe	302	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	340:28d1f895c6fe	304	* @{
mbed_official	340:28d1f895c6fe	305	*/
mbed_official	340:28d1f895c6fe	306
mbed_official	340:28d1f895c6fe	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
mbed_official	340:28d1f895c6fe	308	* @{
mbed_official	340:28d1f895c6fe	309	*/
mbed_official	340:28d1f895c6fe	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	340:28d1f895c6fe	313	/**
mbed_official	340:28d1f895c6fe	314	* @}
mbed_official	340:28d1f895c6fe	315	*/
mbed_official	340:28d1f895c6fe	316
mbed_official	340:28d1f895c6fe	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
mbed_official	340:28d1f895c6fe	318	* @{
mbed_official	340:28d1f895c6fe	319	*/
mbed_official	340:28d1f895c6fe	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	340:28d1f895c6fe	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	340:28d1f895c6fe	322	/**
mbed_official	340:28d1f895c6fe	323	* @}
mbed_official	340:28d1f895c6fe	324	*/
mbed_official	340:28d1f895c6fe	325
mbed_official	340:28d1f895c6fe	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
mbed_official	340:28d1f895c6fe	327	* @{
mbed_official	340:28d1f895c6fe	328	*/
mbed_official	340:28d1f895c6fe	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	340:28d1f895c6fe	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	340:28d1f895c6fe	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	340:28d1f895c6fe	333	/**
mbed_official	340:28d1f895c6fe	334	* @}
mbed_official	340:28d1f895c6fe	335	*/
mbed_official	340:28d1f895c6fe	336
mbed_official	340:28d1f895c6fe	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
mbed_official	340:28d1f895c6fe	338	* @{
mbed_official	340:28d1f895c6fe	339	*/
mbed_official	340:28d1f895c6fe	340
mbed_official	340:28d1f895c6fe	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	340:28d1f895c6fe	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	340:28d1f895c6fe	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	340:28d1f895c6fe	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	340:28d1f895c6fe	346
mbed_official	340:28d1f895c6fe	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	340:28d1f895c6fe	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	340:28d1f895c6fe	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	340:28d1f895c6fe	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	340:28d1f895c6fe	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	340:28d1f895c6fe	352	/**
mbed_official	340:28d1f895c6fe	353	* @}
mbed_official	340:28d1f895c6fe	354	*/
mbed_official	340:28d1f895c6fe	355
mbed_official	340:28d1f895c6fe	356	/** @defgroup TIM_ClockDivision TIM Clock Division
mbed_official	340:28d1f895c6fe	357	* @{
mbed_official	340:28d1f895c6fe	358	*/
mbed_official	340:28d1f895c6fe	359
mbed_official	340:28d1f895c6fe	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	340:28d1f895c6fe	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	340:28d1f895c6fe	363
mbed_official	340:28d1f895c6fe	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	340:28d1f895c6fe	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	340:28d1f895c6fe	367	/**
mbed_official	340:28d1f895c6fe	368	* @}
mbed_official	340:28d1f895c6fe	369	*/
mbed_official	340:28d1f895c6fe	370
mbed_official	340:28d1f895c6fe	371	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
mbed_official	340:28d1f895c6fe	372	* @{
mbed_official	340:28d1f895c6fe	373	*/
mbed_official	340:28d1f895c6fe	374
mbed_official	340:28d1f895c6fe	375	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	376	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	340:28d1f895c6fe	377	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	340:28d1f895c6fe	378	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	340:28d1f895c6fe	379	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	380	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	340:28d1f895c6fe	381	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	382	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	340:28d1f895c6fe	383
mbed_official	340:28d1f895c6fe	384	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	340:28d1f895c6fe	385	((MODE) == TIM_OCMODE_PWM2))
mbed_official	340:28d1f895c6fe	386
mbed_official	340:28d1f895c6fe	387	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	340:28d1f895c6fe	388	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	340:28d1f895c6fe	389	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	340:28d1f895c6fe	390	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	340:28d1f895c6fe	391	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	340:28d1f895c6fe	392	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	340:28d1f895c6fe	393	/**
mbed_official	340:28d1f895c6fe	394	* @}
mbed_official	340:28d1f895c6fe	395	*/
mbed_official	340:28d1f895c6fe	396
mbed_official	340:28d1f895c6fe	397	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
mbed_official	340:28d1f895c6fe	398	* @{
mbed_official	340:28d1f895c6fe	399	*/
mbed_official	340:28d1f895c6fe	400
mbed_official	340:28d1f895c6fe	401	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	402	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	340:28d1f895c6fe	403
mbed_official	340:28d1f895c6fe	404	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
mbed_official	340:28d1f895c6fe	405	((STATE) == TIM_OUTPUTSTATE_ENABLE))
mbed_official	340:28d1f895c6fe	406	/**
mbed_official	340:28d1f895c6fe	407	* @}
mbed_official	340:28d1f895c6fe	408	*/
mbed_official	340:28d1f895c6fe	409	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
mbed_official	340:28d1f895c6fe	410	* @{
mbed_official	340:28d1f895c6fe	411	*/
mbed_official	340:28d1f895c6fe	412	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	413	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	340:28d1f895c6fe	414
mbed_official	340:28d1f895c6fe	415	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	340:28d1f895c6fe	416	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	340:28d1f895c6fe	417	/**
mbed_official	340:28d1f895c6fe	418	* @}
mbed_official	340:28d1f895c6fe	419	*/
mbed_official	340:28d1f895c6fe	420	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
mbed_official	340:28d1f895c6fe	421	* @{
mbed_official	340:28d1f895c6fe	422	*/
mbed_official	340:28d1f895c6fe	423
mbed_official	340:28d1f895c6fe	424	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	425	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	340:28d1f895c6fe	426
mbed_official	340:28d1f895c6fe	427	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
mbed_official	340:28d1f895c6fe	428	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
mbed_official	340:28d1f895c6fe	429	/**
mbed_official	340:28d1f895c6fe	430	* @}
mbed_official	340:28d1f895c6fe	431	*/
mbed_official	340:28d1f895c6fe	432
mbed_official	340:28d1f895c6fe	433	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
mbed_official	340:28d1f895c6fe	434	* @{
mbed_official	340:28d1f895c6fe	435	*/
mbed_official	340:28d1f895c6fe	436
mbed_official	340:28d1f895c6fe	437	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	438	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	340:28d1f895c6fe	439
mbed_official	340:28d1f895c6fe	440	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	340:28d1f895c6fe	441	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	340:28d1f895c6fe	442	/**
mbed_official	340:28d1f895c6fe	443	* @}
mbed_official	340:28d1f895c6fe	444	*/
mbed_official	340:28d1f895c6fe	445
mbed_official	340:28d1f895c6fe	446	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
mbed_official	340:28d1f895c6fe	447	* @{
mbed_official	340:28d1f895c6fe	448	*/
mbed_official	340:28d1f895c6fe	449
mbed_official	340:28d1f895c6fe	450	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	451	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	340:28d1f895c6fe	452
mbed_official	340:28d1f895c6fe	453	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	340:28d1f895c6fe	454	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	340:28d1f895c6fe	455	/**
mbed_official	340:28d1f895c6fe	456	* @}
mbed_official	340:28d1f895c6fe	457	*/
mbed_official	340:28d1f895c6fe	458
mbed_official	340:28d1f895c6fe	459	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
mbed_official	340:28d1f895c6fe	460	* @{
mbed_official	340:28d1f895c6fe	461	*/
mbed_official	340:28d1f895c6fe	462
mbed_official	340:28d1f895c6fe	463	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	340:28d1f895c6fe	464	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	465	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	340:28d1f895c6fe	466	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	340:28d1f895c6fe	467	/**
mbed_official	340:28d1f895c6fe	468	* @}
mbed_official	340:28d1f895c6fe	469	*/
mbed_official	340:28d1f895c6fe	470
mbed_official	340:28d1f895c6fe	471	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
mbed_official	340:28d1f895c6fe	472	* @{
mbed_official	340:28d1f895c6fe	473	*/
mbed_official	340:28d1f895c6fe	474
mbed_official	340:28d1f895c6fe	475	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	340:28d1f895c6fe	476	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	477	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	340:28d1f895c6fe	478	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	340:28d1f895c6fe	479	/**
mbed_official	340:28d1f895c6fe	480	* @}
mbed_official	340:28d1f895c6fe	481	*/
mbed_official	340:28d1f895c6fe	482
mbed_official	340:28d1f895c6fe	483	/** @defgroup TIM_Channel TIM Channel
mbed_official	340:28d1f895c6fe	484	* @{
mbed_official	340:28d1f895c6fe	485	*/
mbed_official	340:28d1f895c6fe	486	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	487	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	488	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	340:28d1f895c6fe	489	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	340:28d1f895c6fe	490	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	340:28d1f895c6fe	491
mbed_official	340:28d1f895c6fe	492	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	340:28d1f895c6fe	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	340:28d1f895c6fe	494	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	340:28d1f895c6fe	495	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	340:28d1f895c6fe	496	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	340:28d1f895c6fe	497
mbed_official	340:28d1f895c6fe	498	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	340:28d1f895c6fe	499	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	340:28d1f895c6fe	500
mbed_official	340:28d1f895c6fe	501	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	340:28d1f895c6fe	502	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	340:28d1f895c6fe	503
mbed_official	340:28d1f895c6fe	504	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	340:28d1f895c6fe	505	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	340:28d1f895c6fe	506	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	340:28d1f895c6fe	507	/**
mbed_official	340:28d1f895c6fe	508	* @}
mbed_official	340:28d1f895c6fe	509	*/
mbed_official	340:28d1f895c6fe	510
mbed_official	340:28d1f895c6fe	511	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
mbed_official	340:28d1f895c6fe	512	* @{
mbed_official	340:28d1f895c6fe	513	*/
mbed_official	340:28d1f895c6fe	514
mbed_official	340:28d1f895c6fe	515	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	340:28d1f895c6fe	516	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	340:28d1f895c6fe	517	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	340:28d1f895c6fe	518
mbed_official	340:28d1f895c6fe	519	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	340:28d1f895c6fe	520	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	340:28d1f895c6fe	521	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	340:28d1f895c6fe	522	/**
mbed_official	340:28d1f895c6fe	523	* @}
mbed_official	340:28d1f895c6fe	524	*/
mbed_official	340:28d1f895c6fe	525
mbed_official	340:28d1f895c6fe	526	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
mbed_official	340:28d1f895c6fe	527	* @{
mbed_official	340:28d1f895c6fe	528	*/
mbed_official	340:28d1f895c6fe	529
mbed_official	340:28d1f895c6fe	530	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	340:28d1f895c6fe	531	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	340:28d1f895c6fe	532	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	340:28d1f895c6fe	533	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	340:28d1f895c6fe	534	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	340:28d1f895c6fe	535
mbed_official	340:28d1f895c6fe	536	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	340:28d1f895c6fe	537	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	340:28d1f895c6fe	538	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	340:28d1f895c6fe	539	/**
mbed_official	340:28d1f895c6fe	540	* @}
mbed_official	340:28d1f895c6fe	541	*/
mbed_official	340:28d1f895c6fe	542
mbed_official	340:28d1f895c6fe	543	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
mbed_official	340:28d1f895c6fe	544	* @{
mbed_official	340:28d1f895c6fe	545	*/
mbed_official	340:28d1f895c6fe	546
mbed_official	340:28d1f895c6fe	547	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	340:28d1f895c6fe	548	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	340:28d1f895c6fe	549	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	340:28d1f895c6fe	550	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	340:28d1f895c6fe	551
mbed_official	340:28d1f895c6fe	552	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	340:28d1f895c6fe	553	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	554	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	340:28d1f895c6fe	555	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	340:28d1f895c6fe	556	/**
mbed_official	340:28d1f895c6fe	557	* @}
mbed_official	340:28d1f895c6fe	558	*/
mbed_official	340:28d1f895c6fe	559
mbed_official	340:28d1f895c6fe	560	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
mbed_official	340:28d1f895c6fe	561	* @{
mbed_official	340:28d1f895c6fe	562	*/
mbed_official	340:28d1f895c6fe	563
mbed_official	340:28d1f895c6fe	564	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	340:28d1f895c6fe	565	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	566
mbed_official	340:28d1f895c6fe	567	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	340:28d1f895c6fe	568	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	340:28d1f895c6fe	569	/**
mbed_official	340:28d1f895c6fe	570	* @}
mbed_official	340:28d1f895c6fe	571	*/
mbed_official	340:28d1f895c6fe	572	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
mbed_official	340:28d1f895c6fe	573	* @{
mbed_official	340:28d1f895c6fe	574	*/
mbed_official	340:28d1f895c6fe	575	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	340:28d1f895c6fe	576	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	340:28d1f895c6fe	577	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	340:28d1f895c6fe	578
mbed_official	340:28d1f895c6fe	579	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	340:28d1f895c6fe	580	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	340:28d1f895c6fe	581	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	340:28d1f895c6fe	582	/**
mbed_official	340:28d1f895c6fe	583	* @}
mbed_official	340:28d1f895c6fe	584	*/
mbed_official	340:28d1f895c6fe	585	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
mbed_official	340:28d1f895c6fe	586	* @{
mbed_official	340:28d1f895c6fe	587	*/
mbed_official	340:28d1f895c6fe	588	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	340:28d1f895c6fe	589	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	340:28d1f895c6fe	590	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	340:28d1f895c6fe	591	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	340:28d1f895c6fe	592	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	340:28d1f895c6fe	593	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	340:28d1f895c6fe	594	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	340:28d1f895c6fe	595	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	340:28d1f895c6fe	596	/**
mbed_official	340:28d1f895c6fe	597	* @}
mbed_official	340:28d1f895c6fe	598	*/
mbed_official	340:28d1f895c6fe	599
mbed_official	340:28d1f895c6fe	600	/** @defgroup TIM_COMMUTATION TIM Commutation
mbed_official	340:28d1f895c6fe	601	* @{
mbed_official	340:28d1f895c6fe	602	*/
mbed_official	340:28d1f895c6fe	603	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	340:28d1f895c6fe	604	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	605
mbed_official	340:28d1f895c6fe	606	/**
mbed_official	340:28d1f895c6fe	607	* @}
mbed_official	340:28d1f895c6fe	608	*/
mbed_official	340:28d1f895c6fe	609	/** @defgroup TIM_DMA_sources TIM DMA Sources
mbed_official	340:28d1f895c6fe	610	* @{
mbed_official	340:28d1f895c6fe	611	*/
mbed_official	340:28d1f895c6fe	612
mbed_official	340:28d1f895c6fe	613	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	340:28d1f895c6fe	614	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	340:28d1f895c6fe	615	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	340:28d1f895c6fe	616	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	340:28d1f895c6fe	617	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	340:28d1f895c6fe	618	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	340:28d1f895c6fe	619	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	340:28d1f895c6fe	620
mbed_official	340:28d1f895c6fe	621	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	340:28d1f895c6fe	622	/**
mbed_official	340:28d1f895c6fe	623	* @}
mbed_official	340:28d1f895c6fe	624	*/
mbed_official	340:28d1f895c6fe	625
mbed_official	340:28d1f895c6fe	626	/** @defgroup TIM_Event_Source TIM Event Source
mbed_official	340:28d1f895c6fe	627	* @{
mbed_official	340:28d1f895c6fe	628	*/
mbed_official	340:28d1f895c6fe	629	#define TIM_EventSource_Update TIM_EGR_UG
mbed_official	340:28d1f895c6fe	630	#define TIM_EventSource_CC1 TIM_EGR_CC1G
mbed_official	340:28d1f895c6fe	631	#define TIM_EventSource_CC2 TIM_EGR_CC2G
mbed_official	340:28d1f895c6fe	632	#define TIM_EventSource_CC3 TIM_EGR_CC3G
mbed_official	340:28d1f895c6fe	633	#define TIM_EventSource_CC4 TIM_EGR_CC4G
mbed_official	340:28d1f895c6fe	634	#define TIM_EventSource_COM TIM_EGR_COMG
mbed_official	340:28d1f895c6fe	635	#define TIM_EventSource_Trigger TIM_EGR_TG
mbed_official	340:28d1f895c6fe	636	#define TIM_EventSource_Break TIM_EGR_BG
mbed_official	340:28d1f895c6fe	637
mbed_official	340:28d1f895c6fe	638	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	340:28d1f895c6fe	639	/**
mbed_official	340:28d1f895c6fe	640	* @}
mbed_official	340:28d1f895c6fe	641	*/
mbed_official	340:28d1f895c6fe	642
mbed_official	340:28d1f895c6fe	643	/** @defgroup TIM_Flag_definition TIM Flag Definition
mbed_official	340:28d1f895c6fe	644	* @{
mbed_official	340:28d1f895c6fe	645	*/
mbed_official	340:28d1f895c6fe	646
mbed_official	340:28d1f895c6fe	647	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	340:28d1f895c6fe	648	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	340:28d1f895c6fe	649	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	340:28d1f895c6fe	650	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	340:28d1f895c6fe	651	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	340:28d1f895c6fe	652	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	340:28d1f895c6fe	653	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	340:28d1f895c6fe	654	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	340:28d1f895c6fe	655	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	340:28d1f895c6fe	656	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	340:28d1f895c6fe	657	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	340:28d1f895c6fe	658	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	340:28d1f895c6fe	659
mbed_official	340:28d1f895c6fe	660	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
mbed_official	340:28d1f895c6fe	661	((FLAG) == TIM_FLAG_CC1) \|\| \
mbed_official	340:28d1f895c6fe	662	((FLAG) == TIM_FLAG_CC2) \|\| \
mbed_official	340:28d1f895c6fe	663	((FLAG) == TIM_FLAG_CC3) \|\| \
mbed_official	340:28d1f895c6fe	664	((FLAG) == TIM_FLAG_CC4) \|\| \
mbed_official	340:28d1f895c6fe	665	((FLAG) == TIM_FLAG_COM) \|\| \
mbed_official	340:28d1f895c6fe	666	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	340:28d1f895c6fe	667	((FLAG) == TIM_FLAG_BREAK) \|\| \
mbed_official	340:28d1f895c6fe	668	((FLAG) == TIM_FLAG_CC1OF) \|\| \
mbed_official	340:28d1f895c6fe	669	((FLAG) == TIM_FLAG_CC2OF) \|\| \
mbed_official	340:28d1f895c6fe	670	((FLAG) == TIM_FLAG_CC3OF) \|\| \
mbed_official	340:28d1f895c6fe	671	((FLAG) == TIM_FLAG_CC4OF))
mbed_official	340:28d1f895c6fe	672	/**
mbed_official	340:28d1f895c6fe	673	* @}
mbed_official	340:28d1f895c6fe	674	*/
mbed_official	340:28d1f895c6fe	675
mbed_official	340:28d1f895c6fe	676	/** @defgroup TIM_Clock_Source TIM Clock Source
mbed_official	340:28d1f895c6fe	677	* @{
mbed_official	340:28d1f895c6fe	678	*/
mbed_official	340:28d1f895c6fe	679	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	340:28d1f895c6fe	680	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	340:28d1f895c6fe	681	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	682	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	340:28d1f895c6fe	683	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	340:28d1f895c6fe	684	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	340:28d1f895c6fe	685	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	686	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	687	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	340:28d1f895c6fe	688	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	340:28d1f895c6fe	689
mbed_official	340:28d1f895c6fe	690	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	340:28d1f895c6fe	691	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	340:28d1f895c6fe	692	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	340:28d1f895c6fe	693	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	340:28d1f895c6fe	694	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	340:28d1f895c6fe	695	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	340:28d1f895c6fe	696	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	340:28d1f895c6fe	697	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	340:28d1f895c6fe	698	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	340:28d1f895c6fe	699	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	340:28d1f895c6fe	700	/**
mbed_official	340:28d1f895c6fe	701	* @}
mbed_official	340:28d1f895c6fe	702	*/
mbed_official	340:28d1f895c6fe	703
mbed_official	340:28d1f895c6fe	704	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
mbed_official	340:28d1f895c6fe	705	* @{
mbed_official	340:28d1f895c6fe	706	*/
mbed_official	340:28d1f895c6fe	707	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	340:28d1f895c6fe	708	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	340:28d1f895c6fe	709	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	340:28d1f895c6fe	710	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	340:28d1f895c6fe	711	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	340:28d1f895c6fe	712
mbed_official	340:28d1f895c6fe	713	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	340:28d1f895c6fe	714	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	340:28d1f895c6fe	715	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	340:28d1f895c6fe	716	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	340:28d1f895c6fe	717	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	340:28d1f895c6fe	718	/**
mbed_official	340:28d1f895c6fe	719	* @}
mbed_official	340:28d1f895c6fe	720	*/
mbed_official	340:28d1f895c6fe	721	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
mbed_official	340:28d1f895c6fe	722	* @{
mbed_official	340:28d1f895c6fe	723	*/
mbed_official	340:28d1f895c6fe	724	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	725	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	726	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	727	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	728
mbed_official	340:28d1f895c6fe	729	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	340:28d1f895c6fe	730	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	731	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	340:28d1f895c6fe	732	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	340:28d1f895c6fe	733	/**
mbed_official	340:28d1f895c6fe	734	* @}
mbed_official	340:28d1f895c6fe	735	*/
mbed_official	340:28d1f895c6fe	736	/** @defgroup TIM_Clock_Filter TIM Clock Filter
mbed_official	340:28d1f895c6fe	737	* @{
mbed_official	340:28d1f895c6fe	738	*/
mbed_official	340:28d1f895c6fe	739
mbed_official	340:28d1f895c6fe	740	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	340:28d1f895c6fe	741	/**
mbed_official	340:28d1f895c6fe	742	* @}
mbed_official	340:28d1f895c6fe	743	*/
mbed_official	340:28d1f895c6fe	744
mbed_official	340:28d1f895c6fe	745	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
mbed_official	340:28d1f895c6fe	746	* @{
mbed_official	340:28d1f895c6fe	747	*/
mbed_official	340:28d1f895c6fe	748	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	340:28d1f895c6fe	749	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	750
mbed_official	340:28d1f895c6fe	751	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	752	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	340:28d1f895c6fe	753	/**
mbed_official	340:28d1f895c6fe	754	* @}
mbed_official	340:28d1f895c6fe	755	*/
mbed_official	340:28d1f895c6fe	756
mbed_official	340:28d1f895c6fe	757	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
mbed_official	340:28d1f895c6fe	758	* @{
mbed_official	340:28d1f895c6fe	759	*/
mbed_official	340:28d1f895c6fe	760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	340:28d1f895c6fe	761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	340:28d1f895c6fe	762
mbed_official	340:28d1f895c6fe	763
mbed_official	340:28d1f895c6fe	764	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	340:28d1f895c6fe	765	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	340:28d1f895c6fe	766	/**
mbed_official	340:28d1f895c6fe	767	* @}
mbed_official	340:28d1f895c6fe	768	*/
mbed_official	340:28d1f895c6fe	769
mbed_official	340:28d1f895c6fe	770	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
mbed_official	340:28d1f895c6fe	771	* @{
mbed_official	340:28d1f895c6fe	772	*/
mbed_official	340:28d1f895c6fe	773	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	774	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	775	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	776	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	777
mbed_official	340:28d1f895c6fe	778	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	340:28d1f895c6fe	779	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	780	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	340:28d1f895c6fe	781	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	340:28d1f895c6fe	782	/**
mbed_official	340:28d1f895c6fe	783	* @}
mbed_official	340:28d1f895c6fe	784	*/
mbed_official	340:28d1f895c6fe	785
mbed_official	340:28d1f895c6fe	786	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
mbed_official	340:28d1f895c6fe	787	* @{
mbed_official	340:28d1f895c6fe	788	*/
mbed_official	340:28d1f895c6fe	789
mbed_official	340:28d1f895c6fe	790	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	340:28d1f895c6fe	791	/**
mbed_official	340:28d1f895c6fe	792	* @}
mbed_official	340:28d1f895c6fe	793	*/
mbed_official	340:28d1f895c6fe	794
mbed_official	340:28d1f895c6fe	795	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
mbed_official	340:28d1f895c6fe	796	* @{
mbed_official	340:28d1f895c6fe	797	*/
mbed_official	340:28d1f895c6fe	798	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	340:28d1f895c6fe	799	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	800
mbed_official	340:28d1f895c6fe	801	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	802	((STATE) == TIM_OSSR_DISABLE))
mbed_official	340:28d1f895c6fe	803	/**
mbed_official	340:28d1f895c6fe	804	* @}
mbed_official	340:28d1f895c6fe	805	*/
mbed_official	340:28d1f895c6fe	806
mbed_official	340:28d1f895c6fe	807	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
mbed_official	340:28d1f895c6fe	808	* @{
mbed_official	340:28d1f895c6fe	809	*/
mbed_official	340:28d1f895c6fe	810	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	340:28d1f895c6fe	811	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	812
mbed_official	340:28d1f895c6fe	813	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	814	((STATE) == TIM_OSSI_DISABLE))
mbed_official	340:28d1f895c6fe	815	/**
mbed_official	340:28d1f895c6fe	816	* @}
mbed_official	340:28d1f895c6fe	817	*/
mbed_official	340:28d1f895c6fe	818	/** @defgroup TIM_Lock_level TIM Lock Configuration
mbed_official	340:28d1f895c6fe	819	* @{
mbed_official	340:28d1f895c6fe	820	*/
mbed_official	340:28d1f895c6fe	821	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	822	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	340:28d1f895c6fe	823	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	340:28d1f895c6fe	824	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	340:28d1f895c6fe	825
mbed_official	340:28d1f895c6fe	826	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	340:28d1f895c6fe	827	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	340:28d1f895c6fe	828	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	340:28d1f895c6fe	829	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	340:28d1f895c6fe	830	/**
mbed_official	340:28d1f895c6fe	831	* @}
mbed_official	340:28d1f895c6fe	832	*/
mbed_official	340:28d1f895c6fe	833	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
mbed_official	340:28d1f895c6fe	834	* @{
mbed_official	340:28d1f895c6fe	835	*/
mbed_official	340:28d1f895c6fe	836	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	340:28d1f895c6fe	837	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	838
mbed_official	340:28d1f895c6fe	839	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	840	((STATE) == TIM_BREAK_DISABLE))
mbed_official	340:28d1f895c6fe	841	/**
mbed_official	340:28d1f895c6fe	842	* @}
mbed_official	340:28d1f895c6fe	843	*/
mbed_official	340:28d1f895c6fe	844	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
mbed_official	340:28d1f895c6fe	845	* @{
mbed_official	340:28d1f895c6fe	846	*/
mbed_official	340:28d1f895c6fe	847	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	848	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	340:28d1f895c6fe	849
mbed_official	340:28d1f895c6fe	850	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	340:28d1f895c6fe	851	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	340:28d1f895c6fe	852	/**
mbed_official	340:28d1f895c6fe	853	* @}
mbed_official	340:28d1f895c6fe	854	*/
mbed_official	340:28d1f895c6fe	855	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
mbed_official	340:28d1f895c6fe	856	* @{
mbed_official	340:28d1f895c6fe	857	*/
mbed_official	340:28d1f895c6fe	858	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	340:28d1f895c6fe	859	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	860
mbed_official	340:28d1f895c6fe	861	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	862	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	340:28d1f895c6fe	863	/**
mbed_official	340:28d1f895c6fe	864	* @}
mbed_official	340:28d1f895c6fe	865	*/
mbed_official	340:28d1f895c6fe	866
mbed_official	340:28d1f895c6fe	867	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	340:28d1f895c6fe	868	* @{
mbed_official	340:28d1f895c6fe	869	*/
mbed_official	340:28d1f895c6fe	870	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	871	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	340:28d1f895c6fe	872	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	340:28d1f895c6fe	873	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	340:28d1f895c6fe	874	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	340:28d1f895c6fe	875	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	340:28d1f895c6fe	876	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	340:28d1f895c6fe	877	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	340:28d1f895c6fe	878
mbed_official	340:28d1f895c6fe	879	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	340:28d1f895c6fe	880	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	881	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	340:28d1f895c6fe	882	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	340:28d1f895c6fe	883	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	340:28d1f895c6fe	884	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	340:28d1f895c6fe	885	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	340:28d1f895c6fe	886	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	340:28d1f895c6fe	887
mbed_official	340:28d1f895c6fe	888
mbed_official	340:28d1f895c6fe	889	/**
mbed_official	340:28d1f895c6fe	890	* @}
mbed_official	340:28d1f895c6fe	891	*/
mbed_official	340:28d1f895c6fe	892
mbed_official	340:28d1f895c6fe	893	/** @defgroup TIM_Slave_Mode TIM Slave Mode
mbed_official	340:28d1f895c6fe	894	* @{
mbed_official	340:28d1f895c6fe	895	*/
mbed_official	340:28d1f895c6fe	896
mbed_official	340:28d1f895c6fe	897	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	898	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	899	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	340:28d1f895c6fe	900	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	340:28d1f895c6fe	901	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	340:28d1f895c6fe	902
mbed_official	340:28d1f895c6fe	903	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	340:28d1f895c6fe	904	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	340:28d1f895c6fe	905	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	340:28d1f895c6fe	906	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	340:28d1f895c6fe	907	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	340:28d1f895c6fe	908	/**
mbed_official	340:28d1f895c6fe	909	* @}
mbed_official	340:28d1f895c6fe	910	*/
mbed_official	340:28d1f895c6fe	911
mbed_official	340:28d1f895c6fe	912	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
mbed_official	340:28d1f895c6fe	913	* @{
mbed_official	340:28d1f895c6fe	914	*/
mbed_official	340:28d1f895c6fe	915
mbed_official	340:28d1f895c6fe	916	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	340:28d1f895c6fe	917	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	918
mbed_official	340:28d1f895c6fe	919	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	340:28d1f895c6fe	920	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	340:28d1f895c6fe	921	/**
mbed_official	340:28d1f895c6fe	922	* @}
mbed_official	340:28d1f895c6fe	923	*/
mbed_official	340:28d1f895c6fe	924	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
mbed_official	340:28d1f895c6fe	925	* @{
mbed_official	340:28d1f895c6fe	926	*/
mbed_official	340:28d1f895c6fe	927
mbed_official	340:28d1f895c6fe	928	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	929	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	340:28d1f895c6fe	930	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	340:28d1f895c6fe	931	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	340:28d1f895c6fe	932	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	340:28d1f895c6fe	933	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	340:28d1f895c6fe	934	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	340:28d1f895c6fe	935	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	340:28d1f895c6fe	936	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	340:28d1f895c6fe	937
mbed_official	340:28d1f895c6fe	938	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	340:28d1f895c6fe	939	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	340:28d1f895c6fe	940	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	340:28d1f895c6fe	941	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	340:28d1f895c6fe	942	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	340:28d1f895c6fe	943	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	340:28d1f895c6fe	944	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	340:28d1f895c6fe	945	((SELECTION) == TIM_TS_ETRF))
mbed_official	340:28d1f895c6fe	946
mbed_official	340:28d1f895c6fe	947	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	340:28d1f895c6fe	948	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	340:28d1f895c6fe	949	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	340:28d1f895c6fe	950	((SELECTION) == TIM_TS_ITR3))
mbed_official	340:28d1f895c6fe	951
mbed_official	340:28d1f895c6fe	952	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	340:28d1f895c6fe	953	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	340:28d1f895c6fe	954	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	340:28d1f895c6fe	955	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	340:28d1f895c6fe	956	((SELECTION) == TIM_TS_NONE))
mbed_official	340:28d1f895c6fe	957	/**
mbed_official	340:28d1f895c6fe	958	* @}
mbed_official	340:28d1f895c6fe	959	*/
mbed_official	340:28d1f895c6fe	960
mbed_official	340:28d1f895c6fe	961	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
mbed_official	340:28d1f895c6fe	962	* @{
mbed_official	340:28d1f895c6fe	963	*/
mbed_official	340:28d1f895c6fe	964	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	340:28d1f895c6fe	965	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	340:28d1f895c6fe	966	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	340:28d1f895c6fe	967	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	340:28d1f895c6fe	968	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	340:28d1f895c6fe	969
mbed_official	340:28d1f895c6fe	970	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	340:28d1f895c6fe	971	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	340:28d1f895c6fe	972	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	340:28d1f895c6fe	973	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	340:28d1f895c6fe	974	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	340:28d1f895c6fe	975	/**
mbed_official	340:28d1f895c6fe	976	* @}
mbed_official	340:28d1f895c6fe	977	*/
mbed_official	340:28d1f895c6fe	978
mbed_official	340:28d1f895c6fe	979	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
mbed_official	340:28d1f895c6fe	980	* @{
mbed_official	340:28d1f895c6fe	981	*/
mbed_official	340:28d1f895c6fe	982	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	340:28d1f895c6fe	983	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	340:28d1f895c6fe	984	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	340:28d1f895c6fe	985	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	340:28d1f895c6fe	986
mbed_official	340:28d1f895c6fe	987	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	340:28d1f895c6fe	988	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	989	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	340:28d1f895c6fe	990	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	340:28d1f895c6fe	991	/**
mbed_official	340:28d1f895c6fe	992	* @}
mbed_official	340:28d1f895c6fe	993	*/
mbed_official	340:28d1f895c6fe	994
mbed_official	340:28d1f895c6fe	995	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
mbed_official	340:28d1f895c6fe	996	* @{
mbed_official	340:28d1f895c6fe	997	*/
mbed_official	340:28d1f895c6fe	998
mbed_official	340:28d1f895c6fe	999	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	340:28d1f895c6fe	1000	/**
mbed_official	340:28d1f895c6fe	1001	* @}
mbed_official	340:28d1f895c6fe	1002	*/
mbed_official	340:28d1f895c6fe	1003
mbed_official	340:28d1f895c6fe	1004	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
mbed_official	340:28d1f895c6fe	1005	* @{
mbed_official	340:28d1f895c6fe	1006	*/
mbed_official	340:28d1f895c6fe	1007
mbed_official	340:28d1f895c6fe	1008	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	1009	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	340:28d1f895c6fe	1010
mbed_official	340:28d1f895c6fe	1011	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	340:28d1f895c6fe	1012	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	340:28d1f895c6fe	1013
mbed_official	340:28d1f895c6fe	1014	/**
mbed_official	340:28d1f895c6fe	1015	* @}
mbed_official	340:28d1f895c6fe	1016	*/
mbed_official	340:28d1f895c6fe	1017
mbed_official	340:28d1f895c6fe	1018	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
mbed_official	340:28d1f895c6fe	1019	* @{
mbed_official	340:28d1f895c6fe	1020	*/
mbed_official	340:28d1f895c6fe	1021	#define TIM_DMABase_CR1 (0x00000000)
mbed_official	340:28d1f895c6fe	1022	#define TIM_DMABase_CR2 (0x00000001)
mbed_official	340:28d1f895c6fe	1023	#define TIM_DMABase_SMCR (0x00000002)
mbed_official	340:28d1f895c6fe	1024	#define TIM_DMABase_DIER (0x00000003)
mbed_official	340:28d1f895c6fe	1025	#define TIM_DMABase_SR (0x00000004)
mbed_official	340:28d1f895c6fe	1026	#define TIM_DMABase_EGR (0x00000005)
mbed_official	340:28d1f895c6fe	1027	#define TIM_DMABase_CCMR1 (0x00000006)
mbed_official	340:28d1f895c6fe	1028	#define TIM_DMABase_CCMR2 (0x00000007)
mbed_official	340:28d1f895c6fe	1029	#define TIM_DMABase_CCER (0x00000008)
mbed_official	340:28d1f895c6fe	1030	#define TIM_DMABase_CNT (0x00000009)
mbed_official	340:28d1f895c6fe	1031	#define TIM_DMABase_PSC (0x0000000A)
mbed_official	340:28d1f895c6fe	1032	#define TIM_DMABase_ARR (0x0000000B)
mbed_official	340:28d1f895c6fe	1033	#define TIM_DMABase_RCR (0x0000000C)
mbed_official	340:28d1f895c6fe	1034	#define TIM_DMABase_CCR1 (0x0000000D)
mbed_official	340:28d1f895c6fe	1035	#define TIM_DMABase_CCR2 (0x0000000E)
mbed_official	340:28d1f895c6fe	1036	#define TIM_DMABase_CCR3 (0x0000000F)
mbed_official	340:28d1f895c6fe	1037	#define TIM_DMABase_CCR4 (0x00000010)
mbed_official	340:28d1f895c6fe	1038	#define TIM_DMABase_BDTR (0x00000011)
mbed_official	340:28d1f895c6fe	1039	#define TIM_DMABase_DCR (0x00000012)
mbed_official	340:28d1f895c6fe	1040	#define TIM_DMABase_OR (0x00000013)
mbed_official	340:28d1f895c6fe	1041
mbed_official	340:28d1f895c6fe	1042	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
mbed_official	340:28d1f895c6fe	1043	((BASE) == TIM_DMABase_CR2) \|\| \
mbed_official	340:28d1f895c6fe	1044	((BASE) == TIM_DMABase_SMCR) \|\| \
mbed_official	340:28d1f895c6fe	1045	((BASE) == TIM_DMABase_DIER) \|\| \
mbed_official	340:28d1f895c6fe	1046	((BASE) == TIM_DMABase_SR) \|\| \
mbed_official	340:28d1f895c6fe	1047	((BASE) == TIM_DMABase_EGR) \|\| \
mbed_official	340:28d1f895c6fe	1048	((BASE) == TIM_DMABase_CCMR1) \|\| \
mbed_official	340:28d1f895c6fe	1049	((BASE) == TIM_DMABase_CCMR2) \|\| \
mbed_official	340:28d1f895c6fe	1050	((BASE) == TIM_DMABase_CCER) \|\| \
mbed_official	340:28d1f895c6fe	1051	((BASE) == TIM_DMABase_CNT) \|\| \
mbed_official	340:28d1f895c6fe	1052	((BASE) == TIM_DMABase_PSC) \|\| \
mbed_official	340:28d1f895c6fe	1053	((BASE) == TIM_DMABase_ARR) \|\| \
mbed_official	340:28d1f895c6fe	1054	((BASE) == TIM_DMABase_RCR) \|\| \
mbed_official	340:28d1f895c6fe	1055	((BASE) == TIM_DMABase_CCR1) \|\| \
mbed_official	340:28d1f895c6fe	1056	((BASE) == TIM_DMABase_CCR2) \|\| \
mbed_official	340:28d1f895c6fe	1057	((BASE) == TIM_DMABase_CCR3) \|\| \
mbed_official	340:28d1f895c6fe	1058	((BASE) == TIM_DMABase_CCR4) \|\| \
mbed_official	340:28d1f895c6fe	1059	((BASE) == TIM_DMABase_BDTR) \|\| \
mbed_official	340:28d1f895c6fe	1060	((BASE) == TIM_DMABase_DCR) \|\| \
mbed_official	340:28d1f895c6fe	1061	((BASE) == TIM_DMABase_OR))
mbed_official	340:28d1f895c6fe	1062	/**
mbed_official	340:28d1f895c6fe	1063	* @}
mbed_official	340:28d1f895c6fe	1064	*/
mbed_official	340:28d1f895c6fe	1065
mbed_official	340:28d1f895c6fe	1066	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
mbed_official	340:28d1f895c6fe	1067	* @{
mbed_official	340:28d1f895c6fe	1068	*/
mbed_official	340:28d1f895c6fe	1069
mbed_official	340:28d1f895c6fe	1070	#define TIM_DMABurstLength_1Transfer (0x00000000)
mbed_official	340:28d1f895c6fe	1071	#define TIM_DMABurstLength_2Transfers (0x00000100)
mbed_official	340:28d1f895c6fe	1072	#define TIM_DMABurstLength_3Transfers (0x00000200)
mbed_official	340:28d1f895c6fe	1073	#define TIM_DMABurstLength_4Transfers (0x00000300)
mbed_official	340:28d1f895c6fe	1074	#define TIM_DMABurstLength_5Transfers (0x00000400)
mbed_official	340:28d1f895c6fe	1075	#define TIM_DMABurstLength_6Transfers (0x00000500)
mbed_official	340:28d1f895c6fe	1076	#define TIM_DMABurstLength_7Transfers (0x00000600)
mbed_official	340:28d1f895c6fe	1077	#define TIM_DMABurstLength_8Transfers (0x00000700)
mbed_official	340:28d1f895c6fe	1078	#define TIM_DMABurstLength_9Transfers (0x00000800)
mbed_official	340:28d1f895c6fe	1079	#define TIM_DMABurstLength_10Transfers (0x00000900)
mbed_official	340:28d1f895c6fe	1080	#define TIM_DMABurstLength_11Transfers (0x00000A00)
mbed_official	340:28d1f895c6fe	1081	#define TIM_DMABurstLength_12Transfers (0x00000B00)
mbed_official	340:28d1f895c6fe	1082	#define TIM_DMABurstLength_13Transfers (0x00000C00)
mbed_official	340:28d1f895c6fe	1083	#define TIM_DMABurstLength_14Transfers (0x00000D00)
mbed_official	340:28d1f895c6fe	1084	#define TIM_DMABurstLength_15Transfers (0x00000E00)
mbed_official	340:28d1f895c6fe	1085	#define TIM_DMABurstLength_16Transfers (0x00000F00)
mbed_official	340:28d1f895c6fe	1086	#define TIM_DMABurstLength_17Transfers (0x00001000)
mbed_official	340:28d1f895c6fe	1087	#define TIM_DMABurstLength_18Transfers (0x00001100)
mbed_official	340:28d1f895c6fe	1088
mbed_official	340:28d1f895c6fe	1089	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
mbed_official	340:28d1f895c6fe	1090	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1091	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1092	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1093	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1094	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1095	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1096	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1097	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1098	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1099	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1100	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1101	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1102	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1103	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1104	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1105	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
mbed_official	340:28d1f895c6fe	1106	((LENGTH) == TIM_DMABurstLength_18Transfers))
mbed_official	340:28d1f895c6fe	1107	/**
mbed_official	340:28d1f895c6fe	1108	* @}
mbed_official	340:28d1f895c6fe	1109	*/
mbed_official	340:28d1f895c6fe	1110
mbed_official	340:28d1f895c6fe	1111	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
mbed_official	340:28d1f895c6fe	1112	* @{
mbed_official	340:28d1f895c6fe	1113	*/
mbed_official	340:28d1f895c6fe	1114
mbed_official	340:28d1f895c6fe	1115	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	340:28d1f895c6fe	1116	/**
mbed_official	340:28d1f895c6fe	1117	* @}
mbed_official	340:28d1f895c6fe	1118	*/
mbed_official	340:28d1f895c6fe	1119
mbed_official	441:d2c15dda23c1	1120	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
mbed_official	340:28d1f895c6fe	1121	* @{
mbed_official	340:28d1f895c6fe	1122	*/
mbed_official	340:28d1f895c6fe	1123	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	340:28d1f895c6fe	1124	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	340:28d1f895c6fe	1125	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	340:28d1f895c6fe	1126	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	340:28d1f895c6fe	1127	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	340:28d1f895c6fe	1128	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	340:28d1f895c6fe	1129	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	340:28d1f895c6fe	1130	/**
mbed_official	340:28d1f895c6fe	1131	* @}
mbed_official	340:28d1f895c6fe	1132	*/
mbed_official	340:28d1f895c6fe	1133
mbed_official	340:28d1f895c6fe	1134	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
mbed_official	340:28d1f895c6fe	1135	* @{
mbed_official	340:28d1f895c6fe	1136	*/
mbed_official	340:28d1f895c6fe	1137	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	340:28d1f895c6fe	1138	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	1139	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	340:28d1f895c6fe	1140	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	340:28d1f895c6fe	1141	/**
mbed_official	340:28d1f895c6fe	1142	* @}
mbed_official	340:28d1f895c6fe	1143	*/
mbed_official	340:28d1f895c6fe	1144
mbed_official	340:28d1f895c6fe	1145	/**
mbed_official	340:28d1f895c6fe	1146	* @}
mbed_official	340:28d1f895c6fe	1147	*/
mbed_official	340:28d1f895c6fe	1148
mbed_official	340:28d1f895c6fe	1149	/* Exported macros -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1150	/** @defgroup TIM_Exported_Macros TIM Exported Macros
mbed_official	340:28d1f895c6fe	1151	* @{
mbed_official	340:28d1f895c6fe	1152	*/
mbed_official	340:28d1f895c6fe	1153
mbed_official	340:28d1f895c6fe	1154	/** @brief Reset TIM handle state
mbed_official	340:28d1f895c6fe	1155	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1156	* @retval None
mbed_official	340:28d1f895c6fe	1157	*/
mbed_official	340:28d1f895c6fe	1158	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	340:28d1f895c6fe	1159
mbed_official	340:28d1f895c6fe	1160	/**
mbed_official	340:28d1f895c6fe	1161	* @brief Enable the TIM peripheral.
mbed_official	340:28d1f895c6fe	1162	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1163	* @retval None
mbed_official	340:28d1f895c6fe	1164	*/
mbed_official	340:28d1f895c6fe	1165	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	/**
mbed_official	340:28d1f895c6fe	1168	* @brief Enable the TIM main Output.
mbed_official	340:28d1f895c6fe	1169	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1170	* @retval None
mbed_official	340:28d1f895c6fe	1171	*/
mbed_official	340:28d1f895c6fe	1172	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	340:28d1f895c6fe	1173
mbed_official	340:28d1f895c6fe	1174	/**
mbed_official	340:28d1f895c6fe	1175	* @brief Disable the TIM peripheral.
mbed_official	340:28d1f895c6fe	1176	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1177	* @retval None
mbed_official	340:28d1f895c6fe	1178	*/
mbed_official	340:28d1f895c6fe	1179	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1180	do { \
mbed_official	340:28d1f895c6fe	1181	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1182	{ \
mbed_official	340:28d1f895c6fe	1183	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1184	{ \
mbed_official	340:28d1f895c6fe	1185	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	340:28d1f895c6fe	1186	} \
mbed_official	340:28d1f895c6fe	1187	} \
mbed_official	340:28d1f895c6fe	1188	} while(0)
mbed_official	340:28d1f895c6fe	1189	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
mbed_official	340:28d1f895c6fe	1190	channels have been disabled */
mbed_official	340:28d1f895c6fe	1191	/**
mbed_official	340:28d1f895c6fe	1192	* @brief Disable the TIM main Output.
mbed_official	340:28d1f895c6fe	1193	* @param __HANDLE__: TIM handle
mbed_official	340:28d1f895c6fe	1194	* @retval None
mbed_official	340:28d1f895c6fe	1195	*/
mbed_official	340:28d1f895c6fe	1196	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1197	do { \
mbed_official	340:28d1f895c6fe	1198	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1199	{ \
mbed_official	340:28d1f895c6fe	1200	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
mbed_official	340:28d1f895c6fe	1201	{ \
mbed_official	340:28d1f895c6fe	1202	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	340:28d1f895c6fe	1203	} \
mbed_official	340:28d1f895c6fe	1204	} \
mbed_official	340:28d1f895c6fe	1205	} while(0)
mbed_official	340:28d1f895c6fe	1206
mbed_official	340:28d1f895c6fe	1207	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1208	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	340:28d1f895c6fe	1209	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1210	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	340:28d1f895c6fe	1211	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	340:28d1f895c6fe	1212	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	340:28d1f895c6fe	1213
mbed_official	340:28d1f895c6fe	1214	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	340:28d1f895c6fe	1215	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1216
mbed_official	340:28d1f895c6fe	1217	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	340:28d1f895c6fe	1218	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	340:28d1f895c6fe	1219
mbed_official	340:28d1f895c6fe	1220	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	340:28d1f895c6fe	1221	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	340:28d1f895c6fe	1222	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	340:28d1f895c6fe	1223	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	340:28d1f895c6fe	1224	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	340:28d1f895c6fe	1225
mbed_official	340:28d1f895c6fe	1226	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
mbed_official	340:28d1f895c6fe	1227	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
mbed_official	340:28d1f895c6fe	1228	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
mbed_official	340:28d1f895c6fe	1229	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
mbed_official	340:28d1f895c6fe	1230	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
mbed_official	340:28d1f895c6fe	1231
mbed_official	340:28d1f895c6fe	1232	/**
mbed_official	340:28d1f895c6fe	1233	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	340:28d1f895c6fe	1234	* calling another time ConfigChannel function.
mbed_official	340:28d1f895c6fe	1235	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1236	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1237	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1242	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	340:28d1f895c6fe	1243	* @retval None
mbed_official	340:28d1f895c6fe	1244	*/
mbed_official	340:28d1f895c6fe	1245	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	340:28d1f895c6fe	1246	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	340:28d1f895c6fe	1247
mbed_official	340:28d1f895c6fe	1248	/**
mbed_official	340:28d1f895c6fe	1249	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	340:28d1f895c6fe	1250	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1251	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	340:28d1f895c6fe	1252	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1253	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	340:28d1f895c6fe	1254	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	340:28d1f895c6fe	1255	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	340:28d1f895c6fe	1256	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	340:28d1f895c6fe	1257	* @retval None
mbed_official	340:28d1f895c6fe	1258	*/
mbed_official	340:28d1f895c6fe	1259	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
mbed_official	340:28d1f895c6fe	1260	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	340:28d1f895c6fe	1261
mbed_official	340:28d1f895c6fe	1262	/**
mbed_official	340:28d1f895c6fe	1263	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	340:28d1f895c6fe	1264	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1265	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	340:28d1f895c6fe	1266	* @retval None
mbed_official	340:28d1f895c6fe	1267	*/
mbed_official	340:28d1f895c6fe	1268	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	340:28d1f895c6fe	1269
mbed_official	340:28d1f895c6fe	1270	/**
mbed_official	340:28d1f895c6fe	1271	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	340:28d1f895c6fe	1272	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1273	* @retval None
mbed_official	340:28d1f895c6fe	1274	*/
mbed_official	340:28d1f895c6fe	1275	#define __HAL_TIM_GetCounter(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1276	((__HANDLE__)->Instance->CNT)
mbed_official	340:28d1f895c6fe	1277
mbed_official	340:28d1f895c6fe	1278	/**
mbed_official	340:28d1f895c6fe	1279	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	340:28d1f895c6fe	1280	* another time any Init function.
mbed_official	340:28d1f895c6fe	1281	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1282	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	340:28d1f895c6fe	1283	* @retval None
mbed_official	340:28d1f895c6fe	1284	*/
mbed_official	340:28d1f895c6fe	1285	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
mbed_official	340:28d1f895c6fe	1286	do{ \
mbed_official	340:28d1f895c6fe	1287	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	340:28d1f895c6fe	1288	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	340:28d1f895c6fe	1289	} while(0)
mbed_official	340:28d1f895c6fe	1290
mbed_official	340:28d1f895c6fe	1291	/**
mbed_official	340:28d1f895c6fe	1292	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	340:28d1f895c6fe	1293	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1294	* @retval None
mbed_official	340:28d1f895c6fe	1295	*/
mbed_official	340:28d1f895c6fe	1296	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1297	((__HANDLE__)->Instance->ARR)
mbed_official	340:28d1f895c6fe	1298
mbed_official	340:28d1f895c6fe	1299	/**
mbed_official	340:28d1f895c6fe	1300	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	340:28d1f895c6fe	1301	* another time any Init function.
mbed_official	340:28d1f895c6fe	1302	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1303	* @param __CKD__: specifies the clock division value.
mbed_official	340:28d1f895c6fe	1304	* This parameter can be one of the following value:
mbed_official	340:28d1f895c6fe	1305	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	340:28d1f895c6fe	1306	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	340:28d1f895c6fe	1307	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	340:28d1f895c6fe	1308	* @retval None
mbed_official	340:28d1f895c6fe	1309	*/
mbed_official	340:28d1f895c6fe	1310	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
mbed_official	340:28d1f895c6fe	1311	do{ \
mbed_official	340:28d1f895c6fe	1312	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
mbed_official	340:28d1f895c6fe	1313	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	340:28d1f895c6fe	1314	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	340:28d1f895c6fe	1315	} while(0)
mbed_official	340:28d1f895c6fe	1316
mbed_official	340:28d1f895c6fe	1317	/**
mbed_official	340:28d1f895c6fe	1318	* @brief Gets the TIM Clock Division value on runtime
mbed_official	340:28d1f895c6fe	1319	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1320	* @retval None
mbed_official	340:28d1f895c6fe	1321	*/
mbed_official	340:28d1f895c6fe	1322	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1323	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	340:28d1f895c6fe	1324
mbed_official	340:28d1f895c6fe	1325	/**
mbed_official	340:28d1f895c6fe	1326	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	340:28d1f895c6fe	1327	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	340:28d1f895c6fe	1328	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1329	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1330	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1331	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	340:28d1f895c6fe	1332	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	340:28d1f895c6fe	1333	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	340:28d1f895c6fe	1334	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	340:28d1f895c6fe	1335	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	340:28d1f895c6fe	1336	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1337	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	340:28d1f895c6fe	1338	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	340:28d1f895c6fe	1339	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	340:28d1f895c6fe	1340	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	340:28d1f895c6fe	1341	* @retval None
mbed_official	340:28d1f895c6fe	1342	*/
mbed_official	340:28d1f895c6fe	1343	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	340:28d1f895c6fe	1344	do{ \
mbed_official	340:28d1f895c6fe	1345	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
mbed_official	340:28d1f895c6fe	1346	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	340:28d1f895c6fe	1347	} while(0)
mbed_official	340:28d1f895c6fe	1348
mbed_official	340:28d1f895c6fe	1349	/**
mbed_official	340:28d1f895c6fe	1350	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	340:28d1f895c6fe	1351	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1352	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	340:28d1f895c6fe	1353	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1354	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	340:28d1f895c6fe	1355	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	340:28d1f895c6fe	1356	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	340:28d1f895c6fe	1357	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	340:28d1f895c6fe	1358	* @retval None
mbed_official	340:28d1f895c6fe	1359	*/
mbed_official	340:28d1f895c6fe	1360	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
mbed_official	340:28d1f895c6fe	1361	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	340:28d1f895c6fe	1362	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	340:28d1f895c6fe	1363	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	340:28d1f895c6fe	1364	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	340:28d1f895c6fe	1365
mbed_official	340:28d1f895c6fe	1366	/**
mbed_official	340:28d1f895c6fe	1367	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	340:28d1f895c6fe	1368	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1369	* @note When the USR bit of the TIMx_CR1 register is set, only counter
mbed_official	340:28d1f895c6fe	1370	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	340:28d1f895c6fe	1371	* enabled)
mbed_official	340:28d1f895c6fe	1372	* @retval None
mbed_official	340:28d1f895c6fe	1373	*/
mbed_official	340:28d1f895c6fe	1374	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1375	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	340:28d1f895c6fe	1376
mbed_official	340:28d1f895c6fe	1377	/**
mbed_official	340:28d1f895c6fe	1378	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	340:28d1f895c6fe	1379	* @param __HANDLE__: TIM handle.
mbed_official	340:28d1f895c6fe	1380	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
mbed_official	340:28d1f895c6fe	1381	* following events generate an update interrupt or DMA request (if
mbed_official	340:28d1f895c6fe	1382	* enabled):
mbed_official	340:28d1f895c6fe	1383	* (+) Counter overflow/underflow
mbed_official	340:28d1f895c6fe	1384	* (+) Setting the UG bit
mbed_official	340:28d1f895c6fe	1385	* (+) Update generation through the slave mode controller
mbed_official	340:28d1f895c6fe	1386	* @retval None
mbed_official	340:28d1f895c6fe	1387	*/
mbed_official	340:28d1f895c6fe	1388	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	340:28d1f895c6fe	1389	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	340:28d1f895c6fe	1390
mbed_official	340:28d1f895c6fe	1391	/**
mbed_official	340:28d1f895c6fe	1392	* @}
mbed_official	340:28d1f895c6fe	1393	*/
mbed_official	340:28d1f895c6fe	1394
mbed_official	340:28d1f895c6fe	1395	/* Include TIM HAL Extension module */
mbed_official	340:28d1f895c6fe	1396	#include "stm32f0xx_hal_tim_ex.h"
mbed_official	340:28d1f895c6fe	1397
mbed_official	340:28d1f895c6fe	1398	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1399	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
mbed_official	340:28d1f895c6fe	1400	* @{
mbed_official	340:28d1f895c6fe	1401	*/
mbed_official	340:28d1f895c6fe	1402
mbed_official	340:28d1f895c6fe	1403	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
mbed_official	340:28d1f895c6fe	1404	* @brief Time Base functions
mbed_official	340:28d1f895c6fe	1405	* @{
mbed_official	340:28d1f895c6fe	1406	*/
mbed_official	340:28d1f895c6fe	1407	/* Time Base functions ********************************************************/
mbed_official	340:28d1f895c6fe	1408	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1409	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1410	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1411	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1412	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1413	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1414	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1415	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1416	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1417	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1418	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1419	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1420	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1421	/**
mbed_official	340:28d1f895c6fe	1422	* @}
mbed_official	340:28d1f895c6fe	1423	*/
mbed_official	340:28d1f895c6fe	1424
mbed_official	340:28d1f895c6fe	1425	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
mbed_official	340:28d1f895c6fe	1426	* @brief Time Output Compare functions
mbed_official	340:28d1f895c6fe	1427	* @{
mbed_official	340:28d1f895c6fe	1428	*/
mbed_official	340:28d1f895c6fe	1429	/* Timer Output Compare functions **********************************************/
mbed_official	340:28d1f895c6fe	1430	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1431	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1432	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1433	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1434	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1435	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1436	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1437	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1438	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1439	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1440	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1441	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1442	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1443	/**
mbed_official	340:28d1f895c6fe	1444	* @}
mbed_official	340:28d1f895c6fe	1445	*/
mbed_official	340:28d1f895c6fe	1446
mbed_official	340:28d1f895c6fe	1447	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
mbed_official	340:28d1f895c6fe	1448	* @brief Time PWM functions
mbed_official	340:28d1f895c6fe	1449	* @{
mbed_official	340:28d1f895c6fe	1450	*/
mbed_official	340:28d1f895c6fe	1451	/* Timer PWM functions *********************************************************/
mbed_official	340:28d1f895c6fe	1452	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1453	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1454	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1455	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1456	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1457	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1458	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1459	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1460	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1461	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1462	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1463	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1464	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1465	/**
mbed_official	340:28d1f895c6fe	1466	* @}
mbed_official	340:28d1f895c6fe	1467	*/
mbed_official	340:28d1f895c6fe	1468
mbed_official	340:28d1f895c6fe	1469	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
mbed_official	340:28d1f895c6fe	1470	* @brief Time Input Capture functions
mbed_official	340:28d1f895c6fe	1471	* @{
mbed_official	340:28d1f895c6fe	1472	*/
mbed_official	340:28d1f895c6fe	1473	/* Timer Input Capture functions ***********************************************/
mbed_official	340:28d1f895c6fe	1474	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1475	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1476	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1477	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1478	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1479	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1480	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1481	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1482	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1483	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1484	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1485	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	340:28d1f895c6fe	1486	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1487	/**
mbed_official	340:28d1f895c6fe	1488	* @}
mbed_official	340:28d1f895c6fe	1489	*/
mbed_official	340:28d1f895c6fe	1490
mbed_official	340:28d1f895c6fe	1491	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
mbed_official	340:28d1f895c6fe	1492	* @brief Time One Pulse functions
mbed_official	340:28d1f895c6fe	1493	* @{
mbed_official	340:28d1f895c6fe	1494	*/
mbed_official	340:28d1f895c6fe	1495	/* Timer One Pulse functions ***************************************************/
mbed_official	340:28d1f895c6fe	1496	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	340:28d1f895c6fe	1497	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1498	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1499	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1500	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1501	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1502	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1503	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1504	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1505	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	340:28d1f895c6fe	1506	/**
mbed_official	340:28d1f895c6fe	1507	* @}
mbed_official	340:28d1f895c6fe	1508	*/
mbed_official	340:28d1f895c6fe	1509
mbed_official	340:28d1f895c6fe	1510	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
mbed_official	340:28d1f895c6fe	1511	* @brief Time Encoder functions
mbed_official	340:28d1f895c6fe	1512	* @{
mbed_official	340:28d1f895c6fe	1513	*/
mbed_official	340:28d1f895c6fe	1514	/* Timer Encoder functions *****************************************************/
mbed_official	340:28d1f895c6fe	1515	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	340:28d1f895c6fe	1516	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1517	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1518	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1519	/* Blocking mode: Polling */
mbed_official	340:28d1f895c6fe	1520	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1521	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1522	/* Non-Blocking mode: Interrupt */
mbed_official	340:28d1f895c6fe	1523	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1524	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1525	/* Non-Blocking mode: DMA */
mbed_official	340:28d1f895c6fe	1526	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	340:28d1f895c6fe	1527	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1528	/**
mbed_official	340:28d1f895c6fe	1529	* @}
mbed_official	340:28d1f895c6fe	1530	*/
mbed_official	340:28d1f895c6fe	1531
mbed_official	340:28d1f895c6fe	1532	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
mbed_official	340:28d1f895c6fe	1533	* @brief IRQ handler management
mbed_official	340:28d1f895c6fe	1534	* @{
mbed_official	340:28d1f895c6fe	1535	*/
mbed_official	340:28d1f895c6fe	1536	/* Interrupt Handler functions **********************************************/
mbed_official	340:28d1f895c6fe	1537	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1538	/**
mbed_official	340:28d1f895c6fe	1539	* @}
mbed_official	340:28d1f895c6fe	1540	*/
mbed_official	340:28d1f895c6fe	1541
mbed_official	340:28d1f895c6fe	1542	/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official	340:28d1f895c6fe	1543	* @brief Peripheral Control functions
mbed_official	340:28d1f895c6fe	1544	* @{
mbed_official	340:28d1f895c6fe	1545	*/
mbed_official	340:28d1f895c6fe	1546	/* Control functions *********************************************************/
mbed_official	340:28d1f895c6fe	1547	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1548	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1549	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1550	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	340:28d1f895c6fe	1551	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1552	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	340:28d1f895c6fe	1553	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	340:28d1f895c6fe	1554	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	340:28d1f895c6fe	1555	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	340:28d1f895c6fe	1556	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	340:28d1f895c6fe	1557	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	340:28d1f895c6fe	1558	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	340:28d1f895c6fe	1559	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	340:28d1f895c6fe	1560	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	340:28d1f895c6fe	1561	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	340:28d1f895c6fe	1562	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	340:28d1f895c6fe	1563	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	340:28d1f895c6fe	1564	/**
mbed_official	340:28d1f895c6fe	1565	* @}
mbed_official	340:28d1f895c6fe	1566	*/
mbed_official	340:28d1f895c6fe	1567
mbed_official	340:28d1f895c6fe	1568	/** @addtogroup TIM_Exported_Functions_Group9
mbed_official	340:28d1f895c6fe	1569	* @brief TIM Callbacks functions
mbed_official	340:28d1f895c6fe	1570	* @{
mbed_official	340:28d1f895c6fe	1571	*/
mbed_official	340:28d1f895c6fe	1572	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	340:28d1f895c6fe	1573	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1574	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1575	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1576	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1577	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1578	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1579	/**
mbed_official	340:28d1f895c6fe	1580	* @}
mbed_official	340:28d1f895c6fe	1581	*/
mbed_official	340:28d1f895c6fe	1582
mbed_official	340:28d1f895c6fe	1583	/** @addtogroup TIM_Exported_Functions_Group10
mbed_official	340:28d1f895c6fe	1584	* @brief Peripheral State functions
mbed_official	340:28d1f895c6fe	1585	* @{
mbed_official	340:28d1f895c6fe	1586	*/
mbed_official	340:28d1f895c6fe	1587	/* Peripheral State functions **************************************************/
mbed_official	340:28d1f895c6fe	1588	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1589	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1590	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1591	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1592	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1593	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	340:28d1f895c6fe	1594	/**
mbed_official	340:28d1f895c6fe	1595	* @}
mbed_official	340:28d1f895c6fe	1596	*/
mbed_official	340:28d1f895c6fe	1597
mbed_official	340:28d1f895c6fe	1598	/**
mbed_official	340:28d1f895c6fe	1599	* @}
mbed_official	340:28d1f895c6fe	1600	*/
mbed_official	340:28d1f895c6fe	1601
mbed_official	340:28d1f895c6fe	1602	/* Private Macros -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1603	/** @defgroup TIM_Private_Macros TIM Private Macros
mbed_official	340:28d1f895c6fe	1604	* @{
mbed_official	340:28d1f895c6fe	1605	*/
mbed_official	340:28d1f895c6fe	1606	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	340:28d1f895c6fe	1607	channels have been disabled */
mbed_official	340:28d1f895c6fe	1608	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	340:28d1f895c6fe	1609	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	340:28d1f895c6fe	1610	/**
mbed_official	340:28d1f895c6fe	1611	* @}
mbed_official	340:28d1f895c6fe	1612	*/
mbed_official	340:28d1f895c6fe	1613
mbed_official	340:28d1f895c6fe	1614	/* Private Functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1615	/** @addtogroup TIM_Private_Functions
mbed_official	340:28d1f895c6fe	1616	* @{
mbed_official	340:28d1f895c6fe	1617	*/
mbed_official	340:28d1f895c6fe	1618	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	340:28d1f895c6fe	1619	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	340:28d1f895c6fe	1620	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	340:28d1f895c6fe	1621	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	1622	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	1623	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	1624	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	340:28d1f895c6fe	1625
mbed_official	340:28d1f895c6fe	1626	/**
mbed_official	340:28d1f895c6fe	1627	* @}
mbed_official	340:28d1f895c6fe	1628	*/
mbed_official	340:28d1f895c6fe	1629
mbed_official	340:28d1f895c6fe	1630	/**
mbed_official	340:28d1f895c6fe	1631	* @}
mbed_official	340:28d1f895c6fe	1632	*/
mbed_official	340:28d1f895c6fe	1633
mbed_official	340:28d1f895c6fe	1634	/**
mbed_official	340:28d1f895c6fe	1635	* @}
mbed_official	340:28d1f895c6fe	1636	*/
mbed_official	340:28d1f895c6fe	1637
mbed_official	340:28d1f895c6fe	1638	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1639	}
mbed_official	340:28d1f895c6fe	1640	#endif
mbed_official	340:28d1f895c6fe	1641
mbed_official	340:28d1f895c6fe	1642	#endif /* __STM32F0xx_HAL_TIM_H */
mbed_official	340:28d1f895c6fe	1643
mbed_official	340:28d1f895c6fe	1644	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	340:28d1f895c6fe	1645

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Type:	Library
Created:	14 Jan 2015
Imports:	4
Forks:	0
Commits:	446
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_tim.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

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