gabriel della-monica
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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c@445:9a3ffe6cfa19, 2015-01-14 (annotated)
- Committer:
- moirans2
- Date:
- Wed Jan 14 20:53:08 2015 +0000
- Revision:
- 445:9a3ffe6cfa19
- Parent:
- 441:d2c15dda23c1
internal clock stm32L051
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_spi.c |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 441:d2c15dda23c1 | 5 | * @version V1.2.0 |
| mbed_official | 441:d2c15dda23c1 | 6 | * @date 11-December-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief SPI HAL module driver. |
| mbed_official | 340:28d1f895c6fe | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 340:28d1f895c6fe | 9 | * functionalities of the SPI peripheral: |
| mbed_official | 340:28d1f895c6fe | 10 | * + Initialization/de-initialization functions |
| mbed_official | 340:28d1f895c6fe | 11 | * + I/O operation functions |
| mbed_official | 340:28d1f895c6fe | 12 | * + Peripheral Control functions |
| mbed_official | 340:28d1f895c6fe | 13 | * + Peripheral State functions |
| mbed_official | 340:28d1f895c6fe | 14 | * |
| mbed_official | 340:28d1f895c6fe | 15 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 16 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 17 | ##### How to use this driver ##### |
| mbed_official | 340:28d1f895c6fe | 18 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 19 | [..] |
| mbed_official | 340:28d1f895c6fe | 20 | The SPI HAL driver can be used as follows: |
| mbed_official | 340:28d1f895c6fe | 21 | |
| mbed_official | 340:28d1f895c6fe | 22 | (#) Declare a SPI_HandleTypeDef handle structure, for example: |
| mbed_official | 340:28d1f895c6fe | 23 | SPI_HandleTypeDef hspi; |
| mbed_official | 340:28d1f895c6fe | 24 | |
| mbed_official | 340:28d1f895c6fe | 25 | (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API: |
| mbed_official | 340:28d1f895c6fe | 26 | (##) Enable the SPIx interface clock |
| mbed_official | 340:28d1f895c6fe | 27 | (##) SPI pins configuration |
| mbed_official | 340:28d1f895c6fe | 28 | (+++) Enable the clock for the SPI GPIOs |
| mbed_official | 340:28d1f895c6fe | 29 | (+++) Configure these SPI pins as alternate function push-pull |
| mbed_official | 340:28d1f895c6fe | 30 | (##) NVIC configuration if you need to use interrupt process |
| mbed_official | 340:28d1f895c6fe | 31 | (+++) Configure the SPIx interrupt priority |
| mbed_official | 340:28d1f895c6fe | 32 | (+++) Enable the NVIC SPI IRQ handle |
| mbed_official | 340:28d1f895c6fe | 33 | (##) DMA Configuration if you need to use DMA process |
| mbed_official | 340:28d1f895c6fe | 34 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
| mbed_official | 340:28d1f895c6fe | 35 | (+++) Enable the DMAx interface clock using |
| mbed_official | 340:28d1f895c6fe | 36 | (+++) Configure the DMA handle parameters |
| mbed_official | 340:28d1f895c6fe | 37 | (+++) Configure the DMA Tx or Rx channel |
| mbed_official | 340:28d1f895c6fe | 38 | (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle |
| mbed_official | 340:28d1f895c6fe | 39 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel |
| mbed_official | 340:28d1f895c6fe | 40 | |
| mbed_official | 340:28d1f895c6fe | 41 | (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS |
| mbed_official | 340:28d1f895c6fe | 42 | management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. |
| mbed_official | 340:28d1f895c6fe | 43 | |
| mbed_official | 340:28d1f895c6fe | 44 | (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: |
| mbed_official | 340:28d1f895c6fe | 45 | (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
| mbed_official | 340:28d1f895c6fe | 46 | by calling the customed HAL_SPI_MspInit(&hspi) API. |
| mbed_official | 340:28d1f895c6fe | 47 | |
| mbed_official | 340:28d1f895c6fe | 48 | [..] |
| mbed_official | 340:28d1f895c6fe | 49 | Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, |
| mbed_official | 340:28d1f895c6fe | 50 | the following table resume the max SPI frequency reached with data size 8bits/16bits: |
| mbed_official | 340:28d1f895c6fe | 51 | +-----------------------------------------------------------------------------------------+ |
| mbed_official | 340:28d1f895c6fe | 52 | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | |
| mbed_official | 340:28d1f895c6fe | 53 | | Process | Tranfert mode |--------------------|--------------------|--------------------| |
| mbed_official | 340:28d1f895c6fe | 54 | | | | Master | Slave | Master | Slave | Master | Slave | |
| mbed_official | 340:28d1f895c6fe | 55 | |=========================================================================================| |
| mbed_official | 340:28d1f895c6fe | 56 | | T | Polling | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | |
| mbed_official | 340:28d1f895c6fe | 57 | | X |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 58 | | / | Interrupt | Fcpu/32 | Fcpu/32 | NA | NA | NA | NA | |
| mbed_official | 340:28d1f895c6fe | 59 | | R |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 60 | | X | DMA | Fcpu/32 | Fcpu/16 | NA | NA | NA | NA | |
| mbed_official | 340:28d1f895c6fe | 61 | |=========|================|==========|=========|==========|=========|==========|=========| |
| mbed_official | 340:28d1f895c6fe | 62 | | | Polling | Fcpu/32 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 63 | | |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 64 | | R | Interrupt | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 65 | | X |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 66 | | | DMA | Fcpu/4 | Fcpu/8 | Fcpu/4 | Fcpu/4 | Fcpu/8 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 67 | |=========|================|==========|=========|==========|=========|==========|=========| |
| mbed_official | 340:28d1f895c6fe | 68 | | | Polling | Fcpu/16 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 69 | | |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 70 | | T | Interrupt | Fcpu/32 | Fcpu/16 | NA | NA | Fcpu/16 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 71 | | X |----------------|----------|---------|----------|---------|----------|---------| |
| mbed_official | 340:28d1f895c6fe | 72 | | | DMA | Fcpu/2 | Fcpu/16 | NA | NA | Fcpu/8 | Fcpu/16 | |
| mbed_official | 340:28d1f895c6fe | 73 | +-----------------------------------------------------------------------------------------+ |
| mbed_official | 340:28d1f895c6fe | 74 | @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), |
| mbed_official | 340:28d1f895c6fe | 75 | SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). |
| mbed_official | 340:28d1f895c6fe | 76 | @note |
| mbed_official | 340:28d1f895c6fe | 77 | (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() |
| mbed_official | 340:28d1f895c6fe | 78 | (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() |
| mbed_official | 340:28d1f895c6fe | 79 | (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() |
| mbed_official | 340:28d1f895c6fe | 80 | |
| mbed_official | 340:28d1f895c6fe | 81 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 82 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 83 | * @attention |
| mbed_official | 340:28d1f895c6fe | 84 | * |
| mbed_official | 340:28d1f895c6fe | 85 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 86 | * |
| mbed_official | 340:28d1f895c6fe | 87 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 88 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 89 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 90 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 91 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 92 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 93 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 94 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 95 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 96 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 97 | * |
| mbed_official | 340:28d1f895c6fe | 98 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 99 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 100 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 101 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 102 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 103 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 104 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 105 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 106 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 107 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 108 | * |
| mbed_official | 340:28d1f895c6fe | 109 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 110 | */ |
| mbed_official | 340:28d1f895c6fe | 111 | |
| mbed_official | 340:28d1f895c6fe | 112 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 113 | #include "stm32f0xx_hal.h" |
| mbed_official | 340:28d1f895c6fe | 114 | |
| mbed_official | 340:28d1f895c6fe | 115 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 116 | * @{ |
| mbed_official | 340:28d1f895c6fe | 117 | */ |
| mbed_official | 340:28d1f895c6fe | 118 | |
| mbed_official | 340:28d1f895c6fe | 119 | /** @defgroup SPI SPI HAL module driver |
| mbed_official | 340:28d1f895c6fe | 120 | * @brief SPI HAL module driver |
| mbed_official | 340:28d1f895c6fe | 121 | * @{ |
| mbed_official | 340:28d1f895c6fe | 122 | */ |
| mbed_official | 340:28d1f895c6fe | 123 | #ifdef HAL_SPI_MODULE_ENABLED |
| mbed_official | 340:28d1f895c6fe | 124 | |
| mbed_official | 340:28d1f895c6fe | 125 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 126 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 127 | |
| mbed_official | 340:28d1f895c6fe | 128 | /** @defgroup SPI_Private_Constants SPI Private Constants |
| mbed_official | 340:28d1f895c6fe | 129 | * @{ |
| mbed_official | 340:28d1f895c6fe | 130 | */ |
| mbed_official | 340:28d1f895c6fe | 131 | #define SPI_DEFAULT_TIMEOUT 50 |
| mbed_official | 441:d2c15dda23c1 | 132 | #define SPI_FIFO_SIZE 4 |
| mbed_official | 340:28d1f895c6fe | 133 | /** |
| mbed_official | 340:28d1f895c6fe | 134 | * @} |
| mbed_official | 340:28d1f895c6fe | 135 | */ |
| mbed_official | 340:28d1f895c6fe | 136 | |
| mbed_official | 340:28d1f895c6fe | 137 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 138 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 139 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 140 | /** @defgroup SPI_Private_Functions SPI Private Functions |
| mbed_official | 340:28d1f895c6fe | 141 | * @{ |
| mbed_official | 340:28d1f895c6fe | 142 | */ |
| mbed_official | 340:28d1f895c6fe | 143 | |
| mbed_official | 441:d2c15dda23c1 | 144 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 145 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 146 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 147 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 148 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 149 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 441:d2c15dda23c1 | 150 | static void SPI_DMAError(DMA_HandleTypeDef *hdma); |
| mbed_official | 340:28d1f895c6fe | 151 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 152 | static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 153 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 154 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 155 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 156 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 157 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 158 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 159 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 160 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 161 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 162 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 163 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 164 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 165 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 166 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 167 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); |
| mbed_official | 340:28d1f895c6fe | 168 | static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 169 | /** |
| mbed_official | 340:28d1f895c6fe | 170 | * @} |
| mbed_official | 340:28d1f895c6fe | 171 | */ |
| mbed_official | 340:28d1f895c6fe | 172 | |
| mbed_official | 340:28d1f895c6fe | 173 | /* Exported functions ---------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 174 | |
| mbed_official | 340:28d1f895c6fe | 175 | /** @defgroup SPI_Exported_Functions SPI Exported Functions |
| mbed_official | 340:28d1f895c6fe | 176 | * @{ |
| mbed_official | 340:28d1f895c6fe | 177 | */ |
| mbed_official | 340:28d1f895c6fe | 178 | |
| mbed_official | 340:28d1f895c6fe | 179 | /** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions |
| mbed_official | 340:28d1f895c6fe | 180 | * @brief Initialization and Configuration functions |
| mbed_official | 340:28d1f895c6fe | 181 | * |
| mbed_official | 340:28d1f895c6fe | 182 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 183 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 184 | ##### Initialization and Configuration functions ##### |
| mbed_official | 340:28d1f895c6fe | 185 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 186 | [..] This subsection provides a set of functions allowing to initialize and |
| mbed_official | 340:28d1f895c6fe | 187 | de-initialiaze the SPIx peripheral: |
| mbed_official | 340:28d1f895c6fe | 188 | |
| mbed_official | 340:28d1f895c6fe | 189 | (+) User must Implement HAL_SPI_MspInit() function in which he configures |
| mbed_official | 340:28d1f895c6fe | 190 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
| mbed_official | 340:28d1f895c6fe | 191 | |
| mbed_official | 340:28d1f895c6fe | 192 | (+) Call the function HAL_SPI_Init() to configure the selected device with |
| mbed_official | 340:28d1f895c6fe | 193 | the selected configuration: |
| mbed_official | 340:28d1f895c6fe | 194 | (++) Mode |
| mbed_official | 340:28d1f895c6fe | 195 | (++) Direction |
| mbed_official | 340:28d1f895c6fe | 196 | (++) Data Size |
| mbed_official | 340:28d1f895c6fe | 197 | (++) Clock Polarity and Phase |
| mbed_official | 340:28d1f895c6fe | 198 | (++) NSS Management |
| mbed_official | 340:28d1f895c6fe | 199 | (++) BaudRate Prescaler |
| mbed_official | 340:28d1f895c6fe | 200 | (++) FirstBit |
| mbed_official | 340:28d1f895c6fe | 201 | (++) TIMode |
| mbed_official | 340:28d1f895c6fe | 202 | (++) CRC Calculation |
| mbed_official | 340:28d1f895c6fe | 203 | (++) CRC Polynomial if CRC enabled |
| mbed_official | 340:28d1f895c6fe | 204 | (++) CRC Length, used only with Data8 and Data16 |
| mbed_official | 340:28d1f895c6fe | 205 | (++) FIFO reception threshold |
| mbed_official | 340:28d1f895c6fe | 206 | |
| mbed_official | 340:28d1f895c6fe | 207 | (+) Call the function HAL_SPI_DeInit() to restore the default configuration |
| mbed_official | 340:28d1f895c6fe | 208 | of the selected SPIx periperal. |
| mbed_official | 340:28d1f895c6fe | 209 | |
| mbed_official | 340:28d1f895c6fe | 210 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 211 | * @{ |
| mbed_official | 340:28d1f895c6fe | 212 | */ |
| mbed_official | 340:28d1f895c6fe | 213 | |
| mbed_official | 340:28d1f895c6fe | 214 | /** |
| mbed_official | 340:28d1f895c6fe | 215 | * @brief Initializes the SPI according to the specified parameters |
| mbed_official | 340:28d1f895c6fe | 216 | * in the SPI_InitTypeDef and create the associated handle. |
| mbed_official | 441:d2c15dda23c1 | 217 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 218 | * the configuration information for SPI module. |
| mbed_official | 340:28d1f895c6fe | 219 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 220 | */ |
| mbed_official | 340:28d1f895c6fe | 221 | HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 222 | { |
| mbed_official | 340:28d1f895c6fe | 223 | uint32_t frxth; |
| mbed_official | 340:28d1f895c6fe | 224 | |
| mbed_official | 340:28d1f895c6fe | 225 | /* Check the SPI handle allocation */ |
| mbed_official | 441:d2c15dda23c1 | 226 | if(hspi == NULL) |
| mbed_official | 340:28d1f895c6fe | 227 | { |
| mbed_official | 340:28d1f895c6fe | 228 | return HAL_ERROR; |
| mbed_official | 340:28d1f895c6fe | 229 | } |
| mbed_official | 340:28d1f895c6fe | 230 | |
| mbed_official | 340:28d1f895c6fe | 231 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 232 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
| mbed_official | 340:28d1f895c6fe | 233 | assert_param(IS_SPI_MODE(hspi->Init.Mode)); |
| mbed_official | 340:28d1f895c6fe | 234 | assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); |
| mbed_official | 340:28d1f895c6fe | 235 | assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); |
| mbed_official | 340:28d1f895c6fe | 236 | assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); |
| mbed_official | 340:28d1f895c6fe | 237 | assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); |
| mbed_official | 340:28d1f895c6fe | 238 | assert_param(IS_SPI_NSS(hspi->Init.NSS)); |
| mbed_official | 340:28d1f895c6fe | 239 | assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); |
| mbed_official | 340:28d1f895c6fe | 240 | assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); |
| mbed_official | 340:28d1f895c6fe | 241 | assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); |
| mbed_official | 340:28d1f895c6fe | 242 | assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); |
| mbed_official | 340:28d1f895c6fe | 243 | assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); |
| mbed_official | 340:28d1f895c6fe | 244 | assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); |
| mbed_official | 340:28d1f895c6fe | 245 | assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); |
| mbed_official | 340:28d1f895c6fe | 246 | |
| mbed_official | 340:28d1f895c6fe | 247 | hspi->State = HAL_SPI_STATE_BUSY; |
| mbed_official | 340:28d1f895c6fe | 248 | |
| mbed_official | 340:28d1f895c6fe | 249 | /* Init the low level hardware : GPIO, CLOCK, NVIC... */ |
| mbed_official | 340:28d1f895c6fe | 250 | HAL_SPI_MspInit(hspi); |
| mbed_official | 340:28d1f895c6fe | 251 | |
| mbed_official | 340:28d1f895c6fe | 252 | /* Disable the selected SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 253 | __HAL_SPI_DISABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 254 | |
| mbed_official | 340:28d1f895c6fe | 255 | /* Align by default the rs fifo threshold on the data size */ |
| mbed_official | 340:28d1f895c6fe | 256 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 257 | { |
| mbed_official | 340:28d1f895c6fe | 258 | frxth = SPI_RXFIFO_THRESHOLD_HF; |
| mbed_official | 340:28d1f895c6fe | 259 | } |
| mbed_official | 340:28d1f895c6fe | 260 | else |
| mbed_official | 340:28d1f895c6fe | 261 | { |
| mbed_official | 340:28d1f895c6fe | 262 | frxth = SPI_RXFIFO_THRESHOLD_QF; |
| mbed_official | 340:28d1f895c6fe | 263 | } |
| mbed_official | 340:28d1f895c6fe | 264 | |
| mbed_official | 340:28d1f895c6fe | 265 | /* CRC calculation is valid only for 16Bit and 8 Bit */ |
| mbed_official | 340:28d1f895c6fe | 266 | if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT )) |
| mbed_official | 340:28d1f895c6fe | 267 | { |
| mbed_official | 340:28d1f895c6fe | 268 | /* CRC must be disabled */ |
| mbed_official | 340:28d1f895c6fe | 269 | hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; |
| mbed_official | 340:28d1f895c6fe | 270 | } |
| mbed_official | 340:28d1f895c6fe | 271 | |
| mbed_official | 340:28d1f895c6fe | 272 | /* Align the CRC Length on the data size */ |
| mbed_official | 340:28d1f895c6fe | 273 | if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) |
| mbed_official | 340:28d1f895c6fe | 274 | { |
| mbed_official | 340:28d1f895c6fe | 275 | /* CRC Lengtht aligned on the data size : value set by default */ |
| mbed_official | 340:28d1f895c6fe | 276 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 277 | { |
| mbed_official | 340:28d1f895c6fe | 278 | hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; |
| mbed_official | 340:28d1f895c6fe | 279 | } |
| mbed_official | 340:28d1f895c6fe | 280 | else |
| mbed_official | 340:28d1f895c6fe | 281 | { |
| mbed_official | 340:28d1f895c6fe | 282 | hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; |
| mbed_official | 340:28d1f895c6fe | 283 | } |
| mbed_official | 340:28d1f895c6fe | 284 | } |
| mbed_official | 340:28d1f895c6fe | 285 | |
| mbed_official | 340:28d1f895c6fe | 286 | /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 287 | /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, |
| mbed_official | 340:28d1f895c6fe | 288 | Communication speed, First bit, CRC calculation state, CRC Length */ |
| mbed_official | 340:28d1f895c6fe | 289 | hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | |
| mbed_official | 340:28d1f895c6fe | 290 | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | |
| mbed_official | 340:28d1f895c6fe | 291 | hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); |
| mbed_official | 340:28d1f895c6fe | 292 | |
| mbed_official | 340:28d1f895c6fe | 293 | if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
| mbed_official | 340:28d1f895c6fe | 294 | { |
| mbed_official | 340:28d1f895c6fe | 295 | hspi->Instance->CR1|= SPI_CR1_CRCL; |
| mbed_official | 340:28d1f895c6fe | 296 | } |
| mbed_official | 340:28d1f895c6fe | 297 | |
| mbed_official | 340:28d1f895c6fe | 298 | /* Configure : NSS management */ |
| mbed_official | 340:28d1f895c6fe | 299 | /* Configure : Rx Fifo Threshold */ |
| mbed_official | 340:28d1f895c6fe | 300 | hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode | |
| mbed_official | 340:28d1f895c6fe | 301 | hspi->Init.DataSize ) | frxth; |
| mbed_official | 340:28d1f895c6fe | 302 | |
| mbed_official | 340:28d1f895c6fe | 303 | /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ |
| mbed_official | 340:28d1f895c6fe | 304 | /* Configure : CRC Polynomial */ |
| mbed_official | 340:28d1f895c6fe | 305 | hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; |
| mbed_official | 340:28d1f895c6fe | 306 | |
| mbed_official | 340:28d1f895c6fe | 307 | /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ |
| mbed_official | 340:28d1f895c6fe | 308 | hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD); |
| mbed_official | 340:28d1f895c6fe | 309 | |
| mbed_official | 340:28d1f895c6fe | 310 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 311 | hspi->State= HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 312 | |
| mbed_official | 340:28d1f895c6fe | 313 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 314 | } |
| mbed_official | 340:28d1f895c6fe | 315 | |
| mbed_official | 340:28d1f895c6fe | 316 | /** |
| mbed_official | 340:28d1f895c6fe | 317 | * @brief DeInitializes the SPI peripheral |
| mbed_official | 441:d2c15dda23c1 | 318 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 319 | * the configuration information for SPI module. |
| mbed_official | 340:28d1f895c6fe | 320 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 321 | */ |
| mbed_official | 340:28d1f895c6fe | 322 | HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 323 | { |
| mbed_official | 340:28d1f895c6fe | 324 | /* Check the SPI handle allocation */ |
| mbed_official | 441:d2c15dda23c1 | 325 | if(hspi == NULL) |
| mbed_official | 340:28d1f895c6fe | 326 | { |
| mbed_official | 441:d2c15dda23c1 | 327 | return HAL_ERROR; |
| mbed_official | 340:28d1f895c6fe | 328 | } |
| mbed_official | 340:28d1f895c6fe | 329 | |
| mbed_official | 340:28d1f895c6fe | 330 | /* Check the parameters */ |
| mbed_official | 340:28d1f895c6fe | 331 | assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); |
| mbed_official | 340:28d1f895c6fe | 332 | hspi->State = HAL_SPI_STATE_BUSY; |
| mbed_official | 340:28d1f895c6fe | 333 | |
| mbed_official | 441:d2c15dda23c1 | 334 | /* check flag before the SPI disable */ |
| mbed_official | 441:d2c15dda23c1 | 335 | SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT); |
| mbed_official | 441:d2c15dda23c1 | 336 | SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT); |
| mbed_official | 441:d2c15dda23c1 | 337 | SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT); |
| mbed_official | 441:d2c15dda23c1 | 338 | |
| mbed_official | 340:28d1f895c6fe | 339 | /* Disable the SPI Peripheral Clock */ |
| mbed_official | 340:28d1f895c6fe | 340 | __HAL_SPI_DISABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 341 | |
| mbed_official | 340:28d1f895c6fe | 342 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ |
| mbed_official | 340:28d1f895c6fe | 343 | HAL_SPI_MspDeInit(hspi); |
| mbed_official | 340:28d1f895c6fe | 344 | |
| mbed_official | 340:28d1f895c6fe | 345 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 346 | hspi->State = HAL_SPI_STATE_RESET; |
| mbed_official | 340:28d1f895c6fe | 347 | |
| mbed_official | 340:28d1f895c6fe | 348 | __HAL_UNLOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 349 | |
| mbed_official | 340:28d1f895c6fe | 350 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 351 | } |
| mbed_official | 340:28d1f895c6fe | 352 | |
| mbed_official | 340:28d1f895c6fe | 353 | /** |
| mbed_official | 340:28d1f895c6fe | 354 | * @brief SPI MSP Init |
| mbed_official | 441:d2c15dda23c1 | 355 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 356 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 357 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 358 | */ |
| mbed_official | 340:28d1f895c6fe | 359 | __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 360 | { |
| mbed_official | 340:28d1f895c6fe | 361 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 362 | the HAL_SPI_MspInit could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 363 | */ |
| mbed_official | 340:28d1f895c6fe | 364 | } |
| mbed_official | 340:28d1f895c6fe | 365 | |
| mbed_official | 340:28d1f895c6fe | 366 | /** |
| mbed_official | 340:28d1f895c6fe | 367 | * @brief SPI MSP DeInit |
| mbed_official | 441:d2c15dda23c1 | 368 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 369 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 370 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 371 | */ |
| mbed_official | 340:28d1f895c6fe | 372 | __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 373 | { |
| mbed_official | 340:28d1f895c6fe | 374 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 375 | the HAL_SPI_MspDeInit could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 376 | */ |
| mbed_official | 340:28d1f895c6fe | 377 | } |
| mbed_official | 340:28d1f895c6fe | 378 | |
| mbed_official | 340:28d1f895c6fe | 379 | /** |
| mbed_official | 340:28d1f895c6fe | 380 | * @} |
| mbed_official | 340:28d1f895c6fe | 381 | */ |
| mbed_official | 340:28d1f895c6fe | 382 | |
| mbed_official | 340:28d1f895c6fe | 383 | /** @defgroup SPI_Exported_Functions_Group2 I/O operation functions |
| mbed_official | 340:28d1f895c6fe | 384 | * @brief Data transfers functions |
| mbed_official | 340:28d1f895c6fe | 385 | * |
| mbed_official | 340:28d1f895c6fe | 386 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 387 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 388 | ##### IO operation functions ##### |
| mbed_official | 340:28d1f895c6fe | 389 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 390 | This subsection provides a set of functions allowing to manage the SPI |
| mbed_official | 340:28d1f895c6fe | 391 | data transfers. |
| mbed_official | 340:28d1f895c6fe | 392 | |
| mbed_official | 340:28d1f895c6fe | 393 | [..] The SPI supports master and slave mode : |
| mbed_official | 340:28d1f895c6fe | 394 | |
| mbed_official | 340:28d1f895c6fe | 395 | (#) There are two modes of transfer: |
| mbed_official | 340:28d1f895c6fe | 396 | (++) Blocking mode: The communication is performed in polling mode. |
| mbed_official | 340:28d1f895c6fe | 397 | The HAL status of all data processing is returned by the same function |
| mbed_official | 340:28d1f895c6fe | 398 | after finishing transfer. |
| mbed_official | 340:28d1f895c6fe | 399 | (++) Non Blocking mode: The communication is performed using Interrupts |
| mbed_official | 340:28d1f895c6fe | 400 | or DMA, These APIs return the HAL status. |
| mbed_official | 340:28d1f895c6fe | 401 | The end of the data processing will be indicated through the |
| mbed_official | 340:28d1f895c6fe | 402 | dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when |
| mbed_official | 340:28d1f895c6fe | 403 | using DMA mode. |
| mbed_official | 340:28d1f895c6fe | 404 | The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks |
| mbed_official | 340:28d1f895c6fe | 405 | will be executed respectivelly at the end of the transmit or Receive process |
| mbed_official | 340:28d1f895c6fe | 406 | The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected |
| mbed_official | 340:28d1f895c6fe | 407 | |
| mbed_official | 340:28d1f895c6fe | 408 | (#) Blocking mode APIs are : |
| mbed_official | 340:28d1f895c6fe | 409 | (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 340:28d1f895c6fe | 410 | (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 441:d2c15dda23c1 | 411 | (++) HAL_SPI_TransmitReceive() in full duplex mode |
| mbed_official | 441:d2c15dda23c1 | 412 | |
| mbed_official | 340:28d1f895c6fe | 413 | (#) Non Blocking mode APIs with Interrupt are : |
| mbed_official | 340:28d1f895c6fe | 414 | (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 340:28d1f895c6fe | 415 | (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 340:28d1f895c6fe | 416 | (++) HAL_SPI_TransmitReceive_IT()in full duplex mode |
| mbed_official | 340:28d1f895c6fe | 417 | (++) HAL_SPI_IRQHandler() |
| mbed_official | 340:28d1f895c6fe | 418 | |
| mbed_official | 340:28d1f895c6fe | 419 | (#) Non Blocking mode functions with DMA are : |
| mbed_official | 340:28d1f895c6fe | 420 | (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 340:28d1f895c6fe | 421 | (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode |
| mbed_official | 340:28d1f895c6fe | 422 | (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode |
| mbed_official | 441:d2c15dda23c1 | 423 | |
| mbed_official | 340:28d1f895c6fe | 424 | (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: |
| mbed_official | 340:28d1f895c6fe | 425 | (++) HAL_SPI_TxCpltCallback() |
| mbed_official | 340:28d1f895c6fe | 426 | (++) HAL_SPI_RxCpltCallback() |
| mbed_official | 340:28d1f895c6fe | 427 | (++) HAL_SPI_ErrorCallback() |
| mbed_official | 340:28d1f895c6fe | 428 | (++) HAL_SPI_TxRxCpltCallback() |
| mbed_official | 340:28d1f895c6fe | 429 | |
| mbed_official | 340:28d1f895c6fe | 430 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 431 | * @{ |
| mbed_official | 340:28d1f895c6fe | 432 | */ |
| mbed_official | 340:28d1f895c6fe | 433 | |
| mbed_official | 340:28d1f895c6fe | 434 | /** |
| mbed_official | 340:28d1f895c6fe | 435 | * @brief Transmit an amount of data in blocking mode |
| mbed_official | 441:d2c15dda23c1 | 436 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 437 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 438 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 439 | * @param Size : amount of data to be sent |
| mbed_official | 441:d2c15dda23c1 | 440 | * @param Timeout : Timeout duration |
| mbed_official | 340:28d1f895c6fe | 441 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 442 | */ |
| mbed_official | 340:28d1f895c6fe | 443 | HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 444 | { |
| mbed_official | 441:d2c15dda23c1 | 445 | uint32_t tickstart = HAL_GetTick(); |
| mbed_official | 441:d2c15dda23c1 | 446 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 441:d2c15dda23c1 | 447 | |
| mbed_official | 340:28d1f895c6fe | 448 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
| mbed_official | 441:d2c15dda23c1 | 449 | |
| mbed_official | 441:d2c15dda23c1 | 450 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 451 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 452 | |
| mbed_official | 441:d2c15dda23c1 | 453 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 340:28d1f895c6fe | 454 | { |
| mbed_official | 441:d2c15dda23c1 | 455 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 456 | goto error; |
| mbed_official | 340:28d1f895c6fe | 457 | } |
| mbed_official | 340:28d1f895c6fe | 458 | |
| mbed_official | 441:d2c15dda23c1 | 459 | if((pData == NULL ) || (Size == 0)) |
| mbed_official | 340:28d1f895c6fe | 460 | { |
| mbed_official | 441:d2c15dda23c1 | 461 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 462 | goto error; |
| mbed_official | 340:28d1f895c6fe | 463 | } |
| mbed_official | 441:d2c15dda23c1 | 464 | |
| mbed_official | 340:28d1f895c6fe | 465 | /* Set the transaction information */ |
| mbed_official | 340:28d1f895c6fe | 466 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
| mbed_official | 340:28d1f895c6fe | 467 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 468 | hspi->pTxBuffPtr = pData; |
| mbed_official | 340:28d1f895c6fe | 469 | hspi->TxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 470 | hspi->TxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 471 | hspi->pRxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 340:28d1f895c6fe | 472 | hspi->RxXferSize = 0; |
| mbed_official | 340:28d1f895c6fe | 473 | hspi->RxXferCount = 0; |
| mbed_official | 340:28d1f895c6fe | 474 | |
| mbed_official | 441:d2c15dda23c1 | 475 | /* Configure communication direction : 1Line */ |
| mbed_official | 441:d2c15dda23c1 | 476 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 441:d2c15dda23c1 | 477 | { |
| mbed_official | 441:d2c15dda23c1 | 478 | __HAL_SPI_1LINE_TX(hspi); |
| mbed_official | 441:d2c15dda23c1 | 479 | } |
| mbed_official | 441:d2c15dda23c1 | 480 | |
| mbed_official | 340:28d1f895c6fe | 481 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 482 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 483 | { |
| mbed_official | 340:28d1f895c6fe | 484 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 485 | } |
| mbed_official | 340:28d1f895c6fe | 486 | |
| mbed_official | 340:28d1f895c6fe | 487 | /* Check if the SPI is already enabled */ |
| mbed_official | 340:28d1f895c6fe | 488 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 489 | { |
| mbed_official | 340:28d1f895c6fe | 490 | /* Enable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 491 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 492 | } |
| mbed_official | 340:28d1f895c6fe | 493 | |
| mbed_official | 340:28d1f895c6fe | 494 | /* Transmit data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 495 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 496 | { |
| mbed_official | 441:d2c15dda23c1 | 497 | /* Transmit data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 498 | while (hspi->TxXferCount > 0) |
| mbed_official | 340:28d1f895c6fe | 499 | { |
| mbed_official | 340:28d1f895c6fe | 500 | /* Wait until TXE flag is set to send data */ |
| mbed_official | 441:d2c15dda23c1 | 501 | if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) |
| mbed_official | 340:28d1f895c6fe | 502 | { |
| mbed_official | 441:d2c15dda23c1 | 503 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
| mbed_official | 441:d2c15dda23c1 | 504 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 441:d2c15dda23c1 | 505 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 506 | } |
| mbed_official | 441:d2c15dda23c1 | 507 | else |
| mbed_official | 441:d2c15dda23c1 | 508 | { |
| mbed_official | 441:d2c15dda23c1 | 509 | /* Timeout management */ |
| mbed_official | 441:d2c15dda23c1 | 510 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
| mbed_official | 441:d2c15dda23c1 | 511 | { |
| mbed_official | 441:d2c15dda23c1 | 512 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 513 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 514 | } |
| mbed_official | 441:d2c15dda23c1 | 515 | } |
| mbed_official | 340:28d1f895c6fe | 516 | } |
| mbed_official | 340:28d1f895c6fe | 517 | } |
| mbed_official | 340:28d1f895c6fe | 518 | /* Transmit data in 8 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 519 | else |
| mbed_official | 340:28d1f895c6fe | 520 | { |
| mbed_official | 340:28d1f895c6fe | 521 | while (hspi->TxXferCount > 0) |
| mbed_official | 340:28d1f895c6fe | 522 | { |
| mbed_official | 441:d2c15dda23c1 | 523 | /* Wait until TXE flag is set to send data */ |
| mbed_official | 441:d2c15dda23c1 | 524 | if((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE) |
| mbed_official | 340:28d1f895c6fe | 525 | { |
| mbed_official | 441:d2c15dda23c1 | 526 | if(hspi->TxXferCount > 1) |
| mbed_official | 340:28d1f895c6fe | 527 | { |
| mbed_official | 441:d2c15dda23c1 | 528 | /* write on the data register in packaing mode */ |
| mbed_official | 441:d2c15dda23c1 | 529 | hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); |
| mbed_official | 441:d2c15dda23c1 | 530 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 441:d2c15dda23c1 | 531 | hspi->TxXferCount -= 2; |
| mbed_official | 340:28d1f895c6fe | 532 | } |
| mbed_official | 441:d2c15dda23c1 | 533 | else |
| mbed_official | 441:d2c15dda23c1 | 534 | { |
| mbed_official | 441:d2c15dda23c1 | 535 | *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++); |
| mbed_official | 441:d2c15dda23c1 | 536 | hspi->TxXferCount--; |
| mbed_official | 441:d2c15dda23c1 | 537 | } |
| mbed_official | 340:28d1f895c6fe | 538 | } |
| mbed_official | 340:28d1f895c6fe | 539 | else |
| mbed_official | 340:28d1f895c6fe | 540 | { |
| mbed_official | 441:d2c15dda23c1 | 541 | /* Timeout management */ |
| mbed_official | 441:d2c15dda23c1 | 542 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
| mbed_official | 340:28d1f895c6fe | 543 | { |
| mbed_official | 441:d2c15dda23c1 | 544 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 545 | goto error; |
| mbed_official | 340:28d1f895c6fe | 546 | } |
| mbed_official | 340:28d1f895c6fe | 547 | } |
| mbed_official | 340:28d1f895c6fe | 548 | } |
| mbed_official | 340:28d1f895c6fe | 549 | } |
| mbed_official | 340:28d1f895c6fe | 550 | |
| mbed_official | 340:28d1f895c6fe | 551 | /* Enable CRC Transmission */ |
| mbed_official | 441:d2c15dda23c1 | 552 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 553 | { |
| mbed_official | 340:28d1f895c6fe | 554 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 555 | } |
| mbed_official | 340:28d1f895c6fe | 556 | |
| mbed_official | 340:28d1f895c6fe | 557 | /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ |
| mbed_official | 340:28d1f895c6fe | 558 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
| mbed_official | 340:28d1f895c6fe | 559 | { |
| mbed_official | 340:28d1f895c6fe | 560 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 561 | } |
| mbed_official | 340:28d1f895c6fe | 562 | |
| mbed_official | 340:28d1f895c6fe | 563 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 564 | { |
| mbed_official | 441:d2c15dda23c1 | 565 | errorcode = HAL_ERROR; |
| mbed_official | 340:28d1f895c6fe | 566 | } |
| mbed_official | 441:d2c15dda23c1 | 567 | |
| mbed_official | 441:d2c15dda23c1 | 568 | error: |
| mbed_official | 441:d2c15dda23c1 | 569 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 570 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 571 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 572 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 573 | } |
| mbed_official | 340:28d1f895c6fe | 574 | |
| mbed_official | 340:28d1f895c6fe | 575 | /** |
| mbed_official | 340:28d1f895c6fe | 576 | * @brief Receive an amount of data in blocking mode |
| mbed_official | 441:d2c15dda23c1 | 577 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 578 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 579 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 580 | * @param Size : amount of data to be sent |
| mbed_official | 441:d2c15dda23c1 | 581 | * @param Timeout : Timeout duration |
| mbed_official | 340:28d1f895c6fe | 582 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 583 | */ |
| mbed_official | 340:28d1f895c6fe | 584 | HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 585 | { |
| mbed_official | 340:28d1f895c6fe | 586 | __IO uint16_t tmpreg; |
| mbed_official | 441:d2c15dda23c1 | 587 | uint32_t tickstart = HAL_GetTick(); |
| mbed_official | 441:d2c15dda23c1 | 588 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 589 | |
| mbed_official | 340:28d1f895c6fe | 590 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
| mbed_official | 340:28d1f895c6fe | 591 | { |
| mbed_official | 340:28d1f895c6fe | 592 | /* the receive process is not supported in 2Lines direction master mode */ |
| mbed_official | 340:28d1f895c6fe | 593 | /* in this case we call the transmitReceive process */ |
| mbed_official | 441:d2c15dda23c1 | 594 | /* Process Locked */ |
| mbed_official | 340:28d1f895c6fe | 595 | return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); |
| mbed_official | 340:28d1f895c6fe | 596 | } |
| mbed_official | 340:28d1f895c6fe | 597 | |
| mbed_official | 340:28d1f895c6fe | 598 | /* Process Locked */ |
| mbed_official | 340:28d1f895c6fe | 599 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 600 | |
| mbed_official | 441:d2c15dda23c1 | 601 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 441:d2c15dda23c1 | 602 | { |
| mbed_official | 441:d2c15dda23c1 | 603 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 604 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 605 | } |
| mbed_official | 441:d2c15dda23c1 | 606 | |
| mbed_official | 441:d2c15dda23c1 | 607 | if((pData == NULL ) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 608 | { |
| mbed_official | 441:d2c15dda23c1 | 609 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 610 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 611 | } |
| mbed_official | 441:d2c15dda23c1 | 612 | |
| mbed_official | 340:28d1f895c6fe | 613 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
| mbed_official | 340:28d1f895c6fe | 614 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 615 | hspi->pRxBuffPtr = pData; |
| mbed_official | 340:28d1f895c6fe | 616 | hspi->RxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 617 | hspi->RxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 618 | hspi->pTxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 340:28d1f895c6fe | 619 | hspi->TxXferSize = 0; |
| mbed_official | 340:28d1f895c6fe | 620 | hspi->TxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 621 | |
| mbed_official | 340:28d1f895c6fe | 622 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 623 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 624 | { |
| mbed_official | 340:28d1f895c6fe | 625 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 441:d2c15dda23c1 | 626 | /* this is done to handle the CRCNEXT before the latest data */ |
| mbed_official | 441:d2c15dda23c1 | 627 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 628 | } |
| mbed_official | 340:28d1f895c6fe | 629 | |
| mbed_official | 340:28d1f895c6fe | 630 | /* Set the Rx Fido thresold */ |
| mbed_official | 340:28d1f895c6fe | 631 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 632 | { |
| mbed_official | 340:28d1f895c6fe | 633 | /* set fiforxthresold according the reception data lenght: 16bit */ |
| mbed_official | 340:28d1f895c6fe | 634 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 635 | } |
| mbed_official | 340:28d1f895c6fe | 636 | else |
| mbed_official | 340:28d1f895c6fe | 637 | { |
| mbed_official | 340:28d1f895c6fe | 638 | /* set fiforxthresold according the reception data lenght: 8bit */ |
| mbed_official | 340:28d1f895c6fe | 639 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 640 | } |
| mbed_official | 340:28d1f895c6fe | 641 | |
| mbed_official | 340:28d1f895c6fe | 642 | /* Configure communication direction 1Line and enabled SPI if needed */ |
| mbed_official | 340:28d1f895c6fe | 643 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 340:28d1f895c6fe | 644 | { |
| mbed_official | 340:28d1f895c6fe | 645 | __HAL_SPI_1LINE_RX(hspi); |
| mbed_official | 340:28d1f895c6fe | 646 | } |
| mbed_official | 340:28d1f895c6fe | 647 | |
| mbed_official | 441:d2c15dda23c1 | 648 | /* Check if the SPI is already enabled */ |
| mbed_official | 340:28d1f895c6fe | 649 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 650 | { |
| mbed_official | 441:d2c15dda23c1 | 651 | /* Enable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 652 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 653 | } |
| mbed_official | 340:28d1f895c6fe | 654 | |
| mbed_official | 340:28d1f895c6fe | 655 | if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 656 | { |
| mbed_official | 441:d2c15dda23c1 | 657 | /* Transfert loop */ |
| mbed_official | 441:d2c15dda23c1 | 658 | while(hspi->RxXferCount > 0) |
| mbed_official | 340:28d1f895c6fe | 659 | { |
| mbed_official | 441:d2c15dda23c1 | 660 | /* Check the RXNE flag */ |
| mbed_official | 441:d2c15dda23c1 | 661 | if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) |
| mbed_official | 340:28d1f895c6fe | 662 | { |
| mbed_official | 441:d2c15dda23c1 | 663 | /* read the received data */ |
| mbed_official | 441:d2c15dda23c1 | 664 | (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 665 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 666 | } |
| mbed_official | 441:d2c15dda23c1 | 667 | else |
| mbed_official | 441:d2c15dda23c1 | 668 | { |
| mbed_official | 441:d2c15dda23c1 | 669 | /* Timeout manamgement */ |
| mbed_official | 441:d2c15dda23c1 | 670 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
| mbed_official | 441:d2c15dda23c1 | 671 | { |
| mbed_official | 441:d2c15dda23c1 | 672 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 673 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 674 | } |
| mbed_official | 441:d2c15dda23c1 | 675 | } |
| mbed_official | 340:28d1f895c6fe | 676 | } |
| mbed_official | 340:28d1f895c6fe | 677 | } |
| mbed_official | 441:d2c15dda23c1 | 678 | else |
| mbed_official | 441:d2c15dda23c1 | 679 | { |
| mbed_official | 441:d2c15dda23c1 | 680 | /* Transfert loop */ |
| mbed_official | 441:d2c15dda23c1 | 681 | while(hspi->RxXferCount > 0) |
| mbed_official | 340:28d1f895c6fe | 682 | { |
| mbed_official | 441:d2c15dda23c1 | 683 | /* Check the RXNE flag */ |
| mbed_official | 441:d2c15dda23c1 | 684 | if((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE) |
| mbed_official | 340:28d1f895c6fe | 685 | { |
| mbed_official | 441:d2c15dda23c1 | 686 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 687 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 441:d2c15dda23c1 | 688 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 689 | } |
| mbed_official | 441:d2c15dda23c1 | 690 | else |
| mbed_official | 441:d2c15dda23c1 | 691 | { |
| mbed_official | 441:d2c15dda23c1 | 692 | /* Timeout mamangement */ |
| mbed_official | 441:d2c15dda23c1 | 693 | if((Timeout == 0) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) |
| mbed_official | 441:d2c15dda23c1 | 694 | { |
| mbed_official | 441:d2c15dda23c1 | 695 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 696 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 697 | } |
| mbed_official | 441:d2c15dda23c1 | 698 | } |
| mbed_official | 441:d2c15dda23c1 | 699 | } |
| mbed_official | 340:28d1f895c6fe | 700 | } |
| mbed_official | 340:28d1f895c6fe | 701 | |
| mbed_official | 441:d2c15dda23c1 | 702 | /* Handle the CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 703 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 704 | { |
| mbed_official | 441:d2c15dda23c1 | 705 | /* freeze the CRC before the latest data */ |
| mbed_official | 441:d2c15dda23c1 | 706 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
| mbed_official | 441:d2c15dda23c1 | 707 | |
| mbed_official | 441:d2c15dda23c1 | 708 | /* Read the latest data */ |
| mbed_official | 441:d2c15dda23c1 | 709 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 710 | { |
| mbed_official | 441:d2c15dda23c1 | 711 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 712 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 713 | } |
| mbed_official | 441:d2c15dda23c1 | 714 | |
| mbed_official | 441:d2c15dda23c1 | 715 | /* Receive last data in 16 Bit mode */ |
| mbed_official | 441:d2c15dda23c1 | 716 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 717 | { |
| mbed_official | 441:d2c15dda23c1 | 718 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 719 | } |
| mbed_official | 441:d2c15dda23c1 | 720 | /* Receive last data in 8 Bit mode */ |
| mbed_official | 441:d2c15dda23c1 | 721 | else |
| mbed_official | 441:d2c15dda23c1 | 722 | { |
| mbed_official | 441:d2c15dda23c1 | 723 | *hspi->pRxBuffPtr = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 724 | } |
| mbed_official | 441:d2c15dda23c1 | 725 | |
| mbed_official | 441:d2c15dda23c1 | 726 | /* Wait until TXE flag */ |
| mbed_official | 441:d2c15dda23c1 | 727 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 728 | { |
| mbed_official | 441:d2c15dda23c1 | 729 | /* Flag Error*/ |
| mbed_official | 441:d2c15dda23c1 | 730 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
| mbed_official | 441:d2c15dda23c1 | 731 | } |
| mbed_official | 441:d2c15dda23c1 | 732 | |
| mbed_official | 441:d2c15dda23c1 | 733 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
| mbed_official | 441:d2c15dda23c1 | 734 | { |
| mbed_official | 340:28d1f895c6fe | 735 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 736 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 737 | } |
| mbed_official | 340:28d1f895c6fe | 738 | else |
| mbed_official | 340:28d1f895c6fe | 739 | { |
| mbed_official | 340:28d1f895c6fe | 740 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 741 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 742 | if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
| mbed_official | 340:28d1f895c6fe | 743 | { |
| mbed_official | 340:28d1f895c6fe | 744 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
| mbed_official | 340:28d1f895c6fe | 745 | { |
| mbed_official | 340:28d1f895c6fe | 746 | /* Erreur on the CRC reception */ |
| mbed_official | 441:d2c15dda23c1 | 747 | hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; |
| mbed_official | 340:28d1f895c6fe | 748 | } |
| mbed_official | 340:28d1f895c6fe | 749 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 750 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 751 | } |
| mbed_official | 340:28d1f895c6fe | 752 | } |
| mbed_official | 340:28d1f895c6fe | 753 | } |
| mbed_official | 340:28d1f895c6fe | 754 | |
| mbed_official | 340:28d1f895c6fe | 755 | /* Check the end of the transaction */ |
| mbed_official | 340:28d1f895c6fe | 756 | if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK) |
| mbed_official | 340:28d1f895c6fe | 757 | { |
| mbed_official | 441:d2c15dda23c1 | 758 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 759 | goto error; |
| mbed_official | 340:28d1f895c6fe | 760 | } |
| mbed_official | 441:d2c15dda23c1 | 761 | |
| mbed_official | 340:28d1f895c6fe | 762 | /* Check if CRC error occurred */ |
| mbed_official | 340:28d1f895c6fe | 763 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 340:28d1f895c6fe | 764 | { |
| mbed_official | 340:28d1f895c6fe | 765 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 766 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 767 | } |
| mbed_official | 441:d2c15dda23c1 | 768 | |
| mbed_official | 441:d2c15dda23c1 | 769 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 441:d2c15dda23c1 | 770 | { |
| mbed_official | 441:d2c15dda23c1 | 771 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 772 | } |
| mbed_official | 340:28d1f895c6fe | 773 | |
| mbed_official | 441:d2c15dda23c1 | 774 | error : |
| mbed_official | 441:d2c15dda23c1 | 775 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 776 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 777 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 778 | } |
| mbed_official | 340:28d1f895c6fe | 779 | |
| mbed_official | 340:28d1f895c6fe | 780 | /** |
| mbed_official | 340:28d1f895c6fe | 781 | * @brief Transmit and Receive an amount of data in blocking mode |
| mbed_official | 441:d2c15dda23c1 | 782 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 783 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 784 | * @param pTxData : pointer to transmission data buffer |
| mbed_official | 441:d2c15dda23c1 | 785 | * @param pRxData : pointer to reception data buffer to be |
| mbed_official | 441:d2c15dda23c1 | 786 | * @param Size : amount of data to be sent |
| mbed_official | 441:d2c15dda23c1 | 787 | * @param Timeout : Timeout duration |
| mbed_official | 340:28d1f895c6fe | 788 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 789 | */ |
| mbed_official | 340:28d1f895c6fe | 790 | HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 791 | { |
| mbed_official | 441:d2c15dda23c1 | 792 | __IO uint16_t tmpreg; |
| mbed_official | 441:d2c15dda23c1 | 793 | uint32_t tickstart = HAL_GetTick(); |
| mbed_official | 441:d2c15dda23c1 | 794 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 795 | |
| mbed_official | 340:28d1f895c6fe | 796 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
| mbed_official | 441:d2c15dda23c1 | 797 | assert_param(pTxData != NULL); |
| mbed_official | 441:d2c15dda23c1 | 798 | |
| mbed_official | 441:d2c15dda23c1 | 799 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 800 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 801 | |
| mbed_official | 441:d2c15dda23c1 | 802 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 340:28d1f895c6fe | 803 | { |
| mbed_official | 441:d2c15dda23c1 | 804 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 805 | goto error; |
| mbed_official | 340:28d1f895c6fe | 806 | } |
| mbed_official | 340:28d1f895c6fe | 807 | |
| mbed_official | 441:d2c15dda23c1 | 808 | if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) |
| mbed_official | 340:28d1f895c6fe | 809 | { |
| mbed_official | 441:d2c15dda23c1 | 810 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 811 | goto error; |
| mbed_official | 340:28d1f895c6fe | 812 | } |
| mbed_official | 340:28d1f895c6fe | 813 | |
| mbed_official | 340:28d1f895c6fe | 814 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
| mbed_official | 340:28d1f895c6fe | 815 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 816 | hspi->pRxBuffPtr = pRxData; |
| mbed_official | 340:28d1f895c6fe | 817 | hspi->RxXferCount = Size; |
| mbed_official | 340:28d1f895c6fe | 818 | hspi->RxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 819 | hspi->pTxBuffPtr = pTxData; |
| mbed_official | 340:28d1f895c6fe | 820 | hspi->TxXferCount = Size; |
| mbed_official | 340:28d1f895c6fe | 821 | hspi->TxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 822 | |
| mbed_official | 340:28d1f895c6fe | 823 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 824 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 825 | { |
| mbed_official | 340:28d1f895c6fe | 826 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 827 | } |
| mbed_official | 340:28d1f895c6fe | 828 | |
| mbed_official | 340:28d1f895c6fe | 829 | /* Set the Rx Fido threshold */ |
| mbed_official | 340:28d1f895c6fe | 830 | if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1)) |
| mbed_official | 340:28d1f895c6fe | 831 | { |
| mbed_official | 340:28d1f895c6fe | 832 | /* set fiforxthreshold according the reception data lenght: 16bit */ |
| mbed_official | 340:28d1f895c6fe | 833 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 834 | } |
| mbed_official | 340:28d1f895c6fe | 835 | else |
| mbed_official | 340:28d1f895c6fe | 836 | { |
| mbed_official | 340:28d1f895c6fe | 837 | /* set fiforxthreshold according the reception data lenght: 8bit */ |
| mbed_official | 340:28d1f895c6fe | 838 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 839 | } |
| mbed_official | 340:28d1f895c6fe | 840 | |
| mbed_official | 340:28d1f895c6fe | 841 | /* Check if the SPI is already enabled */ |
| mbed_official | 340:28d1f895c6fe | 842 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 843 | { |
| mbed_official | 340:28d1f895c6fe | 844 | /* Enable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 845 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 846 | } |
| mbed_official | 340:28d1f895c6fe | 847 | |
| mbed_official | 340:28d1f895c6fe | 848 | /* Transmit and Receive data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 849 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 850 | { |
| mbed_official | 340:28d1f895c6fe | 851 | while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0)) |
| mbed_official | 340:28d1f895c6fe | 852 | { |
| mbed_official | 441:d2c15dda23c1 | 853 | /* Check TXE flag */ |
| mbed_official | 340:28d1f895c6fe | 854 | if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) |
| mbed_official | 340:28d1f895c6fe | 855 | { |
| mbed_official | 340:28d1f895c6fe | 856 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
| mbed_official | 340:28d1f895c6fe | 857 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 858 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 859 | |
| mbed_official | 340:28d1f895c6fe | 860 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 861 | if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 862 | { |
| mbed_official | 441:d2c15dda23c1 | 863 | hspi->Instance->CR1|= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 864 | } |
| mbed_official | 340:28d1f895c6fe | 865 | } |
| mbed_official | 340:28d1f895c6fe | 866 | |
| mbed_official | 441:d2c15dda23c1 | 867 | /* Check RXNE flag */ |
| mbed_official | 340:28d1f895c6fe | 868 | if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) |
| mbed_official | 340:28d1f895c6fe | 869 | { |
| mbed_official | 340:28d1f895c6fe | 870 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 871 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 872 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 873 | } |
| mbed_official | 441:d2c15dda23c1 | 874 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
| mbed_official | 340:28d1f895c6fe | 875 | { |
| mbed_official | 441:d2c15dda23c1 | 876 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 877 | goto error; |
| mbed_official | 340:28d1f895c6fe | 878 | } |
| mbed_official | 340:28d1f895c6fe | 879 | } |
| mbed_official | 340:28d1f895c6fe | 880 | } |
| mbed_official | 340:28d1f895c6fe | 881 | /* Transmit and Receive data in 8 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 882 | else |
| mbed_official | 340:28d1f895c6fe | 883 | { |
| mbed_official | 340:28d1f895c6fe | 884 | while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0)) |
| mbed_official | 340:28d1f895c6fe | 885 | { |
| mbed_official | 441:d2c15dda23c1 | 886 | /* check TXE flag */ |
| mbed_official | 340:28d1f895c6fe | 887 | if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE)) |
| mbed_official | 340:28d1f895c6fe | 888 | { |
| mbed_official | 441:d2c15dda23c1 | 889 | if(hspi->TxXferCount > 1) |
| mbed_official | 340:28d1f895c6fe | 890 | { |
| mbed_official | 340:28d1f895c6fe | 891 | hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); |
| mbed_official | 340:28d1f895c6fe | 892 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 893 | hspi->TxXferCount -= 2; |
| mbed_official | 340:28d1f895c6fe | 894 | } |
| mbed_official | 340:28d1f895c6fe | 895 | else |
| mbed_official | 340:28d1f895c6fe | 896 | { |
| mbed_official | 340:28d1f895c6fe | 897 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
| mbed_official | 340:28d1f895c6fe | 898 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 899 | } |
| mbed_official | 340:28d1f895c6fe | 900 | |
| mbed_official | 340:28d1f895c6fe | 901 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 902 | if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 903 | { |
| mbed_official | 441:d2c15dda23c1 | 904 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 905 | } |
| mbed_official | 340:28d1f895c6fe | 906 | } |
| mbed_official | 340:28d1f895c6fe | 907 | |
| mbed_official | 340:28d1f895c6fe | 908 | /* Wait until RXNE flag is reset */ |
| mbed_official | 340:28d1f895c6fe | 909 | if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE)) |
| mbed_official | 340:28d1f895c6fe | 910 | { |
| mbed_official | 340:28d1f895c6fe | 911 | if(hspi->RxXferCount > 1) |
| mbed_official | 340:28d1f895c6fe | 912 | { |
| mbed_official | 340:28d1f895c6fe | 913 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 914 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 915 | hspi->RxXferCount -= 2; |
| mbed_official | 340:28d1f895c6fe | 916 | if(hspi->RxXferCount <= 1) |
| mbed_official | 340:28d1f895c6fe | 917 | { |
| mbed_official | 340:28d1f895c6fe | 918 | /* set fiforxthresold before to switch on 8 bit data size */ |
| mbed_official | 340:28d1f895c6fe | 919 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 920 | } |
| mbed_official | 340:28d1f895c6fe | 921 | } |
| mbed_official | 340:28d1f895c6fe | 922 | else |
| mbed_official | 340:28d1f895c6fe | 923 | { |
| mbed_official | 340:28d1f895c6fe | 924 | (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 925 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 926 | } |
| mbed_official | 340:28d1f895c6fe | 927 | } |
| mbed_official | 441:d2c15dda23c1 | 928 | if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) |
| mbed_official | 340:28d1f895c6fe | 929 | { |
| mbed_official | 441:d2c15dda23c1 | 930 | errorcode = HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 931 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 932 | } |
| mbed_official | 340:28d1f895c6fe | 933 | } |
| mbed_official | 340:28d1f895c6fe | 934 | } |
| mbed_official | 340:28d1f895c6fe | 935 | |
| mbed_official | 340:28d1f895c6fe | 936 | /* Read CRC from DR to close CRC calculation process */ |
| mbed_official | 340:28d1f895c6fe | 937 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 938 | { |
| mbed_official | 340:28d1f895c6fe | 939 | /* Wait until TXE flag */ |
| mbed_official | 340:28d1f895c6fe | 940 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
| mbed_official | 340:28d1f895c6fe | 941 | { |
| mbed_official | 340:28d1f895c6fe | 942 | /* Erreur on the CRC reception */ |
| mbed_official | 340:28d1f895c6fe | 943 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 944 | } |
| mbed_official | 340:28d1f895c6fe | 945 | |
| mbed_official | 340:28d1f895c6fe | 946 | if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) |
| mbed_official | 340:28d1f895c6fe | 947 | { |
| mbed_official | 340:28d1f895c6fe | 948 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 949 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 950 | } |
| mbed_official | 340:28d1f895c6fe | 951 | else |
| mbed_official | 340:28d1f895c6fe | 952 | { |
| mbed_official | 340:28d1f895c6fe | 953 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 954 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 955 | if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
| mbed_official | 340:28d1f895c6fe | 956 | { |
| mbed_official | 340:28d1f895c6fe | 957 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) |
| mbed_official | 340:28d1f895c6fe | 958 | { |
| mbed_official | 340:28d1f895c6fe | 959 | /* Erreur on the CRC reception */ |
| mbed_official | 340:28d1f895c6fe | 960 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 961 | } |
| mbed_official | 340:28d1f895c6fe | 962 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 963 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 964 | } |
| mbed_official | 340:28d1f895c6fe | 965 | } |
| mbed_official | 340:28d1f895c6fe | 966 | } |
| mbed_official | 340:28d1f895c6fe | 967 | |
| mbed_official | 340:28d1f895c6fe | 968 | /* Check if CRC error occurred */ |
| mbed_official | 340:28d1f895c6fe | 969 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 340:28d1f895c6fe | 970 | { |
| mbed_official | 340:28d1f895c6fe | 971 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 972 | /* Clear CRC Flag */ |
| mbed_official | 340:28d1f895c6fe | 973 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 974 | |
| mbed_official | 441:d2c15dda23c1 | 975 | errorcode = HAL_ERROR; |
| mbed_official | 340:28d1f895c6fe | 976 | } |
| mbed_official | 340:28d1f895c6fe | 977 | |
| mbed_official | 340:28d1f895c6fe | 978 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 979 | { |
| mbed_official | 441:d2c15dda23c1 | 980 | errorcode = HAL_ERROR; |
| mbed_official | 340:28d1f895c6fe | 981 | } |
| mbed_official | 441:d2c15dda23c1 | 982 | |
| mbed_official | 441:d2c15dda23c1 | 983 | error : |
| mbed_official | 441:d2c15dda23c1 | 984 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 985 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 986 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 987 | } |
| mbed_official | 340:28d1f895c6fe | 988 | |
| mbed_official | 340:28d1f895c6fe | 989 | /** |
| mbed_official | 340:28d1f895c6fe | 990 | * @brief Transmit an amount of data in no-blocking mode with Interrupt |
| mbed_official | 441:d2c15dda23c1 | 991 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 992 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 993 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 994 | * @param Size : amount of data to be sent |
| mbed_official | 340:28d1f895c6fe | 995 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 996 | */ |
| mbed_official | 340:28d1f895c6fe | 997 | HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 998 | { |
| mbed_official | 441:d2c15dda23c1 | 999 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1000 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
| mbed_official | 340:28d1f895c6fe | 1001 | |
| mbed_official | 441:d2c15dda23c1 | 1002 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 1003 | __HAL_LOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 1004 | |
| mbed_official | 441:d2c15dda23c1 | 1005 | if((pData == NULL) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 1006 | { |
| mbed_official | 441:d2c15dda23c1 | 1007 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1008 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1009 | } |
| mbed_official | 441:d2c15dda23c1 | 1010 | |
| mbed_official | 441:d2c15dda23c1 | 1011 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 441:d2c15dda23c1 | 1012 | { |
| mbed_official | 441:d2c15dda23c1 | 1013 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1014 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1015 | } |
| mbed_official | 441:d2c15dda23c1 | 1016 | |
| mbed_official | 441:d2c15dda23c1 | 1017 | /* prepore the transfer */ |
| mbed_official | 441:d2c15dda23c1 | 1018 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
| mbed_official | 441:d2c15dda23c1 | 1019 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 441:d2c15dda23c1 | 1020 | hspi->pTxBuffPtr = pData; |
| mbed_official | 441:d2c15dda23c1 | 1021 | hspi->TxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1022 | hspi->TxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1023 | hspi->pRxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 441:d2c15dda23c1 | 1024 | hspi->RxXferSize = 0; |
| mbed_official | 441:d2c15dda23c1 | 1025 | hspi->RxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 1026 | hspi->RxISR = (void (*)(SPI_HandleTypeDef *))NULL; |
| mbed_official | 441:d2c15dda23c1 | 1027 | |
| mbed_official | 441:d2c15dda23c1 | 1028 | /* Set the function for IT treatement */ |
| mbed_official | 441:d2c15dda23c1 | 1029 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
| mbed_official | 441:d2c15dda23c1 | 1030 | { |
| mbed_official | 441:d2c15dda23c1 | 1031 | hspi->TxISR = SPI_TxISR_16BIT; |
| mbed_official | 340:28d1f895c6fe | 1032 | } |
| mbed_official | 340:28d1f895c6fe | 1033 | else |
| mbed_official | 340:28d1f895c6fe | 1034 | { |
| mbed_official | 441:d2c15dda23c1 | 1035 | hspi->TxISR = SPI_TxISR_8BIT; |
| mbed_official | 441:d2c15dda23c1 | 1036 | } |
| mbed_official | 441:d2c15dda23c1 | 1037 | |
| mbed_official | 441:d2c15dda23c1 | 1038 | /* Configure communication direction : 1Line */ |
| mbed_official | 441:d2c15dda23c1 | 1039 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 441:d2c15dda23c1 | 1040 | { |
| mbed_official | 441:d2c15dda23c1 | 1041 | __HAL_SPI_1LINE_TX(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1042 | } |
| mbed_official | 441:d2c15dda23c1 | 1043 | |
| mbed_official | 441:d2c15dda23c1 | 1044 | /* Reset CRC Calculation */ |
| mbed_official | 441:d2c15dda23c1 | 1045 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1046 | { |
| mbed_official | 441:d2c15dda23c1 | 1047 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 1048 | } |
| mbed_official | 441:d2c15dda23c1 | 1049 | |
| mbed_official | 441:d2c15dda23c1 | 1050 | /* Enable TXE and ERR interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 1051 | __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE)); |
| mbed_official | 441:d2c15dda23c1 | 1052 | |
| mbed_official | 441:d2c15dda23c1 | 1053 | |
| mbed_official | 441:d2c15dda23c1 | 1054 | /* Check if the SPI is already enabled */ |
| mbed_official | 441:d2c15dda23c1 | 1055 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 441:d2c15dda23c1 | 1056 | { |
| mbed_official | 441:d2c15dda23c1 | 1057 | /* Enable SPI peripheral */ |
| mbed_official | 441:d2c15dda23c1 | 1058 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1059 | } |
| mbed_official | 441:d2c15dda23c1 | 1060 | |
| mbed_official | 441:d2c15dda23c1 | 1061 | error : |
| mbed_official | 441:d2c15dda23c1 | 1062 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1063 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 1064 | } |
| mbed_official | 340:28d1f895c6fe | 1065 | |
| mbed_official | 340:28d1f895c6fe | 1066 | /** |
| mbed_official | 340:28d1f895c6fe | 1067 | * @brief Receive an amount of data in no-blocking mode with Interrupt |
| mbed_official | 441:d2c15dda23c1 | 1068 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1069 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1070 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 1071 | * @param Size : amount of data to be sent |
| mbed_official | 340:28d1f895c6fe | 1072 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 1073 | */ |
| mbed_official | 340:28d1f895c6fe | 1074 | HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 1075 | { |
| mbed_official | 441:d2c15dda23c1 | 1076 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 441:d2c15dda23c1 | 1077 | |
| mbed_official | 441:d2c15dda23c1 | 1078 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 1079 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1080 | |
| mbed_official | 441:d2c15dda23c1 | 1081 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 340:28d1f895c6fe | 1082 | { |
| mbed_official | 441:d2c15dda23c1 | 1083 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1084 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1085 | } |
| mbed_official | 441:d2c15dda23c1 | 1086 | if((pData == NULL) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 1087 | { |
| mbed_official | 441:d2c15dda23c1 | 1088 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1089 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1090 | } |
| mbed_official | 441:d2c15dda23c1 | 1091 | |
| mbed_official | 441:d2c15dda23c1 | 1092 | /* Configure communication */ |
| mbed_official | 441:d2c15dda23c1 | 1093 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
| mbed_official | 441:d2c15dda23c1 | 1094 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 441:d2c15dda23c1 | 1095 | hspi->pRxBuffPtr = pData; |
| mbed_official | 441:d2c15dda23c1 | 1096 | hspi->RxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1097 | hspi->RxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1098 | hspi->pTxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 441:d2c15dda23c1 | 1099 | hspi->TxXferSize = 0; |
| mbed_official | 441:d2c15dda23c1 | 1100 | hspi->TxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 1101 | |
| mbed_official | 441:d2c15dda23c1 | 1102 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
| mbed_official | 441:d2c15dda23c1 | 1103 | { |
| mbed_official | 340:28d1f895c6fe | 1104 | /* Process Unlocked */ |
| mbed_official | 340:28d1f895c6fe | 1105 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1106 | /* the receive process is not supported in 2Lines direction master mode */ |
| mbed_official | 441:d2c15dda23c1 | 1107 | /* in this we call the transmitReceive process */ |
| mbed_official | 441:d2c15dda23c1 | 1108 | return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size); |
| mbed_official | 441:d2c15dda23c1 | 1109 | } |
| mbed_official | 441:d2c15dda23c1 | 1110 | |
| mbed_official | 441:d2c15dda23c1 | 1111 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1112 | { |
| mbed_official | 441:d2c15dda23c1 | 1113 | hspi->CRCSize = 1; |
| mbed_official | 441:d2c15dda23c1 | 1114 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
| mbed_official | 340:28d1f895c6fe | 1115 | { |
| mbed_official | 441:d2c15dda23c1 | 1116 | hspi->CRCSize = 2; |
| mbed_official | 340:28d1f895c6fe | 1117 | } |
| mbed_official | 340:28d1f895c6fe | 1118 | } |
| mbed_official | 340:28d1f895c6fe | 1119 | else |
| mbed_official | 340:28d1f895c6fe | 1120 | { |
| mbed_official | 441:d2c15dda23c1 | 1121 | hspi->CRCSize = 0; |
| mbed_official | 441:d2c15dda23c1 | 1122 | } |
| mbed_official | 441:d2c15dda23c1 | 1123 | |
| mbed_official | 441:d2c15dda23c1 | 1124 | hspi->TxISR = (void (*)(SPI_HandleTypeDef *))NULL; |
| mbed_official | 441:d2c15dda23c1 | 1125 | /* check the data size to adapt Rx threshold and the set the function for IT treatement */ |
| mbed_official | 441:d2c15dda23c1 | 1126 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
| mbed_official | 441:d2c15dda23c1 | 1127 | { |
| mbed_official | 441:d2c15dda23c1 | 1128 | /* set fiforxthresold according the reception data lenght: 16 bit */ |
| mbed_official | 441:d2c15dda23c1 | 1129 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 441:d2c15dda23c1 | 1130 | hspi->RxISR = SPI_RxISR_16BIT; |
| mbed_official | 441:d2c15dda23c1 | 1131 | } |
| mbed_official | 441:d2c15dda23c1 | 1132 | else |
| mbed_official | 441:d2c15dda23c1 | 1133 | { |
| mbed_official | 441:d2c15dda23c1 | 1134 | /* set fiforxthresold according the reception data lenght: 8 bit */ |
| mbed_official | 441:d2c15dda23c1 | 1135 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 441:d2c15dda23c1 | 1136 | hspi->RxISR = SPI_RxISR_8BIT; |
| mbed_official | 340:28d1f895c6fe | 1137 | } |
| mbed_official | 441:d2c15dda23c1 | 1138 | |
| mbed_official | 441:d2c15dda23c1 | 1139 | /* Configure communication direction : 1Line */ |
| mbed_official | 441:d2c15dda23c1 | 1140 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 441:d2c15dda23c1 | 1141 | { |
| mbed_official | 441:d2c15dda23c1 | 1142 | __HAL_SPI_1LINE_RX(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1143 | } |
| mbed_official | 441:d2c15dda23c1 | 1144 | |
| mbed_official | 441:d2c15dda23c1 | 1145 | /* Reset CRC Calculation */ |
| mbed_official | 441:d2c15dda23c1 | 1146 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1147 | { |
| mbed_official | 441:d2c15dda23c1 | 1148 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1149 | } |
| mbed_official | 441:d2c15dda23c1 | 1150 | |
| mbed_official | 441:d2c15dda23c1 | 1151 | /* Enable TXE and ERR interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 1152 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 441:d2c15dda23c1 | 1153 | |
| mbed_official | 441:d2c15dda23c1 | 1154 | /* Check if the SPI is already enabled */ |
| mbed_official | 441:d2c15dda23c1 | 1155 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 441:d2c15dda23c1 | 1156 | { |
| mbed_official | 441:d2c15dda23c1 | 1157 | /* Enable SPI peripheral */ |
| mbed_official | 441:d2c15dda23c1 | 1158 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1159 | } |
| mbed_official | 441:d2c15dda23c1 | 1160 | |
| mbed_official | 441:d2c15dda23c1 | 1161 | error : |
| mbed_official | 441:d2c15dda23c1 | 1162 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1163 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1164 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 1165 | } |
| mbed_official | 340:28d1f895c6fe | 1166 | |
| mbed_official | 340:28d1f895c6fe | 1167 | /** |
| mbed_official | 340:28d1f895c6fe | 1168 | * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt |
| mbed_official | 441:d2c15dda23c1 | 1169 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1170 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1171 | * @param pTxData : pointer to transmission data buffer |
| mbed_official | 441:d2c15dda23c1 | 1172 | * @param pRxData : pointer to reception data buffer to be |
| mbed_official | 441:d2c15dda23c1 | 1173 | * @param Size : amount of data to be sent |
| mbed_official | 340:28d1f895c6fe | 1174 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 1175 | */ |
| mbed_official | 340:28d1f895c6fe | 1176 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 1177 | { |
| mbed_official | 441:d2c15dda23c1 | 1178 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1179 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
| mbed_official | 340:28d1f895c6fe | 1180 | |
| mbed_official | 441:d2c15dda23c1 | 1181 | /* Process locked */ |
| mbed_official | 441:d2c15dda23c1 | 1182 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1183 | |
| mbed_official | 441:d2c15dda23c1 | 1184 | if(!((hspi->State == HAL_SPI_STATE_READY) || \ |
| mbed_official | 441:d2c15dda23c1 | 1185 | ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) |
| mbed_official | 340:28d1f895c6fe | 1186 | { |
| mbed_official | 441:d2c15dda23c1 | 1187 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1188 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1189 | } |
| mbed_official | 441:d2c15dda23c1 | 1190 | |
| mbed_official | 441:d2c15dda23c1 | 1191 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 1192 | { |
| mbed_official | 441:d2c15dda23c1 | 1193 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1194 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1195 | } |
| mbed_official | 441:d2c15dda23c1 | 1196 | |
| mbed_official | 441:d2c15dda23c1 | 1197 | hspi->CRCSize = 0; |
| mbed_official | 441:d2c15dda23c1 | 1198 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1199 | { |
| mbed_official | 441:d2c15dda23c1 | 1200 | hspi->CRCSize = 1; |
| mbed_official | 441:d2c15dda23c1 | 1201 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) |
| mbed_official | 340:28d1f895c6fe | 1202 | { |
| mbed_official | 441:d2c15dda23c1 | 1203 | hspi->CRCSize = 2; |
| mbed_official | 340:28d1f895c6fe | 1204 | } |
| mbed_official | 441:d2c15dda23c1 | 1205 | } |
| mbed_official | 441:d2c15dda23c1 | 1206 | |
| mbed_official | 441:d2c15dda23c1 | 1207 | if(hspi->State != HAL_SPI_STATE_BUSY_RX) |
| mbed_official | 441:d2c15dda23c1 | 1208 | { |
| mbed_official | 441:d2c15dda23c1 | 1209 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
| mbed_official | 441:d2c15dda23c1 | 1210 | } |
| mbed_official | 441:d2c15dda23c1 | 1211 | |
| mbed_official | 441:d2c15dda23c1 | 1212 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 441:d2c15dda23c1 | 1213 | hspi->pTxBuffPtr = pTxData; |
| mbed_official | 441:d2c15dda23c1 | 1214 | hspi->TxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1215 | hspi->TxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1216 | hspi->pRxBuffPtr = pRxData; |
| mbed_official | 441:d2c15dda23c1 | 1217 | hspi->RxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1218 | hspi->RxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1219 | |
| mbed_official | 441:d2c15dda23c1 | 1220 | /* Set the function for IT treatement */ |
| mbed_official | 441:d2c15dda23c1 | 1221 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) |
| mbed_official | 441:d2c15dda23c1 | 1222 | { |
| mbed_official | 441:d2c15dda23c1 | 1223 | hspi->RxISR = SPI_2linesRxISR_16BIT; |
| mbed_official | 441:d2c15dda23c1 | 1224 | hspi->TxISR = SPI_2linesTxISR_16BIT; |
| mbed_official | 340:28d1f895c6fe | 1225 | } |
| mbed_official | 340:28d1f895c6fe | 1226 | else |
| mbed_official | 340:28d1f895c6fe | 1227 | { |
| mbed_official | 441:d2c15dda23c1 | 1228 | hspi->RxISR = SPI_2linesRxISR_8BIT; |
| mbed_official | 441:d2c15dda23c1 | 1229 | hspi->TxISR = SPI_2linesTxISR_8BIT; |
| mbed_official | 441:d2c15dda23c1 | 1230 | } |
| mbed_official | 441:d2c15dda23c1 | 1231 | |
| mbed_official | 441:d2c15dda23c1 | 1232 | /* Reset CRC Calculation */ |
| mbed_official | 441:d2c15dda23c1 | 1233 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1234 | { |
| mbed_official | 441:d2c15dda23c1 | 1235 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1236 | } |
| mbed_official | 441:d2c15dda23c1 | 1237 | |
| mbed_official | 441:d2c15dda23c1 | 1238 | /* check if packing mode is enabled and if there is more than 2 data to receive */ |
| mbed_official | 441:d2c15dda23c1 | 1239 | if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) |
| mbed_official | 441:d2c15dda23c1 | 1240 | { |
| mbed_official | 441:d2c15dda23c1 | 1241 | /* set fiforxthresold according the reception data lenght: 16 bit */ |
| mbed_official | 441:d2c15dda23c1 | 1242 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 1243 | } |
| mbed_official | 441:d2c15dda23c1 | 1244 | else |
| mbed_official | 441:d2c15dda23c1 | 1245 | { |
| mbed_official | 441:d2c15dda23c1 | 1246 | /* set fiforxthresold according the reception data lenght: 8 bit */ |
| mbed_official | 441:d2c15dda23c1 | 1247 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 441:d2c15dda23c1 | 1248 | } |
| mbed_official | 441:d2c15dda23c1 | 1249 | |
| mbed_official | 441:d2c15dda23c1 | 1250 | /* Enable TXE, RXNE and ERR interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 1251 | __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 441:d2c15dda23c1 | 1252 | |
| mbed_official | 441:d2c15dda23c1 | 1253 | /* Check if the SPI is already enabled */ |
| mbed_official | 441:d2c15dda23c1 | 1254 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 441:d2c15dda23c1 | 1255 | { |
| mbed_official | 441:d2c15dda23c1 | 1256 | /* Enable SPI peripheral */ |
| mbed_official | 441:d2c15dda23c1 | 1257 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1258 | } |
| mbed_official | 441:d2c15dda23c1 | 1259 | |
| mbed_official | 441:d2c15dda23c1 | 1260 | error : |
| mbed_official | 441:d2c15dda23c1 | 1261 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1262 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1263 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 1264 | } |
| mbed_official | 340:28d1f895c6fe | 1265 | |
| mbed_official | 340:28d1f895c6fe | 1266 | /** |
| mbed_official | 340:28d1f895c6fe | 1267 | * @brief Transmit an amount of data in no-blocking mode with DMA |
| mbed_official | 441:d2c15dda23c1 | 1268 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1269 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1270 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 1271 | * @param Size : amount of data to be sent |
| mbed_official | 340:28d1f895c6fe | 1272 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 1273 | */ |
| mbed_official | 340:28d1f895c6fe | 1274 | HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 1275 | { |
| mbed_official | 441:d2c15dda23c1 | 1276 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1277 | assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); |
| mbed_official | 340:28d1f895c6fe | 1278 | |
| mbed_official | 340:28d1f895c6fe | 1279 | /* Process Locked */ |
| mbed_official | 340:28d1f895c6fe | 1280 | __HAL_LOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 1281 | |
| mbed_official | 441:d2c15dda23c1 | 1282 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 441:d2c15dda23c1 | 1283 | { |
| mbed_official | 441:d2c15dda23c1 | 1284 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1285 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1286 | } |
| mbed_official | 441:d2c15dda23c1 | 1287 | |
| mbed_official | 441:d2c15dda23c1 | 1288 | if((pData == NULL) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 1289 | { |
| mbed_official | 441:d2c15dda23c1 | 1290 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1291 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1292 | } |
| mbed_official | 441:d2c15dda23c1 | 1293 | |
| mbed_official | 340:28d1f895c6fe | 1294 | hspi->State = HAL_SPI_STATE_BUSY_TX; |
| mbed_official | 340:28d1f895c6fe | 1295 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 1296 | hspi->pTxBuffPtr = pData; |
| mbed_official | 340:28d1f895c6fe | 1297 | hspi->TxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 1298 | hspi->TxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1299 | hspi->pRxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 340:28d1f895c6fe | 1300 | hspi->RxXferSize = 0; |
| mbed_official | 340:28d1f895c6fe | 1301 | hspi->RxXferCount = 0; |
| mbed_official | 340:28d1f895c6fe | 1302 | |
| mbed_official | 340:28d1f895c6fe | 1303 | /* Configure communication direction : 1Line */ |
| mbed_official | 340:28d1f895c6fe | 1304 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 340:28d1f895c6fe | 1305 | { |
| mbed_official | 340:28d1f895c6fe | 1306 | __HAL_SPI_1LINE_TX(hspi); |
| mbed_official | 340:28d1f895c6fe | 1307 | } |
| mbed_official | 340:28d1f895c6fe | 1308 | |
| mbed_official | 340:28d1f895c6fe | 1309 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 1310 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 1311 | { |
| mbed_official | 340:28d1f895c6fe | 1312 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 1313 | } |
| mbed_official | 340:28d1f895c6fe | 1314 | |
| mbed_official | 441:d2c15dda23c1 | 1315 | /* Set the SPI TxDMA Half transfer complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1316 | hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; |
| mbed_official | 441:d2c15dda23c1 | 1317 | |
| mbed_official | 441:d2c15dda23c1 | 1318 | /* Set the SPI TxDMA transfert complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1319 | hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; |
| mbed_official | 340:28d1f895c6fe | 1320 | |
| mbed_official | 340:28d1f895c6fe | 1321 | /* Set the DMA error callback */ |
| mbed_official | 441:d2c15dda23c1 | 1322 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
| mbed_official | 340:28d1f895c6fe | 1323 | |
| mbed_official | 340:28d1f895c6fe | 1324 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
| mbed_official | 340:28d1f895c6fe | 1325 | /* packing mode is enabled only if the DMA setting is HALWORD */ |
| mbed_official | 340:28d1f895c6fe | 1326 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) |
| mbed_official | 340:28d1f895c6fe | 1327 | { |
| mbed_official | 340:28d1f895c6fe | 1328 | /* Check the even/odd of the data size + crc if enabled */ |
| mbed_official | 340:28d1f895c6fe | 1329 | if((hspi->TxXferCount & 0x1) == 0) |
| mbed_official | 340:28d1f895c6fe | 1330 | { |
| mbed_official | 340:28d1f895c6fe | 1331 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
| mbed_official | 340:28d1f895c6fe | 1332 | hspi->TxXferCount = (hspi->TxXferCount >> 1); |
| mbed_official | 340:28d1f895c6fe | 1333 | } |
| mbed_official | 340:28d1f895c6fe | 1334 | else |
| mbed_official | 340:28d1f895c6fe | 1335 | { |
| mbed_official | 340:28d1f895c6fe | 1336 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
| mbed_official | 340:28d1f895c6fe | 1337 | hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; |
| mbed_official | 340:28d1f895c6fe | 1338 | } |
| mbed_official | 340:28d1f895c6fe | 1339 | } |
| mbed_official | 340:28d1f895c6fe | 1340 | |
| mbed_official | 340:28d1f895c6fe | 1341 | /* Enable the Tx DMA channel */ |
| mbed_official | 340:28d1f895c6fe | 1342 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
| mbed_official | 340:28d1f895c6fe | 1343 | |
| mbed_official | 340:28d1f895c6fe | 1344 | /* Check if the SPI is already enabled */ |
| mbed_official | 340:28d1f895c6fe | 1345 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 1346 | { |
| mbed_official | 340:28d1f895c6fe | 1347 | /* Enable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 1348 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 1349 | } |
| mbed_official | 340:28d1f895c6fe | 1350 | |
| mbed_official | 340:28d1f895c6fe | 1351 | /* Enable Tx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 1352 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
| mbed_official | 340:28d1f895c6fe | 1353 | |
| mbed_official | 441:d2c15dda23c1 | 1354 | error : |
| mbed_official | 340:28d1f895c6fe | 1355 | /* Process Unlocked */ |
| mbed_official | 340:28d1f895c6fe | 1356 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1357 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 1358 | } |
| mbed_official | 340:28d1f895c6fe | 1359 | |
| mbed_official | 340:28d1f895c6fe | 1360 | /** |
| mbed_official | 441:d2c15dda23c1 | 1361 | * @brief Receive an amount of data in no-blocking mode with DMA |
| mbed_official | 441:d2c15dda23c1 | 1362 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1363 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1364 | * @param pData : pointer to data buffer |
| mbed_official | 441:d2c15dda23c1 | 1365 | * @param Size : amount of data to be sent |
| mbed_official | 441:d2c15dda23c1 | 1366 | * @retval HAL status |
| mbed_official | 441:d2c15dda23c1 | 1367 | */ |
| mbed_official | 340:28d1f895c6fe | 1368 | HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 1369 | { |
| mbed_official | 441:d2c15dda23c1 | 1370 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1371 | |
| mbed_official | 340:28d1f895c6fe | 1372 | /* Process Locked */ |
| mbed_official | 340:28d1f895c6fe | 1373 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1374 | |
| mbed_official | 441:d2c15dda23c1 | 1375 | if(hspi->State != HAL_SPI_STATE_READY) |
| mbed_official | 441:d2c15dda23c1 | 1376 | { |
| mbed_official | 441:d2c15dda23c1 | 1377 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1378 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1379 | } |
| mbed_official | 441:d2c15dda23c1 | 1380 | |
| mbed_official | 441:d2c15dda23c1 | 1381 | if((pData == NULL) || (Size == 0)) |
| mbed_official | 441:d2c15dda23c1 | 1382 | { |
| mbed_official | 441:d2c15dda23c1 | 1383 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1384 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1385 | } |
| mbed_official | 441:d2c15dda23c1 | 1386 | |
| mbed_official | 340:28d1f895c6fe | 1387 | hspi->State = HAL_SPI_STATE_BUSY_RX; |
| mbed_official | 340:28d1f895c6fe | 1388 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 340:28d1f895c6fe | 1389 | hspi->pRxBuffPtr = pData; |
| mbed_official | 340:28d1f895c6fe | 1390 | hspi->RxXferSize = Size; |
| mbed_official | 340:28d1f895c6fe | 1391 | hspi->RxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1392 | hspi->pTxBuffPtr = (uint8_t*)NULL; |
| mbed_official | 340:28d1f895c6fe | 1393 | hspi->TxXferSize = 0; |
| mbed_official | 340:28d1f895c6fe | 1394 | hspi->TxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 1395 | |
| mbed_official | 340:28d1f895c6fe | 1396 | if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) |
| mbed_official | 340:28d1f895c6fe | 1397 | { |
| mbed_official | 340:28d1f895c6fe | 1398 | /* Process Unlocked */ |
| mbed_official | 340:28d1f895c6fe | 1399 | __HAL_UNLOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 1400 | /* the receive process is not supported in 2Lines direction master mode */ |
| mbed_official | 340:28d1f895c6fe | 1401 | /* in this case we call the transmitReceive process */ |
| mbed_official | 340:28d1f895c6fe | 1402 | return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size); |
| mbed_official | 340:28d1f895c6fe | 1403 | } |
| mbed_official | 340:28d1f895c6fe | 1404 | |
| mbed_official | 340:28d1f895c6fe | 1405 | /* Configure communication direction : 1Line */ |
| mbed_official | 340:28d1f895c6fe | 1406 | if(hspi->Init.Direction == SPI_DIRECTION_1LINE) |
| mbed_official | 340:28d1f895c6fe | 1407 | { |
| mbed_official | 340:28d1f895c6fe | 1408 | __HAL_SPI_1LINE_RX(hspi); |
| mbed_official | 340:28d1f895c6fe | 1409 | } |
| mbed_official | 340:28d1f895c6fe | 1410 | |
| mbed_official | 340:28d1f895c6fe | 1411 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 1412 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 1413 | { |
| mbed_official | 340:28d1f895c6fe | 1414 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 1415 | } |
| mbed_official | 340:28d1f895c6fe | 1416 | |
| mbed_official | 340:28d1f895c6fe | 1417 | /* packing mode management is enabled by the DMA settings */ |
| mbed_official | 340:28d1f895c6fe | 1418 | if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) |
| mbed_official | 340:28d1f895c6fe | 1419 | { |
| mbed_official | 340:28d1f895c6fe | 1420 | /* Restriction the DMA data received is not allowed in this mode */ |
| mbed_official | 441:d2c15dda23c1 | 1421 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1422 | goto error; |
| mbed_official | 340:28d1f895c6fe | 1423 | } |
| mbed_official | 340:28d1f895c6fe | 1424 | |
| mbed_official | 340:28d1f895c6fe | 1425 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
| mbed_official | 340:28d1f895c6fe | 1426 | if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 340:28d1f895c6fe | 1427 | { |
| mbed_official | 340:28d1f895c6fe | 1428 | /* set fiforxthresold according the reception data lenght: 16bit */ |
| mbed_official | 340:28d1f895c6fe | 1429 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 1430 | } |
| mbed_official | 340:28d1f895c6fe | 1431 | else |
| mbed_official | 340:28d1f895c6fe | 1432 | { |
| mbed_official | 340:28d1f895c6fe | 1433 | /* set fiforxthresold according the reception data lenght: 8bit */ |
| mbed_official | 340:28d1f895c6fe | 1434 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 1435 | } |
| mbed_official | 340:28d1f895c6fe | 1436 | |
| mbed_official | 441:d2c15dda23c1 | 1437 | /* Set the SPI RxDMA Half transfer complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1438 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
| mbed_official | 441:d2c15dda23c1 | 1439 | |
| mbed_official | 441:d2c15dda23c1 | 1440 | /* Set the SPI Rx DMA transfert complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1441 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
| mbed_official | 340:28d1f895c6fe | 1442 | |
| mbed_official | 340:28d1f895c6fe | 1443 | /* Set the DMA error callback */ |
| mbed_official | 441:d2c15dda23c1 | 1444 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
| mbed_official | 340:28d1f895c6fe | 1445 | |
| mbed_official | 340:28d1f895c6fe | 1446 | /* Enable Rx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 1447 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
| mbed_official | 340:28d1f895c6fe | 1448 | |
| mbed_official | 340:28d1f895c6fe | 1449 | /* Enable the Rx DMA channel */ |
| mbed_official | 340:28d1f895c6fe | 1450 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); |
| mbed_official | 340:28d1f895c6fe | 1451 | |
| mbed_official | 340:28d1f895c6fe | 1452 | /* Check if the SPI is already enabled */ |
| mbed_official | 340:28d1f895c6fe | 1453 | if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 340:28d1f895c6fe | 1454 | { |
| mbed_official | 340:28d1f895c6fe | 1455 | /* Enable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 1456 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 1457 | } |
| mbed_official | 340:28d1f895c6fe | 1458 | |
| mbed_official | 441:d2c15dda23c1 | 1459 | error: |
| mbed_official | 441:d2c15dda23c1 | 1460 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1461 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1462 | return errorcode; |
| mbed_official | 340:28d1f895c6fe | 1463 | } |
| mbed_official | 340:28d1f895c6fe | 1464 | |
| mbed_official | 340:28d1f895c6fe | 1465 | /** |
| mbed_official | 340:28d1f895c6fe | 1466 | * @brief Transmit and Receive an amount of data in no-blocking mode with DMA |
| mbed_official | 441:d2c15dda23c1 | 1467 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1468 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1469 | * @param pTxData : pointer to transmission data buffer |
| mbed_official | 441:d2c15dda23c1 | 1470 | * @param pRxData : pointer to reception data buffer |
| mbed_official | 441:d2c15dda23c1 | 1471 | * @param Size : amount of data to be sent |
| mbed_official | 340:28d1f895c6fe | 1472 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 1473 | */ |
| mbed_official | 340:28d1f895c6fe | 1474 | HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) |
| mbed_official | 340:28d1f895c6fe | 1475 | { |
| mbed_official | 441:d2c15dda23c1 | 1476 | HAL_StatusTypeDef errorcode = HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1477 | assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); |
| mbed_official | 340:28d1f895c6fe | 1478 | |
| mbed_official | 441:d2c15dda23c1 | 1479 | /* Process locked */ |
| mbed_official | 441:d2c15dda23c1 | 1480 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1481 | |
| mbed_official | 441:d2c15dda23c1 | 1482 | if(!((hspi->State == HAL_SPI_STATE_READY) || |
| mbed_official | 441:d2c15dda23c1 | 1483 | ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))) |
| mbed_official | 441:d2c15dda23c1 | 1484 | { |
| mbed_official | 441:d2c15dda23c1 | 1485 | errorcode = HAL_BUSY; |
| mbed_official | 441:d2c15dda23c1 | 1486 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1487 | } |
| mbed_official | 441:d2c15dda23c1 | 1488 | |
| mbed_official | 441:d2c15dda23c1 | 1489 | if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) |
| mbed_official | 340:28d1f895c6fe | 1490 | { |
| mbed_official | 441:d2c15dda23c1 | 1491 | errorcode = HAL_ERROR; |
| mbed_official | 441:d2c15dda23c1 | 1492 | goto error; |
| mbed_official | 441:d2c15dda23c1 | 1493 | } |
| mbed_official | 441:d2c15dda23c1 | 1494 | |
| mbed_official | 441:d2c15dda23c1 | 1495 | /* check if the transmit Receive function is not called by a receive master */ |
| mbed_official | 441:d2c15dda23c1 | 1496 | if(hspi->State != HAL_SPI_STATE_BUSY_RX) |
| mbed_official | 441:d2c15dda23c1 | 1497 | { |
| mbed_official | 441:d2c15dda23c1 | 1498 | hspi->State = HAL_SPI_STATE_BUSY_TX_RX; |
| mbed_official | 441:d2c15dda23c1 | 1499 | } |
| mbed_official | 441:d2c15dda23c1 | 1500 | |
| mbed_official | 441:d2c15dda23c1 | 1501 | hspi->ErrorCode = HAL_SPI_ERROR_NONE; |
| mbed_official | 441:d2c15dda23c1 | 1502 | hspi->pTxBuffPtr = (uint8_t *)pTxData; |
| mbed_official | 441:d2c15dda23c1 | 1503 | hspi->TxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1504 | hspi->TxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1505 | hspi->pRxBuffPtr = (uint8_t *)pRxData; |
| mbed_official | 441:d2c15dda23c1 | 1506 | hspi->RxXferSize = Size; |
| mbed_official | 441:d2c15dda23c1 | 1507 | hspi->RxXferCount = Size; |
| mbed_official | 441:d2c15dda23c1 | 1508 | |
| mbed_official | 441:d2c15dda23c1 | 1509 | /* Reset CRC Calculation + increase the rxsize */ |
| mbed_official | 441:d2c15dda23c1 | 1510 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1511 | { |
| mbed_official | 441:d2c15dda23c1 | 1512 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1513 | } |
| mbed_official | 441:d2c15dda23c1 | 1514 | |
| mbed_official | 441:d2c15dda23c1 | 1515 | /* Reset the threshold bit */ |
| mbed_official | 441:d2c15dda23c1 | 1516 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); |
| mbed_official | 441:d2c15dda23c1 | 1517 | |
| mbed_official | 441:d2c15dda23c1 | 1518 | /* the packing mode management is enabled by the DMA settings according the spi data size */ |
| mbed_official | 441:d2c15dda23c1 | 1519 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 441:d2c15dda23c1 | 1520 | { |
| mbed_official | 441:d2c15dda23c1 | 1521 | /* set fiforxthreshold according the reception data lenght: 16bit */ |
| mbed_official | 441:d2c15dda23c1 | 1522 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 441:d2c15dda23c1 | 1523 | } |
| mbed_official | 441:d2c15dda23c1 | 1524 | else |
| mbed_official | 441:d2c15dda23c1 | 1525 | { |
| mbed_official | 441:d2c15dda23c1 | 1526 | /* set fiforxthresold according the reception data lenght: 8bit */ |
| mbed_official | 441:d2c15dda23c1 | 1527 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 1528 | |
| mbed_official | 441:d2c15dda23c1 | 1529 | if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) |
| mbed_official | 340:28d1f895c6fe | 1530 | { |
| mbed_official | 441:d2c15dda23c1 | 1531 | if((hspi->TxXferSize & 0x1) == 0x0) |
| mbed_official | 441:d2c15dda23c1 | 1532 | { |
| mbed_official | 441:d2c15dda23c1 | 1533 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
| mbed_official | 441:d2c15dda23c1 | 1534 | hspi->TxXferCount = hspi->TxXferCount >> 1; |
| mbed_official | 441:d2c15dda23c1 | 1535 | } |
| mbed_official | 441:d2c15dda23c1 | 1536 | else |
| mbed_official | 441:d2c15dda23c1 | 1537 | { |
| mbed_official | 441:d2c15dda23c1 | 1538 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); |
| mbed_official | 441:d2c15dda23c1 | 1539 | hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1; |
| mbed_official | 441:d2c15dda23c1 | 1540 | } |
| mbed_official | 340:28d1f895c6fe | 1541 | } |
| mbed_official | 340:28d1f895c6fe | 1542 | |
| mbed_official | 441:d2c15dda23c1 | 1543 | if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) |
| mbed_official | 340:28d1f895c6fe | 1544 | { |
| mbed_official | 441:d2c15dda23c1 | 1545 | /* set fiforxthresold according the reception data lenght: 16bit */ |
| mbed_official | 340:28d1f895c6fe | 1546 | CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 1547 | |
| mbed_official | 441:d2c15dda23c1 | 1548 | if((hspi->RxXferCount & 0x1) == 0x0 ) |
| mbed_official | 340:28d1f895c6fe | 1549 | { |
| mbed_official | 441:d2c15dda23c1 | 1550 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
| mbed_official | 441:d2c15dda23c1 | 1551 | hspi->RxXferCount = hspi->RxXferCount >> 1; |
| mbed_official | 340:28d1f895c6fe | 1552 | } |
| mbed_official | 441:d2c15dda23c1 | 1553 | else |
| mbed_official | 441:d2c15dda23c1 | 1554 | { |
| mbed_official | 441:d2c15dda23c1 | 1555 | SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); |
| mbed_official | 441:d2c15dda23c1 | 1556 | hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1; |
| mbed_official | 441:d2c15dda23c1 | 1557 | } |
| mbed_official | 340:28d1f895c6fe | 1558 | } |
| mbed_official | 441:d2c15dda23c1 | 1559 | } |
| mbed_official | 441:d2c15dda23c1 | 1560 | |
| mbed_official | 441:d2c15dda23c1 | 1561 | /* Set the SPI Rx DMA transfer complete callback if the transfer request is a |
| mbed_official | 441:d2c15dda23c1 | 1562 | reception request (RXNE) */ |
| mbed_official | 441:d2c15dda23c1 | 1563 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
| mbed_official | 441:d2c15dda23c1 | 1564 | { |
| mbed_official | 441:d2c15dda23c1 | 1565 | /* Set the SPI Rx DMA Half transfer complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1566 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; |
| mbed_official | 441:d2c15dda23c1 | 1567 | hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; |
| mbed_official | 340:28d1f895c6fe | 1568 | } |
| mbed_official | 340:28d1f895c6fe | 1569 | else |
| mbed_official | 340:28d1f895c6fe | 1570 | { |
| mbed_official | 441:d2c15dda23c1 | 1571 | /* Set the SPI Rx DMA Half transfer complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1572 | hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; |
| mbed_official | 441:d2c15dda23c1 | 1573 | hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; |
| mbed_official | 441:d2c15dda23c1 | 1574 | } |
| mbed_official | 441:d2c15dda23c1 | 1575 | |
| mbed_official | 441:d2c15dda23c1 | 1576 | /* Set the DMA error callback */ |
| mbed_official | 441:d2c15dda23c1 | 1577 | hspi->hdmarx->XferErrorCallback = SPI_DMAError; |
| mbed_official | 441:d2c15dda23c1 | 1578 | |
| mbed_official | 441:d2c15dda23c1 | 1579 | /* Enable Rx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 1580 | SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1581 | |
| mbed_official | 441:d2c15dda23c1 | 1582 | /* Enable the Rx DMA channel */ |
| mbed_official | 441:d2c15dda23c1 | 1583 | HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount); |
| mbed_official | 441:d2c15dda23c1 | 1584 | |
| mbed_official | 441:d2c15dda23c1 | 1585 | /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing |
| mbed_official | 441:d2c15dda23c1 | 1586 | is performed in DMA reception complete callback */ |
| mbed_official | 441:d2c15dda23c1 | 1587 | hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; |
| mbed_official | 441:d2c15dda23c1 | 1588 | |
| mbed_official | 441:d2c15dda23c1 | 1589 | /* Set the DMA error callback */ |
| mbed_official | 441:d2c15dda23c1 | 1590 | hspi->hdmatx->XferErrorCallback = SPI_DMAError; |
| mbed_official | 441:d2c15dda23c1 | 1591 | |
| mbed_official | 441:d2c15dda23c1 | 1592 | /* Enable the Tx DMA channel */ |
| mbed_official | 441:d2c15dda23c1 | 1593 | HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); |
| mbed_official | 441:d2c15dda23c1 | 1594 | |
| mbed_official | 441:d2c15dda23c1 | 1595 | /* Check if the SPI is already enabled */ |
| mbed_official | 441:d2c15dda23c1 | 1596 | if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) |
| mbed_official | 441:d2c15dda23c1 | 1597 | { |
| mbed_official | 441:d2c15dda23c1 | 1598 | /* Enable SPI peripheral */ |
| mbed_official | 441:d2c15dda23c1 | 1599 | __HAL_SPI_ENABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 1600 | } |
| mbed_official | 441:d2c15dda23c1 | 1601 | |
| mbed_official | 441:d2c15dda23c1 | 1602 | /* Enable Tx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 1603 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1604 | |
| mbed_official | 441:d2c15dda23c1 | 1605 | error : |
| mbed_official | 441:d2c15dda23c1 | 1606 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1607 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1608 | return errorcode; |
| mbed_official | 441:d2c15dda23c1 | 1609 | } |
| mbed_official | 441:d2c15dda23c1 | 1610 | |
| mbed_official | 441:d2c15dda23c1 | 1611 | /** |
| mbed_official | 441:d2c15dda23c1 | 1612 | * @brief Pauses the DMA Transfer. |
| mbed_official | 441:d2c15dda23c1 | 1613 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1614 | * the configuration information for the specified SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1615 | * @retval HAL status |
| mbed_official | 441:d2c15dda23c1 | 1616 | */ |
| mbed_official | 441:d2c15dda23c1 | 1617 | HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1618 | { |
| mbed_official | 441:d2c15dda23c1 | 1619 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 1620 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1621 | |
| mbed_official | 441:d2c15dda23c1 | 1622 | /* Disable the SPI DMA Tx & Rx requests */ |
| mbed_official | 441:d2c15dda23c1 | 1623 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1624 | |
| mbed_official | 441:d2c15dda23c1 | 1625 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1626 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1627 | |
| mbed_official | 441:d2c15dda23c1 | 1628 | return HAL_OK; |
| mbed_official | 441:d2c15dda23c1 | 1629 | } |
| mbed_official | 441:d2c15dda23c1 | 1630 | |
| mbed_official | 441:d2c15dda23c1 | 1631 | /** |
| mbed_official | 441:d2c15dda23c1 | 1632 | * @brief Resumes the DMA Transfer. |
| mbed_official | 441:d2c15dda23c1 | 1633 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1634 | * the configuration information for the specified SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1635 | * @retval HAL status |
| mbed_official | 441:d2c15dda23c1 | 1636 | */ |
| mbed_official | 441:d2c15dda23c1 | 1637 | HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1638 | { |
| mbed_official | 441:d2c15dda23c1 | 1639 | /* Process Locked */ |
| mbed_official | 441:d2c15dda23c1 | 1640 | __HAL_LOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1641 | |
| mbed_official | 441:d2c15dda23c1 | 1642 | /* Enable the SPI DMA Tx & Rx requests */ |
| mbed_official | 441:d2c15dda23c1 | 1643 | SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1644 | |
| mbed_official | 441:d2c15dda23c1 | 1645 | /* Process Unlocked */ |
| mbed_official | 441:d2c15dda23c1 | 1646 | __HAL_UNLOCK(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1647 | |
| mbed_official | 441:d2c15dda23c1 | 1648 | return HAL_OK; |
| mbed_official | 441:d2c15dda23c1 | 1649 | } |
| mbed_official | 441:d2c15dda23c1 | 1650 | |
| mbed_official | 441:d2c15dda23c1 | 1651 | /** |
| mbed_official | 441:d2c15dda23c1 | 1652 | * @brief Stops the DMA Transfer. |
| mbed_official | 441:d2c15dda23c1 | 1653 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1654 | * the configuration information for the specified SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1655 | * @retval HAL status |
| mbed_official | 441:d2c15dda23c1 | 1656 | */ |
| mbed_official | 441:d2c15dda23c1 | 1657 | HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1658 | { |
| mbed_official | 441:d2c15dda23c1 | 1659 | /* The Lock is not implemented on this API to allow the user application |
| mbed_official | 441:d2c15dda23c1 | 1660 | to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): |
| mbed_official | 441:d2c15dda23c1 | 1661 | when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated |
| mbed_official | 441:d2c15dda23c1 | 1662 | and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() |
| mbed_official | 441:d2c15dda23c1 | 1663 | */ |
| mbed_official | 441:d2c15dda23c1 | 1664 | |
| mbed_official | 441:d2c15dda23c1 | 1665 | /* Abort the SPI DMA tx channel */ |
| mbed_official | 441:d2c15dda23c1 | 1666 | if(hspi->hdmatx != NULL) |
| mbed_official | 441:d2c15dda23c1 | 1667 | { |
| mbed_official | 441:d2c15dda23c1 | 1668 | HAL_DMA_Abort(hspi->hdmatx); |
| mbed_official | 441:d2c15dda23c1 | 1669 | } |
| mbed_official | 441:d2c15dda23c1 | 1670 | /* Abort the SPI DMA rx channel */ |
| mbed_official | 441:d2c15dda23c1 | 1671 | if(hspi->hdmarx != NULL) |
| mbed_official | 441:d2c15dda23c1 | 1672 | { |
| mbed_official | 441:d2c15dda23c1 | 1673 | HAL_DMA_Abort(hspi->hdmarx); |
| mbed_official | 441:d2c15dda23c1 | 1674 | } |
| mbed_official | 441:d2c15dda23c1 | 1675 | |
| mbed_official | 441:d2c15dda23c1 | 1676 | /* Disable the SPI DMA Tx & Rx requests */ |
| mbed_official | 441:d2c15dda23c1 | 1677 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1678 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 1679 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1680 | } |
| mbed_official | 340:28d1f895c6fe | 1681 | |
| mbed_official | 340:28d1f895c6fe | 1682 | /** |
| mbed_official | 340:28d1f895c6fe | 1683 | * @brief This function handles SPI interrupt request. |
| mbed_official | 441:d2c15dda23c1 | 1684 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1685 | * the configuration information for the specified SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1686 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 1687 | */ |
| mbed_official | 340:28d1f895c6fe | 1688 | void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1689 | { |
| mbed_official | 441:d2c15dda23c1 | 1690 | uint32_t itsource = hspi->Instance->CR2; |
| mbed_official | 441:d2c15dda23c1 | 1691 | uint32_t itflag = hspi->Instance->SR; |
| mbed_official | 441:d2c15dda23c1 | 1692 | |
| mbed_official | 340:28d1f895c6fe | 1693 | /* SPI in mode Receiver ----------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1694 | if(((itflag & SPI_FLAG_OVR) == RESET) && |
| mbed_official | 441:d2c15dda23c1 | 1695 | ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) |
| mbed_official | 340:28d1f895c6fe | 1696 | { |
| mbed_official | 340:28d1f895c6fe | 1697 | hspi->RxISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 1698 | return; |
| mbed_official | 340:28d1f895c6fe | 1699 | } |
| mbed_official | 340:28d1f895c6fe | 1700 | |
| mbed_official | 340:28d1f895c6fe | 1701 | /* SPI in mode Tramitter ---------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1702 | if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) |
| mbed_official | 340:28d1f895c6fe | 1703 | { |
| mbed_official | 340:28d1f895c6fe | 1704 | hspi->TxISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 1705 | return; |
| mbed_official | 340:28d1f895c6fe | 1706 | } |
| mbed_official | 340:28d1f895c6fe | 1707 | |
| mbed_official | 340:28d1f895c6fe | 1708 | /* SPI in Erreur Treatment ---------------------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1709 | if((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) |
| mbed_official | 340:28d1f895c6fe | 1710 | { |
| mbed_official | 340:28d1f895c6fe | 1711 | /* SPI Overrun error interrupt occured -------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1712 | if((itflag & SPI_FLAG_OVR) != RESET) |
| mbed_official | 340:28d1f895c6fe | 1713 | { |
| mbed_official | 340:28d1f895c6fe | 1714 | if(hspi->State != HAL_SPI_STATE_BUSY_TX) |
| mbed_official | 340:28d1f895c6fe | 1715 | { |
| mbed_official | 340:28d1f895c6fe | 1716 | hspi->ErrorCode |= HAL_SPI_ERROR_OVR; |
| mbed_official | 340:28d1f895c6fe | 1717 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 1718 | } |
| mbed_official | 340:28d1f895c6fe | 1719 | else |
| mbed_official | 340:28d1f895c6fe | 1720 | { |
| mbed_official | 340:28d1f895c6fe | 1721 | return; |
| mbed_official | 340:28d1f895c6fe | 1722 | } |
| mbed_official | 340:28d1f895c6fe | 1723 | } |
| mbed_official | 340:28d1f895c6fe | 1724 | |
| mbed_official | 340:28d1f895c6fe | 1725 | /* SPI Mode Fault error interrupt occured -------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1726 | if((itflag & SPI_FLAG_MODF) != RESET) |
| mbed_official | 340:28d1f895c6fe | 1727 | { |
| mbed_official | 340:28d1f895c6fe | 1728 | hspi->ErrorCode |= HAL_SPI_ERROR_MODF; |
| mbed_official | 340:28d1f895c6fe | 1729 | __HAL_SPI_CLEAR_MODFFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 1730 | } |
| mbed_official | 340:28d1f895c6fe | 1731 | |
| mbed_official | 340:28d1f895c6fe | 1732 | /* SPI Frame error interrupt occured ----------------------------------------*/ |
| mbed_official | 441:d2c15dda23c1 | 1733 | if((itflag & SPI_FLAG_FRE) != RESET) |
| mbed_official | 340:28d1f895c6fe | 1734 | { |
| mbed_official | 340:28d1f895c6fe | 1735 | hspi->ErrorCode |= HAL_SPI_ERROR_FRE; |
| mbed_official | 340:28d1f895c6fe | 1736 | __HAL_SPI_CLEAR_FREFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 1737 | } |
| mbed_official | 441:d2c15dda23c1 | 1738 | |
| mbed_official | 340:28d1f895c6fe | 1739 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); |
| mbed_official | 340:28d1f895c6fe | 1740 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 1741 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 1742 | return; |
| mbed_official | 340:28d1f895c6fe | 1743 | } |
| mbed_official | 340:28d1f895c6fe | 1744 | } |
| mbed_official | 340:28d1f895c6fe | 1745 | |
| mbed_official | 340:28d1f895c6fe | 1746 | /** |
| mbed_official | 441:d2c15dda23c1 | 1747 | * @brief Flush the RX fifo. |
| mbed_official | 441:d2c15dda23c1 | 1748 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1749 | * the configuration information for the specified SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1750 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 1751 | */ |
| mbed_official | 441:d2c15dda23c1 | 1752 | HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1753 | { |
| mbed_official | 441:d2c15dda23c1 | 1754 | __IO uint32_t tmpreg; |
| mbed_official | 441:d2c15dda23c1 | 1755 | uint8_t count = 0; |
| mbed_official | 441:d2c15dda23c1 | 1756 | while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) |
| mbed_official | 340:28d1f895c6fe | 1757 | { |
| mbed_official | 441:d2c15dda23c1 | 1758 | count++; |
| mbed_official | 441:d2c15dda23c1 | 1759 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 1760 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 1761 | if(count == SPI_FIFO_SIZE) |
| mbed_official | 340:28d1f895c6fe | 1762 | { |
| mbed_official | 441:d2c15dda23c1 | 1763 | return HAL_TIMEOUT; |
| mbed_official | 340:28d1f895c6fe | 1764 | } |
| mbed_official | 441:d2c15dda23c1 | 1765 | }; |
| mbed_official | 441:d2c15dda23c1 | 1766 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 1767 | } |
| mbed_official | 340:28d1f895c6fe | 1768 | |
| mbed_official | 340:28d1f895c6fe | 1769 | /** |
| mbed_official | 340:28d1f895c6fe | 1770 | * @brief Tx Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1771 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1772 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1773 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 1774 | */ |
| mbed_official | 340:28d1f895c6fe | 1775 | __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1776 | { |
| mbed_official | 340:28d1f895c6fe | 1777 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 1778 | the HAL_SPI_TxCpltCallback could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 1779 | */ |
| mbed_official | 340:28d1f895c6fe | 1780 | } |
| mbed_official | 340:28d1f895c6fe | 1781 | |
| mbed_official | 340:28d1f895c6fe | 1782 | /** |
| mbed_official | 340:28d1f895c6fe | 1783 | * @brief Rx Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1784 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1785 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1786 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 1787 | */ |
| mbed_official | 340:28d1f895c6fe | 1788 | __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1789 | { |
| mbed_official | 340:28d1f895c6fe | 1790 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 1791 | the HAL_SPI_RxCpltCallback could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 1792 | */ |
| mbed_official | 340:28d1f895c6fe | 1793 | } |
| mbed_official | 340:28d1f895c6fe | 1794 | |
| mbed_official | 340:28d1f895c6fe | 1795 | /** |
| mbed_official | 340:28d1f895c6fe | 1796 | * @brief Tx and Rx Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1797 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1798 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1799 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 1800 | */ |
| mbed_official | 340:28d1f895c6fe | 1801 | __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1802 | { |
| mbed_official | 340:28d1f895c6fe | 1803 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 1804 | the HAL_SPI_TxRxCpltCallback could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 1805 | */ |
| mbed_official | 340:28d1f895c6fe | 1806 | } |
| mbed_official | 441:d2c15dda23c1 | 1807 | |
| mbed_official | 441:d2c15dda23c1 | 1808 | /** |
| mbed_official | 441:d2c15dda23c1 | 1809 | * @brief Tx Half Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1810 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1811 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1812 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 1813 | */ |
| mbed_official | 441:d2c15dda23c1 | 1814 | __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1815 | { |
| mbed_official | 441:d2c15dda23c1 | 1816 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 441:d2c15dda23c1 | 1817 | the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file |
| mbed_official | 441:d2c15dda23c1 | 1818 | */ |
| mbed_official | 441:d2c15dda23c1 | 1819 | } |
| mbed_official | 441:d2c15dda23c1 | 1820 | |
| mbed_official | 441:d2c15dda23c1 | 1821 | /** |
| mbed_official | 441:d2c15dda23c1 | 1822 | * @brief Rx Half Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1823 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1824 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1825 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 1826 | */ |
| mbed_official | 441:d2c15dda23c1 | 1827 | __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1828 | { |
| mbed_official | 441:d2c15dda23c1 | 1829 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 441:d2c15dda23c1 | 1830 | the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file |
| mbed_official | 441:d2c15dda23c1 | 1831 | */ |
| mbed_official | 441:d2c15dda23c1 | 1832 | } |
| mbed_official | 441:d2c15dda23c1 | 1833 | |
| mbed_official | 441:d2c15dda23c1 | 1834 | /** |
| mbed_official | 441:d2c15dda23c1 | 1835 | * @brief Tx and Rx Transfer completed callbacks |
| mbed_official | 441:d2c15dda23c1 | 1836 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1837 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1838 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 1839 | */ |
| mbed_official | 441:d2c15dda23c1 | 1840 | __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1841 | { |
| mbed_official | 441:d2c15dda23c1 | 1842 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 441:d2c15dda23c1 | 1843 | the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file |
| mbed_official | 441:d2c15dda23c1 | 1844 | */ |
| mbed_official | 441:d2c15dda23c1 | 1845 | } |
| mbed_official | 441:d2c15dda23c1 | 1846 | |
| mbed_official | 340:28d1f895c6fe | 1847 | /** |
| mbed_official | 340:28d1f895c6fe | 1848 | * @brief SPI error callbacks |
| mbed_official | 441:d2c15dda23c1 | 1849 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1850 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1851 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 1852 | */ |
| mbed_official | 340:28d1f895c6fe | 1853 | __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1854 | { |
| mbed_official | 340:28d1f895c6fe | 1855 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 340:28d1f895c6fe | 1856 | the HAL_SPI_ErrorCallback could be implenetd in the user file |
| mbed_official | 340:28d1f895c6fe | 1857 | */ |
| mbed_official | 340:28d1f895c6fe | 1858 | } |
| mbed_official | 340:28d1f895c6fe | 1859 | |
| mbed_official | 340:28d1f895c6fe | 1860 | /** |
| mbed_official | 340:28d1f895c6fe | 1861 | * @} |
| mbed_official | 340:28d1f895c6fe | 1862 | */ |
| mbed_official | 340:28d1f895c6fe | 1863 | |
| mbed_official | 340:28d1f895c6fe | 1864 | /** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions |
| mbed_official | 340:28d1f895c6fe | 1865 | * @brief SPI control functions |
| mbed_official | 340:28d1f895c6fe | 1866 | * |
| mbed_official | 340:28d1f895c6fe | 1867 | @verbatim |
| mbed_official | 340:28d1f895c6fe | 1868 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 1869 | ##### Peripheral Control functions ##### |
| mbed_official | 340:28d1f895c6fe | 1870 | =============================================================================== |
| mbed_official | 340:28d1f895c6fe | 1871 | [..] |
| mbed_official | 340:28d1f895c6fe | 1872 | This subsection provides a set of functions allowing to control the SPI. |
| mbed_official | 340:28d1f895c6fe | 1873 | (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral. |
| mbed_official | 441:d2c15dda23c1 | 1874 | (+) HAL_SPI_GetError() check in run-time Errors occurring during communication |
| mbed_official | 340:28d1f895c6fe | 1875 | @endverbatim |
| mbed_official | 340:28d1f895c6fe | 1876 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1877 | */ |
| mbed_official | 340:28d1f895c6fe | 1878 | |
| mbed_official | 340:28d1f895c6fe | 1879 | /** |
| mbed_official | 340:28d1f895c6fe | 1880 | * @brief Return the SPI state |
| mbed_official | 441:d2c15dda23c1 | 1881 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1882 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1883 | * @retval SPI state |
| mbed_official | 340:28d1f895c6fe | 1884 | */ |
| mbed_official | 340:28d1f895c6fe | 1885 | HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 1886 | { |
| mbed_official | 340:28d1f895c6fe | 1887 | return hspi->State; |
| mbed_official | 340:28d1f895c6fe | 1888 | } |
| mbed_official | 441:d2c15dda23c1 | 1889 | |
| mbed_official | 441:d2c15dda23c1 | 1890 | /** |
| mbed_official | 441:d2c15dda23c1 | 1891 | * @brief Return the SPI error code |
| mbed_official | 441:d2c15dda23c1 | 1892 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1893 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 1894 | * @retval SPI Error Code |
| mbed_official | 441:d2c15dda23c1 | 1895 | */ |
| mbed_official | 441:d2c15dda23c1 | 1896 | uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) |
| mbed_official | 441:d2c15dda23c1 | 1897 | { |
| mbed_official | 441:d2c15dda23c1 | 1898 | return hspi->ErrorCode; |
| mbed_official | 441:d2c15dda23c1 | 1899 | } |
| mbed_official | 441:d2c15dda23c1 | 1900 | |
| mbed_official | 340:28d1f895c6fe | 1901 | /** |
| mbed_official | 340:28d1f895c6fe | 1902 | * @} |
| mbed_official | 340:28d1f895c6fe | 1903 | */ |
| mbed_official | 340:28d1f895c6fe | 1904 | |
| mbed_official | 441:d2c15dda23c1 | 1905 | |
| mbed_official | 340:28d1f895c6fe | 1906 | /** |
| mbed_official | 340:28d1f895c6fe | 1907 | * @} |
| mbed_official | 340:28d1f895c6fe | 1908 | */ |
| mbed_official | 340:28d1f895c6fe | 1909 | |
| mbed_official | 340:28d1f895c6fe | 1910 | /** @addtogroup SPI_Private_Functions SPI Private Functions |
| mbed_official | 340:28d1f895c6fe | 1911 | * @brief Data transfers Private functions |
| mbed_official | 340:28d1f895c6fe | 1912 | * @{ |
| mbed_official | 340:28d1f895c6fe | 1913 | */ |
| mbed_official | 340:28d1f895c6fe | 1914 | |
| mbed_official | 340:28d1f895c6fe | 1915 | /** |
| mbed_official | 441:d2c15dda23c1 | 1916 | * @brief DMA SPI transmit process complete callback |
| mbed_official | 441:d2c15dda23c1 | 1917 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1918 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 1919 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 1920 | */ |
| mbed_official | 441:d2c15dda23c1 | 1921 | static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 1922 | { |
| mbed_official | 441:d2c15dda23c1 | 1923 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 1924 | |
| mbed_official | 441:d2c15dda23c1 | 1925 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
| mbed_official | 441:d2c15dda23c1 | 1926 | { |
| mbed_official | 441:d2c15dda23c1 | 1927 | /* Disable Tx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 1928 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1929 | |
| mbed_official | 441:d2c15dda23c1 | 1930 | /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */ |
| mbed_official | 441:d2c15dda23c1 | 1931 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
| mbed_official | 441:d2c15dda23c1 | 1932 | { |
| mbed_official | 441:d2c15dda23c1 | 1933 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1934 | } |
| mbed_official | 441:d2c15dda23c1 | 1935 | |
| mbed_official | 441:d2c15dda23c1 | 1936 | hspi->TxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 1937 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 1938 | |
| mbed_official | 441:d2c15dda23c1 | 1939 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 441:d2c15dda23c1 | 1940 | { |
| mbed_official | 441:d2c15dda23c1 | 1941 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1942 | return; |
| mbed_official | 441:d2c15dda23c1 | 1943 | } |
| mbed_official | 441:d2c15dda23c1 | 1944 | } |
| mbed_official | 441:d2c15dda23c1 | 1945 | HAL_SPI_TxCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 1946 | } |
| mbed_official | 441:d2c15dda23c1 | 1947 | |
| mbed_official | 441:d2c15dda23c1 | 1948 | /** |
| mbed_official | 441:d2c15dda23c1 | 1949 | * @brief DMA SPI receive process complete callback |
| mbed_official | 441:d2c15dda23c1 | 1950 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 1951 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 1952 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 1953 | */ |
| mbed_official | 441:d2c15dda23c1 | 1954 | static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 1955 | { |
| mbed_official | 441:d2c15dda23c1 | 1956 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 1957 | |
| mbed_official | 441:d2c15dda23c1 | 1958 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
| mbed_official | 441:d2c15dda23c1 | 1959 | { |
| mbed_official | 441:d2c15dda23c1 | 1960 | __IO uint16_t tmpreg; |
| mbed_official | 441:d2c15dda23c1 | 1961 | |
| mbed_official | 441:d2c15dda23c1 | 1962 | /* CRC handling */ |
| mbed_official | 441:d2c15dda23c1 | 1963 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 1964 | { |
| mbed_official | 441:d2c15dda23c1 | 1965 | /* Wait until TXE flag */ |
| mbed_official | 441:d2c15dda23c1 | 1966 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 1967 | { |
| mbed_official | 441:d2c15dda23c1 | 1968 | /* Erreur on the CRC reception */ |
| mbed_official | 441:d2c15dda23c1 | 1969 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 1970 | } |
| mbed_official | 441:d2c15dda23c1 | 1971 | if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) |
| mbed_official | 441:d2c15dda23c1 | 1972 | { |
| mbed_official | 441:d2c15dda23c1 | 1973 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 1974 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 1975 | } |
| mbed_official | 441:d2c15dda23c1 | 1976 | else |
| mbed_official | 441:d2c15dda23c1 | 1977 | { |
| mbed_official | 441:d2c15dda23c1 | 1978 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 1979 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 1980 | if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) |
| mbed_official | 441:d2c15dda23c1 | 1981 | { |
| mbed_official | 441:d2c15dda23c1 | 1982 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 1983 | { |
| mbed_official | 441:d2c15dda23c1 | 1984 | /* Erreur on the CRC reception */ |
| mbed_official | 441:d2c15dda23c1 | 1985 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 1986 | } |
| mbed_official | 441:d2c15dda23c1 | 1987 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 1988 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 1989 | } |
| mbed_official | 441:d2c15dda23c1 | 1990 | } |
| mbed_official | 441:d2c15dda23c1 | 1991 | } |
| mbed_official | 441:d2c15dda23c1 | 1992 | |
| mbed_official | 441:d2c15dda23c1 | 1993 | /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ |
| mbed_official | 441:d2c15dda23c1 | 1994 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 1995 | |
| mbed_official | 441:d2c15dda23c1 | 1996 | /* Check the end of the transaction */ |
| mbed_official | 441:d2c15dda23c1 | 1997 | SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); |
| mbed_official | 441:d2c15dda23c1 | 1998 | |
| mbed_official | 441:d2c15dda23c1 | 1999 | hspi->RxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 2000 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 2001 | |
| mbed_official | 441:d2c15dda23c1 | 2002 | /* Check if CRC error occurred */ |
| mbed_official | 441:d2c15dda23c1 | 2003 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 441:d2c15dda23c1 | 2004 | { |
| mbed_official | 441:d2c15dda23c1 | 2005 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 2006 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2007 | } |
| mbed_official | 441:d2c15dda23c1 | 2008 | |
| mbed_official | 441:d2c15dda23c1 | 2009 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 441:d2c15dda23c1 | 2010 | { |
| mbed_official | 441:d2c15dda23c1 | 2011 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2012 | return; |
| mbed_official | 441:d2c15dda23c1 | 2013 | } |
| mbed_official | 441:d2c15dda23c1 | 2014 | } |
| mbed_official | 441:d2c15dda23c1 | 2015 | HAL_SPI_RxCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2016 | } |
| mbed_official | 441:d2c15dda23c1 | 2017 | |
| mbed_official | 441:d2c15dda23c1 | 2018 | /** |
| mbed_official | 441:d2c15dda23c1 | 2019 | * @brief DMA SPI transmit receive process complete callback |
| mbed_official | 441:d2c15dda23c1 | 2020 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2021 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 2022 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 2023 | */ |
| mbed_official | 441:d2c15dda23c1 | 2024 | static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 2025 | { |
| mbed_official | 441:d2c15dda23c1 | 2026 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 2027 | |
| mbed_official | 441:d2c15dda23c1 | 2028 | if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) |
| mbed_official | 441:d2c15dda23c1 | 2029 | { |
| mbed_official | 441:d2c15dda23c1 | 2030 | __IO int16_t tmpreg; |
| mbed_official | 441:d2c15dda23c1 | 2031 | /* CRC handling */ |
| mbed_official | 441:d2c15dda23c1 | 2032 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 441:d2c15dda23c1 | 2033 | { |
| mbed_official | 441:d2c15dda23c1 | 2034 | if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) |
| mbed_official | 441:d2c15dda23c1 | 2035 | { |
| mbed_official | 441:d2c15dda23c1 | 2036 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 2037 | { |
| mbed_official | 441:d2c15dda23c1 | 2038 | /* Erreur on the CRC reception */ |
| mbed_official | 441:d2c15dda23c1 | 2039 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 2040 | } |
| mbed_official | 441:d2c15dda23c1 | 2041 | tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 2042 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 2043 | } |
| mbed_official | 441:d2c15dda23c1 | 2044 | else |
| mbed_official | 441:d2c15dda23c1 | 2045 | { |
| mbed_official | 441:d2c15dda23c1 | 2046 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 2047 | { |
| mbed_official | 441:d2c15dda23c1 | 2048 | /* Erreur on the CRC reception */ |
| mbed_official | 441:d2c15dda23c1 | 2049 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 2050 | } |
| mbed_official | 441:d2c15dda23c1 | 2051 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 2052 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 2053 | } |
| mbed_official | 441:d2c15dda23c1 | 2054 | } |
| mbed_official | 441:d2c15dda23c1 | 2055 | |
| mbed_official | 441:d2c15dda23c1 | 2056 | /* Disable Rx/Tx DMA Request */ |
| mbed_official | 441:d2c15dda23c1 | 2057 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 2058 | |
| mbed_official | 441:d2c15dda23c1 | 2059 | |
| mbed_official | 441:d2c15dda23c1 | 2060 | hspi->TxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 2061 | hspi->RxXferCount = 0; |
| mbed_official | 441:d2c15dda23c1 | 2062 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 2063 | |
| mbed_official | 441:d2c15dda23c1 | 2064 | /* Check if CRC error occurred */ |
| mbed_official | 441:d2c15dda23c1 | 2065 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 441:d2c15dda23c1 | 2066 | { |
| mbed_official | 441:d2c15dda23c1 | 2067 | hspi->ErrorCode = HAL_SPI_ERROR_CRC; |
| mbed_official | 441:d2c15dda23c1 | 2068 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2069 | } |
| mbed_official | 441:d2c15dda23c1 | 2070 | |
| mbed_official | 441:d2c15dda23c1 | 2071 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 441:d2c15dda23c1 | 2072 | { |
| mbed_official | 441:d2c15dda23c1 | 2073 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2074 | return; |
| mbed_official | 441:d2c15dda23c1 | 2075 | } |
| mbed_official | 441:d2c15dda23c1 | 2076 | } |
| mbed_official | 441:d2c15dda23c1 | 2077 | HAL_SPI_TxRxCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2078 | } |
| mbed_official | 441:d2c15dda23c1 | 2079 | |
| mbed_official | 441:d2c15dda23c1 | 2080 | /** |
| mbed_official | 441:d2c15dda23c1 | 2081 | * @brief DMA SPI half transmit process complete callback |
| mbed_official | 441:d2c15dda23c1 | 2082 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2083 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 2084 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 2085 | */ |
| mbed_official | 441:d2c15dda23c1 | 2086 | static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 2087 | { |
| mbed_official | 441:d2c15dda23c1 | 2088 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 2089 | |
| mbed_official | 441:d2c15dda23c1 | 2090 | HAL_SPI_TxHalfCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2091 | } |
| mbed_official | 441:d2c15dda23c1 | 2092 | |
| mbed_official | 441:d2c15dda23c1 | 2093 | /** |
| mbed_official | 441:d2c15dda23c1 | 2094 | * @brief DMA SPI half receive process complete callback |
| mbed_official | 441:d2c15dda23c1 | 2095 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2096 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 2097 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 2098 | */ |
| mbed_official | 441:d2c15dda23c1 | 2099 | static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 2100 | { |
| mbed_official | 441:d2c15dda23c1 | 2101 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 2102 | |
| mbed_official | 441:d2c15dda23c1 | 2103 | HAL_SPI_RxHalfCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2104 | } |
| mbed_official | 441:d2c15dda23c1 | 2105 | |
| mbed_official | 441:d2c15dda23c1 | 2106 | /** |
| mbed_official | 441:d2c15dda23c1 | 2107 | * @brief DMA SPI Half transmit receive process complete callback |
| mbed_official | 441:d2c15dda23c1 | 2108 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2109 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 2110 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 2111 | */ |
| mbed_official | 441:d2c15dda23c1 | 2112 | static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 2113 | { |
| mbed_official | 441:d2c15dda23c1 | 2114 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 2115 | |
| mbed_official | 441:d2c15dda23c1 | 2116 | HAL_SPI_TxRxHalfCpltCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2117 | } |
| mbed_official | 441:d2c15dda23c1 | 2118 | |
| mbed_official | 441:d2c15dda23c1 | 2119 | /** |
| mbed_official | 441:d2c15dda23c1 | 2120 | * @brief DMA SPI communication error callback |
| mbed_official | 441:d2c15dda23c1 | 2121 | * @param hdma : pointer to a DMA_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2122 | * the configuration information for the specified DMA module. |
| mbed_official | 441:d2c15dda23c1 | 2123 | * @retval None. |
| mbed_official | 441:d2c15dda23c1 | 2124 | */ |
| mbed_official | 441:d2c15dda23c1 | 2125 | static void SPI_DMAError(DMA_HandleTypeDef *hdma) |
| mbed_official | 441:d2c15dda23c1 | 2126 | { |
| mbed_official | 441:d2c15dda23c1 | 2127 | SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 441:d2c15dda23c1 | 2128 | |
| mbed_official | 441:d2c15dda23c1 | 2129 | /* Stop the disable DMA transfer on SPI side */ |
| mbed_official | 441:d2c15dda23c1 | 2130 | CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); |
| mbed_official | 441:d2c15dda23c1 | 2131 | |
| mbed_official | 441:d2c15dda23c1 | 2132 | hspi->ErrorCode|= HAL_SPI_ERROR_DMA; |
| mbed_official | 441:d2c15dda23c1 | 2133 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 441:d2c15dda23c1 | 2134 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2135 | } |
| mbed_official | 441:d2c15dda23c1 | 2136 | |
| mbed_official | 441:d2c15dda23c1 | 2137 | /** |
| mbed_official | 340:28d1f895c6fe | 2138 | * @brief Rx Handler for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2139 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2140 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2141 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2142 | */ |
| mbed_official | 340:28d1f895c6fe | 2143 | static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2144 | { |
| mbed_official | 340:28d1f895c6fe | 2145 | /* Receive data in packing mode */ |
| mbed_official | 340:28d1f895c6fe | 2146 | if(hspi->RxXferCount > 1) |
| mbed_official | 340:28d1f895c6fe | 2147 | { |
| mbed_official | 340:28d1f895c6fe | 2148 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 2149 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2150 | hspi->RxXferCount -= 2; |
| mbed_official | 340:28d1f895c6fe | 2151 | if(hspi->RxXferCount == 1) |
| mbed_official | 340:28d1f895c6fe | 2152 | { |
| mbed_official | 340:28d1f895c6fe | 2153 | /* set fiforxthresold according the reception data lenght: 8bit */ |
| mbed_official | 340:28d1f895c6fe | 2154 | SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); |
| mbed_official | 340:28d1f895c6fe | 2155 | } |
| mbed_official | 340:28d1f895c6fe | 2156 | } |
| mbed_official | 340:28d1f895c6fe | 2157 | /* Receive data in 8 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2158 | else |
| mbed_official | 340:28d1f895c6fe | 2159 | { |
| mbed_official | 340:28d1f895c6fe | 2160 | *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); |
| mbed_official | 340:28d1f895c6fe | 2161 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2162 | } |
| mbed_official | 340:28d1f895c6fe | 2163 | |
| mbed_official | 340:28d1f895c6fe | 2164 | /* check end of the reception */ |
| mbed_official | 340:28d1f895c6fe | 2165 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2166 | { |
| mbed_official | 340:28d1f895c6fe | 2167 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2168 | { |
| mbed_official | 340:28d1f895c6fe | 2169 | hspi->RxISR = SPI_2linesRxISR_8BITCRC; |
| mbed_official | 340:28d1f895c6fe | 2170 | return; |
| mbed_official | 340:28d1f895c6fe | 2171 | } |
| mbed_official | 340:28d1f895c6fe | 2172 | |
| mbed_official | 340:28d1f895c6fe | 2173 | /* Disable RXNE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2174 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
| mbed_official | 340:28d1f895c6fe | 2175 | |
| mbed_official | 340:28d1f895c6fe | 2176 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2177 | { |
| mbed_official | 340:28d1f895c6fe | 2178 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2179 | } |
| mbed_official | 340:28d1f895c6fe | 2180 | } |
| mbed_official | 340:28d1f895c6fe | 2181 | } |
| mbed_official | 340:28d1f895c6fe | 2182 | |
| mbed_official | 340:28d1f895c6fe | 2183 | /** |
| mbed_official | 340:28d1f895c6fe | 2184 | * @brief Rx Handler for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2185 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2186 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2187 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2188 | */ |
| mbed_official | 340:28d1f895c6fe | 2189 | static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2190 | { |
| mbed_official | 441:d2c15dda23c1 | 2191 | __IO uint8_t tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); |
| mbed_official | 441:d2c15dda23c1 | 2192 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 2193 | hspi->CRCSize--; |
| mbed_official | 340:28d1f895c6fe | 2194 | |
| mbed_official | 340:28d1f895c6fe | 2195 | /* check end of the reception */ |
| mbed_official | 340:28d1f895c6fe | 2196 | if(hspi->CRCSize == 0) |
| mbed_official | 340:28d1f895c6fe | 2197 | { |
| mbed_official | 340:28d1f895c6fe | 2198 | /* Disable RXNE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2199 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
| mbed_official | 340:28d1f895c6fe | 2200 | |
| mbed_official | 340:28d1f895c6fe | 2201 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2202 | { |
| mbed_official | 340:28d1f895c6fe | 2203 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2204 | } |
| mbed_official | 340:28d1f895c6fe | 2205 | } |
| mbed_official | 340:28d1f895c6fe | 2206 | } |
| mbed_official | 340:28d1f895c6fe | 2207 | |
| mbed_official | 340:28d1f895c6fe | 2208 | /** |
| mbed_official | 340:28d1f895c6fe | 2209 | * @brief Tx Handler for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2210 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2211 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2212 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2213 | */ |
| mbed_official | 340:28d1f895c6fe | 2214 | static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2215 | { |
| mbed_official | 340:28d1f895c6fe | 2216 | /* Transmit data in packing Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2217 | if(hspi->TxXferCount >= 2) |
| mbed_official | 340:28d1f895c6fe | 2218 | { |
| mbed_official | 340:28d1f895c6fe | 2219 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
| mbed_official | 340:28d1f895c6fe | 2220 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2221 | hspi->TxXferCount -= 2; |
| mbed_official | 340:28d1f895c6fe | 2222 | } |
| mbed_official | 340:28d1f895c6fe | 2223 | /* Transmit data in 8 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2224 | else |
| mbed_official | 340:28d1f895c6fe | 2225 | { |
| mbed_official | 340:28d1f895c6fe | 2226 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
| mbed_official | 340:28d1f895c6fe | 2227 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2228 | } |
| mbed_official | 340:28d1f895c6fe | 2229 | |
| mbed_official | 340:28d1f895c6fe | 2230 | /* check the end of the transmission */ |
| mbed_official | 340:28d1f895c6fe | 2231 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2232 | { |
| mbed_official | 340:28d1f895c6fe | 2233 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2234 | { |
| mbed_official | 340:28d1f895c6fe | 2235 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2236 | } |
| mbed_official | 340:28d1f895c6fe | 2237 | /* Disable TXE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2238 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
| mbed_official | 340:28d1f895c6fe | 2239 | |
| mbed_official | 340:28d1f895c6fe | 2240 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2241 | { |
| mbed_official | 340:28d1f895c6fe | 2242 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2243 | } |
| mbed_official | 340:28d1f895c6fe | 2244 | } |
| mbed_official | 340:28d1f895c6fe | 2245 | } |
| mbed_official | 340:28d1f895c6fe | 2246 | |
| mbed_official | 340:28d1f895c6fe | 2247 | /** |
| mbed_official | 340:28d1f895c6fe | 2248 | * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2249 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2250 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2251 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2252 | */ |
| mbed_official | 340:28d1f895c6fe | 2253 | static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2254 | { |
| mbed_official | 340:28d1f895c6fe | 2255 | /* Receive data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2256 | *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 2257 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2258 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2259 | |
| mbed_official | 340:28d1f895c6fe | 2260 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2261 | { |
| mbed_official | 340:28d1f895c6fe | 2262 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2263 | { |
| mbed_official | 340:28d1f895c6fe | 2264 | hspi->RxISR = SPI_2linesRxISR_16BITCRC; |
| mbed_official | 340:28d1f895c6fe | 2265 | return; |
| mbed_official | 340:28d1f895c6fe | 2266 | } |
| mbed_official | 340:28d1f895c6fe | 2267 | |
| mbed_official | 340:28d1f895c6fe | 2268 | /* Disable RXNE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2269 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
| mbed_official | 340:28d1f895c6fe | 2270 | |
| mbed_official | 340:28d1f895c6fe | 2271 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2272 | { |
| mbed_official | 340:28d1f895c6fe | 2273 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2274 | } |
| mbed_official | 340:28d1f895c6fe | 2275 | } |
| mbed_official | 340:28d1f895c6fe | 2276 | } |
| mbed_official | 340:28d1f895c6fe | 2277 | |
| mbed_official | 340:28d1f895c6fe | 2278 | /** |
| mbed_official | 340:28d1f895c6fe | 2279 | * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2280 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2281 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2282 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2283 | */ |
| mbed_official | 340:28d1f895c6fe | 2284 | static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2285 | { |
| mbed_official | 340:28d1f895c6fe | 2286 | /* Receive data in 16 Bit mode */ |
| mbed_official | 441:d2c15dda23c1 | 2287 | __IO uint16_t tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 2288 | UNUSED(tmpreg); |
| mbed_official | 441:d2c15dda23c1 | 2289 | |
| mbed_official | 340:28d1f895c6fe | 2290 | /* Disable RXNE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2291 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); |
| mbed_official | 340:28d1f895c6fe | 2292 | |
| mbed_official | 340:28d1f895c6fe | 2293 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2294 | } |
| mbed_official | 340:28d1f895c6fe | 2295 | |
| mbed_official | 340:28d1f895c6fe | 2296 | /** |
| mbed_official | 340:28d1f895c6fe | 2297 | * @brief Tx Handler for Transmit and Receive in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2298 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2299 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2300 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2301 | */ |
| mbed_official | 340:28d1f895c6fe | 2302 | static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2303 | { |
| mbed_official | 340:28d1f895c6fe | 2304 | /* Transmit data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2305 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
| mbed_official | 340:28d1f895c6fe | 2306 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2307 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2308 | |
| mbed_official | 340:28d1f895c6fe | 2309 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 2310 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2311 | { |
| mbed_official | 340:28d1f895c6fe | 2312 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2313 | { |
| mbed_official | 340:28d1f895c6fe | 2314 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2315 | } |
| mbed_official | 340:28d1f895c6fe | 2316 | /* Disable TXE interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2317 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); |
| mbed_official | 340:28d1f895c6fe | 2318 | |
| mbed_official | 340:28d1f895c6fe | 2319 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2320 | { |
| mbed_official | 340:28d1f895c6fe | 2321 | SPI_CloseRxTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2322 | } |
| mbed_official | 340:28d1f895c6fe | 2323 | } |
| mbed_official | 340:28d1f895c6fe | 2324 | } |
| mbed_official | 340:28d1f895c6fe | 2325 | |
| mbed_official | 340:28d1f895c6fe | 2326 | /** |
| mbed_official | 340:28d1f895c6fe | 2327 | * @brief Manage the CRC receive in Interrupt context |
| mbed_official | 441:d2c15dda23c1 | 2328 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2329 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2330 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2331 | */ |
| mbed_official | 340:28d1f895c6fe | 2332 | static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2333 | { |
| mbed_official | 441:d2c15dda23c1 | 2334 | __IO uint8_t tmpreg = *((uint8_t*)&hspi->Instance->DR); |
| mbed_official | 441:d2c15dda23c1 | 2335 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 2336 | hspi->CRCSize--; |
| mbed_official | 340:28d1f895c6fe | 2337 | |
| mbed_official | 340:28d1f895c6fe | 2338 | if(hspi->CRCSize == 0) |
| mbed_official | 340:28d1f895c6fe | 2339 | { |
| mbed_official | 340:28d1f895c6fe | 2340 | SPI_CloseRx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2341 | } |
| mbed_official | 340:28d1f895c6fe | 2342 | } |
| mbed_official | 340:28d1f895c6fe | 2343 | |
| mbed_official | 340:28d1f895c6fe | 2344 | /** |
| mbed_official | 340:28d1f895c6fe | 2345 | * @brief Manage the recieve in Interrupt context |
| mbed_official | 441:d2c15dda23c1 | 2346 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2347 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2348 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2349 | */ |
| mbed_official | 340:28d1f895c6fe | 2350 | static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2351 | { |
| mbed_official | 340:28d1f895c6fe | 2352 | *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); |
| mbed_official | 340:28d1f895c6fe | 2353 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2354 | |
| mbed_official | 340:28d1f895c6fe | 2355 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 2356 | if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 2357 | { |
| mbed_official | 340:28d1f895c6fe | 2358 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2359 | } |
| mbed_official | 340:28d1f895c6fe | 2360 | |
| mbed_official | 340:28d1f895c6fe | 2361 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2362 | { |
| mbed_official | 340:28d1f895c6fe | 2363 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2364 | { |
| mbed_official | 340:28d1f895c6fe | 2365 | hspi->RxISR = SPI_RxISR_8BITCRC; |
| mbed_official | 340:28d1f895c6fe | 2366 | return; |
| mbed_official | 340:28d1f895c6fe | 2367 | } |
| mbed_official | 340:28d1f895c6fe | 2368 | SPI_CloseRx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2369 | } |
| mbed_official | 340:28d1f895c6fe | 2370 | } |
| mbed_official | 340:28d1f895c6fe | 2371 | |
| mbed_official | 340:28d1f895c6fe | 2372 | /** |
| mbed_official | 340:28d1f895c6fe | 2373 | * @brief Manage the CRC 16bit recieve in Interrupt context |
| mbed_official | 441:d2c15dda23c1 | 2374 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2375 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2376 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2377 | */ |
| mbed_official | 340:28d1f895c6fe | 2378 | static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2379 | { |
| mbed_official | 340:28d1f895c6fe | 2380 | __IO uint16_t tmpreg; |
| mbed_official | 340:28d1f895c6fe | 2381 | |
| mbed_official | 340:28d1f895c6fe | 2382 | tmpreg = hspi->Instance->DR; |
| mbed_official | 441:d2c15dda23c1 | 2383 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 2384 | |
| mbed_official | 340:28d1f895c6fe | 2385 | /* Disable RXNE and ERR interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2386 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 340:28d1f895c6fe | 2387 | |
| mbed_official | 340:28d1f895c6fe | 2388 | SPI_CloseRx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2389 | } |
| mbed_official | 340:28d1f895c6fe | 2390 | |
| mbed_official | 340:28d1f895c6fe | 2391 | /** |
| mbed_official | 340:28d1f895c6fe | 2392 | * @brief Manage the 16Bit recieve in Interrupt context |
| mbed_official | 441:d2c15dda23c1 | 2393 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2394 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2395 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2396 | */ |
| mbed_official | 340:28d1f895c6fe | 2397 | static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2398 | { |
| mbed_official | 340:28d1f895c6fe | 2399 | *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; |
| mbed_official | 340:28d1f895c6fe | 2400 | hspi->pRxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2401 | hspi->RxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2402 | |
| mbed_official | 340:28d1f895c6fe | 2403 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 2404 | if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 2405 | { |
| mbed_official | 340:28d1f895c6fe | 2406 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2407 | } |
| mbed_official | 340:28d1f895c6fe | 2408 | |
| mbed_official | 340:28d1f895c6fe | 2409 | if(hspi->RxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2410 | { |
| mbed_official | 340:28d1f895c6fe | 2411 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2412 | { |
| mbed_official | 340:28d1f895c6fe | 2413 | hspi->RxISR = SPI_RxISR_16BITCRC; |
| mbed_official | 340:28d1f895c6fe | 2414 | return; |
| mbed_official | 340:28d1f895c6fe | 2415 | } |
| mbed_official | 340:28d1f895c6fe | 2416 | SPI_CloseRx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2417 | } |
| mbed_official | 340:28d1f895c6fe | 2418 | } |
| mbed_official | 340:28d1f895c6fe | 2419 | |
| mbed_official | 340:28d1f895c6fe | 2420 | /** |
| mbed_official | 340:28d1f895c6fe | 2421 | * @brief Handle the data 8Bit transmit in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2422 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2423 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2424 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2425 | */ |
| mbed_official | 340:28d1f895c6fe | 2426 | static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2427 | { |
| mbed_official | 340:28d1f895c6fe | 2428 | *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); |
| mbed_official | 340:28d1f895c6fe | 2429 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2430 | |
| mbed_official | 340:28d1f895c6fe | 2431 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2432 | { |
| mbed_official | 340:28d1f895c6fe | 2433 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2434 | { |
| mbed_official | 340:28d1f895c6fe | 2435 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 2436 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2437 | } |
| mbed_official | 340:28d1f895c6fe | 2438 | SPI_CloseTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2439 | } |
| mbed_official | 340:28d1f895c6fe | 2440 | } |
| mbed_official | 340:28d1f895c6fe | 2441 | |
| mbed_official | 340:28d1f895c6fe | 2442 | /** |
| mbed_official | 340:28d1f895c6fe | 2443 | * @brief Handle the data 16Bit transmit in Interrupt mode |
| mbed_official | 441:d2c15dda23c1 | 2444 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2445 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2446 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2447 | */ |
| mbed_official | 340:28d1f895c6fe | 2448 | static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2449 | { |
| mbed_official | 340:28d1f895c6fe | 2450 | /* Transmit data in 16 Bit mode */ |
| mbed_official | 340:28d1f895c6fe | 2451 | hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); |
| mbed_official | 340:28d1f895c6fe | 2452 | hspi->pTxBuffPtr += sizeof(uint16_t); |
| mbed_official | 340:28d1f895c6fe | 2453 | hspi->TxXferCount--; |
| mbed_official | 340:28d1f895c6fe | 2454 | |
| mbed_official | 340:28d1f895c6fe | 2455 | if(hspi->TxXferCount == 0) |
| mbed_official | 340:28d1f895c6fe | 2456 | { |
| mbed_official | 340:28d1f895c6fe | 2457 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2458 | { |
| mbed_official | 340:28d1f895c6fe | 2459 | /* Enable CRC Transmission */ |
| mbed_official | 340:28d1f895c6fe | 2460 | hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; |
| mbed_official | 340:28d1f895c6fe | 2461 | } |
| mbed_official | 340:28d1f895c6fe | 2462 | SPI_CloseTx_ISR(hspi); |
| mbed_official | 340:28d1f895c6fe | 2463 | } |
| mbed_official | 340:28d1f895c6fe | 2464 | } |
| mbed_official | 340:28d1f895c6fe | 2465 | |
| mbed_official | 340:28d1f895c6fe | 2466 | /** |
| mbed_official | 340:28d1f895c6fe | 2467 | * @brief This function handles SPI Communication Timeout. |
| mbed_official | 441:d2c15dda23c1 | 2468 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2469 | * the configuration information for SPI module. |
| mbed_official | 340:28d1f895c6fe | 2470 | * @param Flag : SPI flag to check |
| mbed_official | 340:28d1f895c6fe | 2471 | * @param State : flag state to check |
| mbed_official | 340:28d1f895c6fe | 2472 | * @param Timeout : Timeout duration |
| mbed_official | 340:28d1f895c6fe | 2473 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 2474 | */ |
| mbed_official | 340:28d1f895c6fe | 2475 | static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 2476 | { |
| mbed_official | 340:28d1f895c6fe | 2477 | uint32_t tickstart = HAL_GetTick(); |
| mbed_official | 340:28d1f895c6fe | 2478 | |
| mbed_official | 340:28d1f895c6fe | 2479 | while((hspi->Instance->SR & Flag) != State) |
| mbed_official | 340:28d1f895c6fe | 2480 | { |
| mbed_official | 340:28d1f895c6fe | 2481 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 340:28d1f895c6fe | 2482 | { |
| mbed_official | 441:d2c15dda23c1 | 2483 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) |
| mbed_official | 340:28d1f895c6fe | 2484 | { |
| mbed_official | 340:28d1f895c6fe | 2485 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
| mbed_official | 340:28d1f895c6fe | 2486 | on both master and slave sides in order to resynchronize the master |
| mbed_official | 340:28d1f895c6fe | 2487 | and slave for their respective CRC calculation */ |
| mbed_official | 340:28d1f895c6fe | 2488 | |
| mbed_official | 340:28d1f895c6fe | 2489 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
| mbed_official | 340:28d1f895c6fe | 2490 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 340:28d1f895c6fe | 2491 | |
| mbed_official | 340:28d1f895c6fe | 2492 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
| mbed_official | 340:28d1f895c6fe | 2493 | { |
| mbed_official | 340:28d1f895c6fe | 2494 | /* Disable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 2495 | __HAL_SPI_DISABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 2496 | } |
| mbed_official | 340:28d1f895c6fe | 2497 | |
| mbed_official | 340:28d1f895c6fe | 2498 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 2499 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2500 | { |
| mbed_official | 340:28d1f895c6fe | 2501 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 2502 | } |
| mbed_official | 340:28d1f895c6fe | 2503 | |
| mbed_official | 340:28d1f895c6fe | 2504 | hspi->State= HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2505 | |
| mbed_official | 340:28d1f895c6fe | 2506 | /* Process Unlocked */ |
| mbed_official | 340:28d1f895c6fe | 2507 | __HAL_UNLOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 2508 | |
| mbed_official | 340:28d1f895c6fe | 2509 | return HAL_TIMEOUT; |
| mbed_official | 340:28d1f895c6fe | 2510 | } |
| mbed_official | 340:28d1f895c6fe | 2511 | } |
| mbed_official | 340:28d1f895c6fe | 2512 | } |
| mbed_official | 340:28d1f895c6fe | 2513 | |
| mbed_official | 340:28d1f895c6fe | 2514 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 2515 | } |
| mbed_official | 340:28d1f895c6fe | 2516 | |
| mbed_official | 340:28d1f895c6fe | 2517 | /** |
| mbed_official | 340:28d1f895c6fe | 2518 | * @brief This function handles SPI Communication Timeout. |
| mbed_official | 441:d2c15dda23c1 | 2519 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2520 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2521 | * @param Fifo : Fifo to check |
| mbed_official | 441:d2c15dda23c1 | 2522 | * @param State : Fifo state to check |
| mbed_official | 340:28d1f895c6fe | 2523 | * @param Timeout : Timeout duration |
| mbed_official | 340:28d1f895c6fe | 2524 | * @retval HAL status |
| mbed_official | 340:28d1f895c6fe | 2525 | */ |
| mbed_official | 340:28d1f895c6fe | 2526 | static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 2527 | { |
| mbed_official | 340:28d1f895c6fe | 2528 | __IO uint8_t tmpreg; |
| mbed_official | 340:28d1f895c6fe | 2529 | uint32_t tickstart = HAL_GetTick(); |
| mbed_official | 340:28d1f895c6fe | 2530 | |
| mbed_official | 340:28d1f895c6fe | 2531 | while((hspi->Instance->SR & Fifo) != State) |
| mbed_official | 340:28d1f895c6fe | 2532 | { |
| mbed_official | 340:28d1f895c6fe | 2533 | if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) |
| mbed_official | 340:28d1f895c6fe | 2534 | { |
| mbed_official | 340:28d1f895c6fe | 2535 | tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); |
| mbed_official | 441:d2c15dda23c1 | 2536 | UNUSED(tmpreg); |
| mbed_official | 340:28d1f895c6fe | 2537 | } |
| mbed_official | 441:d2c15dda23c1 | 2538 | |
| mbed_official | 340:28d1f895c6fe | 2539 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 340:28d1f895c6fe | 2540 | { |
| mbed_official | 441:d2c15dda23c1 | 2541 | if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout)) |
| mbed_official | 340:28d1f895c6fe | 2542 | { |
| mbed_official | 340:28d1f895c6fe | 2543 | /* Disable the SPI and reset the CRC: the CRC value should be cleared |
| mbed_official | 441:d2c15dda23c1 | 2544 | on both master and slave sides in order to resynchronize the master |
| mbed_official | 441:d2c15dda23c1 | 2545 | and slave for their respective CRC calculation */ |
| mbed_official | 340:28d1f895c6fe | 2546 | |
| mbed_official | 340:28d1f895c6fe | 2547 | /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ |
| mbed_official | 340:28d1f895c6fe | 2548 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 340:28d1f895c6fe | 2549 | |
| mbed_official | 340:28d1f895c6fe | 2550 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
| mbed_official | 340:28d1f895c6fe | 2551 | { |
| mbed_official | 340:28d1f895c6fe | 2552 | /* Disable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 2553 | __HAL_SPI_DISABLE(hspi); |
| mbed_official | 340:28d1f895c6fe | 2554 | } |
| mbed_official | 340:28d1f895c6fe | 2555 | |
| mbed_official | 340:28d1f895c6fe | 2556 | /* Reset CRC Calculation */ |
| mbed_official | 340:28d1f895c6fe | 2557 | if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) |
| mbed_official | 340:28d1f895c6fe | 2558 | { |
| mbed_official | 340:28d1f895c6fe | 2559 | __HAL_SPI_RESET_CRC(hspi); |
| mbed_official | 340:28d1f895c6fe | 2560 | } |
| mbed_official | 340:28d1f895c6fe | 2561 | |
| mbed_official | 340:28d1f895c6fe | 2562 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2563 | |
| mbed_official | 340:28d1f895c6fe | 2564 | /* Process Unlocked */ |
| mbed_official | 340:28d1f895c6fe | 2565 | __HAL_UNLOCK(hspi); |
| mbed_official | 340:28d1f895c6fe | 2566 | |
| mbed_official | 340:28d1f895c6fe | 2567 | return HAL_TIMEOUT; |
| mbed_official | 340:28d1f895c6fe | 2568 | } |
| mbed_official | 340:28d1f895c6fe | 2569 | } |
| mbed_official | 340:28d1f895c6fe | 2570 | } |
| mbed_official | 340:28d1f895c6fe | 2571 | |
| mbed_official | 340:28d1f895c6fe | 2572 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 2573 | } |
| mbed_official | 340:28d1f895c6fe | 2574 | |
| mbed_official | 340:28d1f895c6fe | 2575 | /** |
| mbed_official | 340:28d1f895c6fe | 2576 | * @brief This function handles the check of the RX transaction complete. |
| mbed_official | 441:d2c15dda23c1 | 2577 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2578 | * the configuration information for SPI module. |
| mbed_official | 340:28d1f895c6fe | 2579 | * @param Timeout : Timeout duration |
| mbed_official | 441:d2c15dda23c1 | 2580 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2581 | */ |
| mbed_official | 340:28d1f895c6fe | 2582 | static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout) |
| mbed_official | 340:28d1f895c6fe | 2583 | { |
| mbed_official | 340:28d1f895c6fe | 2584 | if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) |
| mbed_official | 340:28d1f895c6fe | 2585 | { |
| mbed_official | 340:28d1f895c6fe | 2586 | /* Disable SPI peripheral */ |
| mbed_official | 340:28d1f895c6fe | 2587 | __HAL_SPI_DISABLE(hspi); |
| mbed_official | 441:d2c15dda23c1 | 2588 | |
| mbed_official | 441:d2c15dda23c1 | 2589 | if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 2590 | { |
| mbed_official | 441:d2c15dda23c1 | 2591 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
| mbed_official | 441:d2c15dda23c1 | 2592 | return HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 2593 | } |
| mbed_official | 441:d2c15dda23c1 | 2594 | if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK) |
| mbed_official | 441:d2c15dda23c1 | 2595 | { |
| mbed_official | 441:d2c15dda23c1 | 2596 | hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; |
| mbed_official | 441:d2c15dda23c1 | 2597 | return HAL_TIMEOUT; |
| mbed_official | 441:d2c15dda23c1 | 2598 | } |
| mbed_official | 441:d2c15dda23c1 | 2599 | } |
| mbed_official | 340:28d1f895c6fe | 2600 | return HAL_OK; |
| mbed_official | 340:28d1f895c6fe | 2601 | } |
| mbed_official | 340:28d1f895c6fe | 2602 | |
| mbed_official | 340:28d1f895c6fe | 2603 | /** |
| mbed_official | 340:28d1f895c6fe | 2604 | * @brief This function handles the close of the RXTX transaction. |
| mbed_official | 441:d2c15dda23c1 | 2605 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2606 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2607 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2608 | */ |
| mbed_official | 340:28d1f895c6fe | 2609 | static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2610 | { |
| mbed_official | 340:28d1f895c6fe | 2611 | /* Disable ERR interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2612 | __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); |
| mbed_official | 340:28d1f895c6fe | 2613 | |
| mbed_official | 340:28d1f895c6fe | 2614 | /* Check if CRC error occurred */ |
| mbed_official | 340:28d1f895c6fe | 2615 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 340:28d1f895c6fe | 2616 | { |
| mbed_official | 340:28d1f895c6fe | 2617 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2618 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 2619 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 2620 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2621 | } |
| mbed_official | 340:28d1f895c6fe | 2622 | else |
| mbed_official | 340:28d1f895c6fe | 2623 | { |
| mbed_official | 340:28d1f895c6fe | 2624 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 2625 | { |
| mbed_official | 340:28d1f895c6fe | 2626 | if(hspi->State == HAL_SPI_STATE_BUSY_RX) |
| mbed_official | 340:28d1f895c6fe | 2627 | { |
| mbed_official | 340:28d1f895c6fe | 2628 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2629 | HAL_SPI_RxCpltCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2630 | } |
| mbed_official | 340:28d1f895c6fe | 2631 | else |
| mbed_official | 340:28d1f895c6fe | 2632 | { |
| mbed_official | 340:28d1f895c6fe | 2633 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2634 | HAL_SPI_TxRxCpltCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2635 | } |
| mbed_official | 340:28d1f895c6fe | 2636 | } |
| mbed_official | 340:28d1f895c6fe | 2637 | else |
| mbed_official | 340:28d1f895c6fe | 2638 | { |
| mbed_official | 340:28d1f895c6fe | 2639 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2640 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2641 | } |
| mbed_official | 340:28d1f895c6fe | 2642 | } |
| mbed_official | 340:28d1f895c6fe | 2643 | } |
| mbed_official | 340:28d1f895c6fe | 2644 | |
| mbed_official | 340:28d1f895c6fe | 2645 | /** |
| mbed_official | 340:28d1f895c6fe | 2646 | * @brief This function handles the close of the RX transaction. |
| mbed_official | 441:d2c15dda23c1 | 2647 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2648 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2649 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2650 | */ |
| mbed_official | 340:28d1f895c6fe | 2651 | static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2652 | { |
| mbed_official | 340:28d1f895c6fe | 2653 | /* Disable RXNE and ERR interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2654 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); |
| mbed_official | 340:28d1f895c6fe | 2655 | |
| mbed_official | 340:28d1f895c6fe | 2656 | /* Check the end of the transaction */ |
| mbed_official | 340:28d1f895c6fe | 2657 | SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); |
| mbed_official | 340:28d1f895c6fe | 2658 | |
| mbed_official | 340:28d1f895c6fe | 2659 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2660 | |
| mbed_official | 340:28d1f895c6fe | 2661 | /* Check if CRC error occurred */ |
| mbed_official | 340:28d1f895c6fe | 2662 | if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) |
| mbed_official | 340:28d1f895c6fe | 2663 | { |
| mbed_official | 340:28d1f895c6fe | 2664 | hspi->ErrorCode|= HAL_SPI_ERROR_CRC; |
| mbed_official | 340:28d1f895c6fe | 2665 | __HAL_SPI_CLEAR_CRCERRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 2666 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2667 | } |
| mbed_official | 340:28d1f895c6fe | 2668 | else |
| mbed_official | 340:28d1f895c6fe | 2669 | { |
| mbed_official | 340:28d1f895c6fe | 2670 | if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 2671 | { |
| mbed_official | 340:28d1f895c6fe | 2672 | HAL_SPI_RxCpltCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2673 | } |
| mbed_official | 340:28d1f895c6fe | 2674 | else |
| mbed_official | 340:28d1f895c6fe | 2675 | { |
| mbed_official | 340:28d1f895c6fe | 2676 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2677 | } |
| mbed_official | 340:28d1f895c6fe | 2678 | } |
| mbed_official | 340:28d1f895c6fe | 2679 | } |
| mbed_official | 340:28d1f895c6fe | 2680 | |
| mbed_official | 340:28d1f895c6fe | 2681 | /** |
| mbed_official | 340:28d1f895c6fe | 2682 | * @brief This function handles the close of the TX transaction. |
| mbed_official | 441:d2c15dda23c1 | 2683 | * @param hspi : pointer to a SPI_HandleTypeDef structure that contains |
| mbed_official | 441:d2c15dda23c1 | 2684 | * the configuration information for SPI module. |
| mbed_official | 441:d2c15dda23c1 | 2685 | * @retval None. |
| mbed_official | 340:28d1f895c6fe | 2686 | */ |
| mbed_official | 340:28d1f895c6fe | 2687 | static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) |
| mbed_official | 340:28d1f895c6fe | 2688 | { |
| mbed_official | 340:28d1f895c6fe | 2689 | /* Disable TXE and ERR interrupt */ |
| mbed_official | 340:28d1f895c6fe | 2690 | __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); |
| mbed_official | 340:28d1f895c6fe | 2691 | |
| mbed_official | 340:28d1f895c6fe | 2692 | /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ |
| mbed_official | 340:28d1f895c6fe | 2693 | if(hspi->Init.Direction == SPI_DIRECTION_2LINES) |
| mbed_official | 340:28d1f895c6fe | 2694 | { |
| mbed_official | 340:28d1f895c6fe | 2695 | __HAL_SPI_CLEAR_OVRFLAG(hspi); |
| mbed_official | 340:28d1f895c6fe | 2696 | } |
| mbed_official | 340:28d1f895c6fe | 2697 | |
| mbed_official | 340:28d1f895c6fe | 2698 | hspi->State = HAL_SPI_STATE_READY; |
| mbed_official | 340:28d1f895c6fe | 2699 | if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 2700 | { |
| mbed_official | 340:28d1f895c6fe | 2701 | HAL_SPI_ErrorCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2702 | } |
| mbed_official | 340:28d1f895c6fe | 2703 | else |
| mbed_official | 340:28d1f895c6fe | 2704 | { |
| mbed_official | 340:28d1f895c6fe | 2705 | HAL_SPI_TxCpltCallback(hspi); |
| mbed_official | 340:28d1f895c6fe | 2706 | } |
| mbed_official | 340:28d1f895c6fe | 2707 | } |
| mbed_official | 340:28d1f895c6fe | 2708 | |
| mbed_official | 340:28d1f895c6fe | 2709 | /** |
| mbed_official | 340:28d1f895c6fe | 2710 | * @} |
| mbed_official | 340:28d1f895c6fe | 2711 | */ |
| mbed_official | 340:28d1f895c6fe | 2712 | |
| mbed_official | 340:28d1f895c6fe | 2713 | #endif /* HAL_SPI_MODULE_ENABLED */ |
| mbed_official | 340:28d1f895c6fe | 2714 | /** |
| mbed_official | 340:28d1f895c6fe | 2715 | * @} |
| mbed_official | 340:28d1f895c6fe | 2716 | */ |
| mbed_official | 340:28d1f895c6fe | 2717 | |
| mbed_official | 340:28d1f895c6fe | 2718 | /** |
| mbed_official | 340:28d1f895c6fe | 2719 | * @} |
| mbed_official | 340:28d1f895c6fe | 2720 | */ |
| mbed_official | 340:28d1f895c6fe | 2721 | |
| mbed_official | 340:28d1f895c6fe | 2722 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |