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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:
moirans2
Date:
Wed Jan 14 20:53:08 2015 +0000
Revision:
445:9a3ffe6cfa19
Parent:
441:d2c15dda23c1 
internal clock stm32L051

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_dma.h
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 441:d2c15dda23c1 5 * @version V1.2.0
mbed_official 441:d2c15dda23c1 6 * @date 11-December-2014
mbed_official 340:28d1f895c6fe 7 * @brief Header file of DMA HAL module.
mbed_official 340:28d1f895c6fe 8 ******************************************************************************
mbed_official 340:28d1f895c6fe 9 * @attention
mbed_official 340:28d1f895c6fe 10 *
mbed_official 340:28d1f895c6fe 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 12 *
mbed_official 340:28d1f895c6fe 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 14 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 16 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 19 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 21 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 22 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 23 *
mbed_official 340:28d1f895c6fe 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 34 *
mbed_official 340:28d1f895c6fe 35 ******************************************************************************
mbed_official 340:28d1f895c6fe 36 */
mbed_official 340:28d1f895c6fe 37
mbed_official 340:28d1f895c6fe 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 340:28d1f895c6fe 39 #ifndef __STM32F0xx_HAL_DMA_H
mbed_official 340:28d1f895c6fe 40 #define __STM32F0xx_HAL_DMA_H
mbed_official 340:28d1f895c6fe 41
mbed_official 340:28d1f895c6fe 42 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 43 extern "C" {
mbed_official 340:28d1f895c6fe 44 #endif
mbed_official 340:28d1f895c6fe 45
mbed_official 340:28d1f895c6fe 46 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 47 #include "stm32f0xx_hal_def.h"
mbed_official 340:28d1f895c6fe 48
mbed_official 340:28d1f895c6fe 49 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 50 * @{
mbed_official 340:28d1f895c6fe 51 */
mbed_official 340:28d1f895c6fe 52
mbed_official 340:28d1f895c6fe 53 /** @addtogroup DMA
mbed_official 340:28d1f895c6fe 54 * @{
mbed_official 340:28d1f895c6fe 55 */
mbed_official 340:28d1f895c6fe 56
mbed_official 340:28d1f895c6fe 57 /* Exported types ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 58 /** @defgroup DMA_Exported_Types DMA Exported Types
mbed_official 340:28d1f895c6fe 59 * @{
mbed_official 340:28d1f895c6fe 60 */
mbed_official 340:28d1f895c6fe 61
mbed_official 340:28d1f895c6fe 62 /**
mbed_official 340:28d1f895c6fe 63 * @brief DMA Configuration Structure definition
mbed_official 340:28d1f895c6fe 64 */
mbed_official 340:28d1f895c6fe 65 typedef struct
mbed_official 340:28d1f895c6fe 66 {
mbed_official 340:28d1f895c6fe 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
mbed_official 340:28d1f895c6fe 68 from memory to memory or from peripheral to memory.
mbed_official 340:28d1f895c6fe 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
mbed_official 340:28d1f895c6fe 70
mbed_official 340:28d1f895c6fe 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
mbed_official 340:28d1f895c6fe 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
mbed_official 340:28d1f895c6fe 73
mbed_official 340:28d1f895c6fe 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
mbed_official 340:28d1f895c6fe 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
mbed_official 340:28d1f895c6fe 76
mbed_official 340:28d1f895c6fe 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
mbed_official 340:28d1f895c6fe 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
mbed_official 340:28d1f895c6fe 79
mbed_official 340:28d1f895c6fe 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
mbed_official 340:28d1f895c6fe 81 This parameter can be a value of @ref DMA_Memory_data_size */
mbed_official 340:28d1f895c6fe 82
mbed_official 340:28d1f895c6fe 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
mbed_official 340:28d1f895c6fe 84 This parameter can be a value of @ref DMA_mode
mbed_official 340:28d1f895c6fe 85 @note The circular buffer mode cannot be used if the memory-to-memory
mbed_official 340:28d1f895c6fe 86 data transfer is configured on the selected Channel */
mbed_official 340:28d1f895c6fe 87
mbed_official 340:28d1f895c6fe 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
mbed_official 340:28d1f895c6fe 89 This parameter can be a value of @ref DMA_Priority_level */
mbed_official 340:28d1f895c6fe 90
mbed_official 340:28d1f895c6fe 91 } DMA_InitTypeDef;
mbed_official 340:28d1f895c6fe 92
mbed_official 340:28d1f895c6fe 93 /**
mbed_official 340:28d1f895c6fe 94 * @brief DMA Configuration enumeration values definition
mbed_official 340:28d1f895c6fe 95 */
mbed_official 340:28d1f895c6fe 96 typedef enum
mbed_official 340:28d1f895c6fe 97 {
mbed_official 340:28d1f895c6fe 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
mbed_official 340:28d1f895c6fe 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
mbed_official 340:28d1f895c6fe 100
mbed_official 340:28d1f895c6fe 101 } DMA_ControlTypeDef;
mbed_official 340:28d1f895c6fe 102
mbed_official 340:28d1f895c6fe 103 /**
mbed_official 340:28d1f895c6fe 104 * @brief HAL DMA State structures definition
mbed_official 340:28d1f895c6fe 105 */
mbed_official 340:28d1f895c6fe 106 typedef enum
mbed_official 340:28d1f895c6fe 107 {
mbed_official 340:28d1f895c6fe 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
mbed_official 340:28d1f895c6fe 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
mbed_official 340:28d1f895c6fe 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
mbed_official 340:28d1f895c6fe 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
mbed_official 340:28d1f895c6fe 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
mbed_official 340:28d1f895c6fe 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
mbed_official 340:28d1f895c6fe 114
mbed_official 340:28d1f895c6fe 115 }HAL_DMA_StateTypeDef;
mbed_official 340:28d1f895c6fe 116
mbed_official 340:28d1f895c6fe 117 /**
mbed_official 340:28d1f895c6fe 118 * @brief HAL DMA Error Code structure definition
mbed_official 340:28d1f895c6fe 119 */
mbed_official 340:28d1f895c6fe 120 typedef enum
mbed_official 340:28d1f895c6fe 121 {
mbed_official 340:28d1f895c6fe 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
mbed_official 340:28d1f895c6fe 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
mbed_official 340:28d1f895c6fe 124
mbed_official 340:28d1f895c6fe 125 }HAL_DMA_LevelCompleteTypeDef;
mbed_official 340:28d1f895c6fe 126
mbed_official 340:28d1f895c6fe 127
mbed_official 340:28d1f895c6fe 128 /**
mbed_official 340:28d1f895c6fe 129 * @brief DMA handle Structure definition
mbed_official 340:28d1f895c6fe 130 */
mbed_official 340:28d1f895c6fe 131 typedef struct __DMA_HandleTypeDef
mbed_official 340:28d1f895c6fe 132 {
mbed_official 340:28d1f895c6fe 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
mbed_official 340:28d1f895c6fe 134
mbed_official 340:28d1f895c6fe 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
mbed_official 340:28d1f895c6fe 136
mbed_official 340:28d1f895c6fe 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
mbed_official 340:28d1f895c6fe 138
mbed_official 340:28d1f895c6fe 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
mbed_official 340:28d1f895c6fe 140
mbed_official 340:28d1f895c6fe 141 void *Parent; /*!< Parent object state */
mbed_official 340:28d1f895c6fe 142
mbed_official 340:28d1f895c6fe 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
mbed_official 340:28d1f895c6fe 144
mbed_official 340:28d1f895c6fe 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
mbed_official 340:28d1f895c6fe 146
mbed_official 340:28d1f895c6fe 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
mbed_official 340:28d1f895c6fe 148
mbed_official 340:28d1f895c6fe 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
mbed_official 340:28d1f895c6fe 150
mbed_official 340:28d1f895c6fe 151 } DMA_HandleTypeDef;
mbed_official 340:28d1f895c6fe 152 /**
mbed_official 340:28d1f895c6fe 153 * @}
mbed_official 340:28d1f895c6fe 154 */
mbed_official 340:28d1f895c6fe 155
mbed_official 340:28d1f895c6fe 156 /* Exported constants --------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
mbed_official 340:28d1f895c6fe 158 * @{
mbed_official 340:28d1f895c6fe 159 */
mbed_official 340:28d1f895c6fe 160
mbed_official 340:28d1f895c6fe 161 /** @defgroup DMA_Error_Code DMA Error Code
mbed_official 340:28d1f895c6fe 162 * @{
mbed_official 340:28d1f895c6fe 163 */
mbed_official 340:28d1f895c6fe 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
mbed_official 340:28d1f895c6fe 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
mbed_official 340:28d1f895c6fe 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
mbed_official 340:28d1f895c6fe 167 /**
mbed_official 340:28d1f895c6fe 168 * @}
mbed_official 340:28d1f895c6fe 169 */
mbed_official 340:28d1f895c6fe 170
mbed_official 340:28d1f895c6fe 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
mbed_official 340:28d1f895c6fe 172 * @{
mbed_official 340:28d1f895c6fe 173 */
mbed_official 340:28d1f895c6fe 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
mbed_official 340:28d1f895c6fe 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
mbed_official 340:28d1f895c6fe 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
mbed_official 340:28d1f895c6fe 177
mbed_official 340:28d1f895c6fe 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
mbed_official 340:28d1f895c6fe 179 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
mbed_official 340:28d1f895c6fe 180 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
mbed_official 340:28d1f895c6fe 181 /**
mbed_official 340:28d1f895c6fe 182 * @}
mbed_official 340:28d1f895c6fe 183 */
mbed_official 340:28d1f895c6fe 184
mbed_official 340:28d1f895c6fe 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
mbed_official 340:28d1f895c6fe 186 * @{
mbed_official 340:28d1f895c6fe 187 */
mbed_official 340:28d1f895c6fe 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
mbed_official 340:28d1f895c6fe 189 /**
mbed_official 340:28d1f895c6fe 190 * @}
mbed_official 340:28d1f895c6fe 191 */
mbed_official 340:28d1f895c6fe 192
mbed_official 340:28d1f895c6fe 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
mbed_official 340:28d1f895c6fe 194 * @{
mbed_official 340:28d1f895c6fe 195 */
mbed_official 340:28d1f895c6fe 196 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
mbed_official 340:28d1f895c6fe 197 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
mbed_official 340:28d1f895c6fe 198
mbed_official 340:28d1f895c6fe 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
mbed_official 340:28d1f895c6fe 200 ((STATE) == DMA_PINC_DISABLE))
mbed_official 340:28d1f895c6fe 201 /**
mbed_official 340:28d1f895c6fe 202 * @}
mbed_official 340:28d1f895c6fe 203 */
mbed_official 340:28d1f895c6fe 204
mbed_official 340:28d1f895c6fe 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
mbed_official 340:28d1f895c6fe 206 * @{
mbed_official 340:28d1f895c6fe 207 */
mbed_official 340:28d1f895c6fe 208 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
mbed_official 340:28d1f895c6fe 209 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
mbed_official 340:28d1f895c6fe 210
mbed_official 340:28d1f895c6fe 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
mbed_official 340:28d1f895c6fe 212 ((STATE) == DMA_MINC_DISABLE))
mbed_official 340:28d1f895c6fe 213 /**
mbed_official 340:28d1f895c6fe 214 * @}
mbed_official 340:28d1f895c6fe 215 */
mbed_official 340:28d1f895c6fe 216
mbed_official 340:28d1f895c6fe 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
mbed_official 340:28d1f895c6fe 218 * @{
mbed_official 340:28d1f895c6fe 219 */
mbed_official 340:28d1f895c6fe 220 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
mbed_official 340:28d1f895c6fe 221 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
mbed_official 340:28d1f895c6fe 222 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
mbed_official 340:28d1f895c6fe 223
mbed_official 340:28d1f895c6fe 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
mbed_official 340:28d1f895c6fe 225 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
mbed_official 340:28d1f895c6fe 226 ((SIZE) == DMA_PDATAALIGN_WORD))
mbed_official 340:28d1f895c6fe 227 /**
mbed_official 340:28d1f895c6fe 228 * @}
mbed_official 340:28d1f895c6fe 229 */
mbed_official 340:28d1f895c6fe 230
mbed_official 340:28d1f895c6fe 231
mbed_official 340:28d1f895c6fe 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
mbed_official 340:28d1f895c6fe 233 * @{
mbed_official 340:28d1f895c6fe 234 */
mbed_official 340:28d1f895c6fe 235 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
mbed_official 340:28d1f895c6fe 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
mbed_official 340:28d1f895c6fe 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
mbed_official 340:28d1f895c6fe 238
mbed_official 340:28d1f895c6fe 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
mbed_official 340:28d1f895c6fe 240 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
mbed_official 340:28d1f895c6fe 241 ((SIZE) == DMA_MDATAALIGN_WORD ))
mbed_official 340:28d1f895c6fe 242 /**
mbed_official 340:28d1f895c6fe 243 * @}
mbed_official 340:28d1f895c6fe 244 */
mbed_official 340:28d1f895c6fe 245
mbed_official 340:28d1f895c6fe 246 /** @defgroup DMA_mode DMA mode
mbed_official 340:28d1f895c6fe 247 * @{
mbed_official 340:28d1f895c6fe 248 */
mbed_official 340:28d1f895c6fe 249 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
mbed_official 340:28d1f895c6fe 250 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
mbed_official 340:28d1f895c6fe 251
mbed_official 340:28d1f895c6fe 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
mbed_official 340:28d1f895c6fe 253 ((MODE) == DMA_CIRCULAR))
mbed_official 340:28d1f895c6fe 254 /**
mbed_official 340:28d1f895c6fe 255 * @}
mbed_official 340:28d1f895c6fe 256 */
mbed_official 340:28d1f895c6fe 257
mbed_official 340:28d1f895c6fe 258 /** @defgroup DMA_Priority_level DMA Priority level
mbed_official 340:28d1f895c6fe 259 * @{
mbed_official 340:28d1f895c6fe 260 */
mbed_official 340:28d1f895c6fe 261 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
mbed_official 340:28d1f895c6fe 262 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
mbed_official 340:28d1f895c6fe 263 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
mbed_official 340:28d1f895c6fe 264 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
mbed_official 340:28d1f895c6fe 265
mbed_official 340:28d1f895c6fe 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
mbed_official 340:28d1f895c6fe 267 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
mbed_official 340:28d1f895c6fe 268 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
mbed_official 340:28d1f895c6fe 269 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
mbed_official 340:28d1f895c6fe 270 /**
mbed_official 340:28d1f895c6fe 271 * @}
mbed_official 340:28d1f895c6fe 272 */
mbed_official 340:28d1f895c6fe 273
mbed_official 340:28d1f895c6fe 274
mbed_official 340:28d1f895c6fe 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
mbed_official 340:28d1f895c6fe 276 * @{
mbed_official 340:28d1f895c6fe 277 */
mbed_official 340:28d1f895c6fe 278
mbed_official 340:28d1f895c6fe 279 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
mbed_official 340:28d1f895c6fe 280 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
mbed_official 340:28d1f895c6fe 281 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
mbed_official 340:28d1f895c6fe 282
mbed_official 340:28d1f895c6fe 283 /**
mbed_official 340:28d1f895c6fe 284 * @}
mbed_official 340:28d1f895c6fe 285 */
mbed_official 340:28d1f895c6fe 286
mbed_official 340:28d1f895c6fe 287 /** @defgroup DMA_flag_definitions DMA flag definitions
mbed_official 340:28d1f895c6fe 288 * @{
mbed_official 340:28d1f895c6fe 289 */
mbed_official 340:28d1f895c6fe 290
mbed_official 441:d2c15dda23c1 291 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
mbed_official 441:d2c15dda23c1 292 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
mbed_official 441:d2c15dda23c1 293 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
mbed_official 441:d2c15dda23c1 294 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
mbed_official 441:d2c15dda23c1 295 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
mbed_official 441:d2c15dda23c1 296 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
mbed_official 441:d2c15dda23c1 297 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
mbed_official 441:d2c15dda23c1 298 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
mbed_official 441:d2c15dda23c1 299 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
mbed_official 441:d2c15dda23c1 300 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
mbed_official 441:d2c15dda23c1 301 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
mbed_official 441:d2c15dda23c1 302 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
mbed_official 441:d2c15dda23c1 303 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
mbed_official 441:d2c15dda23c1 304 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
mbed_official 441:d2c15dda23c1 305 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
mbed_official 441:d2c15dda23c1 306 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
mbed_official 441:d2c15dda23c1 307 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
mbed_official 441:d2c15dda23c1 308 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
mbed_official 441:d2c15dda23c1 309 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
mbed_official 441:d2c15dda23c1 310 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
mbed_official 441:d2c15dda23c1 311 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
mbed_official 441:d2c15dda23c1 312 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
mbed_official 441:d2c15dda23c1 313 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
mbed_official 441:d2c15dda23c1 314 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
mbed_official 441:d2c15dda23c1 315 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
mbed_official 441:d2c15dda23c1 316 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
mbed_official 441:d2c15dda23c1 317 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
mbed_official 441:d2c15dda23c1 318 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
mbed_official 340:28d1f895c6fe 319
mbed_official 340:28d1f895c6fe 320
mbed_official 340:28d1f895c6fe 321 /**
mbed_official 340:28d1f895c6fe 322 * @}
mbed_official 340:28d1f895c6fe 323 */
mbed_official 340:28d1f895c6fe 324
mbed_official 340:28d1f895c6fe 325 /**
mbed_official 340:28d1f895c6fe 326 * @}
mbed_official 340:28d1f895c6fe 327 */
mbed_official 340:28d1f895c6fe 328
mbed_official 340:28d1f895c6fe 329 /* Exported macros -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
mbed_official 340:28d1f895c6fe 331 * @{
mbed_official 340:28d1f895c6fe 332 */
mbed_official 340:28d1f895c6fe 333
mbed_official 340:28d1f895c6fe 334 /** @brief Reset DMA handle state
mbed_official 340:28d1f895c6fe 335 * @param __HANDLE__: DMA handle.
mbed_official 340:28d1f895c6fe 336 * @retval None
mbed_official 340:28d1f895c6fe 337 */
mbed_official 340:28d1f895c6fe 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
mbed_official 340:28d1f895c6fe 339
mbed_official 340:28d1f895c6fe 340 /**
mbed_official 340:28d1f895c6fe 341 * @brief Enable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 342 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 343 * @retval None.
mbed_official 340:28d1f895c6fe 344 */
mbed_official 340:28d1f895c6fe 345 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
mbed_official 340:28d1f895c6fe 346
mbed_official 340:28d1f895c6fe 347 /**
mbed_official 340:28d1f895c6fe 348 * @brief Disable the specified DMA Channel.
mbed_official 340:28d1f895c6fe 349 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 350 * @retval None.
mbed_official 340:28d1f895c6fe 351 */
mbed_official 340:28d1f895c6fe 352 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
mbed_official 340:28d1f895c6fe 353
mbed_official 340:28d1f895c6fe 354
mbed_official 340:28d1f895c6fe 355 /* Interrupt & Flag management */
mbed_official 340:28d1f895c6fe 356
mbed_official 340:28d1f895c6fe 357 /**
mbed_official 340:28d1f895c6fe 358 * @brief Enables the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 359 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 360 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 340:28d1f895c6fe 361 * This parameter can be any combination of the following values:
mbed_official 340:28d1f895c6fe 362 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 363 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 364 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 365 * @retval None
mbed_official 340:28d1f895c6fe 366 */
mbed_official 340:28d1f895c6fe 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
mbed_official 340:28d1f895c6fe 368
mbed_official 340:28d1f895c6fe 369 /**
mbed_official 340:28d1f895c6fe 370 * @brief Disables the specified DMA Channel interrupts.
mbed_official 340:28d1f895c6fe 371 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 372 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
mbed_official 340:28d1f895c6fe 373 * This parameter can be any combination of the following values:
mbed_official 340:28d1f895c6fe 374 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 375 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 376 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 377 * @retval None
mbed_official 340:28d1f895c6fe 378 */
mbed_official 340:28d1f895c6fe 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
mbed_official 340:28d1f895c6fe 380
mbed_official 340:28d1f895c6fe 381 /**
mbed_official 340:28d1f895c6fe 382 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
mbed_official 340:28d1f895c6fe 383 * @param __HANDLE__: DMA handle
mbed_official 340:28d1f895c6fe 384 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
mbed_official 340:28d1f895c6fe 385 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
mbed_official 340:28d1f895c6fe 388 * @arg DMA_IT_TE: Transfer error interrupt mask
mbed_official 340:28d1f895c6fe 389 * @retval The state of DMA_IT (SET or RESET).
mbed_official 340:28d1f895c6fe 390 */
mbed_official 340:28d1f895c6fe 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official 340:28d1f895c6fe 392
mbed_official 340:28d1f895c6fe 393 /**
mbed_official 340:28d1f895c6fe 394 * @}
mbed_official 340:28d1f895c6fe 395 */
mbed_official 340:28d1f895c6fe 396
mbed_official 340:28d1f895c6fe 397 /* Include DMA HAL Extension module */
mbed_official 340:28d1f895c6fe 398 #include "stm32f0xx_hal_dma_ex.h"
mbed_official 340:28d1f895c6fe 399
mbed_official 340:28d1f895c6fe 400 /* Exported functions --------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
mbed_official 340:28d1f895c6fe 402 * @{
mbed_official 340:28d1f895c6fe 403 */
mbed_official 340:28d1f895c6fe 404 /** @addtogroup DMA_Exported_Functions_Group1
mbed_official 340:28d1f895c6fe 405 * @brief Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 406 * @{
mbed_official 340:28d1f895c6fe 407 */
mbed_official 340:28d1f895c6fe 408 /* Initialization and de-initialization functions *****************************/
mbed_official 340:28d1f895c6fe 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 411 /**
mbed_official 340:28d1f895c6fe 412 * @}
mbed_official 340:28d1f895c6fe 413 */
mbed_official 340:28d1f895c6fe 414
mbed_official 340:28d1f895c6fe 415 /** @addtogroup DMA_Exported_Functions_Group2
mbed_official 340:28d1f895c6fe 416 * @brief I/O operation functions
mbed_official 340:28d1f895c6fe 417 * @{
mbed_official 340:28d1f895c6fe 418 */
mbed_official 340:28d1f895c6fe 419 /* IO operation functions *****************************************************/
mbed_official 340:28d1f895c6fe 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 340:28d1f895c6fe 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
mbed_official 340:28d1f895c6fe 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
mbed_official 340:28d1f895c6fe 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 425 /**
mbed_official 340:28d1f895c6fe 426 * @}
mbed_official 340:28d1f895c6fe 427 */
mbed_official 340:28d1f895c6fe 428
mbed_official 340:28d1f895c6fe 429 /* Peripheral State and Error functions ***************************************/
mbed_official 340:28d1f895c6fe 430 /** @addtogroup DMA_Exported_Functions_Group3
mbed_official 340:28d1f895c6fe 431 * @brief Peripheral State functions
mbed_official 340:28d1f895c6fe 432 * @{
mbed_official 340:28d1f895c6fe 433 */
mbed_official 340:28d1f895c6fe 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
mbed_official 340:28d1f895c6fe 436 /**
mbed_official 340:28d1f895c6fe 437 * @}
mbed_official 340:28d1f895c6fe 438 */
mbed_official 340:28d1f895c6fe 439
mbed_official 340:28d1f895c6fe 440 /**
mbed_official 340:28d1f895c6fe 441 * @}
mbed_official 340:28d1f895c6fe 442 */
mbed_official 340:28d1f895c6fe 443
mbed_official 340:28d1f895c6fe 444 /**
mbed_official 340:28d1f895c6fe 445 * @}
mbed_official 340:28d1f895c6fe 446 */
mbed_official 340:28d1f895c6fe 447
mbed_official 340:28d1f895c6fe 448 /**
mbed_official 340:28d1f895c6fe 449 * @}
mbed_official 340:28d1f895c6fe 450 */
mbed_official 340:28d1f895c6fe 451
mbed_official 340:28d1f895c6fe 452 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 453 }
mbed_official 340:28d1f895c6fe 454 #endif
mbed_official 340:28d1f895c6fe 455
mbed_official 340:28d1f895c6fe 456 #endif /* __STM32F0xx_HAL_DMA_H */
mbed_official 340:28d1f895c6fe 457
mbed_official 340:28d1f895c6fe 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 340:28d1f895c6fe 459