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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_adc.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)
- Committer:
- moirans2
- Date:
- Wed Jan 14 20:53:08 2015 +0000
- Revision:
- 445:9a3ffe6cfa19
- Parent:
- 441:d2c15dda23c1
internal clock stm32L051
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_adc.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 441:d2c15dda23c1 | 5 | * @version V1.2.0 |
| mbed_official | 441:d2c15dda23c1 | 6 | * @date 11-December-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief Header file containing functions prototypes of ADC HAL library. |
| mbed_official | 340:28d1f895c6fe | 8 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 9 | * @attention |
| mbed_official | 340:28d1f895c6fe | 10 | * |
| mbed_official | 340:28d1f895c6fe | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 12 | * |
| mbed_official | 340:28d1f895c6fe | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 22 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 23 | * |
| mbed_official | 340:28d1f895c6fe | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 34 | * |
| mbed_official | 340:28d1f895c6fe | 35 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 36 | */ |
| mbed_official | 340:28d1f895c6fe | 37 | |
| mbed_official | 340:28d1f895c6fe | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 39 | #ifndef __STM32F0xx_HAL_ADC_H |
| mbed_official | 340:28d1f895c6fe | 40 | #define __STM32F0xx_HAL_ADC_H |
| mbed_official | 340:28d1f895c6fe | 41 | |
| mbed_official | 340:28d1f895c6fe | 42 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 43 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 44 | #endif |
| mbed_official | 340:28d1f895c6fe | 45 | |
| mbed_official | 340:28d1f895c6fe | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 47 | #include "stm32f0xx_hal_def.h" |
| mbed_official | 340:28d1f895c6fe | 48 | |
| mbed_official | 340:28d1f895c6fe | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 50 | * @{ |
| mbed_official | 340:28d1f895c6fe | 51 | */ |
| mbed_official | 340:28d1f895c6fe | 52 | |
| mbed_official | 340:28d1f895c6fe | 53 | /** @addtogroup ADC |
| mbed_official | 340:28d1f895c6fe | 54 | * @{ |
| mbed_official | 340:28d1f895c6fe | 55 | */ |
| mbed_official | 340:28d1f895c6fe | 56 | |
| mbed_official | 340:28d1f895c6fe | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 58 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| mbed_official | 340:28d1f895c6fe | 59 | * @{ |
| mbed_official | 340:28d1f895c6fe | 60 | */ |
| mbed_official | 340:28d1f895c6fe | 61 | |
| mbed_official | 340:28d1f895c6fe | 62 | /** |
| mbed_official | 340:28d1f895c6fe | 63 | * @brief Structure definition of ADC initialization and regular group |
| mbed_official | 340:28d1f895c6fe | 64 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
| mbed_official | 340:28d1f895c6fe | 65 | * ADC state can be either: |
| mbed_official | 340:28d1f895c6fe | 66 | * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') |
| mbed_official | 340:28d1f895c6fe | 67 | * - For all parameters except 'ClockPrescaler': ADC enabled without conversion on going on regular group. |
| mbed_official | 340:28d1f895c6fe | 68 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
| mbed_official | 441:d2c15dda23c1 | 69 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
| mbed_official | 340:28d1f895c6fe | 70 | */ |
| mbed_official | 340:28d1f895c6fe | 71 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 72 | { |
| mbed_official | 340:28d1f895c6fe | 73 | uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. |
| mbed_official | 340:28d1f895c6fe | 74 | This parameter can be a value of @ref ADC_ClockPrescaler |
| mbed_official | 340:28d1f895c6fe | 75 | Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. |
| mbed_official | 340:28d1f895c6fe | 76 | Note: This parameter can be modified only if the ADC is disabled */ |
| mbed_official | 340:28d1f895c6fe | 77 | uint32_t Resolution; /*!< Configures the ADC resolution. |
| mbed_official | 340:28d1f895c6fe | 78 | This parameter can be a value of @ref ADC_Resolution */ |
| mbed_official | 340:28d1f895c6fe | 79 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| mbed_official | 340:28d1f895c6fe | 80 | This parameter can be a value of @ref ADC_Data_align */ |
| mbed_official | 340:28d1f895c6fe | 81 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. |
| mbed_official | 340:28d1f895c6fe | 82 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
| mbed_official | 340:28d1f895c6fe | 83 | Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): |
| mbed_official | 340:28d1f895c6fe | 84 | If only 1 channel is set: Conversion is performed in single mode. |
| mbed_official | 340:28d1f895c6fe | 85 | If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
| mbed_official | 340:28d1f895c6fe | 86 | Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). |
| mbed_official | 340:28d1f895c6fe | 87 | This parameter can be a value of @ref ADC_Scan_mode */ |
| mbed_official | 340:28d1f895c6fe | 88 | uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. |
| mbed_official | 340:28d1f895c6fe | 89 | This parameter can be a value of @ref ADC_EOCSelection. */ |
| mbed_official | 340:28d1f895c6fe | 90 | uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous |
| mbed_official | 340:28d1f895c6fe | 91 | conversion (for regular group) or previous sequence (for injected group) has been treated by user software. |
| mbed_official | 340:28d1f895c6fe | 92 | This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. |
| mbed_official | 340:28d1f895c6fe | 93 | This parameter can be set to ENABLE or DISABLE. |
| mbed_official | 340:28d1f895c6fe | 94 | Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. |
| mbed_official | 340:28d1f895c6fe | 95 | Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed |
| mbed_official | 340:28d1f895c6fe | 96 | and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ |
| mbed_official | 340:28d1f895c6fe | 97 | uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). |
| mbed_official | 340:28d1f895c6fe | 98 | This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). |
| mbed_official | 340:28d1f895c6fe | 99 | This parameter can be set to ENABLE or DISABLE. |
| mbed_official | 340:28d1f895c6fe | 100 | Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ |
| mbed_official | 340:28d1f895c6fe | 101 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
| mbed_official | 340:28d1f895c6fe | 102 | after the selected trigger occurred (software start or external trigger). |
| mbed_official | 340:28d1f895c6fe | 103 | This parameter can be set to ENABLE or DISABLE. */ |
| mbed_official | 340:28d1f895c6fe | 104 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| mbed_official | 340:28d1f895c6fe | 105 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| mbed_official | 340:28d1f895c6fe | 106 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
| mbed_official | 340:28d1f895c6fe | 107 | This parameter can be set to ENABLE or DISABLE |
| mbed_official | 340:28d1f895c6fe | 108 | Note: Number of discontinuous ranks increment is fixed to one-by-one. */ |
| mbed_official | 340:28d1f895c6fe | 109 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| mbed_official | 340:28d1f895c6fe | 110 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| mbed_official | 340:28d1f895c6fe | 111 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
| mbed_official | 340:28d1f895c6fe | 112 | uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. |
| mbed_official | 340:28d1f895c6fe | 113 | If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
| mbed_official | 340:28d1f895c6fe | 114 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
| mbed_official | 340:28d1f895c6fe | 115 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) |
| mbed_official | 340:28d1f895c6fe | 116 | or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
| mbed_official | 340:28d1f895c6fe | 117 | Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. |
| mbed_official | 340:28d1f895c6fe | 118 | This parameter can be set to ENABLE or DISABLE. */ |
| mbed_official | 340:28d1f895c6fe | 119 | uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten |
| mbed_official | 340:28d1f895c6fe | 120 | This parameter has an effect on regular group only, including in DMA mode. |
| mbed_official | 340:28d1f895c6fe | 121 | This parameter can be a value of @ref ADC_Overrun */ |
| mbed_official | 340:28d1f895c6fe | 122 | }ADC_InitTypeDef; |
| mbed_official | 340:28d1f895c6fe | 123 | |
| mbed_official | 340:28d1f895c6fe | 124 | /** |
| mbed_official | 340:28d1f895c6fe | 125 | * @brief Structure definition of ADC channel for regular group |
| mbed_official | 340:28d1f895c6fe | 126 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
| mbed_official | 340:28d1f895c6fe | 127 | * ADC state can be either: |
| mbed_official | 340:28d1f895c6fe | 128 | * - For all parameters: ADC disabled or enabled without conversion on going on regular group. |
| mbed_official | 340:28d1f895c6fe | 129 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
| mbed_official | 340:28d1f895c6fe | 130 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
| mbed_official | 340:28d1f895c6fe | 131 | */ |
| mbed_official | 340:28d1f895c6fe | 132 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 133 | { |
| mbed_official | 340:28d1f895c6fe | 134 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
| mbed_official | 340:28d1f895c6fe | 135 | This parameter can be a value of @ref ADC_channels |
| mbed_official | 340:28d1f895c6fe | 136 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
| mbed_official | 340:28d1f895c6fe | 137 | uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. |
| mbed_official | 340:28d1f895c6fe | 138 | On STM32F0 devices, rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
| mbed_official | 340:28d1f895c6fe | 139 | Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. |
| mbed_official | 340:28d1f895c6fe | 140 | This parameter can be a value of @ref ADC_rank */ |
| mbed_official | 340:28d1f895c6fe | 141 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
| mbed_official | 340:28d1f895c6fe | 142 | Unit: ADC clock cycles |
| mbed_official | 340:28d1f895c6fe | 143 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). |
| mbed_official | 340:28d1f895c6fe | 144 | This parameter can be a value of @ref ADC_sampling_times |
| mbed_official | 340:28d1f895c6fe | 145 | Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. |
| mbed_official | 340:28d1f895c6fe | 146 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
| mbed_official | 340:28d1f895c6fe | 147 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| mbed_official | 340:28d1f895c6fe | 148 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ |
| mbed_official | 340:28d1f895c6fe | 149 | }ADC_ChannelConfTypeDef; |
| mbed_official | 340:28d1f895c6fe | 150 | |
| mbed_official | 340:28d1f895c6fe | 151 | /** |
| mbed_official | 340:28d1f895c6fe | 152 | * @brief Structure definition of ADC analog watchdog |
| mbed_official | 340:28d1f895c6fe | 153 | * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. |
| mbed_official | 340:28d1f895c6fe | 154 | * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. |
| mbed_official | 340:28d1f895c6fe | 155 | */ |
| mbed_official | 340:28d1f895c6fe | 156 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 157 | { |
| mbed_official | 340:28d1f895c6fe | 158 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. |
| mbed_official | 340:28d1f895c6fe | 159 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
| mbed_official | 340:28d1f895c6fe | 160 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| mbed_official | 340:28d1f895c6fe | 161 | This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. |
| mbed_official | 340:28d1f895c6fe | 162 | This parameter can be a value of @ref ADC_channels. */ |
| mbed_official | 340:28d1f895c6fe | 163 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| mbed_official | 340:28d1f895c6fe | 164 | This parameter can be set to ENABLE or DISABLE */ |
| mbed_official | 340:28d1f895c6fe | 165 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| mbed_official | 340:28d1f895c6fe | 166 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| mbed_official | 340:28d1f895c6fe | 167 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| mbed_official | 340:28d1f895c6fe | 168 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| mbed_official | 340:28d1f895c6fe | 169 | }ADC_AnalogWDGConfTypeDef; |
| mbed_official | 340:28d1f895c6fe | 170 | |
| mbed_official | 340:28d1f895c6fe | 171 | /** |
| mbed_official | 340:28d1f895c6fe | 172 | * @brief HAL ADC state machine: ADC States structure definition |
| mbed_official | 340:28d1f895c6fe | 173 | */ |
| mbed_official | 340:28d1f895c6fe | 174 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 175 | { |
| mbed_official | 340:28d1f895c6fe | 176 | HAL_ADC_STATE_RESET = 0x00, /*!< ADC not yet initialized or disabled */ |
| mbed_official | 340:28d1f895c6fe | 177 | HAL_ADC_STATE_READY = 0x01, /*!< ADC peripheral ready for use */ |
| mbed_official | 340:28d1f895c6fe | 178 | HAL_ADC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 179 | HAL_ADC_STATE_BUSY_REG = 0x12, /*!< Regular conversion is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 180 | HAL_ADC_STATE_BUSY_INJ = 0x22, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ |
| mbed_official | 340:28d1f895c6fe | 181 | HAL_ADC_STATE_BUSY_INJ_REG = 0x32, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ |
| mbed_official | 340:28d1f895c6fe | 182 | HAL_ADC_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| mbed_official | 340:28d1f895c6fe | 183 | HAL_ADC_STATE_ERROR = 0x04, /*!< ADC state error */ |
| mbed_official | 340:28d1f895c6fe | 184 | HAL_ADC_STATE_EOC = 0x05, /*!< Conversion is completed */ |
| mbed_official | 340:28d1f895c6fe | 185 | HAL_ADC_STATE_EOC_REG = 0x15, /*!< Regular conversion is completed */ |
| mbed_official | 340:28d1f895c6fe | 186 | HAL_ADC_STATE_EOC_INJ = 0x25, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ |
| mbed_official | 340:28d1f895c6fe | 187 | HAL_ADC_STATE_EOC_INJ_REG = 0x35, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring an injected group) */ |
| mbed_official | 340:28d1f895c6fe | 188 | HAL_ADC_STATE_AWD = 0x06, /*!< ADC state analog watchdog */ |
| mbed_official | 340:28d1f895c6fe | 189 | HAL_ADC_STATE_AWD2 = 0x07, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ |
| mbed_official | 340:28d1f895c6fe | 190 | HAL_ADC_STATE_AWD3 = 0x08, /*!< Not used on STM32F0xx devices (kept for compatibility with other devices featuring several AWD) */ |
| mbed_official | 340:28d1f895c6fe | 191 | }HAL_ADC_StateTypeDef; |
| mbed_official | 340:28d1f895c6fe | 192 | |
| mbed_official | 340:28d1f895c6fe | 193 | /** |
| mbed_official | 340:28d1f895c6fe | 194 | * @brief ADC handle Structure definition |
| mbed_official | 340:28d1f895c6fe | 195 | */ |
| mbed_official | 340:28d1f895c6fe | 196 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 197 | { |
| mbed_official | 340:28d1f895c6fe | 198 | ADC_TypeDef *Instance; /*!< Register base address */ |
| mbed_official | 340:28d1f895c6fe | 199 | |
| mbed_official | 340:28d1f895c6fe | 200 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| mbed_official | 340:28d1f895c6fe | 201 | |
| mbed_official | 340:28d1f895c6fe | 202 | __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ |
| mbed_official | 340:28d1f895c6fe | 203 | |
| mbed_official | 340:28d1f895c6fe | 204 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| mbed_official | 340:28d1f895c6fe | 205 | |
| mbed_official | 340:28d1f895c6fe | 206 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| mbed_official | 340:28d1f895c6fe | 207 | |
| mbed_official | 340:28d1f895c6fe | 208 | __IO HAL_ADC_StateTypeDef State; /*!< ADC communication state */ |
| mbed_official | 340:28d1f895c6fe | 209 | |
| mbed_official | 340:28d1f895c6fe | 210 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| mbed_official | 340:28d1f895c6fe | 211 | }ADC_HandleTypeDef; |
| mbed_official | 340:28d1f895c6fe | 212 | /** |
| mbed_official | 340:28d1f895c6fe | 213 | * @} |
| mbed_official | 340:28d1f895c6fe | 214 | */ |
| mbed_official | 340:28d1f895c6fe | 215 | |
| mbed_official | 340:28d1f895c6fe | 216 | |
| mbed_official | 340:28d1f895c6fe | 217 | |
| mbed_official | 340:28d1f895c6fe | 218 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 219 | |
| mbed_official | 340:28d1f895c6fe | 220 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| mbed_official | 340:28d1f895c6fe | 221 | * @{ |
| mbed_official | 340:28d1f895c6fe | 222 | */ |
| mbed_official | 340:28d1f895c6fe | 223 | |
| mbed_official | 340:28d1f895c6fe | 224 | /** @defgroup ADC_Error_Code ADC Error Code |
| mbed_official | 340:28d1f895c6fe | 225 | * @{ |
| mbed_official | 340:28d1f895c6fe | 226 | */ |
| mbed_official | 340:28d1f895c6fe | 227 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ |
| mbed_official | 340:28d1f895c6fe | 228 | #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, |
| mbed_official | 340:28d1f895c6fe | 229 | enable/disable, erroneous state */ |
| mbed_official | 340:28d1f895c6fe | 230 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ |
| mbed_official | 340:28d1f895c6fe | 231 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ |
| mbed_official | 340:28d1f895c6fe | 232 | |
| mbed_official | 340:28d1f895c6fe | 233 | /** |
| mbed_official | 340:28d1f895c6fe | 234 | * @} |
| mbed_official | 340:28d1f895c6fe | 235 | */ |
| mbed_official | 340:28d1f895c6fe | 236 | |
| mbed_official | 340:28d1f895c6fe | 237 | /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler |
| mbed_official | 340:28d1f895c6fe | 238 | * @{ |
| mbed_official | 340:28d1f895c6fe | 239 | */ |
| mbed_official | 340:28d1f895c6fe | 240 | #define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ |
| mbed_official | 340:28d1f895c6fe | 241 | |
| mbed_official | 340:28d1f895c6fe | 242 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ |
| mbed_official | 340:28d1f895c6fe | 243 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ |
| mbed_official | 340:28d1f895c6fe | 244 | |
| mbed_official | 340:28d1f895c6fe | 245 | #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */ |
| mbed_official | 340:28d1f895c6fe | 246 | #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */ |
| mbed_official | 340:28d1f895c6fe | 247 | |
| mbed_official | 340:28d1f895c6fe | 248 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \ |
| mbed_official | 340:28d1f895c6fe | 249 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
| mbed_official | 340:28d1f895c6fe | 250 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) |
| mbed_official | 340:28d1f895c6fe | 251 | |
| mbed_official | 340:28d1f895c6fe | 252 | /** |
| mbed_official | 340:28d1f895c6fe | 253 | * @} |
| mbed_official | 340:28d1f895c6fe | 254 | */ |
| mbed_official | 340:28d1f895c6fe | 255 | |
| mbed_official | 340:28d1f895c6fe | 256 | /** @defgroup ADC_Resolution ADC Resolution |
| mbed_official | 340:28d1f895c6fe | 257 | * @{ |
| mbed_official | 340:28d1f895c6fe | 258 | */ |
| mbed_official | 340:28d1f895c6fe | 259 | #define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ |
| mbed_official | 340:28d1f895c6fe | 260 | #define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ |
| mbed_official | 340:28d1f895c6fe | 261 | #define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ |
| mbed_official | 340:28d1f895c6fe | 262 | #define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ |
| mbed_official | 340:28d1f895c6fe | 263 | |
| mbed_official | 340:28d1f895c6fe | 264 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ |
| mbed_official | 340:28d1f895c6fe | 265 | ((RESOLUTION) == ADC_RESOLUTION10b) || \ |
| mbed_official | 340:28d1f895c6fe | 266 | ((RESOLUTION) == ADC_RESOLUTION8b) || \ |
| mbed_official | 340:28d1f895c6fe | 267 | ((RESOLUTION) == ADC_RESOLUTION6b) ) |
| mbed_official | 340:28d1f895c6fe | 268 | /** |
| mbed_official | 340:28d1f895c6fe | 269 | * @} |
| mbed_official | 340:28d1f895c6fe | 270 | */ |
| mbed_official | 340:28d1f895c6fe | 271 | |
| mbed_official | 340:28d1f895c6fe | 272 | /** @defgroup ADC_Data_align ADC Data_align |
| mbed_official | 340:28d1f895c6fe | 273 | * @{ |
| mbed_official | 340:28d1f895c6fe | 274 | */ |
| mbed_official | 340:28d1f895c6fe | 275 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 276 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) |
| mbed_official | 340:28d1f895c6fe | 277 | |
| mbed_official | 340:28d1f895c6fe | 278 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| mbed_official | 340:28d1f895c6fe | 279 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
| mbed_official | 340:28d1f895c6fe | 280 | /** |
| mbed_official | 340:28d1f895c6fe | 281 | * @} |
| mbed_official | 340:28d1f895c6fe | 282 | */ |
| mbed_official | 340:28d1f895c6fe | 283 | |
| mbed_official | 340:28d1f895c6fe | 284 | /** @defgroup ADC_Scan_mode ADC Scan mode |
| mbed_official | 340:28d1f895c6fe | 285 | * @{ |
| mbed_official | 340:28d1f895c6fe | 286 | */ |
| mbed_official | 340:28d1f895c6fe | 287 | /* Note: Scan mode values must be compatible with other STM32 devices having */ |
| mbed_official | 340:28d1f895c6fe | 288 | /* a configurable sequencer. */ |
| mbed_official | 340:28d1f895c6fe | 289 | /* Scan direction setting values are defined by taking in account */ |
| mbed_official | 340:28d1f895c6fe | 290 | /* already defined values for other STM32 devices: */ |
| mbed_official | 340:28d1f895c6fe | 291 | /* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */ |
| mbed_official | 340:28d1f895c6fe | 292 | /* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */ |
| mbed_official | 340:28d1f895c6fe | 293 | /* Scan direction forward is considered as default setting equivalent */ |
| mbed_official | 340:28d1f895c6fe | 294 | /* to scan enable. */ |
| mbed_official | 340:28d1f895c6fe | 295 | /* Scan direction backward is considered as additional setting. */ |
| mbed_official | 340:28d1f895c6fe | 296 | /* In case of migration from another STM32 device, the user will be */ |
| mbed_official | 340:28d1f895c6fe | 297 | /* warned of change of setting choices with assert check. */ |
| mbed_official | 340:28d1f895c6fe | 298 | #define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */ |
| mbed_official | 340:28d1f895c6fe | 299 | #define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */ |
| mbed_official | 340:28d1f895c6fe | 300 | |
| mbed_official | 340:28d1f895c6fe | 301 | #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ |
| mbed_official | 340:28d1f895c6fe | 302 | |
| mbed_official | 340:28d1f895c6fe | 303 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ |
| mbed_official | 340:28d1f895c6fe | 304 | ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) |
| mbed_official | 340:28d1f895c6fe | 305 | /** |
| mbed_official | 340:28d1f895c6fe | 306 | * @} |
| mbed_official | 340:28d1f895c6fe | 307 | */ |
| mbed_official | 340:28d1f895c6fe | 308 | |
| mbed_official | 340:28d1f895c6fe | 309 | /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular |
| mbed_official | 340:28d1f895c6fe | 310 | * @{ |
| mbed_official | 340:28d1f895c6fe | 311 | */ |
| mbed_official | 340:28d1f895c6fe | 312 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 313 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) |
| mbed_official | 340:28d1f895c6fe | 314 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) |
| mbed_official | 340:28d1f895c6fe | 315 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) |
| mbed_official | 340:28d1f895c6fe | 316 | |
| mbed_official | 340:28d1f895c6fe | 317 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| mbed_official | 340:28d1f895c6fe | 318 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
| mbed_official | 340:28d1f895c6fe | 319 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
| mbed_official | 340:28d1f895c6fe | 320 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) |
| mbed_official | 340:28d1f895c6fe | 321 | /** |
| mbed_official | 340:28d1f895c6fe | 322 | * @} |
| mbed_official | 340:28d1f895c6fe | 323 | */ |
| mbed_official | 340:28d1f895c6fe | 324 | |
| mbed_official | 340:28d1f895c6fe | 325 | /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular |
| mbed_official | 340:28d1f895c6fe | 326 | * @{ |
| mbed_official | 340:28d1f895c6fe | 327 | */ |
| mbed_official | 340:28d1f895c6fe | 328 | /* List of external triggers with generic trigger name, sorted by trigger */ |
| mbed_official | 340:28d1f895c6fe | 329 | /* name: */ |
| mbed_official | 340:28d1f895c6fe | 330 | |
| mbed_official | 340:28d1f895c6fe | 331 | /* External triggers of regular group for ADC1 */ |
| mbed_official | 340:28d1f895c6fe | 332 | #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO |
| mbed_official | 340:28d1f895c6fe | 333 | #define ADC_EXTERNALTRIGCONV_T1_CC4 ADC1_2_EXTERNALTRIG_T1_CC4 |
| mbed_official | 340:28d1f895c6fe | 334 | #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO |
| mbed_official | 340:28d1f895c6fe | 335 | #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO |
| mbed_official | 340:28d1f895c6fe | 336 | #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO |
| mbed_official | 340:28d1f895c6fe | 337 | #define ADC_SOFTWARE_START ((uint32_t)0x00000010) |
| mbed_official | 340:28d1f895c6fe | 338 | |
| mbed_official | 340:28d1f895c6fe | 339 | #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ |
| mbed_official | 340:28d1f895c6fe | 340 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC4) || \ |
| mbed_official | 340:28d1f895c6fe | 341 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
| mbed_official | 340:28d1f895c6fe | 342 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ |
| mbed_official | 340:28d1f895c6fe | 343 | ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \ |
| mbed_official | 340:28d1f895c6fe | 344 | ((REGTRIG) == ADC_SOFTWARE_START) ) |
| mbed_official | 340:28d1f895c6fe | 345 | /** |
| mbed_official | 340:28d1f895c6fe | 346 | * @} |
| mbed_official | 340:28d1f895c6fe | 347 | */ |
| mbed_official | 340:28d1f895c6fe | 348 | |
| mbed_official | 340:28d1f895c6fe | 349 | /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular |
| mbed_official | 340:28d1f895c6fe | 350 | * @{ |
| mbed_official | 340:28d1f895c6fe | 351 | */ |
| mbed_official | 340:28d1f895c6fe | 352 | |
| mbed_official | 340:28d1f895c6fe | 353 | /* List of external triggers of regular group for ADC1: */ |
| mbed_official | 340:28d1f895c6fe | 354 | /* (used internally by HAL driver. To not use into HAL structure parameters) */ |
| mbed_official | 340:28d1f895c6fe | 355 | #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 356 | #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) |
| mbed_official | 340:28d1f895c6fe | 357 | #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) |
| mbed_official | 340:28d1f895c6fe | 358 | #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) |
| mbed_official | 340:28d1f895c6fe | 359 | #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) |
| mbed_official | 340:28d1f895c6fe | 360 | |
| mbed_official | 340:28d1f895c6fe | 361 | /** |
| mbed_official | 340:28d1f895c6fe | 362 | * @} |
| mbed_official | 340:28d1f895c6fe | 363 | */ |
| mbed_official | 340:28d1f895c6fe | 364 | |
| mbed_official | 340:28d1f895c6fe | 365 | /** @defgroup ADC_EOCSelection ADC EOCSelection |
| mbed_official | 340:28d1f895c6fe | 366 | * @{ |
| mbed_official | 340:28d1f895c6fe | 367 | */ |
| mbed_official | 340:28d1f895c6fe | 368 | #define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) |
| mbed_official | 340:28d1f895c6fe | 369 | #define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) |
| mbed_official | 340:28d1f895c6fe | 370 | #define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ |
| mbed_official | 340:28d1f895c6fe | 371 | |
| mbed_official | 340:28d1f895c6fe | 372 | #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ |
| mbed_official | 340:28d1f895c6fe | 373 | ((EOC_SELECTION) == EOC_SEQ_CONV) || \ |
| mbed_official | 340:28d1f895c6fe | 374 | ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) ) |
| mbed_official | 340:28d1f895c6fe | 375 | /** |
| mbed_official | 340:28d1f895c6fe | 376 | * @} |
| mbed_official | 340:28d1f895c6fe | 377 | */ |
| mbed_official | 340:28d1f895c6fe | 378 | |
| mbed_official | 340:28d1f895c6fe | 379 | /** @defgroup ADC_Overrun ADC Overrun |
| mbed_official | 340:28d1f895c6fe | 380 | * @{ |
| mbed_official | 340:28d1f895c6fe | 381 | */ |
| mbed_official | 340:28d1f895c6fe | 382 | #define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 383 | #define OVR_DATA_PRESERVED ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 384 | |
| mbed_official | 340:28d1f895c6fe | 385 | #define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \ |
| mbed_official | 340:28d1f895c6fe | 386 | ((OVR) == OVR_DATA_OVERWRITTEN) ) |
| mbed_official | 340:28d1f895c6fe | 387 | /** |
| mbed_official | 340:28d1f895c6fe | 388 | * @} |
| mbed_official | 340:28d1f895c6fe | 389 | */ |
| mbed_official | 340:28d1f895c6fe | 390 | |
| mbed_official | 340:28d1f895c6fe | 391 | /** @defgroup ADC_channels ADC channels |
| mbed_official | 340:28d1f895c6fe | 392 | * @{ |
| mbed_official | 340:28d1f895c6fe | 393 | */ |
| mbed_official | 340:28d1f895c6fe | 394 | /* Note: Depending on devices, some channels may not be available on package */ |
| mbed_official | 340:28d1f895c6fe | 395 | /* pins. Refer to device datasheet for channels availability. */ |
| mbed_official | 340:28d1f895c6fe | 396 | /* Note: Channels are used by bitfields for setting of channel selection */ |
| mbed_official | 340:28d1f895c6fe | 397 | /* (register ADC_CHSELR) and used by number for setting of analog watchdog */ |
| mbed_official | 340:28d1f895c6fe | 398 | /* channel (bits AWDCH in register ADC_CFGR1). */ |
| mbed_official | 340:28d1f895c6fe | 399 | /* Channels are defined with decimal numbers and converted them to bitfields */ |
| mbed_official | 340:28d1f895c6fe | 400 | /* when needed. */ |
| mbed_official | 340:28d1f895c6fe | 401 | #define ADC_CHANNEL_0 ((uint32_t) 0x00000000) |
| mbed_official | 340:28d1f895c6fe | 402 | #define ADC_CHANNEL_1 ((uint32_t) 0x00000001) |
| mbed_official | 340:28d1f895c6fe | 403 | #define ADC_CHANNEL_2 ((uint32_t) 0x00000002) |
| mbed_official | 340:28d1f895c6fe | 404 | #define ADC_CHANNEL_3 ((uint32_t) 0x00000003) |
| mbed_official | 340:28d1f895c6fe | 405 | #define ADC_CHANNEL_4 ((uint32_t) 0x00000004) |
| mbed_official | 340:28d1f895c6fe | 406 | #define ADC_CHANNEL_5 ((uint32_t) 0x00000005) |
| mbed_official | 340:28d1f895c6fe | 407 | #define ADC_CHANNEL_6 ((uint32_t) 0x00000006) |
| mbed_official | 340:28d1f895c6fe | 408 | #define ADC_CHANNEL_7 ((uint32_t) 0x00000007) |
| mbed_official | 340:28d1f895c6fe | 409 | #define ADC_CHANNEL_8 ((uint32_t) 0x00000008) |
| mbed_official | 340:28d1f895c6fe | 410 | #define ADC_CHANNEL_9 ((uint32_t) 0x00000009) |
| mbed_official | 340:28d1f895c6fe | 411 | #define ADC_CHANNEL_10 ((uint32_t) 0x0000000A) |
| mbed_official | 340:28d1f895c6fe | 412 | #define ADC_CHANNEL_11 ((uint32_t) 0x0000000B) |
| mbed_official | 340:28d1f895c6fe | 413 | #define ADC_CHANNEL_12 ((uint32_t) 0x0000000C) |
| mbed_official | 340:28d1f895c6fe | 414 | #define ADC_CHANNEL_13 ((uint32_t) 0x0000000D) |
| mbed_official | 340:28d1f895c6fe | 415 | #define ADC_CHANNEL_14 ((uint32_t) 0x0000000E) |
| mbed_official | 340:28d1f895c6fe | 416 | #define ADC_CHANNEL_15 ((uint32_t) 0x0000000F) |
| mbed_official | 340:28d1f895c6fe | 417 | #define ADC_CHANNEL_16 ((uint32_t) 0x00000010) |
| mbed_official | 340:28d1f895c6fe | 418 | #define ADC_CHANNEL_17 ((uint32_t) 0x00000011) |
| mbed_official | 340:28d1f895c6fe | 419 | #define ADC_CHANNEL_18 ((uint32_t) 0x00000012) |
| mbed_official | 340:28d1f895c6fe | 420 | |
| mbed_official | 340:28d1f895c6fe | 421 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 |
| mbed_official | 340:28d1f895c6fe | 422 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 |
| mbed_official | 340:28d1f895c6fe | 423 | #define ADC_CHANNEL_VBAT ADC_CHANNEL_18 |
| mbed_official | 340:28d1f895c6fe | 424 | |
| mbed_official | 340:28d1f895c6fe | 425 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
| mbed_official | 340:28d1f895c6fe | 426 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
| mbed_official | 340:28d1f895c6fe | 427 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
| mbed_official | 340:28d1f895c6fe | 428 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
| mbed_official | 340:28d1f895c6fe | 429 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
| mbed_official | 340:28d1f895c6fe | 430 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
| mbed_official | 340:28d1f895c6fe | 431 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
| mbed_official | 340:28d1f895c6fe | 432 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
| mbed_official | 340:28d1f895c6fe | 433 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
| mbed_official | 340:28d1f895c6fe | 434 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
| mbed_official | 340:28d1f895c6fe | 435 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
| mbed_official | 340:28d1f895c6fe | 436 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
| mbed_official | 340:28d1f895c6fe | 437 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
| mbed_official | 340:28d1f895c6fe | 438 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
| mbed_official | 340:28d1f895c6fe | 439 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
| mbed_official | 340:28d1f895c6fe | 440 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
| mbed_official | 340:28d1f895c6fe | 441 | ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ |
| mbed_official | 340:28d1f895c6fe | 442 | ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ |
| mbed_official | 340:28d1f895c6fe | 443 | ((CHANNEL) == ADC_CHANNEL_VBAT) ) |
| mbed_official | 340:28d1f895c6fe | 444 | /** |
| mbed_official | 340:28d1f895c6fe | 445 | * @} |
| mbed_official | 340:28d1f895c6fe | 446 | */ |
| mbed_official | 340:28d1f895c6fe | 447 | |
| mbed_official | 340:28d1f895c6fe | 448 | /** @defgroup ADC_rank ADC rank |
| mbed_official | 340:28d1f895c6fe | 449 | * @{ |
| mbed_official | 340:28d1f895c6fe | 450 | */ |
| mbed_official | 340:28d1f895c6fe | 451 | #define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Rank is defined by each channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ |
| mbed_official | 340:28d1f895c6fe | 452 | #define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */ |
| mbed_official | 340:28d1f895c6fe | 453 | |
| mbed_official | 340:28d1f895c6fe | 454 | #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ |
| mbed_official | 340:28d1f895c6fe | 455 | ((WATCHDOG) == ADC_RANK_NONE) ) |
| mbed_official | 340:28d1f895c6fe | 456 | /** |
| mbed_official | 340:28d1f895c6fe | 457 | * @} |
| mbed_official | 340:28d1f895c6fe | 458 | */ |
| mbed_official | 340:28d1f895c6fe | 459 | |
| mbed_official | 340:28d1f895c6fe | 460 | /** @defgroup ADC_sampling_times ADC sampling times |
| mbed_official | 340:28d1f895c6fe | 461 | * @{ |
| mbed_official | 340:28d1f895c6fe | 462 | */ |
| mbed_official | 340:28d1f895c6fe | 463 | #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ |
| mbed_official | 340:28d1f895c6fe | 464 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 465 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 466 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 467 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 468 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 469 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 470 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ |
| mbed_official | 340:28d1f895c6fe | 471 | |
| mbed_official | 340:28d1f895c6fe | 472 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
| mbed_official | 340:28d1f895c6fe | 473 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 474 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 475 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 476 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 477 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 478 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
| mbed_official | 340:28d1f895c6fe | 479 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
| mbed_official | 340:28d1f895c6fe | 480 | /** |
| mbed_official | 340:28d1f895c6fe | 481 | * @} |
| mbed_official | 340:28d1f895c6fe | 482 | */ |
| mbed_official | 340:28d1f895c6fe | 483 | |
| mbed_official | 340:28d1f895c6fe | 484 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
| mbed_official | 340:28d1f895c6fe | 485 | * @{ |
| mbed_official | 340:28d1f895c6fe | 486 | */ |
| mbed_official | 340:28d1f895c6fe | 487 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) |
| mbed_official | 340:28d1f895c6fe | 488 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) |
| mbed_official | 340:28d1f895c6fe | 489 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) |
| mbed_official | 340:28d1f895c6fe | 490 | |
| mbed_official | 340:28d1f895c6fe | 491 | |
| mbed_official | 340:28d1f895c6fe | 492 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
| mbed_official | 340:28d1f895c6fe | 493 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| mbed_official | 340:28d1f895c6fe | 494 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) |
| mbed_official | 340:28d1f895c6fe | 495 | /** |
| mbed_official | 340:28d1f895c6fe | 496 | * @} |
| mbed_official | 340:28d1f895c6fe | 497 | */ |
| mbed_official | 340:28d1f895c6fe | 498 | |
| mbed_official | 340:28d1f895c6fe | 499 | /** @defgroup ADC_Event_type ADC Event type |
| mbed_official | 340:28d1f895c6fe | 500 | * @{ |
| mbed_official | 340:28d1f895c6fe | 501 | */ |
| mbed_official | 340:28d1f895c6fe | 502 | #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ |
| mbed_official | 340:28d1f895c6fe | 503 | #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ |
| mbed_official | 340:28d1f895c6fe | 504 | |
| mbed_official | 340:28d1f895c6fe | 505 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ |
| mbed_official | 340:28d1f895c6fe | 506 | ((EVENT) == OVR_EVENT) ) |
| mbed_official | 340:28d1f895c6fe | 507 | /** |
| mbed_official | 340:28d1f895c6fe | 508 | * @} |
| mbed_official | 340:28d1f895c6fe | 509 | */ |
| mbed_official | 340:28d1f895c6fe | 510 | |
| mbed_official | 340:28d1f895c6fe | 511 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
| mbed_official | 340:28d1f895c6fe | 512 | * @{ |
| mbed_official | 340:28d1f895c6fe | 513 | */ |
| mbed_official | 340:28d1f895c6fe | 514 | #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 515 | #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 516 | #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 517 | #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 518 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 519 | #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ |
| mbed_official | 340:28d1f895c6fe | 520 | /** |
| mbed_official | 340:28d1f895c6fe | 521 | * @} |
| mbed_official | 340:28d1f895c6fe | 522 | */ |
| mbed_official | 340:28d1f895c6fe | 523 | |
| mbed_official | 340:28d1f895c6fe | 524 | /** @defgroup ADC_flags_definition ADC flags definition |
| mbed_official | 340:28d1f895c6fe | 525 | * @{ |
| mbed_official | 340:28d1f895c6fe | 526 | */ |
| mbed_official | 340:28d1f895c6fe | 527 | #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ |
| mbed_official | 340:28d1f895c6fe | 528 | #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ |
| mbed_official | 340:28d1f895c6fe | 529 | #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ |
| mbed_official | 340:28d1f895c6fe | 530 | #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ |
| mbed_official | 340:28d1f895c6fe | 531 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ |
| mbed_official | 340:28d1f895c6fe | 532 | #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ |
| mbed_official | 340:28d1f895c6fe | 533 | |
| mbed_official | 340:28d1f895c6fe | 534 | #define ADC_FLAG_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC | \ |
| mbed_official | 340:28d1f895c6fe | 535 | ADC_FLAG_EOSMP | ADC_FLAG_RDY ) |
| mbed_official | 340:28d1f895c6fe | 536 | |
| mbed_official | 340:28d1f895c6fe | 537 | /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ |
| mbed_official | 340:28d1f895c6fe | 538 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) |
| mbed_official | 340:28d1f895c6fe | 539 | /** |
| mbed_official | 340:28d1f895c6fe | 540 | * @} |
| mbed_official | 340:28d1f895c6fe | 541 | */ |
| mbed_official | 340:28d1f895c6fe | 542 | |
| mbed_official | 340:28d1f895c6fe | 543 | /** @defgroup ADC_range_verification ADC range verification |
| mbed_official | 340:28d1f895c6fe | 544 | * in function of ADC resolution selected (12, 10, 8 or 6 bits) |
| mbed_official | 340:28d1f895c6fe | 545 | * @{ |
| mbed_official | 340:28d1f895c6fe | 546 | */ |
| mbed_official | 340:28d1f895c6fe | 547 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
| mbed_official | 340:28d1f895c6fe | 548 | ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ |
| mbed_official | 340:28d1f895c6fe | 549 | (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ |
| mbed_official | 340:28d1f895c6fe | 550 | (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ |
| mbed_official | 340:28d1f895c6fe | 551 | (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) ) |
| mbed_official | 340:28d1f895c6fe | 552 | /** |
| mbed_official | 340:28d1f895c6fe | 553 | * @} |
| mbed_official | 340:28d1f895c6fe | 554 | */ |
| mbed_official | 340:28d1f895c6fe | 555 | |
| mbed_official | 340:28d1f895c6fe | 556 | /** @defgroup ADC_regular_rank_verification ADC regular rank verification |
| mbed_official | 340:28d1f895c6fe | 557 | * @{ |
| mbed_official | 340:28d1f895c6fe | 558 | */ |
| mbed_official | 340:28d1f895c6fe | 559 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16))) |
| mbed_official | 340:28d1f895c6fe | 560 | /** |
| mbed_official | 340:28d1f895c6fe | 561 | * @} |
| mbed_official | 340:28d1f895c6fe | 562 | */ |
| mbed_official | 340:28d1f895c6fe | 563 | |
| mbed_official | 340:28d1f895c6fe | 564 | /** |
| mbed_official | 340:28d1f895c6fe | 565 | * @} |
| mbed_official | 340:28d1f895c6fe | 566 | */ |
| mbed_official | 340:28d1f895c6fe | 567 | |
| mbed_official | 340:28d1f895c6fe | 568 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 569 | |
| mbed_official | 340:28d1f895c6fe | 570 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| mbed_official | 340:28d1f895c6fe | 571 | * @{ |
| mbed_official | 340:28d1f895c6fe | 572 | */ |
| mbed_official | 340:28d1f895c6fe | 573 | /** @brief Reset ADC handle state |
| mbed_official | 340:28d1f895c6fe | 574 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 575 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 576 | */ |
| mbed_official | 340:28d1f895c6fe | 577 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| mbed_official | 340:28d1f895c6fe | 578 | |
| mbed_official | 340:28d1f895c6fe | 579 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
| mbed_official | 340:28d1f895c6fe | 580 | /* final user. */ |
| mbed_official | 340:28d1f895c6fe | 581 | |
| mbed_official | 340:28d1f895c6fe | 582 | /** |
| mbed_official | 340:28d1f895c6fe | 583 | * @brief Verification of ADC state: enabled or disabled |
| mbed_official | 340:28d1f895c6fe | 584 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 585 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| mbed_official | 340:28d1f895c6fe | 586 | */ |
| mbed_official | 340:28d1f895c6fe | 587 | /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
| mbed_official | 340:28d1f895c6fe | 588 | /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ |
| mbed_official | 340:28d1f895c6fe | 589 | /* set. */ |
| mbed_official | 340:28d1f895c6fe | 590 | #define __HAL_ADC_IS_ENABLED(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 591 | (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ |
| mbed_official | 340:28d1f895c6fe | 592 | (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ |
| mbed_official | 340:28d1f895c6fe | 593 | ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ |
| mbed_official | 340:28d1f895c6fe | 594 | ) ? SET : RESET) |
| mbed_official | 340:28d1f895c6fe | 595 | |
| mbed_official | 340:28d1f895c6fe | 596 | /** |
| mbed_official | 340:28d1f895c6fe | 597 | * @brief Test if conversion trigger of regular group is software start |
| mbed_official | 340:28d1f895c6fe | 598 | * or external trigger. |
| mbed_official | 340:28d1f895c6fe | 599 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 600 | * @retval SET (software start) or RESET (external trigger) |
| mbed_official | 340:28d1f895c6fe | 601 | */ |
| mbed_official | 340:28d1f895c6fe | 602 | #define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 603 | (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) |
| mbed_official | 340:28d1f895c6fe | 604 | |
| mbed_official | 340:28d1f895c6fe | 605 | /** |
| mbed_official | 340:28d1f895c6fe | 606 | * @brief Check if no conversion on going on regular group |
| mbed_official | 340:28d1f895c6fe | 607 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 608 | * @retval SET (conversion is on going) or RESET (no conversion is on going) |
| mbed_official | 340:28d1f895c6fe | 609 | */ |
| mbed_official | 340:28d1f895c6fe | 610 | #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 611 | (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ |
| mbed_official | 340:28d1f895c6fe | 612 | ) ? RESET : SET) |
| mbed_official | 340:28d1f895c6fe | 613 | |
| mbed_official | 340:28d1f895c6fe | 614 | /** |
| mbed_official | 340:28d1f895c6fe | 615 | * @brief Returns resolution bits in CFGR1 register: RES[1:0]. |
| mbed_official | 340:28d1f895c6fe | 616 | * Returned value is among parameters to @ref ADC_Resolution. |
| mbed_official | 340:28d1f895c6fe | 617 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 618 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 619 | */ |
| mbed_official | 340:28d1f895c6fe | 620 | #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) |
| mbed_official | 340:28d1f895c6fe | 621 | |
| mbed_official | 340:28d1f895c6fe | 622 | /** |
| mbed_official | 340:28d1f895c6fe | 623 | * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. |
| mbed_official | 340:28d1f895c6fe | 624 | * Returned value is among parameters to @ref ADC_Resolution. |
| mbed_official | 340:28d1f895c6fe | 625 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 626 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 627 | */ |
| mbed_official | 340:28d1f895c6fe | 628 | #define __HAL_ADC_GET_SAMPLINGTIME(__HANDLE__) (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) |
| mbed_official | 340:28d1f895c6fe | 629 | |
| mbed_official | 340:28d1f895c6fe | 630 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| mbed_official | 340:28d1f895c6fe | 631 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 632 | * @param __INTERRUPT__: ADC interrupt source to check |
| mbed_official | 340:28d1f895c6fe | 633 | * @retval State ofinterruption (SET or RESET) |
| mbed_official | 340:28d1f895c6fe | 634 | */ |
| mbed_official | 340:28d1f895c6fe | 635 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
| mbed_official | 340:28d1f895c6fe | 636 | (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ |
| mbed_official | 340:28d1f895c6fe | 637 | )? SET : RESET \ |
| mbed_official | 340:28d1f895c6fe | 638 | ) |
| mbed_official | 340:28d1f895c6fe | 639 | |
| mbed_official | 340:28d1f895c6fe | 640 | /** |
| mbed_official | 340:28d1f895c6fe | 641 | * @brief Enable the ADC end of conversion interrupt. |
| mbed_official | 340:28d1f895c6fe | 642 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 643 | * @param __INTERRUPT__: ADC Interrupt |
| mbed_official | 340:28d1f895c6fe | 644 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 645 | */ |
| mbed_official | 340:28d1f895c6fe | 646 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
| mbed_official | 340:28d1f895c6fe | 647 | |
| mbed_official | 340:28d1f895c6fe | 648 | /** |
| mbed_official | 340:28d1f895c6fe | 649 | * @brief Disable the ADC end of conversion interrupt. |
| mbed_official | 340:28d1f895c6fe | 650 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 651 | * @param __INTERRUPT__: ADC Interrupt |
| mbed_official | 340:28d1f895c6fe | 652 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 653 | */ |
| mbed_official | 340:28d1f895c6fe | 654 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
| mbed_official | 340:28d1f895c6fe | 655 | |
| mbed_official | 340:28d1f895c6fe | 656 | /** |
| mbed_official | 340:28d1f895c6fe | 657 | * @brief Get the selected ADC's flag status. |
| mbed_official | 340:28d1f895c6fe | 658 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 659 | * @param __FLAG__: ADC flag |
| mbed_official | 340:28d1f895c6fe | 660 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 661 | */ |
| mbed_official | 340:28d1f895c6fe | 662 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 663 | |
| mbed_official | 340:28d1f895c6fe | 664 | /** |
| mbed_official | 340:28d1f895c6fe | 665 | * @brief Clear the ADC's pending flags |
| mbed_official | 340:28d1f895c6fe | 666 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 667 | * @param __FLAG__: ADC flag |
| mbed_official | 340:28d1f895c6fe | 668 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 669 | */ |
| mbed_official | 340:28d1f895c6fe | 670 | /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ |
| mbed_official | 340:28d1f895c6fe | 671 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 672 | |
| mbed_official | 340:28d1f895c6fe | 673 | /** |
| mbed_official | 340:28d1f895c6fe | 674 | * @brief Clear ADC error code (set it to error code: "no error") |
| mbed_official | 340:28d1f895c6fe | 675 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 676 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 677 | */ |
| mbed_official | 340:28d1f895c6fe | 678 | #define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| mbed_official | 340:28d1f895c6fe | 679 | |
| mbed_official | 340:28d1f895c6fe | 680 | |
| mbed_official | 340:28d1f895c6fe | 681 | /** |
| mbed_official | 340:28d1f895c6fe | 682 | * @brief Configure the channel number into channel selection register |
| mbed_official | 340:28d1f895c6fe | 683 | * @param _CHANNEL_: ADC Channel |
| mbed_official | 340:28d1f895c6fe | 684 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 685 | */ |
| mbed_official | 340:28d1f895c6fe | 686 | /* This function converts ADC channels from numbers (see defgroup ADC_channels) |
| mbed_official | 340:28d1f895c6fe | 687 | to bitfields, to get the equivalence of CMSIS channels: |
| mbed_official | 340:28d1f895c6fe | 688 | ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) |
| mbed_official | 340:28d1f895c6fe | 689 | ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) |
| mbed_official | 340:28d1f895c6fe | 690 | ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) |
| mbed_official | 340:28d1f895c6fe | 691 | ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) |
| mbed_official | 340:28d1f895c6fe | 692 | ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) |
| mbed_official | 340:28d1f895c6fe | 693 | ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) |
| mbed_official | 340:28d1f895c6fe | 694 | ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) |
| mbed_official | 340:28d1f895c6fe | 695 | ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) |
| mbed_official | 340:28d1f895c6fe | 696 | ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) |
| mbed_official | 340:28d1f895c6fe | 697 | ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) |
| mbed_official | 340:28d1f895c6fe | 698 | ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) |
| mbed_official | 340:28d1f895c6fe | 699 | ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) |
| mbed_official | 340:28d1f895c6fe | 700 | ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) |
| mbed_official | 340:28d1f895c6fe | 701 | ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) |
| mbed_official | 340:28d1f895c6fe | 702 | ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) |
| mbed_official | 340:28d1f895c6fe | 703 | ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) |
| mbed_official | 340:28d1f895c6fe | 704 | ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) |
| mbed_official | 340:28d1f895c6fe | 705 | ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) |
| mbed_official | 340:28d1f895c6fe | 706 | ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) |
| mbed_official | 340:28d1f895c6fe | 707 | */ |
| mbed_official | 340:28d1f895c6fe | 708 | #define __HAL_ADC_CHSELR_CHANNEL(_CHANNEL_) ( 1U << (_CHANNEL_)) |
| mbed_official | 340:28d1f895c6fe | 709 | |
| mbed_official | 340:28d1f895c6fe | 710 | /** |
| mbed_official | 340:28d1f895c6fe | 711 | * @} |
| mbed_official | 340:28d1f895c6fe | 712 | */ |
| mbed_official | 340:28d1f895c6fe | 713 | |
| mbed_official | 340:28d1f895c6fe | 714 | /** @defgroup ADC_Exported_Macro_internal_HAL_driver ADC Exported Macro internal HAL driver |
| mbed_official | 340:28d1f895c6fe | 715 | * @{ |
| mbed_official | 340:28d1f895c6fe | 716 | */ |
| mbed_official | 340:28d1f895c6fe | 717 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
| mbed_official | 340:28d1f895c6fe | 718 | /* code of final user. */ |
| mbed_official | 340:28d1f895c6fe | 719 | |
| mbed_official | 340:28d1f895c6fe | 720 | /** |
| mbed_official | 340:28d1f895c6fe | 721 | * @brief Set the Analog Watchdog 1 channel. |
| mbed_official | 340:28d1f895c6fe | 722 | * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1. |
| mbed_official | 340:28d1f895c6fe | 723 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 724 | */ |
| mbed_official | 340:28d1f895c6fe | 725 | #define __HAL_ADC_CFGR_AWDCH(_CHANNEL_) ((_CHANNEL_) << 26) |
| mbed_official | 340:28d1f895c6fe | 726 | |
| mbed_official | 340:28d1f895c6fe | 727 | /** |
| mbed_official | 340:28d1f895c6fe | 728 | * @brief Enable ADC discontinuous conversion mode for regular group |
| mbed_official | 441:d2c15dda23c1 | 729 | * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. |
| mbed_official | 340:28d1f895c6fe | 730 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 731 | */ |
| mbed_official | 340:28d1f895c6fe | 732 | #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16) |
| mbed_official | 340:28d1f895c6fe | 733 | |
| mbed_official | 340:28d1f895c6fe | 734 | /** |
| mbed_official | 340:28d1f895c6fe | 735 | * @brief Enable the ADC auto off mode. |
| mbed_official | 340:28d1f895c6fe | 736 | * @param _AUTOOFF_: Auto off bit enable or disable. |
| mbed_official | 340:28d1f895c6fe | 737 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 738 | */ |
| mbed_official | 340:28d1f895c6fe | 739 | #define __HAL_ADC_CFGR1_AUTOOFF(_AUTOOFF_) ((_AUTOOFF_) << 15) |
| mbed_official | 340:28d1f895c6fe | 740 | |
| mbed_official | 340:28d1f895c6fe | 741 | /** |
| mbed_official | 340:28d1f895c6fe | 742 | * @brief Enable the ADC auto delay mode. |
| mbed_official | 340:28d1f895c6fe | 743 | * @param _AUTOWAIT_: Auto delay bit enable or disable. |
| mbed_official | 340:28d1f895c6fe | 744 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 745 | */ |
| mbed_official | 340:28d1f895c6fe | 746 | #define __HAL_ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14) |
| mbed_official | 340:28d1f895c6fe | 747 | |
| mbed_official | 340:28d1f895c6fe | 748 | /** |
| mbed_official | 340:28d1f895c6fe | 749 | * @brief Enable ADC continuous conversion mode. |
| mbed_official | 340:28d1f895c6fe | 750 | * @param _CONTINUOUS_MODE_: Continuous mode. |
| mbed_official | 340:28d1f895c6fe | 751 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 752 | */ |
| mbed_official | 340:28d1f895c6fe | 753 | #define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) |
| mbed_official | 340:28d1f895c6fe | 754 | |
| mbed_official | 340:28d1f895c6fe | 755 | /** |
| mbed_official | 340:28d1f895c6fe | 756 | * @brief Enable ADC overrun mode. |
| mbed_official | 340:28d1f895c6fe | 757 | * @param _OVERRUN_MODE_: Overrun mode. |
| mbed_official | 340:28d1f895c6fe | 758 | * @retval Overun bit setting to be programmed into CFGR register |
| mbed_official | 340:28d1f895c6fe | 759 | */ |
| mbed_official | 340:28d1f895c6fe | 760 | /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ |
| mbed_official | 340:28d1f895c6fe | 761 | /* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */ |
| mbed_official | 340:28d1f895c6fe | 762 | /* default case to be compliant with other STM32 devices. */ |
| mbed_official | 340:28d1f895c6fe | 763 | #define __HAL_ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ |
| mbed_official | 340:28d1f895c6fe | 764 | ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \ |
| mbed_official | 340:28d1f895c6fe | 765 | )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ |
| mbed_official | 340:28d1f895c6fe | 766 | ) |
| mbed_official | 340:28d1f895c6fe | 767 | |
| mbed_official | 340:28d1f895c6fe | 768 | /** |
| mbed_official | 340:28d1f895c6fe | 769 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
| mbed_official | 340:28d1f895c6fe | 770 | * @param _SCAN_MODE_: Scan conversion mode. |
| mbed_official | 340:28d1f895c6fe | 771 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 772 | */ |
| mbed_official | 340:28d1f895c6fe | 773 | #define __HAL_ADC_CFGR1_SCANDIR(_SCAN_MODE_) \ |
| mbed_official | 340:28d1f895c6fe | 774 | ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ |
| mbed_official | 340:28d1f895c6fe | 775 | )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ |
| mbed_official | 340:28d1f895c6fe | 776 | ) |
| mbed_official | 340:28d1f895c6fe | 777 | |
| mbed_official | 340:28d1f895c6fe | 778 | /** |
| mbed_official | 340:28d1f895c6fe | 779 | * @brief Enable the ADC DMA continuous request. |
| mbed_official | 340:28d1f895c6fe | 780 | * @param _DMACONTREQ_MODE_: DMA continuous request mode. |
| mbed_official | 340:28d1f895c6fe | 781 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 782 | */ |
| mbed_official | 340:28d1f895c6fe | 783 | #define __HAL_ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1) |
| mbed_official | 441:d2c15dda23c1 | 784 | |
| mbed_official | 340:28d1f895c6fe | 785 | /** |
| mbed_official | 340:28d1f895c6fe | 786 | * @brief Configure the analog watchdog high threshold into register TR. |
| mbed_official | 340:28d1f895c6fe | 787 | * @param _Threshold_: Threshold value |
| mbed_official | 340:28d1f895c6fe | 788 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 789 | */ |
| mbed_official | 340:28d1f895c6fe | 790 | #define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) |
| mbed_official | 340:28d1f895c6fe | 791 | |
| mbed_official | 340:28d1f895c6fe | 792 | /** |
| mbed_official | 340:28d1f895c6fe | 793 | * @brief Enable the ADC peripheral |
| mbed_official | 340:28d1f895c6fe | 794 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 795 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 796 | */ |
| mbed_official | 340:28d1f895c6fe | 797 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) |
| mbed_official | 340:28d1f895c6fe | 798 | |
| mbed_official | 340:28d1f895c6fe | 799 | /** |
| mbed_official | 340:28d1f895c6fe | 800 | * @brief Verification of hardware constraints before ADC can be enabled |
| mbed_official | 340:28d1f895c6fe | 801 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 802 | * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) |
| mbed_official | 340:28d1f895c6fe | 803 | */ |
| mbed_official | 340:28d1f895c6fe | 804 | #define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 805 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| mbed_official | 441:d2c15dda23c1 | 806 | (ADC_CR_ADCAL | ADC_CR_ADSTP | \ |
| mbed_official | 340:28d1f895c6fe | 807 | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ |
| mbed_official | 340:28d1f895c6fe | 808 | ) == RESET \ |
| mbed_official | 340:28d1f895c6fe | 809 | ) ? SET : RESET) |
| mbed_official | 340:28d1f895c6fe | 810 | |
| mbed_official | 340:28d1f895c6fe | 811 | /** |
| mbed_official | 340:28d1f895c6fe | 812 | * @brief Disable the ADC peripheral |
| mbed_official | 340:28d1f895c6fe | 813 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 814 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 815 | */ |
| mbed_official | 340:28d1f895c6fe | 816 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 817 | do{ \ |
| mbed_official | 340:28d1f895c6fe | 818 | (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ |
| mbed_official | 340:28d1f895c6fe | 819 | __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ |
| mbed_official | 340:28d1f895c6fe | 820 | } while(0) |
| mbed_official | 340:28d1f895c6fe | 821 | |
| mbed_official | 340:28d1f895c6fe | 822 | /** |
| mbed_official | 340:28d1f895c6fe | 823 | * @brief Verification of hardware constraints before ADC can be disabled |
| mbed_official | 340:28d1f895c6fe | 824 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 825 | * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) |
| mbed_official | 340:28d1f895c6fe | 826 | */ |
| mbed_official | 340:28d1f895c6fe | 827 | #define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 828 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| mbed_official | 340:28d1f895c6fe | 829 | (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ |
| mbed_official | 340:28d1f895c6fe | 830 | ) ? SET : RESET) |
| mbed_official | 340:28d1f895c6fe | 831 | |
| mbed_official | 340:28d1f895c6fe | 832 | /** |
| mbed_official | 340:28d1f895c6fe | 833 | * @brief Shift the AWD threshold in function of the selected ADC resolution. |
| mbed_official | 340:28d1f895c6fe | 834 | * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. |
| mbed_official | 340:28d1f895c6fe | 835 | * If resolution 12 bits, no shift. |
| mbed_official | 340:28d1f895c6fe | 836 | * If resolution 10 bits, shift of 2 ranks on the left. |
| mbed_official | 340:28d1f895c6fe | 837 | * If resolution 8 bits, shift of 4 ranks on the left. |
| mbed_official | 340:28d1f895c6fe | 838 | * If resolution 6 bits, shift of 6 ranks on the left. |
| mbed_official | 340:28d1f895c6fe | 839 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
| mbed_official | 340:28d1f895c6fe | 840 | * @param __HANDLE__: ADC handle |
| mbed_official | 340:28d1f895c6fe | 841 | * @param _Threshold_: Value to be shifted |
| mbed_official | 340:28d1f895c6fe | 842 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 843 | */ |
| mbed_official | 340:28d1f895c6fe | 844 | #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ |
| mbed_official | 340:28d1f895c6fe | 845 | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) |
| mbed_official | 340:28d1f895c6fe | 846 | |
| mbed_official | 340:28d1f895c6fe | 847 | /** |
| mbed_official | 340:28d1f895c6fe | 848 | * @} |
| mbed_official | 340:28d1f895c6fe | 849 | */ |
| mbed_official | 340:28d1f895c6fe | 850 | |
| mbed_official | 340:28d1f895c6fe | 851 | /* Include ADC HAL Extension module */ |
| mbed_official | 340:28d1f895c6fe | 852 | #include "stm32f0xx_hal_adc_ex.h" |
| mbed_official | 340:28d1f895c6fe | 853 | |
| mbed_official | 340:28d1f895c6fe | 854 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 855 | /** @addtogroup ADC_Exported_Functions |
| mbed_official | 340:28d1f895c6fe | 856 | * @{ |
| mbed_official | 340:28d1f895c6fe | 857 | */ |
| mbed_official | 340:28d1f895c6fe | 858 | |
| mbed_official | 340:28d1f895c6fe | 859 | /** @addtogroup ADC_Exported_Functions_Group1 |
| mbed_official | 340:28d1f895c6fe | 860 | * @{ |
| mbed_official | 340:28d1f895c6fe | 861 | */ |
| mbed_official | 340:28d1f895c6fe | 862 | |
| mbed_official | 340:28d1f895c6fe | 863 | |
| mbed_official | 340:28d1f895c6fe | 864 | /* Initialization and de-initialization functions **********************************/ |
| mbed_official | 340:28d1f895c6fe | 865 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 866 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| mbed_official | 340:28d1f895c6fe | 867 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 868 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 869 | /** |
| mbed_official | 340:28d1f895c6fe | 870 | * @} |
| mbed_official | 340:28d1f895c6fe | 871 | */ |
| mbed_official | 340:28d1f895c6fe | 872 | |
| mbed_official | 340:28d1f895c6fe | 873 | /* IO operation functions *****************************************************/ |
| mbed_official | 340:28d1f895c6fe | 874 | |
| mbed_official | 340:28d1f895c6fe | 875 | /** @addtogroup ADC_Exported_Functions_Group2 |
| mbed_official | 340:28d1f895c6fe | 876 | * @{ |
| mbed_official | 340:28d1f895c6fe | 877 | */ |
| mbed_official | 340:28d1f895c6fe | 878 | |
| mbed_official | 340:28d1f895c6fe | 879 | |
| mbed_official | 340:28d1f895c6fe | 880 | /* Blocking mode: Polling */ |
| mbed_official | 340:28d1f895c6fe | 881 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 882 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 883 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 884 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 885 | |
| mbed_official | 340:28d1f895c6fe | 886 | /* Non-blocking mode: Interruption */ |
| mbed_official | 340:28d1f895c6fe | 887 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 888 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 889 | |
| mbed_official | 340:28d1f895c6fe | 890 | /* Non-blocking mode: DMA */ |
| mbed_official | 340:28d1f895c6fe | 891 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| mbed_official | 340:28d1f895c6fe | 892 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 893 | |
| mbed_official | 340:28d1f895c6fe | 894 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| mbed_official | 340:28d1f895c6fe | 895 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 896 | |
| mbed_official | 340:28d1f895c6fe | 897 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| mbed_official | 340:28d1f895c6fe | 898 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 899 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 900 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 901 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 902 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| mbed_official | 340:28d1f895c6fe | 903 | /** |
| mbed_official | 340:28d1f895c6fe | 904 | * @} |
| mbed_official | 340:28d1f895c6fe | 905 | */ |
| mbed_official | 340:28d1f895c6fe | 906 | |
| mbed_official | 340:28d1f895c6fe | 907 | |
| mbed_official | 340:28d1f895c6fe | 908 | /* Peripheral Control functions ***********************************************/ |
| mbed_official | 340:28d1f895c6fe | 909 | /** @addtogroup ADC_Exported_Functions_Group3 |
| mbed_official | 340:28d1f895c6fe | 910 | * @{ |
| mbed_official | 340:28d1f895c6fe | 911 | */ |
| mbed_official | 340:28d1f895c6fe | 912 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| mbed_official | 340:28d1f895c6fe | 913 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| mbed_official | 340:28d1f895c6fe | 914 | /** |
| mbed_official | 340:28d1f895c6fe | 915 | * @} |
| mbed_official | 340:28d1f895c6fe | 916 | */ |
| mbed_official | 340:28d1f895c6fe | 917 | |
| mbed_official | 340:28d1f895c6fe | 918 | |
| mbed_official | 340:28d1f895c6fe | 919 | /* Peripheral State functions *************************************************/ |
| mbed_official | 340:28d1f895c6fe | 920 | /** @addtogroup ADC_Exported_Functions_Group4 |
| mbed_official | 340:28d1f895c6fe | 921 | * @{ |
| mbed_official | 340:28d1f895c6fe | 922 | */ |
| mbed_official | 340:28d1f895c6fe | 923 | HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| mbed_official | 340:28d1f895c6fe | 924 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| mbed_official | 340:28d1f895c6fe | 925 | /** |
| mbed_official | 340:28d1f895c6fe | 926 | * @} |
| mbed_official | 340:28d1f895c6fe | 927 | */ |
| mbed_official | 340:28d1f895c6fe | 928 | |
| mbed_official | 340:28d1f895c6fe | 929 | |
| mbed_official | 340:28d1f895c6fe | 930 | /** |
| mbed_official | 340:28d1f895c6fe | 931 | * @} |
| mbed_official | 340:28d1f895c6fe | 932 | */ |
| mbed_official | 340:28d1f895c6fe | 933 | |
| mbed_official | 340:28d1f895c6fe | 934 | |
| mbed_official | 340:28d1f895c6fe | 935 | /** |
| mbed_official | 340:28d1f895c6fe | 936 | * @} |
| mbed_official | 340:28d1f895c6fe | 937 | */ |
| mbed_official | 340:28d1f895c6fe | 938 | |
| mbed_official | 340:28d1f895c6fe | 939 | /** |
| mbed_official | 340:28d1f895c6fe | 940 | * @} |
| mbed_official | 340:28d1f895c6fe | 941 | */ |
| mbed_official | 340:28d1f895c6fe | 942 | |
| mbed_official | 340:28d1f895c6fe | 943 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 944 | } |
| mbed_official | 340:28d1f895c6fe | 945 | #endif |
| mbed_official | 340:28d1f895c6fe | 946 | |
| mbed_official | 340:28d1f895c6fe | 947 | |
| mbed_official | 340:28d1f895c6fe | 948 | #endif /* __STM32F0xx_HAL_ADC_H */ |
| mbed_official | 340:28d1f895c6fe | 949 | |
| mbed_official | 340:28d1f895c6fe | 950 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 340:28d1f895c6fe | 951 |