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targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:
moirans2
Date:
Wed Jan 14 20:53:08 2015 +0000
Revision:
445:9a3ffe6cfa19
Parent:
423:560d1a9f3083 
internal clock stm32L051

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UserRevisionLine numberNew contents of line
mbed_official 423:560d1a9f3083 1 /**
mbed_official 423:560d1a9f3083 2 ******************************************************************************
mbed_official 423:560d1a9f3083 3 * @file system_stm32f0xx.c
mbed_official 423:560d1a9f3083 4 * @author MCD Application Team
mbed_official 423:560d1a9f3083 5 * @version V2.1.0
mbed_official 423:560d1a9f3083 6 * @date 03-Oct-2014
mbed_official 423:560d1a9f3083 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 423:560d1a9f3083 8 *
mbed_official 423:560d1a9f3083 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 423:560d1a9f3083 10 * user application:
mbed_official 423:560d1a9f3083 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 423:560d1a9f3083 12 * before branch to main program. This call is made inside
mbed_official 423:560d1a9f3083 13 * the "startup_stm32f0xx.s" file.
mbed_official 423:560d1a9f3083 14 *
mbed_official 423:560d1a9f3083 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 423:560d1a9f3083 16 * by the user application to setup the SysTick
mbed_official 423:560d1a9f3083 17 * timer or configure other parameters.
mbed_official 423:560d1a9f3083 18 *
mbed_official 423:560d1a9f3083 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 423:560d1a9f3083 20 * be called whenever the core clock is changed
mbed_official 423:560d1a9f3083 21 * during program execution.
mbed_official 423:560d1a9f3083 22 *
mbed_official 423:560d1a9f3083 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 423:560d1a9f3083 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 423:560d1a9f3083 25 * configure the system clock before to branch to main program.
mbed_official 423:560d1a9f3083 26 *
mbed_official 423:560d1a9f3083 27 * 3. This file configures the system clock as follows:
mbed_official 423:560d1a9f3083 28 *=============================================================================
mbed_official 423:560d1a9f3083 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 423:560d1a9f3083 30 * | (external 8 MHz clock) | (internal 48 MHz)
mbed_official 423:560d1a9f3083 31 * | 2- PLL_HSE_XTAL |
mbed_official 423:560d1a9f3083 32 * | (external 8 MHz xtal) |
mbed_official 423:560d1a9f3083 33 *-----------------------------------------------------------------------------
mbed_official 423:560d1a9f3083 34 * SYSCLK(MHz) | 48 | 48
mbed_official 423:560d1a9f3083 35 *-----------------------------------------------------------------------------
mbed_official 423:560d1a9f3083 36 * AHBCLK (MHz) | 48 | 48
mbed_official 423:560d1a9f3083 37 *-----------------------------------------------------------------------------
mbed_official 423:560d1a9f3083 38 * APB1CLK (MHz) | 48 | 48
mbed_official 423:560d1a9f3083 39 *-----------------------------------------------------------------------------
mbed_official 423:560d1a9f3083 40 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 423:560d1a9f3083 41 *=============================================================================
mbed_official 423:560d1a9f3083 42 ******************************************************************************
mbed_official 423:560d1a9f3083 43 * @attention
mbed_official 423:560d1a9f3083 44 *
mbed_official 423:560d1a9f3083 45 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 423:560d1a9f3083 46 *
mbed_official 423:560d1a9f3083 47 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 423:560d1a9f3083 48 * are permitted provided that the following conditions are met:
mbed_official 423:560d1a9f3083 49 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 423:560d1a9f3083 50 * this list of conditions and the following disclaimer.
mbed_official 423:560d1a9f3083 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 423:560d1a9f3083 52 * this list of conditions and the following disclaimer in the documentation
mbed_official 423:560d1a9f3083 53 * and/or other materials provided with the distribution.
mbed_official 423:560d1a9f3083 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 423:560d1a9f3083 55 * may be used to endorse or promote products derived from this software
mbed_official 423:560d1a9f3083 56 * without specific prior written permission.
mbed_official 423:560d1a9f3083 57 *
mbed_official 423:560d1a9f3083 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 423:560d1a9f3083 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 423:560d1a9f3083 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 423:560d1a9f3083 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 423:560d1a9f3083 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 423:560d1a9f3083 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 423:560d1a9f3083 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 423:560d1a9f3083 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 423:560d1a9f3083 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 423:560d1a9f3083 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 423:560d1a9f3083 68 *
mbed_official 423:560d1a9f3083 69 ******************************************************************************
mbed_official 423:560d1a9f3083 70 */
mbed_official 423:560d1a9f3083 71
mbed_official 423:560d1a9f3083 72 /** @addtogroup CMSIS
mbed_official 423:560d1a9f3083 73 * @{
mbed_official 423:560d1a9f3083 74 */
mbed_official 423:560d1a9f3083 75
mbed_official 423:560d1a9f3083 76 /** @addtogroup stm32f0xx_system
mbed_official 423:560d1a9f3083 77 * @{
mbed_official 423:560d1a9f3083 78 */
mbed_official 423:560d1a9f3083 79
mbed_official 423:560d1a9f3083 80 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 423:560d1a9f3083 81 * @{
mbed_official 423:560d1a9f3083 82 */
mbed_official 423:560d1a9f3083 83
mbed_official 423:560d1a9f3083 84 #include "stm32f0xx.h"
mbed_official 423:560d1a9f3083 85
mbed_official 423:560d1a9f3083 86 /**
mbed_official 423:560d1a9f3083 87 * @}
mbed_official 423:560d1a9f3083 88 */
mbed_official 423:560d1a9f3083 89
mbed_official 423:560d1a9f3083 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 423:560d1a9f3083 91 * @{
mbed_official 423:560d1a9f3083 92 */
mbed_official 423:560d1a9f3083 93
mbed_official 423:560d1a9f3083 94 /**
mbed_official 423:560d1a9f3083 95 * @}
mbed_official 423:560d1a9f3083 96 */
mbed_official 423:560d1a9f3083 97
mbed_official 423:560d1a9f3083 98 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 423:560d1a9f3083 99 * @{
mbed_official 423:560d1a9f3083 100 */
mbed_official 423:560d1a9f3083 101 #if !defined (HSE_VALUE)
mbed_official 423:560d1a9f3083 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 423:560d1a9f3083 103 This value can be provided and adapted by the user application. */
mbed_official 423:560d1a9f3083 104 #endif /* HSE_VALUE */
mbed_official 423:560d1a9f3083 105
mbed_official 423:560d1a9f3083 106 #if !defined (HSI_VALUE)
mbed_official 423:560d1a9f3083 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 423:560d1a9f3083 108 This value can be provided and adapted by the user application. */
mbed_official 423:560d1a9f3083 109 #endif /* HSI_VALUE */
mbed_official 423:560d1a9f3083 110 /**
mbed_official 423:560d1a9f3083 111 * @}
mbed_official 423:560d1a9f3083 112 */
mbed_official 423:560d1a9f3083 113
mbed_official 423:560d1a9f3083 114 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 423:560d1a9f3083 115 * @{
mbed_official 423:560d1a9f3083 116 */
mbed_official 423:560d1a9f3083 117
mbed_official 423:560d1a9f3083 118 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 423:560d1a9f3083 119 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 423:560d1a9f3083 120 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 423:560d1a9f3083 121
mbed_official 423:560d1a9f3083 122 /**
mbed_official 423:560d1a9f3083 123 * @}
mbed_official 423:560d1a9f3083 124 */
mbed_official 423:560d1a9f3083 125
mbed_official 423:560d1a9f3083 126 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 423:560d1a9f3083 127 * @{
mbed_official 423:560d1a9f3083 128 */
mbed_official 423:560d1a9f3083 129 /* This variable is updated in three ways:
mbed_official 423:560d1a9f3083 130 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 423:560d1a9f3083 131 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 423:560d1a9f3083 132 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 423:560d1a9f3083 133 Note: If you use this function to configure the system clock there is no need to
mbed_official 423:560d1a9f3083 134 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 423:560d1a9f3083 135 updated automatically.
mbed_official 423:560d1a9f3083 136 */
mbed_official 423:560d1a9f3083 137 uint32_t SystemCoreClock = 48000000;
mbed_official 423:560d1a9f3083 138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 423:560d1a9f3083 139
mbed_official 423:560d1a9f3083 140 /**
mbed_official 423:560d1a9f3083 141 * @}
mbed_official 423:560d1a9f3083 142 */
mbed_official 423:560d1a9f3083 143
mbed_official 423:560d1a9f3083 144 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 423:560d1a9f3083 145 * @{
mbed_official 423:560d1a9f3083 146 */
mbed_official 423:560d1a9f3083 147
mbed_official 423:560d1a9f3083 148 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 423:560d1a9f3083 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 423:560d1a9f3083 150 #endif
mbed_official 423:560d1a9f3083 151
mbed_official 423:560d1a9f3083 152 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 423:560d1a9f3083 153
mbed_official 423:560d1a9f3083 154 /**
mbed_official 423:560d1a9f3083 155 * @}
mbed_official 423:560d1a9f3083 156 */
mbed_official 423:560d1a9f3083 157
mbed_official 423:560d1a9f3083 158 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 423:560d1a9f3083 159 * @{
mbed_official 423:560d1a9f3083 160 */
mbed_official 423:560d1a9f3083 161
mbed_official 423:560d1a9f3083 162 /**
mbed_official 423:560d1a9f3083 163 * @brief Setup the microcontroller system.
mbed_official 423:560d1a9f3083 164 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official 423:560d1a9f3083 165 * @param None
mbed_official 423:560d1a9f3083 166 * @retval None
mbed_official 423:560d1a9f3083 167 */
mbed_official 423:560d1a9f3083 168 void SystemInit(void)
mbed_official 423:560d1a9f3083 169 {
mbed_official 423:560d1a9f3083 170 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 423:560d1a9f3083 171 /* Set HSION bit */
mbed_official 423:560d1a9f3083 172 RCC->CR |= (uint32_t)0x00000001;
mbed_official 423:560d1a9f3083 173
mbed_official 423:560d1a9f3083 174 #if defined (STM32F051x8) || defined (STM32F058x8)
mbed_official 423:560d1a9f3083 175 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 423:560d1a9f3083 176 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 423:560d1a9f3083 177 #else
mbed_official 423:560d1a9f3083 178 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 423:560d1a9f3083 179 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 423:560d1a9f3083 180 #endif /* STM32F051x8 or STM32F058x8 */
mbed_official 423:560d1a9f3083 181
mbed_official 423:560d1a9f3083 182 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 423:560d1a9f3083 183 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 423:560d1a9f3083 184
mbed_official 423:560d1a9f3083 185 /* Reset HSEBYP bit */
mbed_official 423:560d1a9f3083 186 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 423:560d1a9f3083 187
mbed_official 423:560d1a9f3083 188 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 423:560d1a9f3083 189 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 423:560d1a9f3083 190
mbed_official 423:560d1a9f3083 191 /* Reset PREDIV[3:0] bits */
mbed_official 423:560d1a9f3083 192 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 423:560d1a9f3083 193
mbed_official 423:560d1a9f3083 194 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
mbed_official 423:560d1a9f3083 195 /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 423:560d1a9f3083 196 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official 423:560d1a9f3083 197 #elif defined (STM32F091xC) || defined (STM32F098xx)
mbed_official 423:560d1a9f3083 198 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
mbed_official 423:560d1a9f3083 199 RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
mbed_official 423:560d1a9f3083 200 #else
mbed_official 423:560d1a9f3083 201 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 423:560d1a9f3083 202 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official 423:560d1a9f3083 203 #endif
mbed_official 423:560d1a9f3083 204
mbed_official 423:560d1a9f3083 205 /* Reset HSI14 bit */
mbed_official 423:560d1a9f3083 206 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 423:560d1a9f3083 207
mbed_official 423:560d1a9f3083 208 /* Disable all interrupts */
mbed_official 423:560d1a9f3083 209 RCC->CIR = 0x00000000;
mbed_official 423:560d1a9f3083 210
mbed_official 423:560d1a9f3083 211 /* Configure the Cube driver */
mbed_official 423:560d1a9f3083 212 HAL_Init();
mbed_official 423:560d1a9f3083 213
mbed_official 423:560d1a9f3083 214 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 423:560d1a9f3083 215 AHB/APBx prescalers and Flash settings */
mbed_official 423:560d1a9f3083 216 SetSysClock();
mbed_official 423:560d1a9f3083 217 }
mbed_official 423:560d1a9f3083 218
mbed_official 423:560d1a9f3083 219 /**
mbed_official 423:560d1a9f3083 220 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 423:560d1a9f3083 221 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 423:560d1a9f3083 222 * be used by the user application to setup the SysTick timer or configure
mbed_official 423:560d1a9f3083 223 * other parameters.
mbed_official 423:560d1a9f3083 224 *
mbed_official 423:560d1a9f3083 225 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 423:560d1a9f3083 226 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 423:560d1a9f3083 227 * based on this variable will be incorrect.
mbed_official 423:560d1a9f3083 228 *
mbed_official 423:560d1a9f3083 229 * @note - The system frequency computed by this function is not the real
mbed_official 423:560d1a9f3083 230 * frequency in the chip. It is calculated based on the predefined
mbed_official 423:560d1a9f3083 231 * constant and the selected clock source:
mbed_official 423:560d1a9f3083 232 *
mbed_official 423:560d1a9f3083 233 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 423:560d1a9f3083 234 *
mbed_official 423:560d1a9f3083 235 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 423:560d1a9f3083 236 *
mbed_official 423:560d1a9f3083 237 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 423:560d1a9f3083 238 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 423:560d1a9f3083 239 *
mbed_official 423:560d1a9f3083 240 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 423:560d1a9f3083 241 * 8 MHz) but the real value may vary depending on the variations
mbed_official 423:560d1a9f3083 242 * in voltage and temperature.
mbed_official 423:560d1a9f3083 243 *
mbed_official 423:560d1a9f3083 244 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 423:560d1a9f3083 245 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 423:560d1a9f3083 246 * frequency of the crystal used. Otherwise, this function may
mbed_official 423:560d1a9f3083 247 * have wrong result.
mbed_official 423:560d1a9f3083 248 *
mbed_official 423:560d1a9f3083 249 * - The result of this function could be not correct when using fractional
mbed_official 423:560d1a9f3083 250 * value for HSE crystal.
mbed_official 423:560d1a9f3083 251 *
mbed_official 423:560d1a9f3083 252 * @param None
mbed_official 423:560d1a9f3083 253 * @retval None
mbed_official 423:560d1a9f3083 254 */
mbed_official 423:560d1a9f3083 255 void SystemCoreClockUpdate (void)
mbed_official 423:560d1a9f3083 256 {
mbed_official 423:560d1a9f3083 257 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 423:560d1a9f3083 258
mbed_official 423:560d1a9f3083 259 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 423:560d1a9f3083 260 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 423:560d1a9f3083 261
mbed_official 423:560d1a9f3083 262 switch (tmp)
mbed_official 423:560d1a9f3083 263 {
mbed_official 423:560d1a9f3083 264 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 423:560d1a9f3083 265 SystemCoreClock = HSI_VALUE;
mbed_official 423:560d1a9f3083 266 break;
mbed_official 423:560d1a9f3083 267 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 423:560d1a9f3083 268 SystemCoreClock = HSE_VALUE;
mbed_official 423:560d1a9f3083 269 break;
mbed_official 423:560d1a9f3083 270 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 423:560d1a9f3083 271 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 423:560d1a9f3083 272 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 423:560d1a9f3083 273 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 423:560d1a9f3083 274 pllmull = ( pllmull >> 18) + 2;
mbed_official 423:560d1a9f3083 275 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 423:560d1a9f3083 276
mbed_official 423:560d1a9f3083 277 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 423:560d1a9f3083 278 {
mbed_official 423:560d1a9f3083 279 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
mbed_official 423:560d1a9f3083 280 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
mbed_official 423:560d1a9f3083 281 }
mbed_official 423:560d1a9f3083 282 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 423:560d1a9f3083 283 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
mbed_official 423:560d1a9f3083 284 {
mbed_official 423:560d1a9f3083 285 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
mbed_official 423:560d1a9f3083 286 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
mbed_official 423:560d1a9f3083 287 }
mbed_official 423:560d1a9f3083 288 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 423:560d1a9f3083 289 else
mbed_official 423:560d1a9f3083 290 {
mbed_official 423:560d1a9f3083 291 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 423:560d1a9f3083 292 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
mbed_official 423:560d1a9f3083 293 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
mbed_official 423:560d1a9f3083 294 #else
mbed_official 423:560d1a9f3083 295 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
mbed_official 423:560d1a9f3083 296 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 423:560d1a9f3083 297 #endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 423:560d1a9f3083 298 }
mbed_official 423:560d1a9f3083 299 break;
mbed_official 423:560d1a9f3083 300 default: /* HSI used as system clock */
mbed_official 423:560d1a9f3083 301 SystemCoreClock = HSI_VALUE;
mbed_official 423:560d1a9f3083 302 break;
mbed_official 423:560d1a9f3083 303 }
mbed_official 423:560d1a9f3083 304 /* Compute HCLK clock frequency ----------------*/
mbed_official 423:560d1a9f3083 305 /* Get HCLK prescaler */
mbed_official 423:560d1a9f3083 306 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 423:560d1a9f3083 307 /* HCLK clock frequency */
mbed_official 423:560d1a9f3083 308 SystemCoreClock >>= tmp;
mbed_official 423:560d1a9f3083 309 }
mbed_official 423:560d1a9f3083 310
mbed_official 423:560d1a9f3083 311 /**
mbed_official 423:560d1a9f3083 312 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 423:560d1a9f3083 313 * AHB/APBx prescalers and Flash settings
mbed_official 423:560d1a9f3083 314 * @note This function should be called only once the RCC clock configuration
mbed_official 423:560d1a9f3083 315 * is reset to the default reset state (done in SystemInit() function).
mbed_official 423:560d1a9f3083 316 * @param None
mbed_official 423:560d1a9f3083 317 * @retval None
mbed_official 423:560d1a9f3083 318 */
mbed_official 423:560d1a9f3083 319 void SetSysClock(void)
mbed_official 423:560d1a9f3083 320 {
mbed_official 423:560d1a9f3083 321 /* 1- Try to start with HSE and external clock */
mbed_official 423:560d1a9f3083 322 #if USE_PLL_HSE_EXTC != 0
mbed_official 423:560d1a9f3083 323 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 423:560d1a9f3083 324 #endif
mbed_official 423:560d1a9f3083 325 {
mbed_official 423:560d1a9f3083 326 /* 2- If fail try to start with HSE and external xtal */
mbed_official 423:560d1a9f3083 327 #if USE_PLL_HSE_XTAL != 0
mbed_official 423:560d1a9f3083 328 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 423:560d1a9f3083 329 #endif
mbed_official 423:560d1a9f3083 330 {
mbed_official 423:560d1a9f3083 331 /* 3- If fail start with HSI clock */
mbed_official 423:560d1a9f3083 332 if (SetSysClock_PLL_HSI() == 0)
mbed_official 423:560d1a9f3083 333 {
mbed_official 423:560d1a9f3083 334 while(1)
mbed_official 423:560d1a9f3083 335 {
mbed_official 423:560d1a9f3083 336 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 423:560d1a9f3083 337 }
mbed_official 423:560d1a9f3083 338 }
mbed_official 423:560d1a9f3083 339 }
mbed_official 423:560d1a9f3083 340 }
mbed_official 423:560d1a9f3083 341
mbed_official 423:560d1a9f3083 342 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 423:560d1a9f3083 343 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
mbed_official 423:560d1a9f3083 344 }
mbed_official 423:560d1a9f3083 345
mbed_official 423:560d1a9f3083 346 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 423:560d1a9f3083 347 /******************************************************************************/
mbed_official 423:560d1a9f3083 348 /* PLL (clocked by HSE) used as System clock source */
mbed_official 423:560d1a9f3083 349 /******************************************************************************/
mbed_official 423:560d1a9f3083 350 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 423:560d1a9f3083 351 {
mbed_official 423:560d1a9f3083 352 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 423:560d1a9f3083 353 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 423:560d1a9f3083 354
mbed_official 423:560d1a9f3083 355 // Select HSE oscillator as PLL source
mbed_official 423:560d1a9f3083 356 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 423:560d1a9f3083 357 if (bypass == 0) {
mbed_official 423:560d1a9f3083 358 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 423:560d1a9f3083 359 } else {
mbed_official 423:560d1a9f3083 360 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official 423:560d1a9f3083 361 }
mbed_official 423:560d1a9f3083 362 RCC_OscInitStruct.HSI48State = 0; // not used
mbed_official 423:560d1a9f3083 363 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 423:560d1a9f3083 364 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 423:560d1a9f3083 365 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 423:560d1a9f3083 366 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 423:560d1a9f3083 367 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 423:560d1a9f3083 368 return 0; // FAIL
mbed_official 423:560d1a9f3083 369 }
mbed_official 423:560d1a9f3083 370
mbed_official 423:560d1a9f3083 371 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 423:560d1a9f3083 372 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 423:560d1a9f3083 373 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 423:560d1a9f3083 374 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 423:560d1a9f3083 375 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 423:560d1a9f3083 376 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 423:560d1a9f3083 377 return 0; // FAIL
mbed_official 423:560d1a9f3083 378 }
mbed_official 423:560d1a9f3083 379
mbed_official 423:560d1a9f3083 380 return 1; // OK
mbed_official 423:560d1a9f3083 381 }
mbed_official 423:560d1a9f3083 382 #endif
mbed_official 423:560d1a9f3083 383
mbed_official 423:560d1a9f3083 384 /******************************************************************************/
mbed_official 423:560d1a9f3083 385 /* PLL (clocked by HSI) used as System clock source */
mbed_official 423:560d1a9f3083 386 /******************************************************************************/
mbed_official 423:560d1a9f3083 387 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 423:560d1a9f3083 388 {
mbed_official 423:560d1a9f3083 389 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 423:560d1a9f3083 390 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 423:560d1a9f3083 391
mbed_official 423:560d1a9f3083 392 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
mbed_official 423:560d1a9f3083 393 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
mbed_official 423:560d1a9f3083 394 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 423:560d1a9f3083 395 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 423:560d1a9f3083 396 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
mbed_official 423:560d1a9f3083 397 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
mbed_official 423:560d1a9f3083 398 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 423:560d1a9f3083 399 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 423:560d1a9f3083 400 return 0; // FAIL
mbed_official 423:560d1a9f3083 401 }
mbed_official 423:560d1a9f3083 402
mbed_official 423:560d1a9f3083 403 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 423:560d1a9f3083 404 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 423:560d1a9f3083 405 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 423:560d1a9f3083 406 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 423:560d1a9f3083 407 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 423:560d1a9f3083 408 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 423:560d1a9f3083 409 return 0; // FAIL
mbed_official 423:560d1a9f3083 410 }
mbed_official 423:560d1a9f3083 411
mbed_official 423:560d1a9f3083 412 return 1; // OK
mbed_official 423:560d1a9f3083 413 }
mbed_official 423:560d1a9f3083 414
mbed_official 423:560d1a9f3083 415 /* Used for the different timeouts in the HAL */
mbed_official 423:560d1a9f3083 416 void SysTick_Handler(void)
mbed_official 423:560d1a9f3083 417 {
mbed_official 423:560d1a9f3083 418 HAL_IncTick();
mbed_official 423:560d1a9f3083 419 }
mbed_official 423:560d1a9f3083 420
mbed_official 423:560d1a9f3083 421 /**
mbed_official 423:560d1a9f3083 422 * @}
mbed_official 423:560d1a9f3083 423 */
mbed_official 423:560d1a9f3083 424
mbed_official 423:560d1a9f3083 425 /**
mbed_official 423:560d1a9f3083 426 * @}
mbed_official 423:560d1a9f3083 427 */
mbed_official 423:560d1a9f3083 428
mbed_official 423:560d1a9f3083 429 /**
mbed_official 423:560d1a9f3083 430 * @}
mbed_official 423:560d1a9f3083 431 */
mbed_official 423:560d1a9f3083 432
mbed_official 423:560d1a9f3083 433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 423:560d1a9f3083 434