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targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:: moirans2
Date:: Wed Jan 14 20:53:08 2015 +0000
Revision:: 445:9a3ffe6cfa19
Parent:: 423:560d1a9f3083

internal clock stm32L051

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	423:560d1a9f3083	1	/**
mbed_official	423:560d1a9f3083	2	******************************************************************************
mbed_official	423:560d1a9f3083	3	* @file stm32f051x8.h
mbed_official	423:560d1a9f3083	4	* @author MCD Application Team
mbed_official	423:560d1a9f3083	5	* @version V2.1.0
mbed_official	423:560d1a9f3083	6	* @date 03-Oct-2014
mbed_official	423:560d1a9f3083	7	* @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
mbed_official	423:560d1a9f3083	8	* Layer Header File.
mbed_official	423:560d1a9f3083	9	*
mbed_official	423:560d1a9f3083	10	* This file contains:
mbed_official	423:560d1a9f3083	11	* - Data structures and the address mapping for all peripherals
mbed_official	423:560d1a9f3083	12	* - Peripheral's registers declarations and bits definition
mbed_official	423:560d1a9f3083	13	* - Macros to access peripherals registers hardware
mbed_official	423:560d1a9f3083	14	*
mbed_official	423:560d1a9f3083	15	******************************************************************************
mbed_official	423:560d1a9f3083	16	* @attention
mbed_official	423:560d1a9f3083	17	*
mbed_official	423:560d1a9f3083	18	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	423:560d1a9f3083	19	*
mbed_official	423:560d1a9f3083	20	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	423:560d1a9f3083	21	* are permitted provided that the following conditions are met:
mbed_official	423:560d1a9f3083	22	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	423:560d1a9f3083	23	* this list of conditions and the following disclaimer.
mbed_official	423:560d1a9f3083	24	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	423:560d1a9f3083	25	* this list of conditions and the following disclaimer in the documentation
mbed_official	423:560d1a9f3083	26	* and/or other materials provided with the distribution.
mbed_official	423:560d1a9f3083	27	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	423:560d1a9f3083	28	* may be used to endorse or promote products derived from this software
mbed_official	423:560d1a9f3083	29	* without specific prior written permission.
mbed_official	423:560d1a9f3083	30	*
mbed_official	423:560d1a9f3083	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	423:560d1a9f3083	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	423:560d1a9f3083	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	423:560d1a9f3083	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	423:560d1a9f3083	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	423:560d1a9f3083	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	423:560d1a9f3083	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	423:560d1a9f3083	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	423:560d1a9f3083	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	423:560d1a9f3083	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	423:560d1a9f3083	41	*
mbed_official	423:560d1a9f3083	42	******************************************************************************
mbed_official	423:560d1a9f3083	43	*/
mbed_official	423:560d1a9f3083	44
mbed_official	423:560d1a9f3083	45	/** @addtogroup CMSIS_Device
mbed_official	423:560d1a9f3083	46	* @{
mbed_official	423:560d1a9f3083	47	*/
mbed_official	423:560d1a9f3083	48
mbed_official	423:560d1a9f3083	49	/** @addtogroup stm32f051x8
mbed_official	423:560d1a9f3083	50	* @{
mbed_official	423:560d1a9f3083	51	*/
mbed_official	423:560d1a9f3083	52
mbed_official	423:560d1a9f3083	53	#ifndef __STM32F051x8_H
mbed_official	423:560d1a9f3083	54	#define __STM32F051x8_H
mbed_official	423:560d1a9f3083	55
mbed_official	423:560d1a9f3083	56	#ifdef __cplusplus
mbed_official	423:560d1a9f3083	57	extern "C" {
mbed_official	423:560d1a9f3083	58	#endif /* __cplusplus */
mbed_official	423:560d1a9f3083	59
mbed_official	423:560d1a9f3083	60	/** @addtogroup Configuration_section_for_CMSIS
mbed_official	423:560d1a9f3083	61	* @{
mbed_official	423:560d1a9f3083	62	*/
mbed_official	423:560d1a9f3083	63
mbed_official	423:560d1a9f3083	64	/**
mbed_official	423:560d1a9f3083	65	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official	423:560d1a9f3083	66	*/
mbed_official	423:560d1a9f3083	67	#define __CM0_REV 0 /!< Core Revision r0p0 /
mbed_official	423:560d1a9f3083	68	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
mbed_official	423:560d1a9f3083	69	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
mbed_official	423:560d1a9f3083	70	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	423:560d1a9f3083	71
mbed_official	423:560d1a9f3083	72	/**
mbed_official	423:560d1a9f3083	73	* @}
mbed_official	423:560d1a9f3083	74	*/
mbed_official	423:560d1a9f3083	75
mbed_official	423:560d1a9f3083	76	/** @addtogroup Peripheral_interrupt_number_definition
mbed_official	423:560d1a9f3083	77	* @{
mbed_official	423:560d1a9f3083	78	*/
mbed_official	423:560d1a9f3083	79
mbed_official	423:560d1a9f3083	80	/**
mbed_official	423:560d1a9f3083	81	* @brief STM32F051x4/STM32F051x6/STM32F051x8 device Interrupt Number Definition
mbed_official	423:560d1a9f3083	82	*/
mbed_official	423:560d1a9f3083	83	typedef enum
mbed_official	423:560d1a9f3083	84	{
mbed_official	423:560d1a9f3083	85	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
mbed_official	423:560d1a9f3083	86	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
mbed_official	423:560d1a9f3083	87	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
mbed_official	423:560d1a9f3083	88	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
mbed_official	423:560d1a9f3083	89	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
mbed_official	423:560d1a9f3083	90	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
mbed_official	423:560d1a9f3083	91
mbed_official	423:560d1a9f3083	92	/**** STM32F051x4/STM32F051x6/STM32F051x8 specific Interrupt Numbers ************************************/
mbed_official	423:560d1a9f3083	93	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
mbed_official	423:560d1a9f3083	94	PVD_IRQn = 1, /!< PVD Interrupt through EXTI Lines 16 /
mbed_official	423:560d1a9f3083	95	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
mbed_official	423:560d1a9f3083	96	FLASH_IRQn = 3, /!< FLASH global Interrupt /
mbed_official	423:560d1a9f3083	97	RCC_IRQn = 4, /!< RCC global Interrupt /
mbed_official	423:560d1a9f3083	98	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
mbed_official	423:560d1a9f3083	99	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
mbed_official	423:560d1a9f3083	100	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
mbed_official	423:560d1a9f3083	101	TSC_IRQn = 8, /!< Touch Sensing Controller Interrupts /
mbed_official	423:560d1a9f3083	102	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
mbed_official	423:560d1a9f3083	103	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
mbed_official	423:560d1a9f3083	104	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
mbed_official	423:560d1a9f3083	105	ADC1_COMP_IRQn = 12, /!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 /
mbed_official	423:560d1a9f3083	106	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
mbed_official	423:560d1a9f3083	107	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
mbed_official	423:560d1a9f3083	108	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
mbed_official	423:560d1a9f3083	109	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
mbed_official	423:560d1a9f3083	110	TIM6_DAC_IRQn = 17, /!< TIM6 global and DAC channel underrun error Interrupts /
mbed_official	423:560d1a9f3083	111	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
mbed_official	423:560d1a9f3083	112	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
mbed_official	423:560d1a9f3083	113	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
mbed_official	423:560d1a9f3083	114	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
mbed_official	423:560d1a9f3083	115	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
mbed_official	423:560d1a9f3083	116	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
mbed_official	423:560d1a9f3083	117	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
mbed_official	423:560d1a9f3083	118	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
mbed_official	423:560d1a9f3083	119	USART1_IRQn = 27, /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
mbed_official	423:560d1a9f3083	120	USART2_IRQn = 28, /!< USART2 global Interrupt /
mbed_official	423:560d1a9f3083	121	CEC_CAN_IRQn = 30 /!< CEC and CAN global Interrupts & EXTI Line27 Interrupt /
mbed_official	423:560d1a9f3083	122	} IRQn_Type;
mbed_official	423:560d1a9f3083	123
mbed_official	423:560d1a9f3083	124	/**
mbed_official	423:560d1a9f3083	125	* @}
mbed_official	423:560d1a9f3083	126	*/
mbed_official	423:560d1a9f3083	127
mbed_official	423:560d1a9f3083	128	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official	423:560d1a9f3083	129	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official	423:560d1a9f3083	130	#include <stdint.h>
mbed_official	423:560d1a9f3083	131
mbed_official	423:560d1a9f3083	132	/** @addtogroup Peripheral_registers_structures
mbed_official	423:560d1a9f3083	133	* @{
mbed_official	423:560d1a9f3083	134	*/
mbed_official	423:560d1a9f3083	135
mbed_official	423:560d1a9f3083	136	/**
mbed_official	423:560d1a9f3083	137	* @brief Analog to Digital Converter
mbed_official	423:560d1a9f3083	138	*/
mbed_official	423:560d1a9f3083	139
mbed_official	423:560d1a9f3083	140	typedef struct
mbed_official	423:560d1a9f3083	141	{
mbed_official	423:560d1a9f3083	142	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
mbed_official	423:560d1a9f3083	143	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
mbed_official	423:560d1a9f3083	144	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
mbed_official	423:560d1a9f3083	145	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
mbed_official	423:560d1a9f3083	146	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
mbed_official	423:560d1a9f3083	147	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
mbed_official	423:560d1a9f3083	148	uint32_t RESERVED1; /!< Reserved, 0x18 /
mbed_official	423:560d1a9f3083	149	uint32_t RESERVED2; /!< Reserved, 0x1C /
mbed_official	423:560d1a9f3083	150	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
mbed_official	423:560d1a9f3083	151	uint32_t RESERVED3; /!< Reserved, 0x24 /
mbed_official	423:560d1a9f3083	152	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
mbed_official	423:560d1a9f3083	153	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
mbed_official	423:560d1a9f3083	154	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
mbed_official	423:560d1a9f3083	155	}ADC_TypeDef;
mbed_official	423:560d1a9f3083	156
mbed_official	423:560d1a9f3083	157	typedef struct
mbed_official	423:560d1a9f3083	158	{
mbed_official	423:560d1a9f3083	159	__IO uint32_t CCR;
mbed_official	423:560d1a9f3083	160	}ADC_Common_TypeDef;
mbed_official	423:560d1a9f3083	161
mbed_official	423:560d1a9f3083	162	/**
mbed_official	423:560d1a9f3083	163	* @brief HDMI-CEC
mbed_official	423:560d1a9f3083	164	*/
mbed_official	423:560d1a9f3083	165
mbed_official	423:560d1a9f3083	166	typedef struct
mbed_official	423:560d1a9f3083	167	{
mbed_official	423:560d1a9f3083	168	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
mbed_official	423:560d1a9f3083	169	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
mbed_official	423:560d1a9f3083	170	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
mbed_official	423:560d1a9f3083	171	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
mbed_official	423:560d1a9f3083	172	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
mbed_official	423:560d1a9f3083	173	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
mbed_official	423:560d1a9f3083	174	}CEC_TypeDef;
mbed_official	423:560d1a9f3083	175
mbed_official	423:560d1a9f3083	176	/**
mbed_official	423:560d1a9f3083	177	* @brief Comparator
mbed_official	423:560d1a9f3083	178	*/
mbed_official	423:560d1a9f3083	179
mbed_official	423:560d1a9f3083	180	typedef struct
mbed_official	423:560d1a9f3083	181	{
mbed_official	423:560d1a9f3083	182	__IO uint32_t CSR; /!< Comparator 1 & 2 control Status register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	183	}COMP1_2_TypeDef;
mbed_official	423:560d1a9f3083	184
mbed_official	423:560d1a9f3083	185	typedef struct
mbed_official	423:560d1a9f3083	186	{
mbed_official	423:560d1a9f3083	187	__IO uint16_t CSR; /!< Comparator control Status register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	188	}COMP_TypeDef;
mbed_official	423:560d1a9f3083	189
mbed_official	423:560d1a9f3083	190	/**
mbed_official	423:560d1a9f3083	191	* @brief CRC calculation unit
mbed_official	423:560d1a9f3083	192	*/
mbed_official	423:560d1a9f3083	193
mbed_official	423:560d1a9f3083	194	typedef struct
mbed_official	423:560d1a9f3083	195	{
mbed_official	423:560d1a9f3083	196	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	197	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	198	uint8_t RESERVED0; /!< Reserved, 0x05 /
mbed_official	423:560d1a9f3083	199	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	423:560d1a9f3083	200	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	201	uint32_t RESERVED2; /!< Reserved, 0x0C /
mbed_official	423:560d1a9f3083	202	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	203	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	204	}CRC_TypeDef;
mbed_official	423:560d1a9f3083	205
mbed_official	423:560d1a9f3083	206	/**
mbed_official	423:560d1a9f3083	207	* @brief Digital to Analog Converter
mbed_official	423:560d1a9f3083	208	*/
mbed_official	423:560d1a9f3083	209
mbed_official	423:560d1a9f3083	210	typedef struct
mbed_official	423:560d1a9f3083	211	{
mbed_official	423:560d1a9f3083	212	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	213	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	214	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	215	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	216	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	217	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
mbed_official	423:560d1a9f3083	218	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
mbed_official	423:560d1a9f3083	219	}DAC_TypeDef;
mbed_official	423:560d1a9f3083	220
mbed_official	423:560d1a9f3083	221	/**
mbed_official	423:560d1a9f3083	222	* @brief Debug MCU
mbed_official	423:560d1a9f3083	223	*/
mbed_official	423:560d1a9f3083	224
mbed_official	423:560d1a9f3083	225	typedef struct
mbed_official	423:560d1a9f3083	226	{
mbed_official	423:560d1a9f3083	227	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	228	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	229	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	230	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	231	}DBGMCU_TypeDef;
mbed_official	423:560d1a9f3083	232
mbed_official	423:560d1a9f3083	233	/**
mbed_official	423:560d1a9f3083	234	* @brief DMA Controller
mbed_official	423:560d1a9f3083	235	*/
mbed_official	423:560d1a9f3083	236
mbed_official	423:560d1a9f3083	237	typedef struct
mbed_official	423:560d1a9f3083	238	{
mbed_official	423:560d1a9f3083	239	__IO uint32_t CCR; /!< DMA channel x configuration register /
mbed_official	423:560d1a9f3083	240	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
mbed_official	423:560d1a9f3083	241	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
mbed_official	423:560d1a9f3083	242	__IO uint32_t CMAR; /!< DMA channel x memory address register /
mbed_official	423:560d1a9f3083	243	}DMA_Channel_TypeDef;
mbed_official	423:560d1a9f3083	244
mbed_official	423:560d1a9f3083	245	typedef struct
mbed_official	423:560d1a9f3083	246	{
mbed_official	423:560d1a9f3083	247	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	248	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	249	}DMA_TypeDef;
mbed_official	423:560d1a9f3083	250
mbed_official	423:560d1a9f3083	251	/**
mbed_official	423:560d1a9f3083	252	* @brief External Interrupt/Event Controller
mbed_official	423:560d1a9f3083	253	*/
mbed_official	423:560d1a9f3083	254
mbed_official	423:560d1a9f3083	255	typedef struct
mbed_official	423:560d1a9f3083	256	{
mbed_official	423:560d1a9f3083	257	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	258	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	259	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
mbed_official	423:560d1a9f3083	260	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	261	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	262	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	263	}EXTI_TypeDef;
mbed_official	423:560d1a9f3083	264
mbed_official	423:560d1a9f3083	265	/**
mbed_official	423:560d1a9f3083	266	* @brief FLASH Registers
mbed_official	423:560d1a9f3083	267	*/
mbed_official	423:560d1a9f3083	268	typedef struct
mbed_official	423:560d1a9f3083	269	{
mbed_official	423:560d1a9f3083	270	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	271	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	272	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	273	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	274	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	275	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	276	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
mbed_official	423:560d1a9f3083	277	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	278	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	279	}FLASH_TypeDef;
mbed_official	423:560d1a9f3083	280
mbed_official	423:560d1a9f3083	281
mbed_official	423:560d1a9f3083	282	/**
mbed_official	423:560d1a9f3083	283	* @brief Option Bytes Registers
mbed_official	423:560d1a9f3083	284	*/
mbed_official	423:560d1a9f3083	285	typedef struct
mbed_official	423:560d1a9f3083	286	{
mbed_official	423:560d1a9f3083	287	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	288	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
mbed_official	423:560d1a9f3083	289	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
mbed_official	423:560d1a9f3083	290	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
mbed_official	423:560d1a9f3083	291	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	292	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
mbed_official	423:560d1a9f3083	293	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	294	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
mbed_official	423:560d1a9f3083	295	}OB_TypeDef;
mbed_official	423:560d1a9f3083	296
mbed_official	423:560d1a9f3083	297	/**
mbed_official	423:560d1a9f3083	298	* @brief General Purpose I/O
mbed_official	423:560d1a9f3083	299	*/
mbed_official	423:560d1a9f3083	300
mbed_official	423:560d1a9f3083	301	typedef struct
mbed_official	423:560d1a9f3083	302	{
mbed_official	423:560d1a9f3083	303	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	304	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	305	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	306	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	307	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	308	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	309	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
mbed_official	423:560d1a9f3083	310	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	311	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
mbed_official	423:560d1a9f3083	312	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	313	}GPIO_TypeDef;
mbed_official	423:560d1a9f3083	314
mbed_official	423:560d1a9f3083	315	/**
mbed_official	423:560d1a9f3083	316	* @brief SysTem Configuration
mbed_official	423:560d1a9f3083	317	*/
mbed_official	423:560d1a9f3083	318
mbed_official	423:560d1a9f3083	319	typedef struct
mbed_official	423:560d1a9f3083	320	{
mbed_official	423:560d1a9f3083	321	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	322	uint32_t RESERVED; /!< Reserved, 0x04 /
mbed_official	423:560d1a9f3083	323	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
mbed_official	423:560d1a9f3083	324	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	325	}SYSCFG_TypeDef;
mbed_official	423:560d1a9f3083	326
mbed_official	423:560d1a9f3083	327	/**
mbed_official	423:560d1a9f3083	328	* @brief Inter-integrated Circuit Interface
mbed_official	423:560d1a9f3083	329	*/
mbed_official	423:560d1a9f3083	330
mbed_official	423:560d1a9f3083	331	typedef struct
mbed_official	423:560d1a9f3083	332	{
mbed_official	423:560d1a9f3083	333	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	334	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	335	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	336	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	337	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	338	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	339	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	340	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	341	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	342	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	343	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	344	}I2C_TypeDef;
mbed_official	423:560d1a9f3083	345
mbed_official	423:560d1a9f3083	346	/**
mbed_official	423:560d1a9f3083	347	* @brief Independent WATCHDOG
mbed_official	423:560d1a9f3083	348	*/
mbed_official	423:560d1a9f3083	349
mbed_official	423:560d1a9f3083	350	typedef struct
mbed_official	423:560d1a9f3083	351	{
mbed_official	423:560d1a9f3083	352	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	353	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	354	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	355	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	356	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	357	}IWDG_TypeDef;
mbed_official	423:560d1a9f3083	358
mbed_official	423:560d1a9f3083	359	/**
mbed_official	423:560d1a9f3083	360	* @brief Power Control
mbed_official	423:560d1a9f3083	361	*/
mbed_official	423:560d1a9f3083	362
mbed_official	423:560d1a9f3083	363	typedef struct
mbed_official	423:560d1a9f3083	364	{
mbed_official	423:560d1a9f3083	365	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	366	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	367	}PWR_TypeDef;
mbed_official	423:560d1a9f3083	368
mbed_official	423:560d1a9f3083	369	/**
mbed_official	423:560d1a9f3083	370	* @brief Reset and Clock Control
mbed_official	423:560d1a9f3083	371	*/
mbed_official	423:560d1a9f3083	372	typedef struct
mbed_official	423:560d1a9f3083	373	{
mbed_official	423:560d1a9f3083	374	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	375	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	376	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	377	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	378	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	379	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	380	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	381	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	382	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	383	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	384	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	385	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
mbed_official	423:560d1a9f3083	386	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
mbed_official	423:560d1a9f3083	387	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
mbed_official	423:560d1a9f3083	388	}RCC_TypeDef;
mbed_official	423:560d1a9f3083	389
mbed_official	423:560d1a9f3083	390	/**
mbed_official	423:560d1a9f3083	391	* @brief Real-Time Clock
mbed_official	423:560d1a9f3083	392	*/
mbed_official	423:560d1a9f3083	393
mbed_official	423:560d1a9f3083	394	typedef struct
mbed_official	423:560d1a9f3083	395	{
mbed_official	423:560d1a9f3083	396	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	397	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	398	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	399	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	400	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	401	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	402	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	403	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	404	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	405	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	406	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	407	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
mbed_official	423:560d1a9f3083	408	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
mbed_official	423:560d1a9f3083	409	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
mbed_official	423:560d1a9f3083	410	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
mbed_official	423:560d1a9f3083	411	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
mbed_official	423:560d1a9f3083	412	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
mbed_official	423:560d1a9f3083	413	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
mbed_official	423:560d1a9f3083	414	uint32_t RESERVED4; /!< Reserved, Address offset: 0x48 /
mbed_official	423:560d1a9f3083	415	uint32_t RESERVED5; /!< Reserved, Address offset: 0x4C /
mbed_official	423:560d1a9f3083	416	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
mbed_official	423:560d1a9f3083	417	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
mbed_official	423:560d1a9f3083	418	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
mbed_official	423:560d1a9f3083	419	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
mbed_official	423:560d1a9f3083	420	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
mbed_official	423:560d1a9f3083	421	}RTC_TypeDef;
mbed_official	423:560d1a9f3083	422
mbed_official	423:560d1a9f3083	423	/**
mbed_official	423:560d1a9f3083	424	* @brief Serial Peripheral Interface
mbed_official	423:560d1a9f3083	425	*/
mbed_official	423:560d1a9f3083	426
mbed_official	423:560d1a9f3083	427	typedef struct
mbed_official	423:560d1a9f3083	428	{
mbed_official	423:560d1a9f3083	429	__IO uint16_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
mbed_official	423:560d1a9f3083	430	uint16_t RESERVED0; /!< Reserved, 0x02 /
mbed_official	423:560d1a9f3083	431	__IO uint16_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	432	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	423:560d1a9f3083	433	__IO uint16_t SR; /!< SPI Status register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	434	uint16_t RESERVED2; /!< Reserved, 0x0A /
mbed_official	423:560d1a9f3083	435	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	436	uint16_t RESERVED3; /!< Reserved, 0x0E /
mbed_official	423:560d1a9f3083	437	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
mbed_official	423:560d1a9f3083	438	uint16_t RESERVED4; /!< Reserved, 0x12 /
mbed_official	423:560d1a9f3083	439	__IO uint16_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
mbed_official	423:560d1a9f3083	440	uint16_t RESERVED5; /!< Reserved, 0x16 /
mbed_official	423:560d1a9f3083	441	__IO uint16_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
mbed_official	423:560d1a9f3083	442	uint16_t RESERVED6; /!< Reserved, 0x1A /
mbed_official	423:560d1a9f3083	443	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	444	uint16_t RESERVED7; /!< Reserved, 0x1E /
mbed_official	423:560d1a9f3083	445	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	446	uint16_t RESERVED8; /!< Reserved, 0x22 /
mbed_official	423:560d1a9f3083	447	}SPI_TypeDef;
mbed_official	423:560d1a9f3083	448
mbed_official	423:560d1a9f3083	449	/**
mbed_official	423:560d1a9f3083	450	* @brief TIM
mbed_official	423:560d1a9f3083	451	*/
mbed_official	423:560d1a9f3083	452	typedef struct
mbed_official	423:560d1a9f3083	453	{
mbed_official	423:560d1a9f3083	454	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	455	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	456	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	457	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	458	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	459	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	460	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	461	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	462	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	463	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	464	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	465	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
mbed_official	423:560d1a9f3083	466	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
mbed_official	423:560d1a9f3083	467	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
mbed_official	423:560d1a9f3083	468	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
mbed_official	423:560d1a9f3083	469	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
mbed_official	423:560d1a9f3083	470	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
mbed_official	423:560d1a9f3083	471	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
mbed_official	423:560d1a9f3083	472	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
mbed_official	423:560d1a9f3083	473	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
mbed_official	423:560d1a9f3083	474	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
mbed_official	423:560d1a9f3083	475	}TIM_TypeDef;
mbed_official	423:560d1a9f3083	476
mbed_official	423:560d1a9f3083	477	/**
mbed_official	423:560d1a9f3083	478	* @brief Touch Sensing Controller (TSC)
mbed_official	423:560d1a9f3083	479	*/
mbed_official	423:560d1a9f3083	480	typedef struct
mbed_official	423:560d1a9f3083	481	{
mbed_official	423:560d1a9f3083	482	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	483	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	484	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	485	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	486	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	487	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	488	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	489	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	490	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	491	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	492	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	493	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
mbed_official	423:560d1a9f3083	494	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
mbed_official	423:560d1a9f3083	495	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
mbed_official	423:560d1a9f3083	496	}TSC_TypeDef;
mbed_official	423:560d1a9f3083	497
mbed_official	423:560d1a9f3083	498	/**
mbed_official	423:560d1a9f3083	499	* @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official	423:560d1a9f3083	500	*/
mbed_official	423:560d1a9f3083	501
mbed_official	423:560d1a9f3083	502	typedef struct
mbed_official	423:560d1a9f3083	503	{
mbed_official	423:560d1a9f3083	504	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	505	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	506	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	507	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
mbed_official	423:560d1a9f3083	508	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
mbed_official	423:560d1a9f3083	509	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
mbed_official	423:560d1a9f3083	510	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
mbed_official	423:560d1a9f3083	511	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
mbed_official	423:560d1a9f3083	512	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
mbed_official	423:560d1a9f3083	513	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
mbed_official	423:560d1a9f3083	514	uint16_t RESERVED1; /!< Reserved, 0x26 /
mbed_official	423:560d1a9f3083	515	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
mbed_official	423:560d1a9f3083	516	uint16_t RESERVED2; /!< Reserved, 0x2A /
mbed_official	423:560d1a9f3083	517	}USART_TypeDef;
mbed_official	423:560d1a9f3083	518
mbed_official	423:560d1a9f3083	519	/**
mbed_official	423:560d1a9f3083	520	* @brief Window WATCHDOG
mbed_official	423:560d1a9f3083	521	*/
mbed_official	423:560d1a9f3083	522	typedef struct
mbed_official	423:560d1a9f3083	523	{
mbed_official	423:560d1a9f3083	524	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
mbed_official	423:560d1a9f3083	525	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
mbed_official	423:560d1a9f3083	526	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
mbed_official	423:560d1a9f3083	527	}WWDG_TypeDef;
mbed_official	423:560d1a9f3083	528
mbed_official	423:560d1a9f3083	529	/**
mbed_official	423:560d1a9f3083	530	* @}
mbed_official	423:560d1a9f3083	531	*/
mbed_official	423:560d1a9f3083	532
mbed_official	423:560d1a9f3083	533	/** @addtogroup Peripheral_memory_map
mbed_official	423:560d1a9f3083	534	* @{
mbed_official	423:560d1a9f3083	535	*/
mbed_official	423:560d1a9f3083	536
mbed_official	423:560d1a9f3083	537	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
mbed_official	423:560d1a9f3083	538	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
mbed_official	423:560d1a9f3083	539	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
mbed_official	423:560d1a9f3083	540
mbed_official	423:560d1a9f3083	541	/!< Peripheral memory map /
mbed_official	423:560d1a9f3083	542	#define APBPERIPH_BASE PERIPH_BASE
mbed_official	423:560d1a9f3083	543	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official	423:560d1a9f3083	544	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official	423:560d1a9f3083	545
mbed_official	423:560d1a9f3083	546	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official	423:560d1a9f3083	547	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official	423:560d1a9f3083	548	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official	423:560d1a9f3083	549	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official	423:560d1a9f3083	550	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official	423:560d1a9f3083	551	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official	423:560d1a9f3083	552	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official	423:560d1a9f3083	553	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official	423:560d1a9f3083	554	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official	423:560d1a9f3083	555	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official	423:560d1a9f3083	556	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official	423:560d1a9f3083	557	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official	423:560d1a9f3083	558	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
mbed_official	423:560d1a9f3083	559	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official	423:560d1a9f3083	560
mbed_official	423:560d1a9f3083	561	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official	423:560d1a9f3083	562	#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official	423:560d1a9f3083	563	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official	423:560d1a9f3083	564	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official	423:560d1a9f3083	565	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official	423:560d1a9f3083	566	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official	423:560d1a9f3083	567	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official	423:560d1a9f3083	568	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official	423:560d1a9f3083	569	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official	423:560d1a9f3083	570	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official	423:560d1a9f3083	571	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official	423:560d1a9f3083	572	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official	423:560d1a9f3083	573
mbed_official	423:560d1a9f3083	574	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official	423:560d1a9f3083	575	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official	423:560d1a9f3083	576	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official	423:560d1a9f3083	577	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official	423:560d1a9f3083	578	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official	423:560d1a9f3083	579	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official	423:560d1a9f3083	580
mbed_official	423:560d1a9f3083	581	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official	423:560d1a9f3083	582	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
mbed_official	423:560d1a9f3083	583	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
mbed_official	423:560d1a9f3083	584	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official	423:560d1a9f3083	585	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official	423:560d1a9f3083	586
mbed_official	423:560d1a9f3083	587	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official	423:560d1a9f3083	588	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official	423:560d1a9f3083	589	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official	423:560d1a9f3083	590	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official	423:560d1a9f3083	591	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official	423:560d1a9f3083	592
mbed_official	423:560d1a9f3083	593	/**
mbed_official	423:560d1a9f3083	594	* @}
mbed_official	423:560d1a9f3083	595	*/
mbed_official	423:560d1a9f3083	596
mbed_official	423:560d1a9f3083	597	/** @addtogroup Peripheral_declaration
mbed_official	423:560d1a9f3083	598	* @{
mbed_official	423:560d1a9f3083	599	*/
mbed_official	423:560d1a9f3083	600
mbed_official	423:560d1a9f3083	601	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official	423:560d1a9f3083	602	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official	423:560d1a9f3083	603	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official	423:560d1a9f3083	604	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official	423:560d1a9f3083	605	#define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official	423:560d1a9f3083	606	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official	423:560d1a9f3083	607	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official	423:560d1a9f3083	608	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official	423:560d1a9f3083	609	#define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official	423:560d1a9f3083	610	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official	423:560d1a9f3083	611	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official	423:560d1a9f3083	612	#define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official	423:560d1a9f3083	613	#define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official	423:560d1a9f3083	614	#define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official	423:560d1a9f3083	615	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official	423:560d1a9f3083	616	#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
mbed_official	423:560d1a9f3083	617	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official	423:560d1a9f3083	618	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
mbed_official	423:560d1a9f3083	619	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official	423:560d1a9f3083	620	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official	423:560d1a9f3083	621	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official	423:560d1a9f3083	622	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official	423:560d1a9f3083	623	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official	423:560d1a9f3083	624	#define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official	423:560d1a9f3083	625	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official	423:560d1a9f3083	626	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official	423:560d1a9f3083	627	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official	423:560d1a9f3083	628	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official	423:560d1a9f3083	629	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official	423:560d1a9f3083	630	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official	423:560d1a9f3083	631	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official	423:560d1a9f3083	632	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official	423:560d1a9f3083	633	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official	423:560d1a9f3083	634	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official	423:560d1a9f3083	635	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official	423:560d1a9f3083	636	#define OB ((OB_TypeDef *) OB_BASE)
mbed_official	423:560d1a9f3083	637	#define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official	423:560d1a9f3083	638	#define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official	423:560d1a9f3083	639	#define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official	423:560d1a9f3083	640	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official	423:560d1a9f3083	641	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official	423:560d1a9f3083	642	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official	423:560d1a9f3083	643	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official	423:560d1a9f3083	644	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official	423:560d1a9f3083	645
mbed_official	423:560d1a9f3083	646	/**
mbed_official	423:560d1a9f3083	647	* @}
mbed_official	423:560d1a9f3083	648	*/
mbed_official	423:560d1a9f3083	649
mbed_official	423:560d1a9f3083	650	/** @addtogroup Exported_constants
mbed_official	423:560d1a9f3083	651	* @{
mbed_official	423:560d1a9f3083	652	*/
mbed_official	423:560d1a9f3083	653
mbed_official	423:560d1a9f3083	654	/** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official	423:560d1a9f3083	655	* @{
mbed_official	423:560d1a9f3083	656	*/
mbed_official	423:560d1a9f3083	657
mbed_official	423:560d1a9f3083	658	/******************************************************************************/
mbed_official	423:560d1a9f3083	659	/* Peripheral Registers Bits Definition */
mbed_official	423:560d1a9f3083	660	/******************************************************************************/
mbed_official	423:560d1a9f3083	661	/******************************************************************************/
mbed_official	423:560d1a9f3083	662	/* */
mbed_official	423:560d1a9f3083	663	/* Analog to Digital Converter (ADC) */
mbed_official	423:560d1a9f3083	664	/* */
mbed_official	423:560d1a9f3083	665	/******************************************************************************/
mbed_official	423:560d1a9f3083	666	/****************** Bits definition for ADC_ISR register ****************/
mbed_official	423:560d1a9f3083	667	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
mbed_official	423:560d1a9f3083	668	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
mbed_official	423:560d1a9f3083	669	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
mbed_official	423:560d1a9f3083	670	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
mbed_official	423:560d1a9f3083	671	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
mbed_official	423:560d1a9f3083	672	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
mbed_official	423:560d1a9f3083	673
mbed_official	423:560d1a9f3083	674	/* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	675	#define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official	423:560d1a9f3083	676
mbed_official	423:560d1a9f3083	677	/****************** Bits definition for ADC_IER register ****************/
mbed_official	423:560d1a9f3083	678	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
mbed_official	423:560d1a9f3083	679	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
mbed_official	423:560d1a9f3083	680	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
mbed_official	423:560d1a9f3083	681	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
mbed_official	423:560d1a9f3083	682	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
mbed_official	423:560d1a9f3083	683	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
mbed_official	423:560d1a9f3083	684
mbed_official	423:560d1a9f3083	685	/* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	686	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official	423:560d1a9f3083	687
mbed_official	423:560d1a9f3083	688	/****************** Bits definition for ADC_CR register *****************/
mbed_official	423:560d1a9f3083	689	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
mbed_official	423:560d1a9f3083	690	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
mbed_official	423:560d1a9f3083	691	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
mbed_official	423:560d1a9f3083	692	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
mbed_official	423:560d1a9f3083	693	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
mbed_official	423:560d1a9f3083	694
mbed_official	423:560d1a9f3083	695	/***************** Bits definition for ADC_CFGR1 register ***************/
mbed_official	423:560d1a9f3083	696	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
mbed_official	423:560d1a9f3083	697	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	698	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	699	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	700	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
mbed_official	423:560d1a9f3083	701	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
mbed_official	423:560d1a9f3083	702	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
mbed_official	423:560d1a9f3083	703	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
mbed_official	423:560d1a9f3083	704	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
mbed_official	423:560d1a9f3083	705	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
mbed_official	423:560d1a9f3083	706	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
mbed_official	423:560d1a9f3083	707	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
mbed_official	423:560d1a9f3083	708	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
mbed_official	423:560d1a9f3083	709	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
mbed_official	423:560d1a9f3083	710	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	423:560d1a9f3083	711	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	423:560d1a9f3083	712	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
mbed_official	423:560d1a9f3083	713	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
mbed_official	423:560d1a9f3083	714	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
mbed_official	423:560d1a9f3083	715	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
mbed_official	423:560d1a9f3083	716	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
mbed_official	423:560d1a9f3083	717	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
mbed_official	423:560d1a9f3083	718	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	423:560d1a9f3083	719	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	423:560d1a9f3083	720	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
mbed_official	423:560d1a9f3083	721	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
mbed_official	423:560d1a9f3083	722	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
mbed_official	423:560d1a9f3083	723
mbed_official	423:560d1a9f3083	724	/* Old WAIT bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	725	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official	423:560d1a9f3083	726
mbed_official	423:560d1a9f3083	727	/***************** Bits definition for ADC_CFGR2 register ***************/
mbed_official	423:560d1a9f3083	728	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
mbed_official	423:560d1a9f3083	729	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
mbed_official	423:560d1a9f3083	730	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
mbed_official	423:560d1a9f3083	731
mbed_official	423:560d1a9f3083	732	/* Old bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	733	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
mbed_official	423:560d1a9f3083	734	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
mbed_official	423:560d1a9f3083	735
mbed_official	423:560d1a9f3083	736	/**************** Bit definition for ADC_SMPR register ******************/
mbed_official	423:560d1a9f3083	737	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	423:560d1a9f3083	738	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	423:560d1a9f3083	739	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	423:560d1a9f3083	740	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	423:560d1a9f3083	741
mbed_official	423:560d1a9f3083	742	/* Old bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	743	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
mbed_official	423:560d1a9f3083	744	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
mbed_official	423:560d1a9f3083	745	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
mbed_official	423:560d1a9f3083	746	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
mbed_official	423:560d1a9f3083	747
mbed_official	423:560d1a9f3083	748	/***************** Bit definition for ADC_TR register ******************/
mbed_official	423:560d1a9f3083	749	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
mbed_official	423:560d1a9f3083	750	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
mbed_official	423:560d1a9f3083	751
mbed_official	423:560d1a9f3083	752	/* Old bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	753	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
mbed_official	423:560d1a9f3083	754	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
mbed_official	423:560d1a9f3083	755
mbed_official	423:560d1a9f3083	756	/**************** Bit definition for ADC_CHSELR register ****************/
mbed_official	423:560d1a9f3083	757	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
mbed_official	423:560d1a9f3083	758	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
mbed_official	423:560d1a9f3083	759	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
mbed_official	423:560d1a9f3083	760	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
mbed_official	423:560d1a9f3083	761	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
mbed_official	423:560d1a9f3083	762	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
mbed_official	423:560d1a9f3083	763	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
mbed_official	423:560d1a9f3083	764	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
mbed_official	423:560d1a9f3083	765	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
mbed_official	423:560d1a9f3083	766	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
mbed_official	423:560d1a9f3083	767	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
mbed_official	423:560d1a9f3083	768	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
mbed_official	423:560d1a9f3083	769	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
mbed_official	423:560d1a9f3083	770	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
mbed_official	423:560d1a9f3083	771	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
mbed_official	423:560d1a9f3083	772	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
mbed_official	423:560d1a9f3083	773	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
mbed_official	423:560d1a9f3083	774	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
mbed_official	423:560d1a9f3083	775	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
mbed_official	423:560d1a9f3083	776
mbed_official	423:560d1a9f3083	777	/****************** Bit definition for ADC_DR register ******************/
mbed_official	423:560d1a9f3083	778	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
mbed_official	423:560d1a9f3083	779
mbed_official	423:560d1a9f3083	780	/***************** Bit definition for ADC_CCR register ******************/
mbed_official	423:560d1a9f3083	781	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
mbed_official	423:560d1a9f3083	782	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
mbed_official	423:560d1a9f3083	783	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
mbed_official	423:560d1a9f3083	784
mbed_official	423:560d1a9f3083	785
mbed_official	423:560d1a9f3083	786	/******************************************************************************/
mbed_official	423:560d1a9f3083	787	/* */
mbed_official	423:560d1a9f3083	788	/* HDMI-CEC (CEC) */
mbed_official	423:560d1a9f3083	789	/* */
mbed_official	423:560d1a9f3083	790	/******************************************************************************/
mbed_official	423:560d1a9f3083	791
mbed_official	423:560d1a9f3083	792	/***************** Bit definition for CEC_CR register *******************/
mbed_official	423:560d1a9f3083	793	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
mbed_official	423:560d1a9f3083	794	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
mbed_official	423:560d1a9f3083	795	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
mbed_official	423:560d1a9f3083	796
mbed_official	423:560d1a9f3083	797	/***************** Bit definition for CEC_CFGR register *****************/
mbed_official	423:560d1a9f3083	798	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
mbed_official	423:560d1a9f3083	799	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
mbed_official	423:560d1a9f3083	800	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
mbed_official	423:560d1a9f3083	801	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
mbed_official	423:560d1a9f3083	802	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Bit Period Error gener. /
mbed_official	423:560d1a9f3083	803	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast No Error generation /
mbed_official	423:560d1a9f3083	804	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
mbed_official	423:560d1a9f3083	805	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
mbed_official	423:560d1a9f3083	806	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
mbed_official	423:560d1a9f3083	807
mbed_official	423:560d1a9f3083	808	/***************** Bit definition for CEC_TXDR register *****************/
mbed_official	423:560d1a9f3083	809	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
mbed_official	423:560d1a9f3083	810
mbed_official	423:560d1a9f3083	811	/***************** Bit definition for CEC_RXDR register *****************/
mbed_official	423:560d1a9f3083	812	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
mbed_official	423:560d1a9f3083	813
mbed_official	423:560d1a9f3083	814	/***************** Bit definition for CEC_ISR register ******************/
mbed_official	423:560d1a9f3083	815	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
mbed_official	423:560d1a9f3083	816	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
mbed_official	423:560d1a9f3083	817	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
mbed_official	423:560d1a9f3083	818	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
mbed_official	423:560d1a9f3083	819	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
mbed_official	423:560d1a9f3083	820	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
mbed_official	423:560d1a9f3083	821	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
mbed_official	423:560d1a9f3083	822	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
mbed_official	423:560d1a9f3083	823	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
mbed_official	423:560d1a9f3083	824	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
mbed_official	423:560d1a9f3083	825	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
mbed_official	423:560d1a9f3083	826	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
mbed_official	423:560d1a9f3083	827	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
mbed_official	423:560d1a9f3083	828
mbed_official	423:560d1a9f3083	829	/***************** Bit definition for CEC_IER register ******************/
mbed_official	423:560d1a9f3083	830	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
mbed_official	423:560d1a9f3083	831	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
mbed_official	423:560d1a9f3083	832	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
mbed_official	423:560d1a9f3083	833	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
mbed_official	423:560d1a9f3083	834	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
mbed_official	423:560d1a9f3083	835	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
mbed_official	423:560d1a9f3083	836	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
mbed_official	423:560d1a9f3083	837	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
mbed_official	423:560d1a9f3083	838	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
mbed_official	423:560d1a9f3083	839	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
mbed_official	423:560d1a9f3083	840	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
mbed_official	423:560d1a9f3083	841	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
mbed_official	423:560d1a9f3083	842	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
mbed_official	423:560d1a9f3083	843
mbed_official	423:560d1a9f3083	844
mbed_official	423:560d1a9f3083	845	/******************************************************************************/
mbed_official	423:560d1a9f3083	846	/* */
mbed_official	423:560d1a9f3083	847	/* Analog Comparators (COMP) */
mbed_official	423:560d1a9f3083	848	/* */
mbed_official	423:560d1a9f3083	849	/******************************************************************************/
mbed_official	423:560d1a9f3083	850	/********************* Bit definition for COMP_CSR register *************/
mbed_official	423:560d1a9f3083	851	/* COMP1 bits definition */
mbed_official	423:560d1a9f3083	852	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
mbed_official	423:560d1a9f3083	853	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< SW1 switch control /
mbed_official	423:560d1a9f3083	854	#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
mbed_official	423:560d1a9f3083	855	#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
mbed_official	423:560d1a9f3083	856	#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
mbed_official	423:560d1a9f3083	857	#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
mbed_official	423:560d1a9f3083	858	#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
mbed_official	423:560d1a9f3083	859	#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
mbed_official	423:560d1a9f3083	860	#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
mbed_official	423:560d1a9f3083	861	#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /!< COMP1 output select /
mbed_official	423:560d1a9f3083	862	#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /!< COMP1 output select bit 0 /
mbed_official	423:560d1a9f3083	863	#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /!< COMP1 output select bit 1 /
mbed_official	423:560d1a9f3083	864	#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /!< COMP1 output select bit 2 /
mbed_official	423:560d1a9f3083	865	#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /!< COMP1 output polarity /
mbed_official	423:560d1a9f3083	866	#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /!< COMP1 hysteresis /
mbed_official	423:560d1a9f3083	867	#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /!< COMP1 hysteresis bit 0 /
mbed_official	423:560d1a9f3083	868	#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /!< COMP1 hysteresis bit 1 /
mbed_official	423:560d1a9f3083	869	#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /!< COMP1 output level /
mbed_official	423:560d1a9f3083	870	#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /!< COMP1 lock /
mbed_official	423:560d1a9f3083	871	/* COMP2 bits definition */
mbed_official	423:560d1a9f3083	872	#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /!< COMP2 enable /
mbed_official	423:560d1a9f3083	873	#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /!< COMP2 power mode /
mbed_official	423:560d1a9f3083	874	#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /!< COMP2 power mode bit 0 /
mbed_official	423:560d1a9f3083	875	#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /!< COMP2 power mode bit 1 /
mbed_official	423:560d1a9f3083	876	#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /!< COMP2 inverting input select /
mbed_official	423:560d1a9f3083	877	#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /!< COMP2 inverting input select bit 0 /
mbed_official	423:560d1a9f3083	878	#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /!< COMP2 inverting input select bit 1 /
mbed_official	423:560d1a9f3083	879	#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /!< COMP2 inverting input select bit 2 /
mbed_official	423:560d1a9f3083	880	#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /!< Comparators window mode enable /
mbed_official	423:560d1a9f3083	881	#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /!< COMP2 output select /
mbed_official	423:560d1a9f3083	882	#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /!< COMP2 output select bit 0 /
mbed_official	423:560d1a9f3083	883	#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /!< COMP2 output select bit 1 /
mbed_official	423:560d1a9f3083	884	#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /!< COMP2 output select bit 2 /
mbed_official	423:560d1a9f3083	885	#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /!< COMP2 output polarity /
mbed_official	423:560d1a9f3083	886	#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /!< COMP2 hysteresis /
mbed_official	423:560d1a9f3083	887	#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /!< COMP2 hysteresis bit 0 /
mbed_official	423:560d1a9f3083	888	#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /!< COMP2 hysteresis bit 1 /
mbed_official	423:560d1a9f3083	889	#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
mbed_official	423:560d1a9f3083	890	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
mbed_official	423:560d1a9f3083	891	/* COMPx bits definition */
mbed_official	423:560d1a9f3083	892	#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /!< COMPx enable /
mbed_official	423:560d1a9f3083	893	#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /!< COMPx power mode /
mbed_official	423:560d1a9f3083	894	#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /!< COMPx power mode bit 0 /
mbed_official	423:560d1a9f3083	895	#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /!< COMPx power mode bit 1 /
mbed_official	423:560d1a9f3083	896	#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /!< COMPx inverting input select /
mbed_official	423:560d1a9f3083	897	#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /!< COMPx inverting input select bit 0 /
mbed_official	423:560d1a9f3083	898	#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /!< COMPx inverting input select bit 1 /
mbed_official	423:560d1a9f3083	899	#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /!< COMPx inverting input select bit 2 /
mbed_official	423:560d1a9f3083	900	#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /!< COMPx output select /
mbed_official	423:560d1a9f3083	901	#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /!< COMPx output select bit 0 /
mbed_official	423:560d1a9f3083	902	#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /!< COMPx output select bit 1 /
mbed_official	423:560d1a9f3083	903	#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /!< COMPx output select bit 2 /
mbed_official	423:560d1a9f3083	904	#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /!< COMPx output polarity /
mbed_official	423:560d1a9f3083	905	#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /!< COMPx hysteresis /
mbed_official	423:560d1a9f3083	906	#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /!< COMPx hysteresis bit 0 /
mbed_official	423:560d1a9f3083	907	#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /!< COMPx hysteresis bit 1 /
mbed_official	423:560d1a9f3083	908	#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /!< COMPx output level /
mbed_official	423:560d1a9f3083	909	#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /!< COMPx lock /
mbed_official	423:560d1a9f3083	910
mbed_official	423:560d1a9f3083	911	/******************************************************************************/
mbed_official	423:560d1a9f3083	912	/* */
mbed_official	423:560d1a9f3083	913	/* CRC calculation unit (CRC) */
mbed_official	423:560d1a9f3083	914	/* */
mbed_official	423:560d1a9f3083	915	/******************************************************************************/
mbed_official	423:560d1a9f3083	916	/***************** Bit definition for CRC_DR register *******************/
mbed_official	423:560d1a9f3083	917	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
mbed_official	423:560d1a9f3083	918
mbed_official	423:560d1a9f3083	919	/***************** Bit definition for CRC_IDR register ******************/
mbed_official	423:560d1a9f3083	920	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
mbed_official	423:560d1a9f3083	921
mbed_official	423:560d1a9f3083	922	/****************** Bit definition for CRC_CR register ******************/
mbed_official	423:560d1a9f3083	923	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
mbed_official	423:560d1a9f3083	924	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
mbed_official	423:560d1a9f3083	925	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
mbed_official	423:560d1a9f3083	926	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
mbed_official	423:560d1a9f3083	927	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
mbed_official	423:560d1a9f3083	928
mbed_official	423:560d1a9f3083	929	/***************** Bit definition for CRC_INIT register *****************/
mbed_official	423:560d1a9f3083	930	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
mbed_official	423:560d1a9f3083	931
mbed_official	423:560d1a9f3083	932
mbed_official	423:560d1a9f3083	933	/******************************************************************************/
mbed_official	423:560d1a9f3083	934	/* */
mbed_official	423:560d1a9f3083	935	/* Digital to Analog Converter (DAC) */
mbed_official	423:560d1a9f3083	936	/* */
mbed_official	423:560d1a9f3083	937	/******************************************************************************/
mbed_official	423:560d1a9f3083	938	/****************** Bit definition for DAC_CR register ******************/
mbed_official	423:560d1a9f3083	939	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
mbed_official	423:560d1a9f3083	940	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
mbed_official	423:560d1a9f3083	941	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
mbed_official	423:560d1a9f3083	942
mbed_official	423:560d1a9f3083	943	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
mbed_official	423:560d1a9f3083	944	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	423:560d1a9f3083	945	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	423:560d1a9f3083	946	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	423:560d1a9f3083	947
mbed_official	423:560d1a9f3083	948	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
mbed_official	423:560d1a9f3083	949	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!< DAC channel1 DMA Underrun Interrupt enable /
mbed_official	423:560d1a9f3083	950
mbed_official	423:560d1a9f3083	951
mbed_official	423:560d1a9f3083	952	/*************** Bit definition for DAC_SWTRIGR register ****************/
mbed_official	423:560d1a9f3083	953	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
mbed_official	423:560d1a9f3083	954
mbed_official	423:560d1a9f3083	955	/*************** Bit definition for DAC_DHR12R1 register ****************/
mbed_official	423:560d1a9f3083	956	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
mbed_official	423:560d1a9f3083	957
mbed_official	423:560d1a9f3083	958	/*************** Bit definition for DAC_DHR12L1 register ****************/
mbed_official	423:560d1a9f3083	959	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
mbed_official	423:560d1a9f3083	960
mbed_official	423:560d1a9f3083	961	/**************** Bit definition for DAC_DHR8R1 register ****************/
mbed_official	423:560d1a9f3083	962	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
mbed_official	423:560d1a9f3083	963
mbed_official	423:560d1a9f3083	964	/*************** Bit definition for DAC_DHR12RD register ****************/
mbed_official	423:560d1a9f3083	965	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
mbed_official	423:560d1a9f3083	966
mbed_official	423:560d1a9f3083	967	/*************** Bit definition for DAC_DHR12LD register ****************/
mbed_official	423:560d1a9f3083	968	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
mbed_official	423:560d1a9f3083	969
mbed_official	423:560d1a9f3083	970	/**************** Bit definition for DAC_DHR8RD register ****************/
mbed_official	423:560d1a9f3083	971	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
mbed_official	423:560d1a9f3083	972
mbed_official	423:560d1a9f3083	973	/***************** Bit definition for DAC_DOR1 register *****************/
mbed_official	423:560d1a9f3083	974	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
mbed_official	423:560d1a9f3083	975
mbed_official	423:560d1a9f3083	976	/****************** Bit definition for DAC_SR register ******************/
mbed_official	423:560d1a9f3083	977	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
mbed_official	423:560d1a9f3083	978
mbed_official	423:560d1a9f3083	979
mbed_official	423:560d1a9f3083	980	/******************************************************************************/
mbed_official	423:560d1a9f3083	981	/* */
mbed_official	423:560d1a9f3083	982	/* Debug MCU (DBGMCU) */
mbed_official	423:560d1a9f3083	983	/* */
mbed_official	423:560d1a9f3083	984	/******************************************************************************/
mbed_official	423:560d1a9f3083	985
mbed_official	423:560d1a9f3083	986	/************** Bit definition for DBGMCU_IDCODE register ***************/
mbed_official	423:560d1a9f3083	987	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
mbed_official	423:560d1a9f3083	988
mbed_official	423:560d1a9f3083	989	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
mbed_official	423:560d1a9f3083	990	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	991	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	992	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	993	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	423:560d1a9f3083	994	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	423:560d1a9f3083	995	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
mbed_official	423:560d1a9f3083	996	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
mbed_official	423:560d1a9f3083	997	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
mbed_official	423:560d1a9f3083	998	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
mbed_official	423:560d1a9f3083	999	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
mbed_official	423:560d1a9f3083	1000	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
mbed_official	423:560d1a9f3083	1001	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
mbed_official	423:560d1a9f3083	1002	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
mbed_official	423:560d1a9f3083	1003	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
mbed_official	423:560d1a9f3083	1004	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
mbed_official	423:560d1a9f3083	1005	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
mbed_official	423:560d1a9f3083	1006
mbed_official	423:560d1a9f3083	1007	/**************** Bit definition for DBGMCU_CR register *****************/
mbed_official	423:560d1a9f3083	1008	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
mbed_official	423:560d1a9f3083	1009	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
mbed_official	423:560d1a9f3083	1010
mbed_official	423:560d1a9f3083	1011	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official	423:560d1a9f3083	1012	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1013	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1014	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)/
mbed_official	423:560d1a9f3083	1015	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1016	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
mbed_official	423:560d1a9f3083	1017	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
mbed_official	423:560d1a9f3083	1018	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
mbed_official	423:560d1a9f3083	1019	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
mbed_official	423:560d1a9f3083	1020
mbed_official	423:560d1a9f3083	1021	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official	423:560d1a9f3083	1022	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1023	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) /
mbed_official	423:560d1a9f3083	1024	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1025	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
mbed_official	423:560d1a9f3083	1026
mbed_official	423:560d1a9f3083	1027	/******************************************************************************/
mbed_official	423:560d1a9f3083	1028	/* */
mbed_official	423:560d1a9f3083	1029	/* DMA Controller (DMA) */
mbed_official	423:560d1a9f3083	1030	/* */
mbed_official	423:560d1a9f3083	1031	/******************************************************************************/
mbed_official	423:560d1a9f3083	1032	/***************** Bit definition for DMA_ISR register ******************/
mbed_official	423:560d1a9f3083	1033	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
mbed_official	423:560d1a9f3083	1034	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
mbed_official	423:560d1a9f3083	1035	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
mbed_official	423:560d1a9f3083	1036	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
mbed_official	423:560d1a9f3083	1037	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
mbed_official	423:560d1a9f3083	1038	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
mbed_official	423:560d1a9f3083	1039	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
mbed_official	423:560d1a9f3083	1040	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
mbed_official	423:560d1a9f3083	1041	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
mbed_official	423:560d1a9f3083	1042	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
mbed_official	423:560d1a9f3083	1043	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
mbed_official	423:560d1a9f3083	1044	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
mbed_official	423:560d1a9f3083	1045	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
mbed_official	423:560d1a9f3083	1046	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
mbed_official	423:560d1a9f3083	1047	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
mbed_official	423:560d1a9f3083	1048	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
mbed_official	423:560d1a9f3083	1049	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
mbed_official	423:560d1a9f3083	1050	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
mbed_official	423:560d1a9f3083	1051	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
mbed_official	423:560d1a9f3083	1052	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
mbed_official	423:560d1a9f3083	1053
mbed_official	423:560d1a9f3083	1054	/***************** Bit definition for DMA_IFCR register *****************/
mbed_official	423:560d1a9f3083	1055	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
mbed_official	423:560d1a9f3083	1056	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
mbed_official	423:560d1a9f3083	1057	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
mbed_official	423:560d1a9f3083	1058	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
mbed_official	423:560d1a9f3083	1059	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
mbed_official	423:560d1a9f3083	1060	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
mbed_official	423:560d1a9f3083	1061	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
mbed_official	423:560d1a9f3083	1062	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
mbed_official	423:560d1a9f3083	1063	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
mbed_official	423:560d1a9f3083	1064	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
mbed_official	423:560d1a9f3083	1065	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
mbed_official	423:560d1a9f3083	1066	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
mbed_official	423:560d1a9f3083	1067	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
mbed_official	423:560d1a9f3083	1068	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
mbed_official	423:560d1a9f3083	1069	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
mbed_official	423:560d1a9f3083	1070	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
mbed_official	423:560d1a9f3083	1071	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
mbed_official	423:560d1a9f3083	1072	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
mbed_official	423:560d1a9f3083	1073	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
mbed_official	423:560d1a9f3083	1074	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
mbed_official	423:560d1a9f3083	1075
mbed_official	423:560d1a9f3083	1076	/***************** Bit definition for DMA_CCR register ******************/
mbed_official	423:560d1a9f3083	1077	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
mbed_official	423:560d1a9f3083	1078	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
mbed_official	423:560d1a9f3083	1079	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
mbed_official	423:560d1a9f3083	1080	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
mbed_official	423:560d1a9f3083	1081	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
mbed_official	423:560d1a9f3083	1082	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
mbed_official	423:560d1a9f3083	1083	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
mbed_official	423:560d1a9f3083	1084	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
mbed_official	423:560d1a9f3083	1085
mbed_official	423:560d1a9f3083	1086	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	423:560d1a9f3083	1087	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1088	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1089
mbed_official	423:560d1a9f3083	1090	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	423:560d1a9f3083	1091	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1092	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1093
mbed_official	423:560d1a9f3083	1094	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
mbed_official	423:560d1a9f3083	1095	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1096	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1097
mbed_official	423:560d1a9f3083	1098	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
mbed_official	423:560d1a9f3083	1099
mbed_official	423:560d1a9f3083	1100	/**************** Bit definition for DMA_CNDTR register *****************/
mbed_official	423:560d1a9f3083	1101	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
mbed_official	423:560d1a9f3083	1102
mbed_official	423:560d1a9f3083	1103	/**************** Bit definition for DMA_CPAR register ******************/
mbed_official	423:560d1a9f3083	1104	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
mbed_official	423:560d1a9f3083	1105
mbed_official	423:560d1a9f3083	1106	/**************** Bit definition for DMA_CMAR register ******************/
mbed_official	423:560d1a9f3083	1107	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
mbed_official	423:560d1a9f3083	1108
mbed_official	423:560d1a9f3083	1109	/******************************************************************************/
mbed_official	423:560d1a9f3083	1110	/* */
mbed_official	423:560d1a9f3083	1111	/* External Interrupt/Event Controller (EXTI) */
mbed_official	423:560d1a9f3083	1112	/* */
mbed_official	423:560d1a9f3083	1113	/******************************************************************************/
mbed_official	423:560d1a9f3083	1114	/***************** Bit definition for EXTI_IMR register *****************/
mbed_official	423:560d1a9f3083	1115	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
mbed_official	423:560d1a9f3083	1116	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
mbed_official	423:560d1a9f3083	1117	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
mbed_official	423:560d1a9f3083	1118	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
mbed_official	423:560d1a9f3083	1119	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
mbed_official	423:560d1a9f3083	1120	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
mbed_official	423:560d1a9f3083	1121	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
mbed_official	423:560d1a9f3083	1122	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
mbed_official	423:560d1a9f3083	1123	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
mbed_official	423:560d1a9f3083	1124	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
mbed_official	423:560d1a9f3083	1125	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
mbed_official	423:560d1a9f3083	1126	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
mbed_official	423:560d1a9f3083	1127	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
mbed_official	423:560d1a9f3083	1128	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
mbed_official	423:560d1a9f3083	1129	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
mbed_official	423:560d1a9f3083	1130	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
mbed_official	423:560d1a9f3083	1131	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
mbed_official	423:560d1a9f3083	1132	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
mbed_official	423:560d1a9f3083	1133	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
mbed_official	423:560d1a9f3083	1134	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
mbed_official	423:560d1a9f3083	1135	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
mbed_official	423:560d1a9f3083	1136	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
mbed_official	423:560d1a9f3083	1137	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
mbed_official	423:560d1a9f3083	1138	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
mbed_official	423:560d1a9f3083	1139
mbed_official	423:560d1a9f3083	1140	/**************** Bit definition for EXTI_EMR register ******************/
mbed_official	423:560d1a9f3083	1141	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
mbed_official	423:560d1a9f3083	1142	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
mbed_official	423:560d1a9f3083	1143	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
mbed_official	423:560d1a9f3083	1144	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
mbed_official	423:560d1a9f3083	1145	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
mbed_official	423:560d1a9f3083	1146	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
mbed_official	423:560d1a9f3083	1147	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
mbed_official	423:560d1a9f3083	1148	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
mbed_official	423:560d1a9f3083	1149	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
mbed_official	423:560d1a9f3083	1150	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
mbed_official	423:560d1a9f3083	1151	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
mbed_official	423:560d1a9f3083	1152	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
mbed_official	423:560d1a9f3083	1153	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
mbed_official	423:560d1a9f3083	1154	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
mbed_official	423:560d1a9f3083	1155	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
mbed_official	423:560d1a9f3083	1156	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
mbed_official	423:560d1a9f3083	1157	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
mbed_official	423:560d1a9f3083	1158	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
mbed_official	423:560d1a9f3083	1159	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
mbed_official	423:560d1a9f3083	1160	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
mbed_official	423:560d1a9f3083	1161	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
mbed_official	423:560d1a9f3083	1162	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
mbed_official	423:560d1a9f3083	1163	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
mbed_official	423:560d1a9f3083	1164	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
mbed_official	423:560d1a9f3083	1165
mbed_official	423:560d1a9f3083	1166	/***************** Bit definition for EXTI_RTSR register ****************/
mbed_official	423:560d1a9f3083	1167	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
mbed_official	423:560d1a9f3083	1168	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
mbed_official	423:560d1a9f3083	1169	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
mbed_official	423:560d1a9f3083	1170	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
mbed_official	423:560d1a9f3083	1171	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
mbed_official	423:560d1a9f3083	1172	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
mbed_official	423:560d1a9f3083	1173	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
mbed_official	423:560d1a9f3083	1174	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
mbed_official	423:560d1a9f3083	1175	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
mbed_official	423:560d1a9f3083	1176	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
mbed_official	423:560d1a9f3083	1177	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
mbed_official	423:560d1a9f3083	1178	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
mbed_official	423:560d1a9f3083	1179	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
mbed_official	423:560d1a9f3083	1180	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
mbed_official	423:560d1a9f3083	1181	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
mbed_official	423:560d1a9f3083	1182	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
mbed_official	423:560d1a9f3083	1183	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
mbed_official	423:560d1a9f3083	1184	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
mbed_official	423:560d1a9f3083	1185	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
mbed_official	423:560d1a9f3083	1186
mbed_official	423:560d1a9f3083	1187	/***************** Bit definition for EXTI_FTSR register *****************/
mbed_official	423:560d1a9f3083	1188	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
mbed_official	423:560d1a9f3083	1189	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
mbed_official	423:560d1a9f3083	1190	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
mbed_official	423:560d1a9f3083	1191	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
mbed_official	423:560d1a9f3083	1192	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
mbed_official	423:560d1a9f3083	1193	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
mbed_official	423:560d1a9f3083	1194	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
mbed_official	423:560d1a9f3083	1195	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
mbed_official	423:560d1a9f3083	1196	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
mbed_official	423:560d1a9f3083	1197	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
mbed_official	423:560d1a9f3083	1198	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
mbed_official	423:560d1a9f3083	1199	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
mbed_official	423:560d1a9f3083	1200	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
mbed_official	423:560d1a9f3083	1201	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
mbed_official	423:560d1a9f3083	1202	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
mbed_official	423:560d1a9f3083	1203	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
mbed_official	423:560d1a9f3083	1204	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
mbed_official	423:560d1a9f3083	1205	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
mbed_official	423:560d1a9f3083	1206	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
mbed_official	423:560d1a9f3083	1207
mbed_official	423:560d1a9f3083	1208	/***************** Bit definition for EXTI_SWIER register *****************/
mbed_official	423:560d1a9f3083	1209	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
mbed_official	423:560d1a9f3083	1210	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
mbed_official	423:560d1a9f3083	1211	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
mbed_official	423:560d1a9f3083	1212	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
mbed_official	423:560d1a9f3083	1213	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
mbed_official	423:560d1a9f3083	1214	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
mbed_official	423:560d1a9f3083	1215	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
mbed_official	423:560d1a9f3083	1216	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
mbed_official	423:560d1a9f3083	1217	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
mbed_official	423:560d1a9f3083	1218	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
mbed_official	423:560d1a9f3083	1219	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
mbed_official	423:560d1a9f3083	1220	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
mbed_official	423:560d1a9f3083	1221	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
mbed_official	423:560d1a9f3083	1222	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
mbed_official	423:560d1a9f3083	1223	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
mbed_official	423:560d1a9f3083	1224	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
mbed_official	423:560d1a9f3083	1225	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
mbed_official	423:560d1a9f3083	1226	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
mbed_official	423:560d1a9f3083	1227	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
mbed_official	423:560d1a9f3083	1228
mbed_official	423:560d1a9f3083	1229	/**************** Bit definition for EXTI_PR register *******************/
mbed_official	423:560d1a9f3083	1230	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
mbed_official	423:560d1a9f3083	1231	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
mbed_official	423:560d1a9f3083	1232	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
mbed_official	423:560d1a9f3083	1233	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
mbed_official	423:560d1a9f3083	1234	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
mbed_official	423:560d1a9f3083	1235	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
mbed_official	423:560d1a9f3083	1236	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
mbed_official	423:560d1a9f3083	1237	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
mbed_official	423:560d1a9f3083	1238	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
mbed_official	423:560d1a9f3083	1239	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
mbed_official	423:560d1a9f3083	1240	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
mbed_official	423:560d1a9f3083	1241	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
mbed_official	423:560d1a9f3083	1242	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
mbed_official	423:560d1a9f3083	1243	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
mbed_official	423:560d1a9f3083	1244	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
mbed_official	423:560d1a9f3083	1245	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
mbed_official	423:560d1a9f3083	1246	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
mbed_official	423:560d1a9f3083	1247	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
mbed_official	423:560d1a9f3083	1248	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
mbed_official	423:560d1a9f3083	1249
mbed_official	423:560d1a9f3083	1250	/******************************************************************************/
mbed_official	423:560d1a9f3083	1251	/* */
mbed_official	423:560d1a9f3083	1252	/* FLASH and Option Bytes Registers */
mbed_official	423:560d1a9f3083	1253	/* */
mbed_official	423:560d1a9f3083	1254	/******************************************************************************/
mbed_official	423:560d1a9f3083	1255
mbed_official	423:560d1a9f3083	1256	/***************** Bit definition for FLASH_ACR register ****************/
mbed_official	423:560d1a9f3083	1257	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
mbed_official	423:560d1a9f3083	1258
mbed_official	423:560d1a9f3083	1259	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
mbed_official	423:560d1a9f3083	1260	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
mbed_official	423:560d1a9f3083	1261
mbed_official	423:560d1a9f3083	1262	/**************** Bit definition for FLASH_KEYR register ****************/
mbed_official	423:560d1a9f3083	1263	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
mbed_official	423:560d1a9f3083	1264
mbed_official	423:560d1a9f3083	1265	/*************** Bit definition for FLASH_OPTKEYR register **************/
mbed_official	423:560d1a9f3083	1266	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
mbed_official	423:560d1a9f3083	1267
mbed_official	423:560d1a9f3083	1268	/**************** FLASH Keys ********************************************/
mbed_official	423:560d1a9f3083	1269	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
mbed_official	423:560d1a9f3083	1270	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official	423:560d1a9f3083	1271	to unlock the write access to the FPEC. */
mbed_official	423:560d1a9f3083	1272
mbed_official	423:560d1a9f3083	1273	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
mbed_official	423:560d1a9f3083	1274	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official	423:560d1a9f3083	1275	unlock the write access to the option byte block */
mbed_official	423:560d1a9f3083	1276
mbed_official	423:560d1a9f3083	1277	/**************** Bit definition for FLASH_SR register *****************/
mbed_official	423:560d1a9f3083	1278	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
mbed_official	423:560d1a9f3083	1279	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
mbed_official	423:560d1a9f3083	1280	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
mbed_official	423:560d1a9f3083	1281	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
mbed_official	423:560d1a9f3083	1282	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
mbed_official	423:560d1a9f3083	1283
mbed_official	423:560d1a9f3083	1284	/***************** Bit definition for FLASH_CR register *****************/
mbed_official	423:560d1a9f3083	1285	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
mbed_official	423:560d1a9f3083	1286	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
mbed_official	423:560d1a9f3083	1287	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
mbed_official	423:560d1a9f3083	1288	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
mbed_official	423:560d1a9f3083	1289	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
mbed_official	423:560d1a9f3083	1290	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
mbed_official	423:560d1a9f3083	1291	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
mbed_official	423:560d1a9f3083	1292	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
mbed_official	423:560d1a9f3083	1293	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
mbed_official	423:560d1a9f3083	1294	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
mbed_official	423:560d1a9f3083	1295	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
mbed_official	423:560d1a9f3083	1296
mbed_official	423:560d1a9f3083	1297	/***************** Bit definition for FLASH_AR register *****************/
mbed_official	423:560d1a9f3083	1298	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
mbed_official	423:560d1a9f3083	1299
mbed_official	423:560d1a9f3083	1300	/**************** Bit definition for FLASH_OBR register *****************/
mbed_official	423:560d1a9f3083	1301	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
mbed_official	423:560d1a9f3083	1302	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
mbed_official	423:560d1a9f3083	1303	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
mbed_official	423:560d1a9f3083	1304
mbed_official	423:560d1a9f3083	1305	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
mbed_official	423:560d1a9f3083	1306	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
mbed_official	423:560d1a9f3083	1307	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
mbed_official	423:560d1a9f3083	1308	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
mbed_official	423:560d1a9f3083	1309	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
mbed_official	423:560d1a9f3083	1310	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
mbed_official	423:560d1a9f3083	1311
mbed_official	423:560d1a9f3083	1312	/* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	1313	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official	423:560d1a9f3083	1314
mbed_official	423:560d1a9f3083	1315	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official	423:560d1a9f3083	1316	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official	423:560d1a9f3083	1317
mbed_official	423:560d1a9f3083	1318	/**************** Bit definition for FLASH_WRPR register ****************/
mbed_official	423:560d1a9f3083	1319	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
mbed_official	423:560d1a9f3083	1320
mbed_official	423:560d1a9f3083	1321	/----------------------------------------------------------------------------/
mbed_official	423:560d1a9f3083	1322
mbed_official	423:560d1a9f3083	1323	/**************** Bit definition for OB_RDP register ********************/
mbed_official	423:560d1a9f3083	1324	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
mbed_official	423:560d1a9f3083	1325	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
mbed_official	423:560d1a9f3083	1326
mbed_official	423:560d1a9f3083	1327	/**************** Bit definition for OB_USER register *******************/
mbed_official	423:560d1a9f3083	1328	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
mbed_official	423:560d1a9f3083	1329	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
mbed_official	423:560d1a9f3083	1330
mbed_official	423:560d1a9f3083	1331	/**************** Bit definition for OB_WRP0 register *******************/
mbed_official	423:560d1a9f3083	1332	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
mbed_official	423:560d1a9f3083	1333	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
mbed_official	423:560d1a9f3083	1334
mbed_official	423:560d1a9f3083	1335	/**************** Bit definition for OB_WRP1 register *******************/
mbed_official	423:560d1a9f3083	1336	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
mbed_official	423:560d1a9f3083	1337	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
mbed_official	423:560d1a9f3083	1338
mbed_official	423:560d1a9f3083	1339	/******************************************************************************/
mbed_official	423:560d1a9f3083	1340	/* */
mbed_official	423:560d1a9f3083	1341	/* General Purpose IOs (GPIO) */
mbed_official	423:560d1a9f3083	1342	/* */
mbed_official	423:560d1a9f3083	1343	/******************************************************************************/
mbed_official	423:560d1a9f3083	1344	/***************** Bit definition for GPIO_MODER register ***************/
mbed_official	423:560d1a9f3083	1345	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official	423:560d1a9f3083	1346	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1347	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1348	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official	423:560d1a9f3083	1349	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1350	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1351	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official	423:560d1a9f3083	1352	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1353	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1354	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official	423:560d1a9f3083	1355	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1356	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1357	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official	423:560d1a9f3083	1358	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1359	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1360	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official	423:560d1a9f3083	1361	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1362	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1363	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official	423:560d1a9f3083	1364	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1365	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1366	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official	423:560d1a9f3083	1367	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1368	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1369	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official	423:560d1a9f3083	1370	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	1371	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	1372	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official	423:560d1a9f3083	1373	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	1374	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	1375	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	1376	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	1377	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	1378	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official	423:560d1a9f3083	1379	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	1380	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	1381	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official	423:560d1a9f3083	1382	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	1383	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	1384	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official	423:560d1a9f3083	1385	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	1386	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	1387	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official	423:560d1a9f3083	1388	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official	423:560d1a9f3083	1389	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official	423:560d1a9f3083	1390	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official	423:560d1a9f3083	1391	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official	423:560d1a9f3083	1392	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	1393
mbed_official	423:560d1a9f3083	1394	/**************** Bit definition for GPIO_OTYPER register ***************/
mbed_official	423:560d1a9f3083	1395	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1396	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1397	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1398	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1399	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1400	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1401	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1402	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1403	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1404	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1405	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1406	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1407	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1408	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1409	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1410	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1411
mbed_official	423:560d1a9f3083	1412	/************** Bit definition for GPIO_OSPEEDR register ****************/
mbed_official	423:560d1a9f3083	1413	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official	423:560d1a9f3083	1414	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1415	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1416	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official	423:560d1a9f3083	1417	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1418	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1419	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official	423:560d1a9f3083	1420	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1421	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1422	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official	423:560d1a9f3083	1423	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1424	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1425	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official	423:560d1a9f3083	1426	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1427	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1428	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official	423:560d1a9f3083	1429	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1430	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1431	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official	423:560d1a9f3083	1432	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1433	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1434	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official	423:560d1a9f3083	1435	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1436	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1437	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official	423:560d1a9f3083	1438	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	1439	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	1440	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official	423:560d1a9f3083	1441	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	1442	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	1443	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	1444	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	1445	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	1446	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official	423:560d1a9f3083	1447	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	1448	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	1449	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official	423:560d1a9f3083	1450	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	1451	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	1452	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official	423:560d1a9f3083	1453	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	1454	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	1455	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official	423:560d1a9f3083	1456	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official	423:560d1a9f3083	1457	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official	423:560d1a9f3083	1458	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official	423:560d1a9f3083	1459	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official	423:560d1a9f3083	1460	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	1461
mbed_official	423:560d1a9f3083	1462	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official	423:560d1a9f3083	1463	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official	423:560d1a9f3083	1464	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official	423:560d1a9f3083	1465	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official	423:560d1a9f3083	1466	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official	423:560d1a9f3083	1467	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official	423:560d1a9f3083	1468	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official	423:560d1a9f3083	1469	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official	423:560d1a9f3083	1470	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official	423:560d1a9f3083	1471	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official	423:560d1a9f3083	1472	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official	423:560d1a9f3083	1473	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official	423:560d1a9f3083	1474	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official	423:560d1a9f3083	1475	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official	423:560d1a9f3083	1476	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official	423:560d1a9f3083	1477	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official	423:560d1a9f3083	1478	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official	423:560d1a9f3083	1479	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official	423:560d1a9f3083	1480	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official	423:560d1a9f3083	1481	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official	423:560d1a9f3083	1482	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official	423:560d1a9f3083	1483	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official	423:560d1a9f3083	1484	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official	423:560d1a9f3083	1485	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official	423:560d1a9f3083	1486	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official	423:560d1a9f3083	1487	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official	423:560d1a9f3083	1488	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official	423:560d1a9f3083	1489	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official	423:560d1a9f3083	1490	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official	423:560d1a9f3083	1491	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official	423:560d1a9f3083	1492	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official	423:560d1a9f3083	1493	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official	423:560d1a9f3083	1494	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official	423:560d1a9f3083	1495	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official	423:560d1a9f3083	1496	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official	423:560d1a9f3083	1497	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official	423:560d1a9f3083	1498	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official	423:560d1a9f3083	1499	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official	423:560d1a9f3083	1500	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official	423:560d1a9f3083	1501	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official	423:560d1a9f3083	1502	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official	423:560d1a9f3083	1503	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official	423:560d1a9f3083	1504	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official	423:560d1a9f3083	1505	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official	423:560d1a9f3083	1506	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official	423:560d1a9f3083	1507	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official	423:560d1a9f3083	1508	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official	423:560d1a9f3083	1509	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official	423:560d1a9f3083	1510	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official	423:560d1a9f3083	1511
mbed_official	423:560d1a9f3083	1512	/***************** Bit definition for GPIO_PUPDR register ****************/
mbed_official	423:560d1a9f3083	1513	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official	423:560d1a9f3083	1514	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1515	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1516	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official	423:560d1a9f3083	1517	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1518	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1519	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official	423:560d1a9f3083	1520	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1521	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1522	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official	423:560d1a9f3083	1523	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1524	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1525	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official	423:560d1a9f3083	1526	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1527	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1528	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official	423:560d1a9f3083	1529	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1530	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1531	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official	423:560d1a9f3083	1532	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1533	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1534	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official	423:560d1a9f3083	1535	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1536	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1537	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official	423:560d1a9f3083	1538	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	1539	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	1540	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official	423:560d1a9f3083	1541	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	1542	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	1543	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	1544	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	1545	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	1546	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official	423:560d1a9f3083	1547	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	1548	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	1549	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official	423:560d1a9f3083	1550	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	1551	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	1552	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official	423:560d1a9f3083	1553	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	1554	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	1555	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official	423:560d1a9f3083	1556	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official	423:560d1a9f3083	1557	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official	423:560d1a9f3083	1558	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official	423:560d1a9f3083	1559	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official	423:560d1a9f3083	1560	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	1561
mbed_official	423:560d1a9f3083	1562	/***************** Bit definition for GPIO_IDR register *****************/
mbed_official	423:560d1a9f3083	1563	#define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1564	#define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1565	#define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1566	#define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1567	#define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1568	#define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1569	#define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1570	#define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1571	#define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1572	#define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1573	#define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1574	#define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1575	#define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1576	#define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1577	#define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1578	#define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1579
mbed_official	423:560d1a9f3083	1580	/**************** Bit definition for GPIO_ODR register ******************/
mbed_official	423:560d1a9f3083	1581	#define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1582	#define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1583	#define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1584	#define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1585	#define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1586	#define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1587	#define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1588	#define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1589	#define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1590	#define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1591	#define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1592	#define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1593	#define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1594	#define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1595	#define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1596	#define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1597
mbed_official	423:560d1a9f3083	1598	/**************** Bit definition for GPIO_BSRR register ******************/
mbed_official	423:560d1a9f3083	1599	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1600	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1601	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1602	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1603	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1604	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1605	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1606	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1607	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1608	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1609	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1610	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1611	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1612	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1613	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1614	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1615	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	1616	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	1617	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	1618	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	1619	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	1620	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	1621	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	1622	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	1623	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	1624	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	1625	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	1626	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	1627	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official	423:560d1a9f3083	1628	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official	423:560d1a9f3083	1629	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official	423:560d1a9f3083	1630	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	1631
mbed_official	423:560d1a9f3083	1632	/**************** Bit definition for GPIO_LCKR register ******************/
mbed_official	423:560d1a9f3083	1633	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1634	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1635	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1636	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1637	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1638	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1639	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1640	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1641	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1642	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1643	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1644	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1645	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1646	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1647	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1648	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1649	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	1650
mbed_official	423:560d1a9f3083	1651	/**************** Bit definition for GPIO_AFRL register ******************/
mbed_official	423:560d1a9f3083	1652	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	1653	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official	423:560d1a9f3083	1654	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	1655	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official	423:560d1a9f3083	1656	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	1657	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official	423:560d1a9f3083	1658	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official	423:560d1a9f3083	1659	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official	423:560d1a9f3083	1660
mbed_official	423:560d1a9f3083	1661	/**************** Bit definition for GPIO_AFRH register ******************/
mbed_official	423:560d1a9f3083	1662	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	1663	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official	423:560d1a9f3083	1664	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	1665	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official	423:560d1a9f3083	1666	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	1667	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official	423:560d1a9f3083	1668	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official	423:560d1a9f3083	1669	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official	423:560d1a9f3083	1670
mbed_official	423:560d1a9f3083	1671	/**************** Bit definition for GPIO_BRR register *******************/
mbed_official	423:560d1a9f3083	1672	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	1673	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	1674	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	1675	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	1676	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	1677	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	1678	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	1679	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	1680	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	1681	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	1682	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	1683	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	1684	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	1685	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	1686	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	1687	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	1688
mbed_official	423:560d1a9f3083	1689	/******************************************************************************/
mbed_official	423:560d1a9f3083	1690	/* */
mbed_official	423:560d1a9f3083	1691	/* Inter-integrated Circuit Interface (I2C) */
mbed_official	423:560d1a9f3083	1692	/* */
mbed_official	423:560d1a9f3083	1693	/******************************************************************************/
mbed_official	423:560d1a9f3083	1694
mbed_official	423:560d1a9f3083	1695	/***************** Bit definition for I2C_CR1 register *****************/
mbed_official	423:560d1a9f3083	1696	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
mbed_official	423:560d1a9f3083	1697	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
mbed_official	423:560d1a9f3083	1698	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
mbed_official	423:560d1a9f3083	1699	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
mbed_official	423:560d1a9f3083	1700	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
mbed_official	423:560d1a9f3083	1701	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
mbed_official	423:560d1a9f3083	1702	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
mbed_official	423:560d1a9f3083	1703	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
mbed_official	423:560d1a9f3083	1704	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
mbed_official	423:560d1a9f3083	1705	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
mbed_official	423:560d1a9f3083	1706	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
mbed_official	423:560d1a9f3083	1707	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
mbed_official	423:560d1a9f3083	1708	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
mbed_official	423:560d1a9f3083	1709	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
mbed_official	423:560d1a9f3083	1710	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
mbed_official	423:560d1a9f3083	1711	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
mbed_official	423:560d1a9f3083	1712	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
mbed_official	423:560d1a9f3083	1713	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
mbed_official	423:560d1a9f3083	1714	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
mbed_official	423:560d1a9f3083	1715	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
mbed_official	423:560d1a9f3083	1716	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
mbed_official	423:560d1a9f3083	1717
mbed_official	423:560d1a9f3083	1718	/**************** Bit definition for I2C_CR2 register ******************/
mbed_official	423:560d1a9f3083	1719	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
mbed_official	423:560d1a9f3083	1720	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
mbed_official	423:560d1a9f3083	1721	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
mbed_official	423:560d1a9f3083	1722	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
mbed_official	423:560d1a9f3083	1723	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
mbed_official	423:560d1a9f3083	1724	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
mbed_official	423:560d1a9f3083	1725	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
mbed_official	423:560d1a9f3083	1726	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
mbed_official	423:560d1a9f3083	1727	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
mbed_official	423:560d1a9f3083	1728	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
mbed_official	423:560d1a9f3083	1729	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
mbed_official	423:560d1a9f3083	1730
mbed_official	423:560d1a9f3083	1731	/***************** Bit definition for I2C_OAR1 register ****************/
mbed_official	423:560d1a9f3083	1732	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
mbed_official	423:560d1a9f3083	1733	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
mbed_official	423:560d1a9f3083	1734	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
mbed_official	423:560d1a9f3083	1735
mbed_official	423:560d1a9f3083	1736	/***************** Bit definition for I2C_OAR2 register ****************/
mbed_official	423:560d1a9f3083	1737	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
mbed_official	423:560d1a9f3083	1738	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
mbed_official	423:560d1a9f3083	1739	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
mbed_official	423:560d1a9f3083	1740
mbed_official	423:560d1a9f3083	1741	/***************** Bit definition for I2C_TIMINGR register **************/
mbed_official	423:560d1a9f3083	1742	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
mbed_official	423:560d1a9f3083	1743	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
mbed_official	423:560d1a9f3083	1744	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
mbed_official	423:560d1a9f3083	1745	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
mbed_official	423:560d1a9f3083	1746	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
mbed_official	423:560d1a9f3083	1747
mbed_official	423:560d1a9f3083	1748	/***************** Bit definition for I2C_TIMEOUTR register **************/
mbed_official	423:560d1a9f3083	1749	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
mbed_official	423:560d1a9f3083	1750	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
mbed_official	423:560d1a9f3083	1751	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
mbed_official	423:560d1a9f3083	1752	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
mbed_official	423:560d1a9f3083	1753	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
mbed_official	423:560d1a9f3083	1754
mbed_official	423:560d1a9f3083	1755	/**************** Bit definition for I2C_ISR register ******************/
mbed_official	423:560d1a9f3083	1756	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
mbed_official	423:560d1a9f3083	1757	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
mbed_official	423:560d1a9f3083	1758	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
mbed_official	423:560d1a9f3083	1759	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
mbed_official	423:560d1a9f3083	1760	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
mbed_official	423:560d1a9f3083	1761	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
mbed_official	423:560d1a9f3083	1762	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
mbed_official	423:560d1a9f3083	1763	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
mbed_official	423:560d1a9f3083	1764	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
mbed_official	423:560d1a9f3083	1765	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
mbed_official	423:560d1a9f3083	1766	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
mbed_official	423:560d1a9f3083	1767	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
mbed_official	423:560d1a9f3083	1768	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
mbed_official	423:560d1a9f3083	1769	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
mbed_official	423:560d1a9f3083	1770	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
mbed_official	423:560d1a9f3083	1771	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
mbed_official	423:560d1a9f3083	1772	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
mbed_official	423:560d1a9f3083	1773
mbed_official	423:560d1a9f3083	1774	/**************** Bit definition for I2C_ICR register ******************/
mbed_official	423:560d1a9f3083	1775	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
mbed_official	423:560d1a9f3083	1776	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
mbed_official	423:560d1a9f3083	1777	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
mbed_official	423:560d1a9f3083	1778	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
mbed_official	423:560d1a9f3083	1779	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
mbed_official	423:560d1a9f3083	1780	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
mbed_official	423:560d1a9f3083	1781	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
mbed_official	423:560d1a9f3083	1782	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
mbed_official	423:560d1a9f3083	1783	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
mbed_official	423:560d1a9f3083	1784
mbed_official	423:560d1a9f3083	1785	/**************** Bit definition for I2C_PECR register *****************/
mbed_official	423:560d1a9f3083	1786	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
mbed_official	423:560d1a9f3083	1787
mbed_official	423:560d1a9f3083	1788	/**************** Bit definition for I2C_RXDR register *******************/
mbed_official	423:560d1a9f3083	1789	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
mbed_official	423:560d1a9f3083	1790
mbed_official	423:560d1a9f3083	1791	/**************** Bit definition for I2C_TXDR register *****************/
mbed_official	423:560d1a9f3083	1792	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
mbed_official	423:560d1a9f3083	1793
mbed_official	423:560d1a9f3083	1794	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1795	/* */
mbed_official	423:560d1a9f3083	1796	/* Independent WATCHDOG (IWDG) */
mbed_official	423:560d1a9f3083	1797	/* */
mbed_official	423:560d1a9f3083	1798	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1799	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	423:560d1a9f3083	1800	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
mbed_official	423:560d1a9f3083	1801
mbed_official	423:560d1a9f3083	1802	/***************** Bit definition for IWDG_PR register *****************/
mbed_official	423:560d1a9f3083	1803	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
mbed_official	423:560d1a9f3083	1804	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1805	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1806	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1807
mbed_official	423:560d1a9f3083	1808	/***************** Bit definition for IWDG_RLR register ****************/
mbed_official	423:560d1a9f3083	1809	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
mbed_official	423:560d1a9f3083	1810
mbed_official	423:560d1a9f3083	1811	/***************** Bit definition for IWDG_SR register *****************/
mbed_official	423:560d1a9f3083	1812	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
mbed_official	423:560d1a9f3083	1813	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
mbed_official	423:560d1a9f3083	1814	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
mbed_official	423:560d1a9f3083	1815
mbed_official	423:560d1a9f3083	1816	/***************** Bit definition for IWDG_KR register *****************/
mbed_official	423:560d1a9f3083	1817	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
mbed_official	423:560d1a9f3083	1818
mbed_official	423:560d1a9f3083	1819	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1820	/* */
mbed_official	423:560d1a9f3083	1821	/* Power Control (PWR) */
mbed_official	423:560d1a9f3083	1822	/* */
mbed_official	423:560d1a9f3083	1823	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1824
mbed_official	423:560d1a9f3083	1825	/****************** Bit definition for PWR_CR register *****************/
mbed_official	423:560d1a9f3083	1826	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
mbed_official	423:560d1a9f3083	1827	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
mbed_official	423:560d1a9f3083	1828	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
mbed_official	423:560d1a9f3083	1829	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
mbed_official	423:560d1a9f3083	1830	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
mbed_official	423:560d1a9f3083	1831
mbed_official	423:560d1a9f3083	1832	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
mbed_official	423:560d1a9f3083	1833	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1834	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1835	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1836
mbed_official	423:560d1a9f3083	1837	/!< PVD level configuration /
mbed_official	423:560d1a9f3083	1838	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
mbed_official	423:560d1a9f3083	1839	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
mbed_official	423:560d1a9f3083	1840	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
mbed_official	423:560d1a9f3083	1841	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
mbed_official	423:560d1a9f3083	1842	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
mbed_official	423:560d1a9f3083	1843	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
mbed_official	423:560d1a9f3083	1844	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
mbed_official	423:560d1a9f3083	1845	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
mbed_official	423:560d1a9f3083	1846
mbed_official	423:560d1a9f3083	1847	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
mbed_official	423:560d1a9f3083	1848
mbed_official	423:560d1a9f3083	1849	/***************** Bit definition for PWR_CSR register *****************/
mbed_official	423:560d1a9f3083	1850	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
mbed_official	423:560d1a9f3083	1851	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
mbed_official	423:560d1a9f3083	1852	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
mbed_official	423:560d1a9f3083	1853	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
mbed_official	423:560d1a9f3083	1854
mbed_official	423:560d1a9f3083	1855	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
mbed_official	423:560d1a9f3083	1856	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
mbed_official	423:560d1a9f3083	1857
mbed_official	423:560d1a9f3083	1858	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1859	/* */
mbed_official	423:560d1a9f3083	1860	/* Reset and Clock Control */
mbed_official	423:560d1a9f3083	1861	/* */
mbed_official	423:560d1a9f3083	1862	/*****************************************************************************/
mbed_official	423:560d1a9f3083	1863
mbed_official	423:560d1a9f3083	1864	/****************** Bit definition for RCC_CR register *****************/
mbed_official	423:560d1a9f3083	1865	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
mbed_official	423:560d1a9f3083	1866	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
mbed_official	423:560d1a9f3083	1867
mbed_official	423:560d1a9f3083	1868	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
mbed_official	423:560d1a9f3083	1869	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
mbed_official	423:560d1a9f3083	1870	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
mbed_official	423:560d1a9f3083	1871	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
mbed_official	423:560d1a9f3083	1872	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
mbed_official	423:560d1a9f3083	1873	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
mbed_official	423:560d1a9f3083	1874
mbed_official	423:560d1a9f3083	1875	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
mbed_official	423:560d1a9f3083	1876	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	1877	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	1878	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	423:560d1a9f3083	1879	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	423:560d1a9f3083	1880	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	423:560d1a9f3083	1881	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
mbed_official	423:560d1a9f3083	1882	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
mbed_official	423:560d1a9f3083	1883	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
mbed_official	423:560d1a9f3083	1884
mbed_official	423:560d1a9f3083	1885	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
mbed_official	423:560d1a9f3083	1886	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
mbed_official	423:560d1a9f3083	1887	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
mbed_official	423:560d1a9f3083	1888	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
mbed_official	423:560d1a9f3083	1889	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
mbed_official	423:560d1a9f3083	1890	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
mbed_official	423:560d1a9f3083	1891
mbed_official	423:560d1a9f3083	1892	/****************** Bit definition for RCC_CFGR register ***************/
mbed_official	423:560d1a9f3083	1893	/!< SW configuration /
mbed_official	423:560d1a9f3083	1894	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
mbed_official	423:560d1a9f3083	1895	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1896	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1897
mbed_official	423:560d1a9f3083	1898	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
mbed_official	423:560d1a9f3083	1899	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
mbed_official	423:560d1a9f3083	1900	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
mbed_official	423:560d1a9f3083	1901
mbed_official	423:560d1a9f3083	1902	/!< SWS configuration /
mbed_official	423:560d1a9f3083	1903	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
mbed_official	423:560d1a9f3083	1904	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1905	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1906
mbed_official	423:560d1a9f3083	1907	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
mbed_official	423:560d1a9f3083	1908	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
mbed_official	423:560d1a9f3083	1909	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
mbed_official	423:560d1a9f3083	1910
mbed_official	423:560d1a9f3083	1911	/!< HPRE configuration /
mbed_official	423:560d1a9f3083	1912	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
mbed_official	423:560d1a9f3083	1913	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1914	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1915	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1916	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
mbed_official	423:560d1a9f3083	1917
mbed_official	423:560d1a9f3083	1918	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
mbed_official	423:560d1a9f3083	1919	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
mbed_official	423:560d1a9f3083	1920	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
mbed_official	423:560d1a9f3083	1921	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
mbed_official	423:560d1a9f3083	1922	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
mbed_official	423:560d1a9f3083	1923	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
mbed_official	423:560d1a9f3083	1924	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
mbed_official	423:560d1a9f3083	1925	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
mbed_official	423:560d1a9f3083	1926	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
mbed_official	423:560d1a9f3083	1927
mbed_official	423:560d1a9f3083	1928	/!< PPRE configuration /
mbed_official	423:560d1a9f3083	1929	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
mbed_official	423:560d1a9f3083	1930	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1931	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1932	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1933
mbed_official	423:560d1a9f3083	1934	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
mbed_official	423:560d1a9f3083	1935	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
mbed_official	423:560d1a9f3083	1936	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
mbed_official	423:560d1a9f3083	1937	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
mbed_official	423:560d1a9f3083	1938	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
mbed_official	423:560d1a9f3083	1939
mbed_official	423:560d1a9f3083	1940	/!< ADCPPRE configuration /
mbed_official	423:560d1a9f3083	1941	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
mbed_official	423:560d1a9f3083	1942
mbed_official	423:560d1a9f3083	1943	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
mbed_official	423:560d1a9f3083	1944	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
mbed_official	423:560d1a9f3083	1945
mbed_official	423:560d1a9f3083	1946	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
mbed_official	423:560d1a9f3083	1947	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
mbed_official	423:560d1a9f3083	1948	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
mbed_official	423:560d1a9f3083	1949
mbed_official	423:560d1a9f3083	1950	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
mbed_official	423:560d1a9f3083	1951	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
mbed_official	423:560d1a9f3083	1952	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
mbed_official	423:560d1a9f3083	1953
mbed_official	423:560d1a9f3083	1954	/!< PLLMUL configuration /
mbed_official	423:560d1a9f3083	1955	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
mbed_official	423:560d1a9f3083	1956	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1957	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1958	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1959	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
mbed_official	423:560d1a9f3083	1960
mbed_official	423:560d1a9f3083	1961	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
mbed_official	423:560d1a9f3083	1962	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
mbed_official	423:560d1a9f3083	1963	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
mbed_official	423:560d1a9f3083	1964	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
mbed_official	423:560d1a9f3083	1965	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
mbed_official	423:560d1a9f3083	1966	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
mbed_official	423:560d1a9f3083	1967	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
mbed_official	423:560d1a9f3083	1968	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
mbed_official	423:560d1a9f3083	1969	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
mbed_official	423:560d1a9f3083	1970	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
mbed_official	423:560d1a9f3083	1971	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
mbed_official	423:560d1a9f3083	1972	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
mbed_official	423:560d1a9f3083	1973	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
mbed_official	423:560d1a9f3083	1974	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
mbed_official	423:560d1a9f3083	1975	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
mbed_official	423:560d1a9f3083	1976
mbed_official	423:560d1a9f3083	1977	/!< MCO configuration /
mbed_official	423:560d1a9f3083	1978	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
mbed_official	423:560d1a9f3083	1979	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	1980	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	1981	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	1982
mbed_official	423:560d1a9f3083	1983	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	423:560d1a9f3083	1984	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
mbed_official	423:560d1a9f3083	1985	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
mbed_official	423:560d1a9f3083	1986	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
mbed_official	423:560d1a9f3083	1987	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
mbed_official	423:560d1a9f3083	1988	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
mbed_official	423:560d1a9f3083	1989	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
mbed_official	423:560d1a9f3083	1990	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
mbed_official	423:560d1a9f3083	1991
mbed_official	423:560d1a9f3083	1992	/!<*************** Bit definition for RCC_CIR register ***************/
mbed_official	423:560d1a9f3083	1993	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1994	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1995	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1996	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1997	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1998	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
mbed_official	423:560d1a9f3083	1999	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
mbed_official	423:560d1a9f3083	2000	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2001	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2002	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2003	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2004	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2005	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
mbed_official	423:560d1a9f3083	2006	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2007	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2008	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2009	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2010	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2011	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
mbed_official	423:560d1a9f3083	2012	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
mbed_official	423:560d1a9f3083	2013
mbed_official	423:560d1a9f3083	2014	/*************** Bit definition for RCC_APB2RSTR register **************/
mbed_official	423:560d1a9f3083	2015	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
mbed_official	423:560d1a9f3083	2016	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
mbed_official	423:560d1a9f3083	2017	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
mbed_official	423:560d1a9f3083	2018	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
mbed_official	423:560d1a9f3083	2019	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
mbed_official	423:560d1a9f3083	2020	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
mbed_official	423:560d1a9f3083	2021	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
mbed_official	423:560d1a9f3083	2022	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
mbed_official	423:560d1a9f3083	2023	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
mbed_official	423:560d1a9f3083	2024
mbed_official	423:560d1a9f3083	2025	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
mbed_official	423:560d1a9f3083	2026	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official	423:560d1a9f3083	2027
mbed_official	423:560d1a9f3083	2028	/*************** Bit definition for RCC_APB1RSTR register **************/
mbed_official	423:560d1a9f3083	2029	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
mbed_official	423:560d1a9f3083	2030	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
mbed_official	423:560d1a9f3083	2031	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
mbed_official	423:560d1a9f3083	2032	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
mbed_official	423:560d1a9f3083	2033	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
mbed_official	423:560d1a9f3083	2034	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
mbed_official	423:560d1a9f3083	2035	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
mbed_official	423:560d1a9f3083	2036	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
mbed_official	423:560d1a9f3083	2037	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
mbed_official	423:560d1a9f3083	2038	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
mbed_official	423:560d1a9f3083	2039	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC clock reset /
mbed_official	423:560d1a9f3083	2040	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC clock reset /
mbed_official	423:560d1a9f3083	2041
mbed_official	423:560d1a9f3083	2042	/**************** Bit definition for RCC_AHBENR register ***************/
mbed_official	423:560d1a9f3083	2043	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
mbed_official	423:560d1a9f3083	2044	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
mbed_official	423:560d1a9f3083	2045	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
mbed_official	423:560d1a9f3083	2046	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
mbed_official	423:560d1a9f3083	2047	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
mbed_official	423:560d1a9f3083	2048	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
mbed_official	423:560d1a9f3083	2049	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
mbed_official	423:560d1a9f3083	2050	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
mbed_official	423:560d1a9f3083	2051	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
mbed_official	423:560d1a9f3083	2052	#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /!< TS controller clock enable /
mbed_official	423:560d1a9f3083	2053
mbed_official	423:560d1a9f3083	2054	/* Old Bit definition maintained for legacy purpose */
mbed_official	423:560d1a9f3083	2055	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
mbed_official	423:560d1a9f3083	2056	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
mbed_official	423:560d1a9f3083	2057
mbed_official	423:560d1a9f3083	2058	/*************** Bit definition for RCC_APB2ENR register ***************/
mbed_official	423:560d1a9f3083	2059	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
mbed_official	423:560d1a9f3083	2060	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
mbed_official	423:560d1a9f3083	2061	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
mbed_official	423:560d1a9f3083	2062	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
mbed_official	423:560d1a9f3083	2063	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
mbed_official	423:560d1a9f3083	2064	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
mbed_official	423:560d1a9f3083	2065	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
mbed_official	423:560d1a9f3083	2066	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
mbed_official	423:560d1a9f3083	2067	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
mbed_official	423:560d1a9f3083	2068
mbed_official	423:560d1a9f3083	2069	/* Old Bit definition maintained for legacy purpose */
mbed_official	423:560d1a9f3083	2070	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
mbed_official	423:560d1a9f3083	2071	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
mbed_official	423:560d1a9f3083	2072
mbed_official	423:560d1a9f3083	2073	/*************** Bit definition for RCC_APB1ENR register ***************/
mbed_official	423:560d1a9f3083	2074	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
mbed_official	423:560d1a9f3083	2075	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
mbed_official	423:560d1a9f3083	2076	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
mbed_official	423:560d1a9f3083	2077	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
mbed_official	423:560d1a9f3083	2078	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
mbed_official	423:560d1a9f3083	2079	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
mbed_official	423:560d1a9f3083	2080	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
mbed_official	423:560d1a9f3083	2081	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
mbed_official	423:560d1a9f3083	2082	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
mbed_official	423:560d1a9f3083	2083	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
mbed_official	423:560d1a9f3083	2084	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC clock enable /
mbed_official	423:560d1a9f3083	2085	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC clock enable /
mbed_official	423:560d1a9f3083	2086
mbed_official	423:560d1a9f3083	2087	/***************** Bit definition for RCC_BDCR register ****************/
mbed_official	423:560d1a9f3083	2088	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
mbed_official	423:560d1a9f3083	2089	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
mbed_official	423:560d1a9f3083	2090	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
mbed_official	423:560d1a9f3083	2091
mbed_official	423:560d1a9f3083	2092	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
mbed_official	423:560d1a9f3083	2093	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2094	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2095
mbed_official	423:560d1a9f3083	2096	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
mbed_official	423:560d1a9f3083	2097	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2098	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2099
mbed_official	423:560d1a9f3083	2100	/!< RTC configuration /
mbed_official	423:560d1a9f3083	2101	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
mbed_official	423:560d1a9f3083	2102	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
mbed_official	423:560d1a9f3083	2103	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
mbed_official	423:560d1a9f3083	2104	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
mbed_official	423:560d1a9f3083	2105
mbed_official	423:560d1a9f3083	2106	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
mbed_official	423:560d1a9f3083	2107	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
mbed_official	423:560d1a9f3083	2108
mbed_official	423:560d1a9f3083	2109	/***************** Bit definition for RCC_CSR register *****************/
mbed_official	423:560d1a9f3083	2110	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
mbed_official	423:560d1a9f3083	2111	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
mbed_official	423:560d1a9f3083	2112	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
mbed_official	423:560d1a9f3083	2113	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
mbed_official	423:560d1a9f3083	2114	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
mbed_official	423:560d1a9f3083	2115	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
mbed_official	423:560d1a9f3083	2116	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
mbed_official	423:560d1a9f3083	2117	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
mbed_official	423:560d1a9f3083	2118	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
mbed_official	423:560d1a9f3083	2119	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
mbed_official	423:560d1a9f3083	2120	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
mbed_official	423:560d1a9f3083	2121
mbed_official	423:560d1a9f3083	2122	/* Old Bit definition maintained for legacy purpose */
mbed_official	423:560d1a9f3083	2123	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
mbed_official	423:560d1a9f3083	2124
mbed_official	423:560d1a9f3083	2125	/***************** Bit definition for RCC_AHBRSTR register *************/
mbed_official	423:560d1a9f3083	2126	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
mbed_official	423:560d1a9f3083	2127	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
mbed_official	423:560d1a9f3083	2128	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
mbed_official	423:560d1a9f3083	2129	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
mbed_official	423:560d1a9f3083	2130	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
mbed_official	423:560d1a9f3083	2131	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /!< TS clock reset /
mbed_official	423:560d1a9f3083	2132
mbed_official	423:560d1a9f3083	2133	/* Old Bit definition maintained for legacy purpose */
mbed_official	423:560d1a9f3083	2134	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS clock reset /
mbed_official	423:560d1a9f3083	2135
mbed_official	423:560d1a9f3083	2136	/***************** Bit definition for RCC_CFGR2 register ***************/
mbed_official	423:560d1a9f3083	2137	/!< PREDIV configuration /
mbed_official	423:560d1a9f3083	2138	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
mbed_official	423:560d1a9f3083	2139	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2140	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2141	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
mbed_official	423:560d1a9f3083	2142	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
mbed_official	423:560d1a9f3083	2143
mbed_official	423:560d1a9f3083	2144	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
mbed_official	423:560d1a9f3083	2145	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
mbed_official	423:560d1a9f3083	2146	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
mbed_official	423:560d1a9f3083	2147	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
mbed_official	423:560d1a9f3083	2148	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
mbed_official	423:560d1a9f3083	2149	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
mbed_official	423:560d1a9f3083	2150	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
mbed_official	423:560d1a9f3083	2151	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
mbed_official	423:560d1a9f3083	2152	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
mbed_official	423:560d1a9f3083	2153	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
mbed_official	423:560d1a9f3083	2154	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
mbed_official	423:560d1a9f3083	2155	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
mbed_official	423:560d1a9f3083	2156	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
mbed_official	423:560d1a9f3083	2157	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
mbed_official	423:560d1a9f3083	2158	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
mbed_official	423:560d1a9f3083	2159	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
mbed_official	423:560d1a9f3083	2160
mbed_official	423:560d1a9f3083	2161	/***************** Bit definition for RCC_CFGR3 register ***************/
mbed_official	423:560d1a9f3083	2162	/!< USART1 Clock source selection /
mbed_official	423:560d1a9f3083	2163	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
mbed_official	423:560d1a9f3083	2164	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2165	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2166
mbed_official	423:560d1a9f3083	2167	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
mbed_official	423:560d1a9f3083	2168	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
mbed_official	423:560d1a9f3083	2169	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
mbed_official	423:560d1a9f3083	2170	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
mbed_official	423:560d1a9f3083	2171
mbed_official	423:560d1a9f3083	2172	/!< I2C1 Clock source selection /
mbed_official	423:560d1a9f3083	2173	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
mbed_official	423:560d1a9f3083	2174
mbed_official	423:560d1a9f3083	2175	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
mbed_official	423:560d1a9f3083	2176	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
mbed_official	423:560d1a9f3083	2177
mbed_official	423:560d1a9f3083	2178	/!< CEC Clock source selection /
mbed_official	423:560d1a9f3083	2179	#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /!< CECSW bits /
mbed_official	423:560d1a9f3083	2180
mbed_official	423:560d1a9f3083	2181	#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
mbed_official	423:560d1a9f3083	2182	#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /!< LSE clock selected as HDMI CEC entry clock source /
mbed_official	423:560d1a9f3083	2183
mbed_official	423:560d1a9f3083	2184	/!< USART2 Clock source selection /
mbed_official	423:560d1a9f3083	2185	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
mbed_official	423:560d1a9f3083	2186	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2187	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2188
mbed_official	423:560d1a9f3083	2189	#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART2 clock source /
mbed_official	423:560d1a9f3083	2190	#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /!< System clock selected as USART2 clock source /
mbed_official	423:560d1a9f3083	2191	#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /!< LSE oscillator clock used as USART2 clock source /
mbed_official	423:560d1a9f3083	2192	#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /!< HSI oscillator clock used as USART2 clock source /
mbed_official	423:560d1a9f3083	2193
mbed_official	423:560d1a9f3083	2194	/***************** Bit definition for RCC_CR2 register *****************/
mbed_official	423:560d1a9f3083	2195	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
mbed_official	423:560d1a9f3083	2196	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
mbed_official	423:560d1a9f3083	2197	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
mbed_official	423:560d1a9f3083	2198	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
mbed_official	423:560d1a9f3083	2199	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
mbed_official	423:560d1a9f3083	2200
mbed_official	423:560d1a9f3083	2201	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2202	/* */
mbed_official	423:560d1a9f3083	2203	/* Real-Time Clock (RTC) */
mbed_official	423:560d1a9f3083	2204	/* */
mbed_official	423:560d1a9f3083	2205	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2206	/****************** Bits definition for RTC_TR register ****************/
mbed_official	423:560d1a9f3083	2207	#define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	2208	#define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	2209	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	2210	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	2211	#define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	2212	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2213	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	2214	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2215	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	2216	#define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official	423:560d1a9f3083	2217	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2218	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2219	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2220	#define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	2221	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2222	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2223	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2224	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2225	#define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official	423:560d1a9f3083	2226	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2227	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2228	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2229	#define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	2230	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2231	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2232	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2233	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2234
mbed_official	423:560d1a9f3083	2235	/****************** Bits definition for RTC_DR register ****************/
mbed_official	423:560d1a9f3083	2236	#define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official	423:560d1a9f3083	2237	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	2238	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	2239	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	2240	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	2241	#define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	2242	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2243	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	2244	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2245	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	2246	#define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official	423:560d1a9f3083	2247	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2248	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2249	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2250	#define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2251	#define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	2252	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2253	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2254	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2255	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2256	#define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official	423:560d1a9f3083	2257	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2258	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2259	#define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	2260	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2261	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2262	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2263	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2264
mbed_official	423:560d1a9f3083	2265	/****************** Bits definition for RTC_CR register ****************/
mbed_official	423:560d1a9f3083	2266	#define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	2267	#define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official	423:560d1a9f3083	2268	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	2269	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	2270	#define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	2271	#define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	2272	#define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2273	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	2274	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2275	#define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2276	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2277	#define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2278	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2279	#define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2280	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2281	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2282	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2283
mbed_official	423:560d1a9f3083	2284	/****************** Bits definition for RTC_ISR register ***************/
mbed_official	423:560d1a9f3083	2285	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2286	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2287	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2288	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2289	#define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2290	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2291	#define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	2292	#define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2293	#define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2294	#define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2295	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2296	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2297
mbed_official	423:560d1a9f3083	2298	/****************** Bits definition for RTC_PRER register **************/
mbed_official	423:560d1a9f3083	2299	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official	423:560d1a9f3083	2300	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official	423:560d1a9f3083	2301
mbed_official	423:560d1a9f3083	2302	/****************** Bits definition for RTC_ALRMAR register ************/
mbed_official	423:560d1a9f3083	2303	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	2304	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official	423:560d1a9f3083	2305	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official	423:560d1a9f3083	2306	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official	423:560d1a9f3083	2307	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official	423:560d1a9f3083	2308	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official	423:560d1a9f3083	2309	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	2310	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	2311	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	2312	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	2313	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official	423:560d1a9f3083	2314	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	2315	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	2316	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	2317	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	2318	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	2319	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2320	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	2321	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2322	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	2323	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2324	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official	423:560d1a9f3083	2325	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2326	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2327	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2328	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	2329	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2330	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2331	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2332	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2333	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	2334	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official	423:560d1a9f3083	2335	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2336	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2337	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2338	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	2339	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2340	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2341	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2342	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2343
mbed_official	423:560d1a9f3083	2344	/****************** Bits definition for RTC_WPR register ***************/
mbed_official	423:560d1a9f3083	2345	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official	423:560d1a9f3083	2346
mbed_official	423:560d1a9f3083	2347	/****************** Bits definition for RTC_SSR register ***************/
mbed_official	423:560d1a9f3083	2348	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official	423:560d1a9f3083	2349
mbed_official	423:560d1a9f3083	2350	/****************** Bits definition for RTC_SHIFTR register ************/
mbed_official	423:560d1a9f3083	2351	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official	423:560d1a9f3083	2352	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official	423:560d1a9f3083	2353
mbed_official	423:560d1a9f3083	2354	/****************** Bits definition for RTC_TSTR register **************/
mbed_official	423:560d1a9f3083	2355	#define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official	423:560d1a9f3083	2356	#define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official	423:560d1a9f3083	2357	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official	423:560d1a9f3083	2358	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official	423:560d1a9f3083	2359	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official	423:560d1a9f3083	2360	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official	423:560d1a9f3083	2361	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official	423:560d1a9f3083	2362	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2363	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official	423:560d1a9f3083	2364	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official	423:560d1a9f3083	2365	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2366	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2367	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2368	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	2369	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2370	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2371	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2372	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2373	#define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official	423:560d1a9f3083	2374	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2375	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2376	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2377	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	2378	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2379	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2380	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2381	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2382
mbed_official	423:560d1a9f3083	2383	/****************** Bits definition for RTC_TSDR register **************/
mbed_official	423:560d1a9f3083	2384	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official	423:560d1a9f3083	2385	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2386	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2387	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2388	#define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2389	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official	423:560d1a9f3083	2390	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2391	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2392	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2393	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2394	#define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official	423:560d1a9f3083	2395	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2396	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2397	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official	423:560d1a9f3083	2398	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2399	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2400	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2401	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2402
mbed_official	423:560d1a9f3083	2403	/****************** Bits definition for RTC_TSSSR register *************/
mbed_official	423:560d1a9f3083	2404	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official	423:560d1a9f3083	2405
mbed_official	423:560d1a9f3083	2406	/****************** Bits definition for RTC_CALR register **************/
mbed_official	423:560d1a9f3083	2407	#define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2408	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2409	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2410	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official	423:560d1a9f3083	2411	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2412	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2413	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2414	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2415	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2416	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official	423:560d1a9f3083	2417	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official	423:560d1a9f3083	2418	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	2419	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2420
mbed_official	423:560d1a9f3083	2421	/****************** Bits definition for RTC_TAFCR register *************/
mbed_official	423:560d1a9f3083	2422	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official	423:560d1a9f3083	2423	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official	423:560d1a9f3083	2424	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official	423:560d1a9f3083	2425	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official	423:560d1a9f3083	2426	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official	423:560d1a9f3083	2427	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official	423:560d1a9f3083	2428	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official	423:560d1a9f3083	2429	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official	423:560d1a9f3083	2430	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official	423:560d1a9f3083	2431	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official	423:560d1a9f3083	2432	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official	423:560d1a9f3083	2433	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official	423:560d1a9f3083	2434	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official	423:560d1a9f3083	2435	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official	423:560d1a9f3083	2436	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official	423:560d1a9f3083	2437	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official	423:560d1a9f3083	2438	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official	423:560d1a9f3083	2439	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official	423:560d1a9f3083	2440
mbed_official	423:560d1a9f3083	2441	/****************** Bits definition for RTC_ALRMASSR register **********/
mbed_official	423:560d1a9f3083	2442	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official	423:560d1a9f3083	2443	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official	423:560d1a9f3083	2444	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official	423:560d1a9f3083	2445	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official	423:560d1a9f3083	2446	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official	423:560d1a9f3083	2447	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official	423:560d1a9f3083	2448
mbed_official	423:560d1a9f3083	2449	/****************** Bits definition for RTC_BKP0R register *************/
mbed_official	423:560d1a9f3083	2450	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official	423:560d1a9f3083	2451
mbed_official	423:560d1a9f3083	2452	/****************** Bits definition for RTC_BKP1R register *************/
mbed_official	423:560d1a9f3083	2453	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official	423:560d1a9f3083	2454
mbed_official	423:560d1a9f3083	2455	/****************** Bits definition for RTC_BKP2R register *************/
mbed_official	423:560d1a9f3083	2456	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official	423:560d1a9f3083	2457
mbed_official	423:560d1a9f3083	2458	/****************** Bits definition for RTC_BKP3R register *************/
mbed_official	423:560d1a9f3083	2459	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official	423:560d1a9f3083	2460
mbed_official	423:560d1a9f3083	2461	/****************** Bits definition for RTC_BKP4R register *************/
mbed_official	423:560d1a9f3083	2462	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official	423:560d1a9f3083	2463
mbed_official	423:560d1a9f3083	2464	/****************** Number of backup registers ****************************/
mbed_official	423:560d1a9f3083	2465	#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official	423:560d1a9f3083	2466
mbed_official	423:560d1a9f3083	2467	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2468	/* */
mbed_official	423:560d1a9f3083	2469	/* Serial Peripheral Interface (SPI) */
mbed_official	423:560d1a9f3083	2470	/* */
mbed_official	423:560d1a9f3083	2471	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2472	/***************** Bit definition for SPI_CR1 register *****************/
mbed_official	423:560d1a9f3083	2473	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
mbed_official	423:560d1a9f3083	2474	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
mbed_official	423:560d1a9f3083	2475	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
mbed_official	423:560d1a9f3083	2476	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
mbed_official	423:560d1a9f3083	2477	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2478	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2479	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
mbed_official	423:560d1a9f3083	2480	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
mbed_official	423:560d1a9f3083	2481	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
mbed_official	423:560d1a9f3083	2482	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
mbed_official	423:560d1a9f3083	2483	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
mbed_official	423:560d1a9f3083	2484	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
mbed_official	423:560d1a9f3083	2485	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
mbed_official	423:560d1a9f3083	2486	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
mbed_official	423:560d1a9f3083	2487	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
mbed_official	423:560d1a9f3083	2488	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
mbed_official	423:560d1a9f3083	2489	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
mbed_official	423:560d1a9f3083	2490
mbed_official	423:560d1a9f3083	2491	/***************** Bit definition for SPI_CR2 register *****************/
mbed_official	423:560d1a9f3083	2492	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
mbed_official	423:560d1a9f3083	2493	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
mbed_official	423:560d1a9f3083	2494	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
mbed_official	423:560d1a9f3083	2495	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
mbed_official	423:560d1a9f3083	2496	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
mbed_official	423:560d1a9f3083	2497	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
mbed_official	423:560d1a9f3083	2498	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
mbed_official	423:560d1a9f3083	2499	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
mbed_official	423:560d1a9f3083	2500	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
mbed_official	423:560d1a9f3083	2501	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2502	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2503	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
mbed_official	423:560d1a9f3083	2504	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
mbed_official	423:560d1a9f3083	2505	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
mbed_official	423:560d1a9f3083	2506	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
mbed_official	423:560d1a9f3083	2507	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
mbed_official	423:560d1a9f3083	2508
mbed_official	423:560d1a9f3083	2509	/****************** Bit definition for SPI_SR register *****************/
mbed_official	423:560d1a9f3083	2510	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
mbed_official	423:560d1a9f3083	2511	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
mbed_official	423:560d1a9f3083	2512	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
mbed_official	423:560d1a9f3083	2513	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
mbed_official	423:560d1a9f3083	2514	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
mbed_official	423:560d1a9f3083	2515	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
mbed_official	423:560d1a9f3083	2516	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
mbed_official	423:560d1a9f3083	2517	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
mbed_official	423:560d1a9f3083	2518	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
mbed_official	423:560d1a9f3083	2519	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
mbed_official	423:560d1a9f3083	2520	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2521	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2522	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
mbed_official	423:560d1a9f3083	2523	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
mbed_official	423:560d1a9f3083	2524	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	2525
mbed_official	423:560d1a9f3083	2526	/****************** Bit definition for SPI_DR register *****************/
mbed_official	423:560d1a9f3083	2527	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
mbed_official	423:560d1a9f3083	2528
mbed_official	423:560d1a9f3083	2529	/***************** Bit definition for SPI_CRCPR register ***************/
mbed_official	423:560d1a9f3083	2530	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
mbed_official	423:560d1a9f3083	2531
mbed_official	423:560d1a9f3083	2532	/**************** Bit definition for SPI_RXCRCR register ***************/
mbed_official	423:560d1a9f3083	2533	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
mbed_official	423:560d1a9f3083	2534
mbed_official	423:560d1a9f3083	2535	/**************** Bit definition for SPI_TXCRCR register ***************/
mbed_official	423:560d1a9f3083	2536	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
mbed_official	423:560d1a9f3083	2537
mbed_official	423:560d1a9f3083	2538	/**************** Bit definition for SPI_I2SCFGR register **************/
mbed_official	423:560d1a9f3083	2539	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
mbed_official	423:560d1a9f3083	2540	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
mbed_official	423:560d1a9f3083	2541	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2542	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2543	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
mbed_official	423:560d1a9f3083	2544	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
mbed_official	423:560d1a9f3083	2545	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2546	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2547	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
mbed_official	423:560d1a9f3083	2548	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
mbed_official	423:560d1a9f3083	2549	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2550	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2551	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
mbed_official	423:560d1a9f3083	2552	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
mbed_official	423:560d1a9f3083	2553
mbed_official	423:560d1a9f3083	2554	/**************** Bit definition for SPI_I2SPR register ****************/
mbed_official	423:560d1a9f3083	2555	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
mbed_official	423:560d1a9f3083	2556	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
mbed_official	423:560d1a9f3083	2557	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
mbed_official	423:560d1a9f3083	2558
mbed_official	423:560d1a9f3083	2559	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2560	/* */
mbed_official	423:560d1a9f3083	2561	/* System Configuration (SYSCFG) */
mbed_official	423:560d1a9f3083	2562	/* */
mbed_official	423:560d1a9f3083	2563	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2564	/*************** Bit definition for SYSCFG_CFGR1 register **************/
mbed_official	423:560d1a9f3083	2565	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
mbed_official	423:560d1a9f3083	2566	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
mbed_official	423:560d1a9f3083	2567	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
mbed_official	423:560d1a9f3083	2568
mbed_official	423:560d1a9f3083	2569	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /!< DMA remap mask /
mbed_official	423:560d1a9f3083	2570	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
mbed_official	423:560d1a9f3083	2571	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
mbed_official	423:560d1a9f3083	2572	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
mbed_official	423:560d1a9f3083	2573	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
mbed_official	423:560d1a9f3083	2574	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
mbed_official	423:560d1a9f3083	2575
mbed_official	423:560d1a9f3083	2576	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
mbed_official	423:560d1a9f3083	2577	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
mbed_official	423:560d1a9f3083	2578	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
mbed_official	423:560d1a9f3083	2579	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
mbed_official	423:560d1a9f3083	2580
mbed_official	423:560d1a9f3083	2581	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
mbed_official	423:560d1a9f3083	2582	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
mbed_official	423:560d1a9f3083	2583	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
mbed_official	423:560d1a9f3083	2584	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
mbed_official	423:560d1a9f3083	2585	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
mbed_official	423:560d1a9f3083	2586
mbed_official	423:560d1a9f3083	2587	/**
mbed_official	423:560d1a9f3083	2588	* @brief EXTI0 configuration
mbed_official	423:560d1a9f3083	2589	*/
mbed_official	423:560d1a9f3083	2590	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
mbed_official	423:560d1a9f3083	2591	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
mbed_official	423:560d1a9f3083	2592	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
mbed_official	423:560d1a9f3083	2593	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
mbed_official	423:560d1a9f3083	2594	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
mbed_official	423:560d1a9f3083	2595
mbed_official	423:560d1a9f3083	2596	/**
mbed_official	423:560d1a9f3083	2597	* @brief EXTI1 configuration
mbed_official	423:560d1a9f3083	2598	*/
mbed_official	423:560d1a9f3083	2599	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
mbed_official	423:560d1a9f3083	2600	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
mbed_official	423:560d1a9f3083	2601	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
mbed_official	423:560d1a9f3083	2602	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
mbed_official	423:560d1a9f3083	2603	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
mbed_official	423:560d1a9f3083	2604
mbed_official	423:560d1a9f3083	2605	/**
mbed_official	423:560d1a9f3083	2606	* @brief EXTI2 configuration
mbed_official	423:560d1a9f3083	2607	*/
mbed_official	423:560d1a9f3083	2608	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
mbed_official	423:560d1a9f3083	2609	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
mbed_official	423:560d1a9f3083	2610	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
mbed_official	423:560d1a9f3083	2611	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
mbed_official	423:560d1a9f3083	2612	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
mbed_official	423:560d1a9f3083	2613
mbed_official	423:560d1a9f3083	2614	/**
mbed_official	423:560d1a9f3083	2615	* @brief EXTI3 configuration
mbed_official	423:560d1a9f3083	2616	*/
mbed_official	423:560d1a9f3083	2617	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
mbed_official	423:560d1a9f3083	2618	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
mbed_official	423:560d1a9f3083	2619	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
mbed_official	423:560d1a9f3083	2620	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
mbed_official	423:560d1a9f3083	2621	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
mbed_official	423:560d1a9f3083	2622
mbed_official	423:560d1a9f3083	2623	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
mbed_official	423:560d1a9f3083	2624	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
mbed_official	423:560d1a9f3083	2625	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
mbed_official	423:560d1a9f3083	2626	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
mbed_official	423:560d1a9f3083	2627	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
mbed_official	423:560d1a9f3083	2628
mbed_official	423:560d1a9f3083	2629	/**
mbed_official	423:560d1a9f3083	2630	* @brief EXTI4 configuration
mbed_official	423:560d1a9f3083	2631	*/
mbed_official	423:560d1a9f3083	2632	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
mbed_official	423:560d1a9f3083	2633	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
mbed_official	423:560d1a9f3083	2634	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
mbed_official	423:560d1a9f3083	2635	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
mbed_official	423:560d1a9f3083	2636	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
mbed_official	423:560d1a9f3083	2637
mbed_official	423:560d1a9f3083	2638	/**
mbed_official	423:560d1a9f3083	2639	* @brief EXTI5 configuration
mbed_official	423:560d1a9f3083	2640	*/
mbed_official	423:560d1a9f3083	2641	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
mbed_official	423:560d1a9f3083	2642	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
mbed_official	423:560d1a9f3083	2643	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
mbed_official	423:560d1a9f3083	2644	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
mbed_official	423:560d1a9f3083	2645	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
mbed_official	423:560d1a9f3083	2646
mbed_official	423:560d1a9f3083	2647	/**
mbed_official	423:560d1a9f3083	2648	* @brief EXTI6 configuration
mbed_official	423:560d1a9f3083	2649	*/
mbed_official	423:560d1a9f3083	2650	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
mbed_official	423:560d1a9f3083	2651	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
mbed_official	423:560d1a9f3083	2652	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
mbed_official	423:560d1a9f3083	2653	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
mbed_official	423:560d1a9f3083	2654	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
mbed_official	423:560d1a9f3083	2655
mbed_official	423:560d1a9f3083	2656	/**
mbed_official	423:560d1a9f3083	2657	* @brief EXTI7 configuration
mbed_official	423:560d1a9f3083	2658	*/
mbed_official	423:560d1a9f3083	2659	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
mbed_official	423:560d1a9f3083	2660	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
mbed_official	423:560d1a9f3083	2661	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
mbed_official	423:560d1a9f3083	2662	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
mbed_official	423:560d1a9f3083	2663	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
mbed_official	423:560d1a9f3083	2664
mbed_official	423:560d1a9f3083	2665	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
mbed_official	423:560d1a9f3083	2666	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
mbed_official	423:560d1a9f3083	2667	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
mbed_official	423:560d1a9f3083	2668	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
mbed_official	423:560d1a9f3083	2669	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
mbed_official	423:560d1a9f3083	2670
mbed_official	423:560d1a9f3083	2671	/**
mbed_official	423:560d1a9f3083	2672	* @brief EXTI8 configuration
mbed_official	423:560d1a9f3083	2673	*/
mbed_official	423:560d1a9f3083	2674	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
mbed_official	423:560d1a9f3083	2675	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
mbed_official	423:560d1a9f3083	2676	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
mbed_official	423:560d1a9f3083	2677	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
mbed_official	423:560d1a9f3083	2678	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!< PF[8] pin /
mbed_official	423:560d1a9f3083	2679
mbed_official	423:560d1a9f3083	2680	/**
mbed_official	423:560d1a9f3083	2681	* @brief EXTI9 configuration
mbed_official	423:560d1a9f3083	2682	*/
mbed_official	423:560d1a9f3083	2683	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
mbed_official	423:560d1a9f3083	2684	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
mbed_official	423:560d1a9f3083	2685	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
mbed_official	423:560d1a9f3083	2686	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
mbed_official	423:560d1a9f3083	2687	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
mbed_official	423:560d1a9f3083	2688
mbed_official	423:560d1a9f3083	2689	/**
mbed_official	423:560d1a9f3083	2690	* @brief EXTI10 configuration
mbed_official	423:560d1a9f3083	2691	*/
mbed_official	423:560d1a9f3083	2692	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
mbed_official	423:560d1a9f3083	2693	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
mbed_official	423:560d1a9f3083	2694	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
mbed_official	423:560d1a9f3083	2695	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
mbed_official	423:560d1a9f3083	2696	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
mbed_official	423:560d1a9f3083	2697
mbed_official	423:560d1a9f3083	2698	/**
mbed_official	423:560d1a9f3083	2699	* @brief EXTI11 configuration
mbed_official	423:560d1a9f3083	2700	*/
mbed_official	423:560d1a9f3083	2701	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
mbed_official	423:560d1a9f3083	2702	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
mbed_official	423:560d1a9f3083	2703	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
mbed_official	423:560d1a9f3083	2704	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
mbed_official	423:560d1a9f3083	2705	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!< PF[11] pin /
mbed_official	423:560d1a9f3083	2706
mbed_official	423:560d1a9f3083	2707	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
mbed_official	423:560d1a9f3083	2708	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
mbed_official	423:560d1a9f3083	2709	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
mbed_official	423:560d1a9f3083	2710	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
mbed_official	423:560d1a9f3083	2711	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
mbed_official	423:560d1a9f3083	2712
mbed_official	423:560d1a9f3083	2713	/**
mbed_official	423:560d1a9f3083	2714	* @brief EXTI12 configuration
mbed_official	423:560d1a9f3083	2715	*/
mbed_official	423:560d1a9f3083	2716	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
mbed_official	423:560d1a9f3083	2717	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
mbed_official	423:560d1a9f3083	2718	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
mbed_official	423:560d1a9f3083	2719	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
mbed_official	423:560d1a9f3083	2720	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!< PF[12] pin /
mbed_official	423:560d1a9f3083	2721
mbed_official	423:560d1a9f3083	2722	/**
mbed_official	423:560d1a9f3083	2723	* @brief EXTI13 configuration
mbed_official	423:560d1a9f3083	2724	*/
mbed_official	423:560d1a9f3083	2725	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
mbed_official	423:560d1a9f3083	2726	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
mbed_official	423:560d1a9f3083	2727	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
mbed_official	423:560d1a9f3083	2728	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
mbed_official	423:560d1a9f3083	2729	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!< PF[13] pin /
mbed_official	423:560d1a9f3083	2730
mbed_official	423:560d1a9f3083	2731	/**
mbed_official	423:560d1a9f3083	2732	* @brief EXTI14 configuration
mbed_official	423:560d1a9f3083	2733	*/
mbed_official	423:560d1a9f3083	2734	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
mbed_official	423:560d1a9f3083	2735	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
mbed_official	423:560d1a9f3083	2736	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
mbed_official	423:560d1a9f3083	2737	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
mbed_official	423:560d1a9f3083	2738	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!< PF[14] pin /
mbed_official	423:560d1a9f3083	2739
mbed_official	423:560d1a9f3083	2740	/**
mbed_official	423:560d1a9f3083	2741	* @brief EXTI15 configuration
mbed_official	423:560d1a9f3083	2742	*/
mbed_official	423:560d1a9f3083	2743	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
mbed_official	423:560d1a9f3083	2744	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
mbed_official	423:560d1a9f3083	2745	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
mbed_official	423:560d1a9f3083	2746	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
mbed_official	423:560d1a9f3083	2747	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!< PF[15] pin /
mbed_official	423:560d1a9f3083	2748
mbed_official	423:560d1a9f3083	2749	/*************** Bit definition for SYSCFG_CFGR2 register **************/
mbed_official	423:560d1a9f3083	2750	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
mbed_official	423:560d1a9f3083	2751	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
mbed_official	423:560d1a9f3083	2752	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
mbed_official	423:560d1a9f3083	2753	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
mbed_official	423:560d1a9f3083	2754	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
mbed_official	423:560d1a9f3083	2755
mbed_official	423:560d1a9f3083	2756	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2757	/* */
mbed_official	423:560d1a9f3083	2758	/* Timers (TIM) */
mbed_official	423:560d1a9f3083	2759	/* */
mbed_official	423:560d1a9f3083	2760	/*****************************************************************************/
mbed_official	423:560d1a9f3083	2761	/***************** Bit definition for TIM_CR1 register *****************/
mbed_official	423:560d1a9f3083	2762	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
mbed_official	423:560d1a9f3083	2763	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
mbed_official	423:560d1a9f3083	2764	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
mbed_official	423:560d1a9f3083	2765	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
mbed_official	423:560d1a9f3083	2766	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
mbed_official	423:560d1a9f3083	2767
mbed_official	423:560d1a9f3083	2768	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
mbed_official	423:560d1a9f3083	2769	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2770	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2771
mbed_official	423:560d1a9f3083	2772	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
mbed_official	423:560d1a9f3083	2773
mbed_official	423:560d1a9f3083	2774	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
mbed_official	423:560d1a9f3083	2775	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2776	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2777
mbed_official	423:560d1a9f3083	2778	/***************** Bit definition for TIM_CR2 register *****************/
mbed_official	423:560d1a9f3083	2779	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
mbed_official	423:560d1a9f3083	2780	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
mbed_official	423:560d1a9f3083	2781	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
mbed_official	423:560d1a9f3083	2782
mbed_official	423:560d1a9f3083	2783	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
mbed_official	423:560d1a9f3083	2784	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2785	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2786	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2787
mbed_official	423:560d1a9f3083	2788	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
mbed_official	423:560d1a9f3083	2789	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
mbed_official	423:560d1a9f3083	2790	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
mbed_official	423:560d1a9f3083	2791	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
mbed_official	423:560d1a9f3083	2792	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
mbed_official	423:560d1a9f3083	2793	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
mbed_official	423:560d1a9f3083	2794	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
mbed_official	423:560d1a9f3083	2795	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
mbed_official	423:560d1a9f3083	2796
mbed_official	423:560d1a9f3083	2797	/***************** Bit definition for TIM_SMCR register ****************/
mbed_official	423:560d1a9f3083	2798	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
mbed_official	423:560d1a9f3083	2799	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2800	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2801	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2802
mbed_official	423:560d1a9f3083	2803	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
mbed_official	423:560d1a9f3083	2804
mbed_official	423:560d1a9f3083	2805	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
mbed_official	423:560d1a9f3083	2806	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2807	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2808	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2809
mbed_official	423:560d1a9f3083	2810	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
mbed_official	423:560d1a9f3083	2811
mbed_official	423:560d1a9f3083	2812	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
mbed_official	423:560d1a9f3083	2813	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2814	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2815	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2816	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	423:560d1a9f3083	2817
mbed_official	423:560d1a9f3083	2818	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
mbed_official	423:560d1a9f3083	2819	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2820	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2821
mbed_official	423:560d1a9f3083	2822	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
mbed_official	423:560d1a9f3083	2823	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
mbed_official	423:560d1a9f3083	2824
mbed_official	423:560d1a9f3083	2825	/***************** Bit definition for TIM_DIER register ****************/
mbed_official	423:560d1a9f3083	2826	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
mbed_official	423:560d1a9f3083	2827	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
mbed_official	423:560d1a9f3083	2828	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
mbed_official	423:560d1a9f3083	2829	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
mbed_official	423:560d1a9f3083	2830	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
mbed_official	423:560d1a9f3083	2831	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
mbed_official	423:560d1a9f3083	2832	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
mbed_official	423:560d1a9f3083	2833	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
mbed_official	423:560d1a9f3083	2834	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
mbed_official	423:560d1a9f3083	2835	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
mbed_official	423:560d1a9f3083	2836	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
mbed_official	423:560d1a9f3083	2837	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
mbed_official	423:560d1a9f3083	2838	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
mbed_official	423:560d1a9f3083	2839	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
mbed_official	423:560d1a9f3083	2840	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
mbed_official	423:560d1a9f3083	2841
mbed_official	423:560d1a9f3083	2842	/****************** Bit definition for TIM_SR register *****************/
mbed_official	423:560d1a9f3083	2843	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
mbed_official	423:560d1a9f3083	2844	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
mbed_official	423:560d1a9f3083	2845	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
mbed_official	423:560d1a9f3083	2846	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
mbed_official	423:560d1a9f3083	2847	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
mbed_official	423:560d1a9f3083	2848	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
mbed_official	423:560d1a9f3083	2849	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
mbed_official	423:560d1a9f3083	2850	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
mbed_official	423:560d1a9f3083	2851	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
mbed_official	423:560d1a9f3083	2852	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
mbed_official	423:560d1a9f3083	2853	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
mbed_official	423:560d1a9f3083	2854	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
mbed_official	423:560d1a9f3083	2855
mbed_official	423:560d1a9f3083	2856	/***************** Bit definition for TIM_EGR register *****************/
mbed_official	423:560d1a9f3083	2857	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
mbed_official	423:560d1a9f3083	2858	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
mbed_official	423:560d1a9f3083	2859	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
mbed_official	423:560d1a9f3083	2860	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
mbed_official	423:560d1a9f3083	2861	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
mbed_official	423:560d1a9f3083	2862	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
mbed_official	423:560d1a9f3083	2863	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
mbed_official	423:560d1a9f3083	2864	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
mbed_official	423:560d1a9f3083	2865
mbed_official	423:560d1a9f3083	2866	/**************** Bit definition for TIM_CCMR1 register ****************/
mbed_official	423:560d1a9f3083	2867	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
mbed_official	423:560d1a9f3083	2868	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2869	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2870
mbed_official	423:560d1a9f3083	2871	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
mbed_official	423:560d1a9f3083	2872	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
mbed_official	423:560d1a9f3083	2873
mbed_official	423:560d1a9f3083	2874	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
mbed_official	423:560d1a9f3083	2875	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2876	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2877	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2878
mbed_official	423:560d1a9f3083	2879	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
mbed_official	423:560d1a9f3083	2880
mbed_official	423:560d1a9f3083	2881	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
mbed_official	423:560d1a9f3083	2882	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2883	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2884
mbed_official	423:560d1a9f3083	2885	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
mbed_official	423:560d1a9f3083	2886	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
mbed_official	423:560d1a9f3083	2887
mbed_official	423:560d1a9f3083	2888	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
mbed_official	423:560d1a9f3083	2889	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2890	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2891	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2892
mbed_official	423:560d1a9f3083	2893	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
mbed_official	423:560d1a9f3083	2894
mbed_official	423:560d1a9f3083	2895	/---------------------------------------------------------------------------/
mbed_official	423:560d1a9f3083	2896
mbed_official	423:560d1a9f3083	2897	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
mbed_official	423:560d1a9f3083	2898	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2899	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2900
mbed_official	423:560d1a9f3083	2901	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
mbed_official	423:560d1a9f3083	2902	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2903	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2904	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2905	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	423:560d1a9f3083	2906
mbed_official	423:560d1a9f3083	2907	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
mbed_official	423:560d1a9f3083	2908	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2909	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2910
mbed_official	423:560d1a9f3083	2911	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
mbed_official	423:560d1a9f3083	2912	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2913	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2914	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2915	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	423:560d1a9f3083	2916
mbed_official	423:560d1a9f3083	2917	/**************** Bit definition for TIM_CCMR2 register ****************/
mbed_official	423:560d1a9f3083	2918	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
mbed_official	423:560d1a9f3083	2919	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2920	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2921
mbed_official	423:560d1a9f3083	2922	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
mbed_official	423:560d1a9f3083	2923	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
mbed_official	423:560d1a9f3083	2924
mbed_official	423:560d1a9f3083	2925	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
mbed_official	423:560d1a9f3083	2926	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2927	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2928	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2929
mbed_official	423:560d1a9f3083	2930	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
mbed_official	423:560d1a9f3083	2931
mbed_official	423:560d1a9f3083	2932	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
mbed_official	423:560d1a9f3083	2933	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2934	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2935
mbed_official	423:560d1a9f3083	2936	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
mbed_official	423:560d1a9f3083	2937	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
mbed_official	423:560d1a9f3083	2938
mbed_official	423:560d1a9f3083	2939	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
mbed_official	423:560d1a9f3083	2940	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2941	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2942	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2943
mbed_official	423:560d1a9f3083	2944	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
mbed_official	423:560d1a9f3083	2945
mbed_official	423:560d1a9f3083	2946	/---------------------------------------------------------------------------/
mbed_official	423:560d1a9f3083	2947
mbed_official	423:560d1a9f3083	2948	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
mbed_official	423:560d1a9f3083	2949	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2950	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2951
mbed_official	423:560d1a9f3083	2952	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
mbed_official	423:560d1a9f3083	2953	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2954	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2955	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2956	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
mbed_official	423:560d1a9f3083	2957
mbed_official	423:560d1a9f3083	2958	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
mbed_official	423:560d1a9f3083	2959	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2960	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2961
mbed_official	423:560d1a9f3083	2962	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
mbed_official	423:560d1a9f3083	2963	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	2964	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	2965	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	2966	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
mbed_official	423:560d1a9f3083	2967
mbed_official	423:560d1a9f3083	2968	/***************** Bit definition for TIM_CCER register ****************/
mbed_official	423:560d1a9f3083	2969	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
mbed_official	423:560d1a9f3083	2970	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
mbed_official	423:560d1a9f3083	2971	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
mbed_official	423:560d1a9f3083	2972	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
mbed_official	423:560d1a9f3083	2973	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
mbed_official	423:560d1a9f3083	2974	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
mbed_official	423:560d1a9f3083	2975	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
mbed_official	423:560d1a9f3083	2976	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
mbed_official	423:560d1a9f3083	2977	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
mbed_official	423:560d1a9f3083	2978	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
mbed_official	423:560d1a9f3083	2979	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
mbed_official	423:560d1a9f3083	2980	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
mbed_official	423:560d1a9f3083	2981	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
mbed_official	423:560d1a9f3083	2982	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
mbed_official	423:560d1a9f3083	2983	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
mbed_official	423:560d1a9f3083	2984
mbed_official	423:560d1a9f3083	2985	/***************** Bit definition for TIM_CNT register *****************/
mbed_official	423:560d1a9f3083	2986	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
mbed_official	423:560d1a9f3083	2987
mbed_official	423:560d1a9f3083	2988	/***************** Bit definition for TIM_PSC register *****************/
mbed_official	423:560d1a9f3083	2989	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
mbed_official	423:560d1a9f3083	2990
mbed_official	423:560d1a9f3083	2991	/***************** Bit definition for TIM_ARR register *****************/
mbed_official	423:560d1a9f3083	2992	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
mbed_official	423:560d1a9f3083	2993
mbed_official	423:560d1a9f3083	2994	/***************** Bit definition for TIM_RCR register *****************/
mbed_official	423:560d1a9f3083	2995	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
mbed_official	423:560d1a9f3083	2996
mbed_official	423:560d1a9f3083	2997	/***************** Bit definition for TIM_CCR1 register ****************/
mbed_official	423:560d1a9f3083	2998	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
mbed_official	423:560d1a9f3083	2999
mbed_official	423:560d1a9f3083	3000	/***************** Bit definition for TIM_CCR2 register ****************/
mbed_official	423:560d1a9f3083	3001	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
mbed_official	423:560d1a9f3083	3002
mbed_official	423:560d1a9f3083	3003	/***************** Bit definition for TIM_CCR3 register ****************/
mbed_official	423:560d1a9f3083	3004	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
mbed_official	423:560d1a9f3083	3005
mbed_official	423:560d1a9f3083	3006	/***************** Bit definition for TIM_CCR4 register ****************/
mbed_official	423:560d1a9f3083	3007	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
mbed_official	423:560d1a9f3083	3008
mbed_official	423:560d1a9f3083	3009	/***************** Bit definition for TIM_BDTR register ****************/
mbed_official	423:560d1a9f3083	3010	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
mbed_official	423:560d1a9f3083	3011	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3012	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3013	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3014	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3015	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3016	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
mbed_official	423:560d1a9f3083	3017	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
mbed_official	423:560d1a9f3083	3018	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
mbed_official	423:560d1a9f3083	3019
mbed_official	423:560d1a9f3083	3020	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
mbed_official	423:560d1a9f3083	3021	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3022	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3023
mbed_official	423:560d1a9f3083	3024	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
mbed_official	423:560d1a9f3083	3025	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
mbed_official	423:560d1a9f3083	3026	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
mbed_official	423:560d1a9f3083	3027	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
mbed_official	423:560d1a9f3083	3028	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
mbed_official	423:560d1a9f3083	3029	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
mbed_official	423:560d1a9f3083	3030
mbed_official	423:560d1a9f3083	3031	/***************** Bit definition for TIM_DCR register *****************/
mbed_official	423:560d1a9f3083	3032	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
mbed_official	423:560d1a9f3083	3033	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3034	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3035	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3036	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3037	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3038
mbed_official	423:560d1a9f3083	3039	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
mbed_official	423:560d1a9f3083	3040	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3041	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3042	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3043	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3044	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3045
mbed_official	423:560d1a9f3083	3046	/***************** Bit definition for TIM_DMAR register ****************/
mbed_official	423:560d1a9f3083	3047	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
mbed_official	423:560d1a9f3083	3048
mbed_official	423:560d1a9f3083	3049	/***************** Bit definition for TIM14_OR register ******************/
mbed_official	423:560d1a9f3083	3050	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
mbed_official	423:560d1a9f3083	3051	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3052	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3053
mbed_official	423:560d1a9f3083	3054	/******************************************************************************/
mbed_official	423:560d1a9f3083	3055	/* */
mbed_official	423:560d1a9f3083	3056	/* Touch Sensing Controller (TSC) */
mbed_official	423:560d1a9f3083	3057	/* */
mbed_official	423:560d1a9f3083	3058	/******************************************************************************/
mbed_official	423:560d1a9f3083	3059	/***************** Bit definition for TSC_CR register *******************/
mbed_official	423:560d1a9f3083	3060	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
mbed_official	423:560d1a9f3083	3061	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
mbed_official	423:560d1a9f3083	3062	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
mbed_official	423:560d1a9f3083	3063	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
mbed_official	423:560d1a9f3083	3064	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
mbed_official	423:560d1a9f3083	3065
mbed_official	423:560d1a9f3083	3066	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
mbed_official	423:560d1a9f3083	3067	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3068	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3069	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3070
mbed_official	423:560d1a9f3083	3071	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
mbed_official	423:560d1a9f3083	3072	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3073	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3074	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3075
mbed_official	423:560d1a9f3083	3076	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
mbed_official	423:560d1a9f3083	3077	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
mbed_official	423:560d1a9f3083	3078
mbed_official	423:560d1a9f3083	3079	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
mbed_official	423:560d1a9f3083	3080	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3081	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3082	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3083	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3084	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3085	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
mbed_official	423:560d1a9f3083	3086	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
mbed_official	423:560d1a9f3083	3087
mbed_official	423:560d1a9f3083	3088	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
mbed_official	423:560d1a9f3083	3089	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3090	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3091	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3092	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3093
mbed_official	423:560d1a9f3083	3094	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
mbed_official	423:560d1a9f3083	3095	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3096	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3097	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3098	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3099
mbed_official	423:560d1a9f3083	3100	/***************** Bit definition for TSC_IER register ******************/
mbed_official	423:560d1a9f3083	3101	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
mbed_official	423:560d1a9f3083	3102	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
mbed_official	423:560d1a9f3083	3103
mbed_official	423:560d1a9f3083	3104	/***************** Bit definition for TSC_ICR register ******************/
mbed_official	423:560d1a9f3083	3105	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
mbed_official	423:560d1a9f3083	3106	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
mbed_official	423:560d1a9f3083	3107
mbed_official	423:560d1a9f3083	3108	/***************** Bit definition for TSC_ISR register ******************/
mbed_official	423:560d1a9f3083	3109	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
mbed_official	423:560d1a9f3083	3110	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
mbed_official	423:560d1a9f3083	3111
mbed_official	423:560d1a9f3083	3112	/***************** Bit definition for TSC_IOHCR register ****************/
mbed_official	423:560d1a9f3083	3113	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3114	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3115	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3116	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3117	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3118	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3119	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3120	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3121	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3122	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3123	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3124	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3125	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3126	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3127	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3128	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3129	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3130	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3131	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3132	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3133	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3134	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3135	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3136	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3137	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3138	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3139	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3140	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3141	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3142	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3143	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3144	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
mbed_official	423:560d1a9f3083	3145
mbed_official	423:560d1a9f3083	3146	/***************** Bit definition for TSC_IOASCR register ***************/
mbed_official	423:560d1a9f3083	3147	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3148	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3149	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3150	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3151	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3152	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3153	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3154	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3155	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3156	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3157	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3158	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3159	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3160	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3161	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3162	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3163	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3164	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3165	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3166	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3167	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3168	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3169	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3170	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3171	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3172	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3173	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3174	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3175	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
mbed_official	423:560d1a9f3083	3176	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
mbed_official	423:560d1a9f3083	3177	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
mbed_official	423:560d1a9f3083	3178	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
mbed_official	423:560d1a9f3083	3179
mbed_official	423:560d1a9f3083	3180	/***************** Bit definition for TSC_IOSCR register ****************/
mbed_official	423:560d1a9f3083	3181	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3182	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3183	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3184	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3185	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3186	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3187	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3188	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3189	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3190	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3191	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3192	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3193	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3194	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3195	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3196	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3197	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3198	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3199	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3200	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3201	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3202	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3203	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3204	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3205	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3206	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3207	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3208	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3209	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
mbed_official	423:560d1a9f3083	3210	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
mbed_official	423:560d1a9f3083	3211	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
mbed_official	423:560d1a9f3083	3212	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
mbed_official	423:560d1a9f3083	3213
mbed_official	423:560d1a9f3083	3214	/***************** Bit definition for TSC_IOCCR register ****************/
mbed_official	423:560d1a9f3083	3215	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
mbed_official	423:560d1a9f3083	3216	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
mbed_official	423:560d1a9f3083	3217	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
mbed_official	423:560d1a9f3083	3218	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
mbed_official	423:560d1a9f3083	3219	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
mbed_official	423:560d1a9f3083	3220	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
mbed_official	423:560d1a9f3083	3221	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
mbed_official	423:560d1a9f3083	3222	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
mbed_official	423:560d1a9f3083	3223	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
mbed_official	423:560d1a9f3083	3224	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
mbed_official	423:560d1a9f3083	3225	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
mbed_official	423:560d1a9f3083	3226	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
mbed_official	423:560d1a9f3083	3227	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
mbed_official	423:560d1a9f3083	3228	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
mbed_official	423:560d1a9f3083	3229	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
mbed_official	423:560d1a9f3083	3230	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
mbed_official	423:560d1a9f3083	3231	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
mbed_official	423:560d1a9f3083	3232	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
mbed_official	423:560d1a9f3083	3233	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
mbed_official	423:560d1a9f3083	3234	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
mbed_official	423:560d1a9f3083	3235	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
mbed_official	423:560d1a9f3083	3236	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
mbed_official	423:560d1a9f3083	3237	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
mbed_official	423:560d1a9f3083	3238	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
mbed_official	423:560d1a9f3083	3239	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
mbed_official	423:560d1a9f3083	3240	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
mbed_official	423:560d1a9f3083	3241	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
mbed_official	423:560d1a9f3083	3242	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
mbed_official	423:560d1a9f3083	3243	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
mbed_official	423:560d1a9f3083	3244	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
mbed_official	423:560d1a9f3083	3245	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
mbed_official	423:560d1a9f3083	3246	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
mbed_official	423:560d1a9f3083	3247
mbed_official	423:560d1a9f3083	3248	/***************** Bit definition for TSC_IOGCSR register ***************/
mbed_official	423:560d1a9f3083	3249	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
mbed_official	423:560d1a9f3083	3250	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
mbed_official	423:560d1a9f3083	3251	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
mbed_official	423:560d1a9f3083	3252	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
mbed_official	423:560d1a9f3083	3253	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
mbed_official	423:560d1a9f3083	3254	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
mbed_official	423:560d1a9f3083	3255	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
mbed_official	423:560d1a9f3083	3256	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
mbed_official	423:560d1a9f3083	3257	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
mbed_official	423:560d1a9f3083	3258	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
mbed_official	423:560d1a9f3083	3259	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
mbed_official	423:560d1a9f3083	3260	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
mbed_official	423:560d1a9f3083	3261	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
mbed_official	423:560d1a9f3083	3262	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
mbed_official	423:560d1a9f3083	3263	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
mbed_official	423:560d1a9f3083	3264	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
mbed_official	423:560d1a9f3083	3265
mbed_official	423:560d1a9f3083	3266	/***************** Bit definition for TSC_IOGXCR register ***************/
mbed_official	423:560d1a9f3083	3267	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
mbed_official	423:560d1a9f3083	3268
mbed_official	423:560d1a9f3083	3269	/******************************************************************************/
mbed_official	423:560d1a9f3083	3270	/* */
mbed_official	423:560d1a9f3083	3271	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official	423:560d1a9f3083	3272	/* */
mbed_official	423:560d1a9f3083	3273	/******************************************************************************/
mbed_official	423:560d1a9f3083	3274	/**************** Bit definition for USART_CR1 register *****************/
mbed_official	423:560d1a9f3083	3275	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
mbed_official	423:560d1a9f3083	3276	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
mbed_official	423:560d1a9f3083	3277	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
mbed_official	423:560d1a9f3083	3278	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
mbed_official	423:560d1a9f3083	3279	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
mbed_official	423:560d1a9f3083	3280	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
mbed_official	423:560d1a9f3083	3281	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
mbed_official	423:560d1a9f3083	3282	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
mbed_official	423:560d1a9f3083	3283	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
mbed_official	423:560d1a9f3083	3284	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
mbed_official	423:560d1a9f3083	3285	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
mbed_official	423:560d1a9f3083	3286	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
mbed_official	423:560d1a9f3083	3287	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
mbed_official	423:560d1a9f3083	3288	#define USART_CR1_M ((uint32_t)0x00001000) /!< SmartCard Length /
mbed_official	423:560d1a9f3083	3289	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
mbed_official	423:560d1a9f3083	3290	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
mbed_official	423:560d1a9f3083	3291	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
mbed_official	423:560d1a9f3083	3292	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
mbed_official	423:560d1a9f3083	3293	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3294	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3295	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	3296	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
mbed_official	423:560d1a9f3083	3297	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
mbed_official	423:560d1a9f3083	3298	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
mbed_official	423:560d1a9f3083	3299	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3300	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3301	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	3302	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
mbed_official	423:560d1a9f3083	3303	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
mbed_official	423:560d1a9f3083	3304	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
mbed_official	423:560d1a9f3083	3305	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
mbed_official	423:560d1a9f3083	3306
mbed_official	423:560d1a9f3083	3307	/**************** Bit definition for USART_CR2 register *****************/
mbed_official	423:560d1a9f3083	3308	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
mbed_official	423:560d1a9f3083	3309	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
mbed_official	423:560d1a9f3083	3310	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
mbed_official	423:560d1a9f3083	3311	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
mbed_official	423:560d1a9f3083	3312	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
mbed_official	423:560d1a9f3083	3313	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
mbed_official	423:560d1a9f3083	3314	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
mbed_official	423:560d1a9f3083	3315	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
mbed_official	423:560d1a9f3083	3316	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3317	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3318	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
mbed_official	423:560d1a9f3083	3319	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
mbed_official	423:560d1a9f3083	3320	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
mbed_official	423:560d1a9f3083	3321	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
mbed_official	423:560d1a9f3083	3322	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
mbed_official	423:560d1a9f3083	3323	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
mbed_official	423:560d1a9f3083	3324	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
mbed_official	423:560d1a9f3083	3325	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
mbed_official	423:560d1a9f3083	3326	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3327	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3328	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
mbed_official	423:560d1a9f3083	3329	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
mbed_official	423:560d1a9f3083	3330
mbed_official	423:560d1a9f3083	3331	/**************** Bit definition for USART_CR3 register *****************/
mbed_official	423:560d1a9f3083	3332	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
mbed_official	423:560d1a9f3083	3333	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
mbed_official	423:560d1a9f3083	3334	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
mbed_official	423:560d1a9f3083	3335	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
mbed_official	423:560d1a9f3083	3336	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
mbed_official	423:560d1a9f3083	3337	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
mbed_official	423:560d1a9f3083	3338	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
mbed_official	423:560d1a9f3083	3339	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
mbed_official	423:560d1a9f3083	3340	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
mbed_official	423:560d1a9f3083	3341	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
mbed_official	423:560d1a9f3083	3342	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
mbed_official	423:560d1a9f3083	3343	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
mbed_official	423:560d1a9f3083	3344	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
mbed_official	423:560d1a9f3083	3345	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
mbed_official	423:560d1a9f3083	3346	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
mbed_official	423:560d1a9f3083	3347	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
mbed_official	423:560d1a9f3083	3348	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
mbed_official	423:560d1a9f3083	3349	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3350	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3351	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
mbed_official	423:560d1a9f3083	3352	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
mbed_official	423:560d1a9f3083	3353	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
mbed_official	423:560d1a9f3083	3354	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
mbed_official	423:560d1a9f3083	3355	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
mbed_official	423:560d1a9f3083	3356
mbed_official	423:560d1a9f3083	3357	/**************** Bit definition for USART_BRR register *****************/
mbed_official	423:560d1a9f3083	3358	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
mbed_official	423:560d1a9f3083	3359	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
mbed_official	423:560d1a9f3083	3360
mbed_official	423:560d1a9f3083	3361	/**************** Bit definition for USART_GTPR register ****************/
mbed_official	423:560d1a9f3083	3362	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
mbed_official	423:560d1a9f3083	3363	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
mbed_official	423:560d1a9f3083	3364
mbed_official	423:560d1a9f3083	3365
mbed_official	423:560d1a9f3083	3366	/***************** Bit definition for USART_RTOR register ***************/
mbed_official	423:560d1a9f3083	3367	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
mbed_official	423:560d1a9f3083	3368	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
mbed_official	423:560d1a9f3083	3369
mbed_official	423:560d1a9f3083	3370	/***************** Bit definition for USART_RQR register ****************/
mbed_official	423:560d1a9f3083	3371	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
mbed_official	423:560d1a9f3083	3372	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
mbed_official	423:560d1a9f3083	3373	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
mbed_official	423:560d1a9f3083	3374	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
mbed_official	423:560d1a9f3083	3375	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
mbed_official	423:560d1a9f3083	3376
mbed_official	423:560d1a9f3083	3377	/***************** Bit definition for USART_ISR register ****************/
mbed_official	423:560d1a9f3083	3378	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
mbed_official	423:560d1a9f3083	3379	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
mbed_official	423:560d1a9f3083	3380	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
mbed_official	423:560d1a9f3083	3381	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
mbed_official	423:560d1a9f3083	3382	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
mbed_official	423:560d1a9f3083	3383	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
mbed_official	423:560d1a9f3083	3384	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
mbed_official	423:560d1a9f3083	3385	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
mbed_official	423:560d1a9f3083	3386	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
mbed_official	423:560d1a9f3083	3387	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
mbed_official	423:560d1a9f3083	3388	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
mbed_official	423:560d1a9f3083	3389	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
mbed_official	423:560d1a9f3083	3390	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
mbed_official	423:560d1a9f3083	3391	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
mbed_official	423:560d1a9f3083	3392	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
mbed_official	423:560d1a9f3083	3393	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
mbed_official	423:560d1a9f3083	3394	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
mbed_official	423:560d1a9f3083	3395	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
mbed_official	423:560d1a9f3083	3396	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
mbed_official	423:560d1a9f3083	3397	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
mbed_official	423:560d1a9f3083	3398	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
mbed_official	423:560d1a9f3083	3399	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
mbed_official	423:560d1a9f3083	3400
mbed_official	423:560d1a9f3083	3401	/***************** Bit definition for USART_ICR register ****************/
mbed_official	423:560d1a9f3083	3402	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
mbed_official	423:560d1a9f3083	3403	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
mbed_official	423:560d1a9f3083	3404	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
mbed_official	423:560d1a9f3083	3405	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
mbed_official	423:560d1a9f3083	3406	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
mbed_official	423:560d1a9f3083	3407	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
mbed_official	423:560d1a9f3083	3408	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
mbed_official	423:560d1a9f3083	3409	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
mbed_official	423:560d1a9f3083	3410	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
mbed_official	423:560d1a9f3083	3411	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
mbed_official	423:560d1a9f3083	3412	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
mbed_official	423:560d1a9f3083	3413	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
mbed_official	423:560d1a9f3083	3414
mbed_official	423:560d1a9f3083	3415	/***************** Bit definition for USART_RDR register ****************/
mbed_official	423:560d1a9f3083	3416	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
mbed_official	423:560d1a9f3083	3417
mbed_official	423:560d1a9f3083	3418	/***************** Bit definition for USART_TDR register ****************/
mbed_official	423:560d1a9f3083	3419	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
mbed_official	423:560d1a9f3083	3420
mbed_official	423:560d1a9f3083	3421	/******************************************************************************/
mbed_official	423:560d1a9f3083	3422	/* */
mbed_official	423:560d1a9f3083	3423	/* Window WATCHDOG (WWDG) */
mbed_official	423:560d1a9f3083	3424	/* */
mbed_official	423:560d1a9f3083	3425	/******************************************************************************/
mbed_official	423:560d1a9f3083	3426	/***************** Bit definition for WWDG_CR register ******************/
mbed_official	423:560d1a9f3083	3427	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
mbed_official	423:560d1a9f3083	3428	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3429	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3430	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3431	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3432	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3433	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
mbed_official	423:560d1a9f3083	3434	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
mbed_official	423:560d1a9f3083	3435
mbed_official	423:560d1a9f3083	3436	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
mbed_official	423:560d1a9f3083	3437
mbed_official	423:560d1a9f3083	3438	/***************** Bit definition for WWDG_CFR register *****************/
mbed_official	423:560d1a9f3083	3439	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
mbed_official	423:560d1a9f3083	3440	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3441	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3442	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
mbed_official	423:560d1a9f3083	3443	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
mbed_official	423:560d1a9f3083	3444	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
mbed_official	423:560d1a9f3083	3445	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
mbed_official	423:560d1a9f3083	3446	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
mbed_official	423:560d1a9f3083	3447
mbed_official	423:560d1a9f3083	3448	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
mbed_official	423:560d1a9f3083	3449	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
mbed_official	423:560d1a9f3083	3450	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
mbed_official	423:560d1a9f3083	3451
mbed_official	423:560d1a9f3083	3452	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
mbed_official	423:560d1a9f3083	3453
mbed_official	423:560d1a9f3083	3454	/***************** Bit definition for WWDG_SR register ******************/
mbed_official	423:560d1a9f3083	3455	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
mbed_official	423:560d1a9f3083	3456
mbed_official	423:560d1a9f3083	3457	/**
mbed_official	423:560d1a9f3083	3458	* @}
mbed_official	423:560d1a9f3083	3459	*/
mbed_official	423:560d1a9f3083	3460
mbed_official	423:560d1a9f3083	3461	/**
mbed_official	423:560d1a9f3083	3462	* @}
mbed_official	423:560d1a9f3083	3463	*/
mbed_official	423:560d1a9f3083	3464
mbed_official	423:560d1a9f3083	3465
mbed_official	423:560d1a9f3083	3466	/** @addtogroup Exported_macro
mbed_official	423:560d1a9f3083	3467	* @{
mbed_official	423:560d1a9f3083	3468	*/
mbed_official	423:560d1a9f3083	3469
mbed_official	423:560d1a9f3083	3470	/**************************** ADC Instances *******************************/
mbed_official	423:560d1a9f3083	3471	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official	423:560d1a9f3083	3472
mbed_official	423:560d1a9f3083	3473	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official	423:560d1a9f3083	3474
mbed_official	423:560d1a9f3083	3475	/**************************** COMP Instances *******************************/
mbed_official	423:560d1a9f3083	3476	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
mbed_official	423:560d1a9f3083	3477	((INSTANCE) == COMP2))
mbed_official	423:560d1a9f3083	3478
mbed_official	423:560d1a9f3083	3479	#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
mbed_official	423:560d1a9f3083	3480
mbed_official	423:560d1a9f3083	3481	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
mbed_official	423:560d1a9f3083	3482
mbed_official	423:560d1a9f3083	3483	/**************************** CEC Instances *******************************/
mbed_official	423:560d1a9f3083	3484	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official	423:560d1a9f3083	3485
mbed_official	423:560d1a9f3083	3486	/**************************** CRC Instances *******************************/
mbed_official	423:560d1a9f3083	3487	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official	423:560d1a9f3083	3488
mbed_official	423:560d1a9f3083	3489	/***************************** DAC Instances ******************************/
mbed_official	423:560d1a9f3083	3490	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official	423:560d1a9f3083	3491
mbed_official	423:560d1a9f3083	3492	/***************************** DMA Instances ****************************/
mbed_official	423:560d1a9f3083	3493	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
mbed_official	423:560d1a9f3083	3494	((INSTANCE) == DMA1_Channel2) \|\| \
mbed_official	423:560d1a9f3083	3495	((INSTANCE) == DMA1_Channel3) \|\| \
mbed_official	423:560d1a9f3083	3496	((INSTANCE) == DMA1_Channel4) \|\| \
mbed_official	423:560d1a9f3083	3497	((INSTANCE) == DMA1_Channel5))
mbed_official	423:560d1a9f3083	3498
mbed_official	423:560d1a9f3083	3499	/**************************** GPIO Instances ******************************/
mbed_official	423:560d1a9f3083	3500	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	423:560d1a9f3083	3501	((INSTANCE) == GPIOB) \|\| \
mbed_official	423:560d1a9f3083	3502	((INSTANCE) == GPIOC) \|\| \
mbed_official	423:560d1a9f3083	3503	((INSTANCE) == GPIOD) \|\| \
mbed_official	423:560d1a9f3083	3504	((INSTANCE) == GPIOF))
mbed_official	423:560d1a9f3083	3505
mbed_official	423:560d1a9f3083	3506	/**************************** GPIO Lock Instances **************************/
mbed_official	423:560d1a9f3083	3507	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	423:560d1a9f3083	3508	((INSTANCE) == GPIOB))
mbed_official	423:560d1a9f3083	3509
mbed_official	423:560d1a9f3083	3510	/**************************** I2C Instances *******************************/
mbed_official	423:560d1a9f3083	3511	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
mbed_official	423:560d1a9f3083	3512	((INSTANCE) == I2C2))
mbed_official	423:560d1a9f3083	3513
mbed_official	423:560d1a9f3083	3514	/**************************** I2S Instances *******************************/
mbed_official	423:560d1a9f3083	3515	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
mbed_official	423:560d1a9f3083	3516	((INSTANCE) == SPI2))
mbed_official	423:560d1a9f3083	3517
mbed_official	423:560d1a9f3083	3518	/**************************** IWDG Instances ******************************/
mbed_official	423:560d1a9f3083	3519	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official	423:560d1a9f3083	3520
mbed_official	423:560d1a9f3083	3521	/**************************** RTC Instances *******************************/
mbed_official	423:560d1a9f3083	3522	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official	423:560d1a9f3083	3523
mbed_official	423:560d1a9f3083	3524	/**************************** SMBUS Instances *******************************/
mbed_official	423:560d1a9f3083	3525	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	423:560d1a9f3083	3526
mbed_official	423:560d1a9f3083	3527	/**************************** SPI Instances *******************************/
mbed_official	423:560d1a9f3083	3528	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
mbed_official	423:560d1a9f3083	3529	((INSTANCE) == SPI2))
mbed_official	423:560d1a9f3083	3530
mbed_official	423:560d1a9f3083	3531	/**************************** TIM Instances *******************************/
mbed_official	423:560d1a9f3083	3532	#define IS_TIM_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3533	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3534	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3535	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3536	((INSTANCE) == TIM6) \|\| \
mbed_official	423:560d1a9f3083	3537	((INSTANCE) == TIM14) \|\| \
mbed_official	423:560d1a9f3083	3538	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3539	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3540	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3541
mbed_official	423:560d1a9f3083	3542	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3543	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3544	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3545	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3546	((INSTANCE) == TIM14) \|\| \
mbed_official	423:560d1a9f3083	3547	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3548	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3549	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3550
mbed_official	423:560d1a9f3083	3551	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3552	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3553	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3554	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3555	((INSTANCE) == TIM15))
mbed_official	423:560d1a9f3083	3556
mbed_official	423:560d1a9f3083	3557	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3558	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3559	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3560	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3561
mbed_official	423:560d1a9f3083	3562	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3563	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3564	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3565	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3566
mbed_official	423:560d1a9f3083	3567	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3568	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3569	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3570	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3571
mbed_official	423:560d1a9f3083	3572	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3573	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3574	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3575	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3576
mbed_official	423:560d1a9f3083	3577	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3578	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3579	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3580	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3581	((INSTANCE) == TIM15))
mbed_official	423:560d1a9f3083	3582
mbed_official	423:560d1a9f3083	3583	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3584	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3585	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3586	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3587	((INSTANCE) == TIM15))
mbed_official	423:560d1a9f3083	3588
mbed_official	423:560d1a9f3083	3589	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3590	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3591	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3592	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3593
mbed_official	423:560d1a9f3083	3594	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3595	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3596	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3597	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3598
mbed_official	423:560d1a9f3083	3599	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3600	(((INSTANCE) == TIM1))
mbed_official	423:560d1a9f3083	3601
mbed_official	423:560d1a9f3083	3602	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3603	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3604	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3605	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3606
mbed_official	423:560d1a9f3083	3607	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3608	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3609	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3610	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3611	((INSTANCE) == TIM6) \|\| \
mbed_official	423:560d1a9f3083	3612	((INSTANCE) == TIM15))
mbed_official	423:560d1a9f3083	3613
mbed_official	423:560d1a9f3083	3614	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3615	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3616	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3617	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3618	((INSTANCE) == TIM15))
mbed_official	423:560d1a9f3083	3619
mbed_official	423:560d1a9f3083	3620	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3621	((INSTANCE) == TIM2)
mbed_official	423:560d1a9f3083	3622
mbed_official	423:560d1a9f3083	3623	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3624	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3625	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3626	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3627	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3628	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3629	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3630
mbed_official	423:560d1a9f3083	3631	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3632	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3633	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3634	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3635	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3636
mbed_official	423:560d1a9f3083	3637	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	423:560d1a9f3083	3638	((((INSTANCE) == TIM1) && \
mbed_official	423:560d1a9f3083	3639	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	423:560d1a9f3083	3640	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	423:560d1a9f3083	3641	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	423:560d1a9f3083	3642	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	423:560d1a9f3083	3643	\|\| \
mbed_official	423:560d1a9f3083	3644	(((INSTANCE) == TIM2) && \
mbed_official	423:560d1a9f3083	3645	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	423:560d1a9f3083	3646	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	423:560d1a9f3083	3647	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	423:560d1a9f3083	3648	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	423:560d1a9f3083	3649	\|\| \
mbed_official	423:560d1a9f3083	3650	(((INSTANCE) == TIM3) && \
mbed_official	423:560d1a9f3083	3651	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	423:560d1a9f3083	3652	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	423:560d1a9f3083	3653	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	423:560d1a9f3083	3654	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	423:560d1a9f3083	3655	\|\| \
mbed_official	423:560d1a9f3083	3656	(((INSTANCE) == TIM14) && \
mbed_official	423:560d1a9f3083	3657	(((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official	423:560d1a9f3083	3658	\|\| \
mbed_official	423:560d1a9f3083	3659	(((INSTANCE) == TIM15) && \
mbed_official	423:560d1a9f3083	3660	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	423:560d1a9f3083	3661	((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official	423:560d1a9f3083	3662	\|\| \
mbed_official	423:560d1a9f3083	3663	(((INSTANCE) == TIM16) && \
mbed_official	423:560d1a9f3083	3664	(((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official	423:560d1a9f3083	3665	\|\| \
mbed_official	423:560d1a9f3083	3666	(((INSTANCE) == TIM17) && \
mbed_official	423:560d1a9f3083	3667	(((CHANNEL) == TIM_CHANNEL_1))))
mbed_official	423:560d1a9f3083	3668
mbed_official	423:560d1a9f3083	3669	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	423:560d1a9f3083	3670	((((INSTANCE) == TIM1) && \
mbed_official	423:560d1a9f3083	3671	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	423:560d1a9f3083	3672	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	423:560d1a9f3083	3673	((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official	423:560d1a9f3083	3674	\|\| \
mbed_official	423:560d1a9f3083	3675	(((INSTANCE) == TIM15) && \
mbed_official	423:560d1a9f3083	3676	((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official	423:560d1a9f3083	3677	\|\| \
mbed_official	423:560d1a9f3083	3678	(((INSTANCE) == TIM16) && \
mbed_official	423:560d1a9f3083	3679	((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official	423:560d1a9f3083	3680	\|\| \
mbed_official	423:560d1a9f3083	3681	(((INSTANCE) == TIM17) && \
mbed_official	423:560d1a9f3083	3682	((CHANNEL) == TIM_CHANNEL_1)))
mbed_official	423:560d1a9f3083	3683
mbed_official	423:560d1a9f3083	3684	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3685	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3686	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3687	((INSTANCE) == TIM3))
mbed_official	423:560d1a9f3083	3688
mbed_official	423:560d1a9f3083	3689	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3690	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3691	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3692	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3693	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3694
mbed_official	423:560d1a9f3083	3695	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3696	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3697	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3698	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3699	((INSTANCE) == TIM14) \|\| \
mbed_official	423:560d1a9f3083	3700	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3701	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3702	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3703
mbed_official	423:560d1a9f3083	3704	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3705	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3706	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3707	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3708	((INSTANCE) == TIM6) \|\| \
mbed_official	423:560d1a9f3083	3709	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3710	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3711	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3712
mbed_official	423:560d1a9f3083	3713	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3714	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3715	((INSTANCE) == TIM2) \|\| \
mbed_official	423:560d1a9f3083	3716	((INSTANCE) == TIM3) \|\| \
mbed_official	423:560d1a9f3083	3717	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3718	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3719	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3720
mbed_official	423:560d1a9f3083	3721	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3722	(((INSTANCE) == TIM1) \|\| \
mbed_official	423:560d1a9f3083	3723	((INSTANCE) == TIM15) \|\| \
mbed_official	423:560d1a9f3083	3724	((INSTANCE) == TIM16) \|\| \
mbed_official	423:560d1a9f3083	3725	((INSTANCE) == TIM17))
mbed_official	423:560d1a9f3083	3726
mbed_official	423:560d1a9f3083	3727	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official	423:560d1a9f3083	3728	((INSTANCE) == TIM14)
mbed_official	423:560d1a9f3083	3729
mbed_official	423:560d1a9f3083	3730	/**************************** TSC Instances *******************************/
mbed_official	423:560d1a9f3083	3731	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official	423:560d1a9f3083	3732
mbed_official	423:560d1a9f3083	3733	/********************* UART Instances : IRDA mode *************************/
mbed_official	423:560d1a9f3083	3734	#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3735
mbed_official	423:560d1a9f3083	3736	/******************* UART Instances : Smard card mode *********************/
mbed_official	423:560d1a9f3083	3737	#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3738
mbed_official	423:560d1a9f3083	3739	/****************** USART Instances : Synchronous mode ********************/
mbed_official	423:560d1a9f3083	3740	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	423:560d1a9f3083	3741	((INSTANCE) == USART2))
mbed_official	423:560d1a9f3083	3742
mbed_official	423:560d1a9f3083	3743	/****************** USART Instances : auto Baud rate detection ************/
mbed_official	423:560d1a9f3083	3744	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3745
mbed_official	423:560d1a9f3083	3746	/****************** UART Instances : Asynchronous mode ********************/
mbed_official	423:560d1a9f3083	3747	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	423:560d1a9f3083	3748	((INSTANCE) == USART2))
mbed_official	423:560d1a9f3083	3749
mbed_official	423:560d1a9f3083	3750	/****************** UART Instances : Half-Duplex mode ********************/
mbed_official	423:560d1a9f3083	3751	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	423:560d1a9f3083	3752	((INSTANCE) == USART2))
mbed_official	423:560d1a9f3083	3753
mbed_official	423:560d1a9f3083	3754	/**************** UART Instances : Hardware Flow control ******************/
mbed_official	423:560d1a9f3083	3755	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	423:560d1a9f3083	3756	((INSTANCE) == USART2))
mbed_official	423:560d1a9f3083	3757
mbed_official	423:560d1a9f3083	3758	/**************** UART Instances : LIN mode ******************/
mbed_official	423:560d1a9f3083	3759	#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3760
mbed_official	423:560d1a9f3083	3761	/**************** UART Instances : wakeup from stop mode ******************/
mbed_official	423:560d1a9f3083	3762	#define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3763
mbed_official	423:560d1a9f3083	3764	/**************** UART Instances : Auto Baud Rate detection ******************/
mbed_official	423:560d1a9f3083	3765	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
mbed_official	423:560d1a9f3083	3766
mbed_official	423:560d1a9f3083	3767	/**************** UART Instances : Driver enable detection ******************/
mbed_official	423:560d1a9f3083	3768	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
mbed_official	423:560d1a9f3083	3769	((INSTANCE) == USART2))
mbed_official	423:560d1a9f3083	3770
mbed_official	423:560d1a9f3083	3771	/**************************** WWDG Instances ******************************/
mbed_official	423:560d1a9f3083	3772	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official	423:560d1a9f3083	3773
mbed_official	423:560d1a9f3083	3774	/**
mbed_official	423:560d1a9f3083	3775	* @}
mbed_official	423:560d1a9f3083	3776	*/
mbed_official	423:560d1a9f3083	3777
mbed_official	423:560d1a9f3083	3778
mbed_official	423:560d1a9f3083	3779	/******************************************************************************/
mbed_official	423:560d1a9f3083	3780	/* For a painless codes migration between the STM32F0xx device product */
mbed_official	423:560d1a9f3083	3781	/* lines, the aliases defined below are put in place to overcome the */
mbed_official	423:560d1a9f3083	3782	/* differences in the interrupt handlers and IRQn definitions. */
mbed_official	423:560d1a9f3083	3783	/* No need to update developed interrupt code when moving across */
mbed_official	423:560d1a9f3083	3784	/* product lines within the same STM32F0 Family */
mbed_official	423:560d1a9f3083	3785	/******************************************************************************/
mbed_official	423:560d1a9f3083	3786
mbed_official	423:560d1a9f3083	3787	/* Aliases for __IRQn */
mbed_official	423:560d1a9f3083	3788	#define PVD_VDDIO2_IRQn PVD_IRQn
mbed_official	423:560d1a9f3083	3789	#define RCC_CRS_IRQn RCC_IRQn
mbed_official	423:560d1a9f3083	3790	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
mbed_official	423:560d1a9f3083	3791	#define ADC1_IRQn ADC1_COMP_IRQn
mbed_official	423:560d1a9f3083	3792	#define TIM6_IRQn TIM6_DAC_IRQn
mbed_official	423:560d1a9f3083	3793
mbed_official	423:560d1a9f3083	3794	/* Aliases for __IRQHandler */
mbed_official	423:560d1a9f3083	3795	#define PVD_VDDIO2_IRQHandler PVD_IRQHandler
mbed_official	423:560d1a9f3083	3796	#define RCC_CRS_IRQHandler RCC_IRQHandler
mbed_official	423:560d1a9f3083	3797	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
mbed_official	423:560d1a9f3083	3798	#define ADC1_IRQHandler ADC1_COMP_IRQHandler
mbed_official	423:560d1a9f3083	3799	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
mbed_official	423:560d1a9f3083	3800
mbed_official	423:560d1a9f3083	3801	#ifdef __cplusplus
mbed_official	423:560d1a9f3083	3802	}
mbed_official	423:560d1a9f3083	3803	#endif /* __cplusplus */
mbed_official	423:560d1a9f3083	3804
mbed_official	423:560d1a9f3083	3805	#endif /* __STM32F051x8_H */
mbed_official	423:560d1a9f3083	3806
mbed_official	423:560d1a9f3083	3807	/**
mbed_official	423:560d1a9f3083	3808	* @}
mbed_official	423:560d1a9f3083	3809	*/
mbed_official	423:560d1a9f3083	3810
mbed_official	423:560d1a9f3083	3811	/**
mbed_official	423:560d1a9f3083	3812	* @}
mbed_official	423:560d1a9f3083	3813	*/
mbed_official	423:560d1a9f3083	3814
mbed_official	423:560d1a9f3083	3815	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	14 Jan 2015
Imports:	4
Forks:	0
Commits:	446
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)

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