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targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h@425:91481e778ca2, 2014-12-03 (annotated)

Committer:
mbed_official
Date:
Wed Dec 03 09:45:08 2014 +0000
Revision:
425:91481e778ca2
Parent:
270:e2babe29baf8 
Synchronized with git revision da233f6e5eb075b1e8d1fcc1438f74d3cb08e2ab



Full URL: https://github.com/mbedmicro/mbed/commit/da233f6e5eb075b1e8d1fcc1438f74d3cb08e2ab/



Targets: Fix GCC ARM linker script for STM32L1  (STM32L152XE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 85:e1a8e879a6a9 1 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
mbed_official 85:e1a8e879a6a9 2 *
mbed_official 85:e1a8e879a6a9 3 * The information contained herein is property of Nordic Semiconductor ASA.
mbed_official 85:e1a8e879a6a9 4 * Terms and conditions of usage are described in detail in NORDIC
mbed_official 85:e1a8e879a6a9 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
mbed_official 85:e1a8e879a6a9 6 *
mbed_official 85:e1a8e879a6a9 7 * Licensees are granted free, non-transferable use of the information. NO
mbed_official 85:e1a8e879a6a9 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
mbed_official 85:e1a8e879a6a9 9 * the file.
mbed_official 85:e1a8e879a6a9 10 *
mbed_official 85:e1a8e879a6a9 11 */
mbed_official 85:e1a8e879a6a9 12
mbed_official 85:e1a8e879a6a9 13
mbed_official 85:e1a8e879a6a9 14 #ifndef __NRF51_BITS_H
mbed_official 85:e1a8e879a6a9 15 #define __NRF51_BITS_H
mbed_official 85:e1a8e879a6a9 16
mbed_official 85:e1a8e879a6a9 17 /*lint ++flb "Enter library region */
mbed_official 85:e1a8e879a6a9 18
mbed_official 85:e1a8e879a6a9 19 //#include <core_cm0.h>
mbed_official 85:e1a8e879a6a9 20
mbed_official 85:e1a8e879a6a9 21 /* Peripheral: AAR */
mbed_official 85:e1a8e879a6a9 22 /* Description: Accelerated Address Resolver. */
mbed_official 85:e1a8e879a6a9 23
mbed_official 85:e1a8e879a6a9 24 /* Register: AAR_INTENSET */
mbed_official 85:e1a8e879a6a9 25 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 26
mbed_official 85:e1a8e879a6a9 27 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
mbed_official 85:e1a8e879a6a9 28 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
mbed_official 85:e1a8e879a6a9 29 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
mbed_official 85:e1a8e879a6a9 30 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 31 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 32 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 33
mbed_official 85:e1a8e879a6a9 34 /* Bit 1 : Enable interrupt on RESOLVED event. */
mbed_official 85:e1a8e879a6a9 35 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
mbed_official 85:e1a8e879a6a9 36 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
mbed_official 85:e1a8e879a6a9 37 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 38 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 39 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 40
mbed_official 85:e1a8e879a6a9 41 /* Bit 0 : Enable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 42 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 43 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 44 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 45 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 46 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 47
mbed_official 85:e1a8e879a6a9 48 /* Register: AAR_INTENCLR */
mbed_official 85:e1a8e879a6a9 49 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 50
mbed_official 85:e1a8e879a6a9 51 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
mbed_official 85:e1a8e879a6a9 52 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
mbed_official 85:e1a8e879a6a9 53 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
mbed_official 85:e1a8e879a6a9 54 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 55 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 56 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 57
mbed_official 85:e1a8e879a6a9 58 /* Bit 1 : Disable interrupt on RESOLVED event. */
mbed_official 85:e1a8e879a6a9 59 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
mbed_official 85:e1a8e879a6a9 60 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
mbed_official 85:e1a8e879a6a9 61 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 62 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 63 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 64
mbed_official 85:e1a8e879a6a9 65 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
mbed_official 85:e1a8e879a6a9 66 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 67 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 68 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 69 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 70 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 71
mbed_official 85:e1a8e879a6a9 72 /* Register: AAR_STATUS */
mbed_official 85:e1a8e879a6a9 73 /* Description: Resolution status. */
mbed_official 85:e1a8e879a6a9 74
mbed_official 85:e1a8e879a6a9 75 /* Bits 3..0 : The IRK used last time an address was resolved. */
mbed_official 85:e1a8e879a6a9 76 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
mbed_official 85:e1a8e879a6a9 77 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
mbed_official 85:e1a8e879a6a9 78
mbed_official 85:e1a8e879a6a9 79 /* Register: AAR_ENABLE */
mbed_official 85:e1a8e879a6a9 80 /* Description: Enable AAR. */
mbed_official 85:e1a8e879a6a9 81
mbed_official 85:e1a8e879a6a9 82 /* Bits 1..0 : Enable AAR. */
mbed_official 85:e1a8e879a6a9 83 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 84 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 85 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
mbed_official 85:e1a8e879a6a9 86 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
mbed_official 85:e1a8e879a6a9 87
mbed_official 85:e1a8e879a6a9 88 /* Register: AAR_NIRK */
mbed_official 85:e1a8e879a6a9 89 /* Description: Number of Identity root Keys in the IRK data structure. */
mbed_official 85:e1a8e879a6a9 90
mbed_official 85:e1a8e879a6a9 91 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
mbed_official 85:e1a8e879a6a9 92 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
mbed_official 85:e1a8e879a6a9 93 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
mbed_official 85:e1a8e879a6a9 94
mbed_official 85:e1a8e879a6a9 95 /* Register: AAR_POWER */
mbed_official 85:e1a8e879a6a9 96 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 97
mbed_official 85:e1a8e879a6a9 98 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 99 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 100 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 101 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 102 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 103
mbed_official 85:e1a8e879a6a9 104
mbed_official 85:e1a8e879a6a9 105 /* Peripheral: ADC */
mbed_official 85:e1a8e879a6a9 106 /* Description: Analog to digital converter. */
mbed_official 85:e1a8e879a6a9 107
mbed_official 85:e1a8e879a6a9 108 /* Register: ADC_INTENSET */
mbed_official 85:e1a8e879a6a9 109 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 110
mbed_official 85:e1a8e879a6a9 111 /* Bit 0 : Enable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 112 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 113 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 114 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 115 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 116 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 117
mbed_official 85:e1a8e879a6a9 118 /* Register: ADC_INTENCLR */
mbed_official 85:e1a8e879a6a9 119 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 120
mbed_official 85:e1a8e879a6a9 121 /* Bit 0 : Disable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 122 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 123 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 124 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 125 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 126 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 127
mbed_official 85:e1a8e879a6a9 128 /* Register: ADC_BUSY */
mbed_official 85:e1a8e879a6a9 129 /* Description: ADC busy register. */
mbed_official 85:e1a8e879a6a9 130
mbed_official 85:e1a8e879a6a9 131 /* Bit 0 : ADC busy register. */
mbed_official 85:e1a8e879a6a9 132 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
mbed_official 85:e1a8e879a6a9 133 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
mbed_official 85:e1a8e879a6a9 134 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
mbed_official 85:e1a8e879a6a9 135 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
mbed_official 85:e1a8e879a6a9 136
mbed_official 85:e1a8e879a6a9 137 /* Register: ADC_ENABLE */
mbed_official 85:e1a8e879a6a9 138 /* Description: ADC enable. */
mbed_official 85:e1a8e879a6a9 139
mbed_official 85:e1a8e879a6a9 140 /* Bits 1..0 : ADC enable. */
mbed_official 85:e1a8e879a6a9 141 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 142 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 143 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
mbed_official 85:e1a8e879a6a9 144 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
mbed_official 85:e1a8e879a6a9 145
mbed_official 85:e1a8e879a6a9 146 /* Register: ADC_CONFIG */
mbed_official 85:e1a8e879a6a9 147 /* Description: ADC configuration register. */
mbed_official 85:e1a8e879a6a9 148
mbed_official 85:e1a8e879a6a9 149 /* Bits 17..16 : ADC external reference pin selection. */
mbed_official 85:e1a8e879a6a9 150 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 151 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 152 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
mbed_official 85:e1a8e879a6a9 153 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
mbed_official 85:e1a8e879a6a9 154 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
mbed_official 85:e1a8e879a6a9 155
mbed_official 85:e1a8e879a6a9 156 /* Bits 15..8 : ADC analog pin selection. */
mbed_official 85:e1a8e879a6a9 157 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
mbed_official 85:e1a8e879a6a9 158 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
mbed_official 85:e1a8e879a6a9 159 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
mbed_official 85:e1a8e879a6a9 160 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
mbed_official 85:e1a8e879a6a9 161 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
mbed_official 85:e1a8e879a6a9 162 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
mbed_official 85:e1a8e879a6a9 163 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
mbed_official 85:e1a8e879a6a9 164 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
mbed_official 85:e1a8e879a6a9 165 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
mbed_official 85:e1a8e879a6a9 166 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
mbed_official 85:e1a8e879a6a9 167 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
mbed_official 85:e1a8e879a6a9 168
mbed_official 85:e1a8e879a6a9 169 /* Bits 6..5 : ADC reference selection. */
mbed_official 85:e1a8e879a6a9 170 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
mbed_official 85:e1a8e879a6a9 171 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
mbed_official 85:e1a8e879a6a9 172 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
mbed_official 85:e1a8e879a6a9 173 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
mbed_official 85:e1a8e879a6a9 174 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
mbed_official 85:e1a8e879a6a9 175 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
mbed_official 85:e1a8e879a6a9 176
mbed_official 85:e1a8e879a6a9 177 /* Bits 4..2 : ADC input selection. */
mbed_official 85:e1a8e879a6a9 178 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
mbed_official 85:e1a8e879a6a9 179 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
mbed_official 85:e1a8e879a6a9 180 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
mbed_official 85:e1a8e879a6a9 181 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
mbed_official 85:e1a8e879a6a9 182 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
mbed_official 85:e1a8e879a6a9 183 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
mbed_official 85:e1a8e879a6a9 184 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
mbed_official 85:e1a8e879a6a9 185
mbed_official 85:e1a8e879a6a9 186 /* Bits 1..0 : ADC resolution. */
mbed_official 85:e1a8e879a6a9 187 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
mbed_official 85:e1a8e879a6a9 188 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
mbed_official 85:e1a8e879a6a9 189 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
mbed_official 85:e1a8e879a6a9 190 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
mbed_official 85:e1a8e879a6a9 191 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
mbed_official 85:e1a8e879a6a9 192
mbed_official 85:e1a8e879a6a9 193 /* Register: ADC_RESULT */
mbed_official 85:e1a8e879a6a9 194 /* Description: Result of ADC conversion. */
mbed_official 85:e1a8e879a6a9 195
mbed_official 85:e1a8e879a6a9 196 /* Bits 9..0 : Result of ADC conversion. */
mbed_official 85:e1a8e879a6a9 197 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
mbed_official 85:e1a8e879a6a9 198 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
mbed_official 85:e1a8e879a6a9 199
mbed_official 85:e1a8e879a6a9 200 /* Register: ADC_POWER */
mbed_official 85:e1a8e879a6a9 201 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 202
mbed_official 85:e1a8e879a6a9 203 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 204 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 205 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 206 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 207 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 208
mbed_official 85:e1a8e879a6a9 209
mbed_official 85:e1a8e879a6a9 210 /* Peripheral: AMLI */
mbed_official 85:e1a8e879a6a9 211 /* Description: AHB Multi-Layer Interface. */
mbed_official 85:e1a8e879a6a9 212
mbed_official 85:e1a8e879a6a9 213 /* Register: AMLI_RAMPRI_CPU0 */
mbed_official 85:e1a8e879a6a9 214 /* Description: Configurable priority configuration register for CPU0. */
mbed_official 85:e1a8e879a6a9 215
mbed_official 85:e1a8e879a6a9 216 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 217 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 218 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 219
mbed_official 85:e1a8e879a6a9 220 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 221 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 222 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 223
mbed_official 85:e1a8e879a6a9 224 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 225 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 226 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 227
mbed_official 85:e1a8e879a6a9 228 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 229 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 230 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 231
mbed_official 85:e1a8e879a6a9 232 /* Register: AMLI_RAMPRI_SPIS1 */
mbed_official 85:e1a8e879a6a9 233 /* Description: Configurable priority configuration register for SPIS1. */
mbed_official 85:e1a8e879a6a9 234
mbed_official 85:e1a8e879a6a9 235 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 236 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 237 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 238
mbed_official 85:e1a8e879a6a9 239 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 240 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 241 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 242
mbed_official 85:e1a8e879a6a9 243 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 244 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 245 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 246
mbed_official 85:e1a8e879a6a9 247 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 248 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 249 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 250
mbed_official 85:e1a8e879a6a9 251 /* Register: AMLI_RAMPRI_RADIO */
mbed_official 85:e1a8e879a6a9 252 /* Description: Configurable priority configuration register for RADIO. */
mbed_official 85:e1a8e879a6a9 253
mbed_official 85:e1a8e879a6a9 254 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 255 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 256 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 257
mbed_official 85:e1a8e879a6a9 258 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 259 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 260 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 261
mbed_official 85:e1a8e879a6a9 262 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 263 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 264 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 265
mbed_official 85:e1a8e879a6a9 266 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 267 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 268 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 269
mbed_official 85:e1a8e879a6a9 270 /* Register: AMLI_RAMPRI_ECB */
mbed_official 85:e1a8e879a6a9 271 /* Description: Configurable priority configuration register for ECB. */
mbed_official 85:e1a8e879a6a9 272
mbed_official 85:e1a8e879a6a9 273 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 274 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 275 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 276
mbed_official 85:e1a8e879a6a9 277 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 278 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 279 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 280
mbed_official 85:e1a8e879a6a9 281 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 282 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 283 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 284
mbed_official 85:e1a8e879a6a9 285 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 286 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 287 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 288
mbed_official 85:e1a8e879a6a9 289 /* Register: AMLI_RAMPRI_CCM */
mbed_official 85:e1a8e879a6a9 290 /* Description: Configurable priority configuration register for CCM. */
mbed_official 85:e1a8e879a6a9 291
mbed_official 85:e1a8e879a6a9 292 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 293 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 294 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 295
mbed_official 85:e1a8e879a6a9 296 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 297 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 298 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 299
mbed_official 85:e1a8e879a6a9 300 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 301 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 302 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 303
mbed_official 85:e1a8e879a6a9 304 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 305 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 306 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 307
mbed_official 85:e1a8e879a6a9 308 /* Register: AMLI_RAMPRI_AAR */
mbed_official 85:e1a8e879a6a9 309 /* Description: Configurable priority configuration register for AAR. */
mbed_official 85:e1a8e879a6a9 310
mbed_official 85:e1a8e879a6a9 311 /* Bits 15..12 : Configuration field for RAM block 3. */
mbed_official 85:e1a8e879a6a9 312 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
mbed_official 85:e1a8e879a6a9 313 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
mbed_official 85:e1a8e879a6a9 314
mbed_official 85:e1a8e879a6a9 315 /* Bits 11..8 : Configuration field for RAM block 2. */
mbed_official 85:e1a8e879a6a9 316 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
mbed_official 85:e1a8e879a6a9 317 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
mbed_official 85:e1a8e879a6a9 318
mbed_official 85:e1a8e879a6a9 319 /* Bits 7..4 : Configuration field for RAM block 1. */
mbed_official 85:e1a8e879a6a9 320 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
mbed_official 85:e1a8e879a6a9 321 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
mbed_official 85:e1a8e879a6a9 322
mbed_official 85:e1a8e879a6a9 323 /* Bits 3..0 : Configuration field for RAM block 0. */
mbed_official 85:e1a8e879a6a9 324 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
mbed_official 85:e1a8e879a6a9 325 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
mbed_official 85:e1a8e879a6a9 326
mbed_official 85:e1a8e879a6a9 327 /* Peripheral: CCM */
mbed_official 85:e1a8e879a6a9 328 /* Description: AES CCM Mode Encryption. */
mbed_official 85:e1a8e879a6a9 329
mbed_official 85:e1a8e879a6a9 330 /* Register: CCM_SHORTS */
mbed_official 85:e1a8e879a6a9 331 /* Description: Shortcut for the CCM. */
mbed_official 85:e1a8e879a6a9 332
mbed_official 85:e1a8e879a6a9 333 /* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
mbed_official 85:e1a8e879a6a9 334 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
mbed_official 85:e1a8e879a6a9 335 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
mbed_official 85:e1a8e879a6a9 336 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 337 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 338
mbed_official 85:e1a8e879a6a9 339 /* Register: CCM_INTENSET */
mbed_official 85:e1a8e879a6a9 340 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 341
mbed_official 85:e1a8e879a6a9 342 /* Bit 2 : Enable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 343 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 344 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 345 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 346 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 347 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 348
mbed_official 85:e1a8e879a6a9 349 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
mbed_official 85:e1a8e879a6a9 350 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
mbed_official 85:e1a8e879a6a9 351 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
mbed_official 85:e1a8e879a6a9 352 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 353 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 354 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 355
mbed_official 85:e1a8e879a6a9 356 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
mbed_official 85:e1a8e879a6a9 357 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
mbed_official 85:e1a8e879a6a9 358 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
mbed_official 85:e1a8e879a6a9 359 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 360 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 361 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 362
mbed_official 85:e1a8e879a6a9 363 /* Register: CCM_INTENCLR */
mbed_official 85:e1a8e879a6a9 364 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 365
mbed_official 85:e1a8e879a6a9 366 /* Bit 2 : Disable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 367 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 368 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 369 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 370 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 371 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 372
mbed_official 85:e1a8e879a6a9 373 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
mbed_official 85:e1a8e879a6a9 374 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
mbed_official 85:e1a8e879a6a9 375 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
mbed_official 85:e1a8e879a6a9 376 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 377 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 378 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 379
mbed_official 85:e1a8e879a6a9 380 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
mbed_official 85:e1a8e879a6a9 381 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
mbed_official 85:e1a8e879a6a9 382 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
mbed_official 85:e1a8e879a6a9 383 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 384 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 385 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 386
mbed_official 85:e1a8e879a6a9 387 /* Register: CCM_MICSTATUS */
mbed_official 85:e1a8e879a6a9 388 /* Description: CCM RX MIC check result. */
mbed_official 85:e1a8e879a6a9 389
mbed_official 85:e1a8e879a6a9 390 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
mbed_official 85:e1a8e879a6a9 391 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
mbed_official 85:e1a8e879a6a9 392 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
mbed_official 85:e1a8e879a6a9 393 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
mbed_official 85:e1a8e879a6a9 394 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
mbed_official 85:e1a8e879a6a9 395
mbed_official 85:e1a8e879a6a9 396 /* Register: CCM_ENABLE */
mbed_official 85:e1a8e879a6a9 397 /* Description: CCM enable. */
mbed_official 85:e1a8e879a6a9 398
mbed_official 85:e1a8e879a6a9 399 /* Bits 1..0 : CCM enable. */
mbed_official 85:e1a8e879a6a9 400 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 401 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 402 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
mbed_official 85:e1a8e879a6a9 403 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
mbed_official 85:e1a8e879a6a9 404
mbed_official 85:e1a8e879a6a9 405 /* Register: CCM_MODE */
mbed_official 85:e1a8e879a6a9 406 /* Description: Operation mode. */
mbed_official 85:e1a8e879a6a9 407
mbed_official 85:e1a8e879a6a9 408 /* Bit 0 : CCM mode operation. */
mbed_official 85:e1a8e879a6a9 409 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
mbed_official 85:e1a8e879a6a9 410 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
mbed_official 85:e1a8e879a6a9 411 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
mbed_official 85:e1a8e879a6a9 412 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
mbed_official 85:e1a8e879a6a9 413
mbed_official 85:e1a8e879a6a9 414 /* Register: CCM_POWER */
mbed_official 85:e1a8e879a6a9 415 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 416
mbed_official 85:e1a8e879a6a9 417 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 418 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 419 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 420 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 421 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 422
mbed_official 85:e1a8e879a6a9 423
mbed_official 85:e1a8e879a6a9 424 /* Peripheral: CLOCK */
mbed_official 85:e1a8e879a6a9 425 /* Description: Clock control. */
mbed_official 85:e1a8e879a6a9 426
mbed_official 85:e1a8e879a6a9 427 /* Register: CLOCK_INTENSET */
mbed_official 85:e1a8e879a6a9 428 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 429
mbed_official 85:e1a8e879a6a9 430 /* Bit 4 : Enable interrupt on CTTO event. */
mbed_official 85:e1a8e879a6a9 431 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
mbed_official 85:e1a8e879a6a9 432 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
mbed_official 85:e1a8e879a6a9 433 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 434 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 435 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 436
mbed_official 85:e1a8e879a6a9 437 /* Bit 3 : Enable interrupt on DONE event. */
mbed_official 85:e1a8e879a6a9 438 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
mbed_official 85:e1a8e879a6a9 439 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
mbed_official 85:e1a8e879a6a9 440 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 441 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 442 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 443
mbed_official 85:e1a8e879a6a9 444 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
mbed_official 85:e1a8e879a6a9 445 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 446 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 447 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 448 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 449 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 450
mbed_official 85:e1a8e879a6a9 451 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
mbed_official 85:e1a8e879a6a9 452 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 453 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 454 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 455 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 456 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 457
mbed_official 85:e1a8e879a6a9 458 /* Register: CLOCK_INTENCLR */
mbed_official 85:e1a8e879a6a9 459 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 460
mbed_official 85:e1a8e879a6a9 461 /* Bit 4 : Disable interrupt on CTTO event. */
mbed_official 85:e1a8e879a6a9 462 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
mbed_official 85:e1a8e879a6a9 463 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
mbed_official 85:e1a8e879a6a9 464 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 465 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 466 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 467
mbed_official 85:e1a8e879a6a9 468 /* Bit 3 : Disable interrupt on DONE event. */
mbed_official 85:e1a8e879a6a9 469 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
mbed_official 85:e1a8e879a6a9 470 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
mbed_official 85:e1a8e879a6a9 471 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 472 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 473 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 474
mbed_official 85:e1a8e879a6a9 475 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
mbed_official 85:e1a8e879a6a9 476 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 477 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 478 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 479 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 480 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 481
mbed_official 85:e1a8e879a6a9 482 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
mbed_official 85:e1a8e879a6a9 483 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 484 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
mbed_official 85:e1a8e879a6a9 485 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 486 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 487 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 488
mbed_official 85:e1a8e879a6a9 489 /* Register: CLOCK_HFCLKSTAT */
mbed_official 85:e1a8e879a6a9 490 /* Description: High frequency clock status. */
mbed_official 85:e1a8e879a6a9 491
mbed_official 85:e1a8e879a6a9 492 /* Bit 16 : State for the HFCLK. */
mbed_official 85:e1a8e879a6a9 493 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
mbed_official 85:e1a8e879a6a9 494 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
mbed_official 85:e1a8e879a6a9 495 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
mbed_official 85:e1a8e879a6a9 496 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
mbed_official 85:e1a8e879a6a9 497
mbed_official 85:e1a8e879a6a9 498 /* Bit 0 : Active clock source for the HF clock. */
mbed_official 85:e1a8e879a6a9 499 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
mbed_official 85:e1a8e879a6a9 500 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
mbed_official 85:e1a8e879a6a9 501 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
mbed_official 85:e1a8e879a6a9 502 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
mbed_official 85:e1a8e879a6a9 503
mbed_official 85:e1a8e879a6a9 504 /* Register: CLOCK_LFCLKSTAT */
mbed_official 85:e1a8e879a6a9 505 /* Description: Low frequency clock status. */
mbed_official 85:e1a8e879a6a9 506
mbed_official 85:e1a8e879a6a9 507 /* Bit 16 : State for the LF clock. */
mbed_official 85:e1a8e879a6a9 508 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
mbed_official 85:e1a8e879a6a9 509 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
mbed_official 85:e1a8e879a6a9 510 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
mbed_official 85:e1a8e879a6a9 511 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
mbed_official 85:e1a8e879a6a9 512
mbed_official 85:e1a8e879a6a9 513 /* Bits 1..0 : Active clock source for the LF clock. */
mbed_official 85:e1a8e879a6a9 514 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
mbed_official 85:e1a8e879a6a9 515 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
mbed_official 85:e1a8e879a6a9 516 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 517 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 518 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 519
mbed_official 85:e1a8e879a6a9 520 /* Register: CLOCK_LFCLKSRC */
mbed_official 85:e1a8e879a6a9 521 /* Description: Clock source for the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 522
mbed_official 85:e1a8e879a6a9 523 /* Bits 1..0 : Clock source. */
mbed_official 85:e1a8e879a6a9 524 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
mbed_official 85:e1a8e879a6a9 525 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
mbed_official 85:e1a8e879a6a9 526 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
mbed_official 85:e1a8e879a6a9 527 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
mbed_official 85:e1a8e879a6a9 528 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
mbed_official 85:e1a8e879a6a9 529
mbed_official 85:e1a8e879a6a9 530 /* Register: CLOCK_CTIV */
mbed_official 85:e1a8e879a6a9 531 /* Description: Calibration timer interval. */
mbed_official 85:e1a8e879a6a9 532
mbed_official 85:e1a8e879a6a9 533 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
mbed_official 85:e1a8e879a6a9 534 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
mbed_official 85:e1a8e879a6a9 535 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
mbed_official 85:e1a8e879a6a9 536
mbed_official 85:e1a8e879a6a9 537 /* Register: CLOCK_XTALFREQ */
mbed_official 85:e1a8e879a6a9 538 /* Description: Crystal frequency. */
mbed_official 85:e1a8e879a6a9 539
mbed_official 85:e1a8e879a6a9 540 /* Bits 7..0 : External Xtal frequency selection. */
mbed_official 85:e1a8e879a6a9 541 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
mbed_official 85:e1a8e879a6a9 542 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
mbed_official 85:e1a8e879a6a9 543 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */
mbed_official 85:e1a8e879a6a9 544 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */
mbed_official 85:e1a8e879a6a9 545
mbed_official 85:e1a8e879a6a9 546
mbed_official 85:e1a8e879a6a9 547 /* Peripheral: COMP */
mbed_official 85:e1a8e879a6a9 548 /* Description: Comparator. */
mbed_official 85:e1a8e879a6a9 549
mbed_official 85:e1a8e879a6a9 550 /* Register: COMP_SHORTS */
mbed_official 85:e1a8e879a6a9 551 /* Description: Shortcut for the COMP. */
mbed_official 85:e1a8e879a6a9 552
mbed_official 85:e1a8e879a6a9 553 /* Bit 4 : Short-cut between CROSS event and STOP task. */
mbed_official 85:e1a8e879a6a9 554 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
mbed_official 85:e1a8e879a6a9 555 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
mbed_official 85:e1a8e879a6a9 556 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 557 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 558
mbed_official 85:e1a8e879a6a9 559 /* Bit 3 : Short-cut between UP event and STOP task. */
mbed_official 85:e1a8e879a6a9 560 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
mbed_official 85:e1a8e879a6a9 561 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
mbed_official 85:e1a8e879a6a9 562 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 563 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 564
mbed_official 85:e1a8e879a6a9 565 /* Bit 2 : Short-cut between DOWN event and STOP task. */
mbed_official 85:e1a8e879a6a9 566 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
mbed_official 85:e1a8e879a6a9 567 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
mbed_official 85:e1a8e879a6a9 568 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 569 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 570
mbed_official 85:e1a8e879a6a9 571 /* Bit 1 : Short-cut between RADY event and STOP task. */
mbed_official 85:e1a8e879a6a9 572 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
mbed_official 85:e1a8e879a6a9 573 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
mbed_official 85:e1a8e879a6a9 574 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 575 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 576
mbed_official 85:e1a8e879a6a9 577 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
mbed_official 85:e1a8e879a6a9 578 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
mbed_official 85:e1a8e879a6a9 579 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
mbed_official 85:e1a8e879a6a9 580 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 581 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 582
mbed_official 85:e1a8e879a6a9 583 /* Register: COMP_INTENSET */
mbed_official 85:e1a8e879a6a9 584 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 585
mbed_official 85:e1a8e879a6a9 586 /* Bit 3 : Enable interrupt on CROSS event. */
mbed_official 85:e1a8e879a6a9 587 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
mbed_official 85:e1a8e879a6a9 588 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
mbed_official 85:e1a8e879a6a9 589 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 590 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 591 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 592
mbed_official 85:e1a8e879a6a9 593 /* Bit 2 : Enable interrupt on UP event. */
mbed_official 85:e1a8e879a6a9 594 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
mbed_official 85:e1a8e879a6a9 595 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
mbed_official 85:e1a8e879a6a9 596 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 597 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 598 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 599
mbed_official 85:e1a8e879a6a9 600 /* Bit 1 : Enable interrupt on DOWN event. */
mbed_official 85:e1a8e879a6a9 601 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
mbed_official 85:e1a8e879a6a9 602 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
mbed_official 85:e1a8e879a6a9 603 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 604 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 605 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 606
mbed_official 85:e1a8e879a6a9 607 /* Bit 0 : Enable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 608 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 609 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 610 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 611 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 612 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 613
mbed_official 85:e1a8e879a6a9 614 /* Register: COMP_INTENCLR */
mbed_official 85:e1a8e879a6a9 615 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 616
mbed_official 85:e1a8e879a6a9 617 /* Bit 3 : Disable interrupt on CROSS event. */
mbed_official 85:e1a8e879a6a9 618 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
mbed_official 85:e1a8e879a6a9 619 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
mbed_official 85:e1a8e879a6a9 620 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 621 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 622 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 623
mbed_official 85:e1a8e879a6a9 624 /* Bit 2 : Disable interrupt on UP event. */
mbed_official 85:e1a8e879a6a9 625 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
mbed_official 85:e1a8e879a6a9 626 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
mbed_official 85:e1a8e879a6a9 627 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 628 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 629 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 630
mbed_official 85:e1a8e879a6a9 631 /* Bit 1 : Disable interrupt on DOWN event. */
mbed_official 85:e1a8e879a6a9 632 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
mbed_official 85:e1a8e879a6a9 633 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
mbed_official 85:e1a8e879a6a9 634 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 635 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 636 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 637
mbed_official 85:e1a8e879a6a9 638 /* Bit 0 : Disable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 639 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 640 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 641 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 642 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 643 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 644
mbed_official 85:e1a8e879a6a9 645 /* Register: COMP_RESULT */
mbed_official 85:e1a8e879a6a9 646 /* Description: Compare result. */
mbed_official 85:e1a8e879a6a9 647
mbed_official 85:e1a8e879a6a9 648 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
mbed_official 85:e1a8e879a6a9 649 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
mbed_official 85:e1a8e879a6a9 650 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
mbed_official 85:e1a8e879a6a9 651 #define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
mbed_official 85:e1a8e879a6a9 652 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
mbed_official 85:e1a8e879a6a9 653
mbed_official 85:e1a8e879a6a9 654 /* Register: COMP_ENABLE */
mbed_official 85:e1a8e879a6a9 655 /* Description: Enable the COMP. */
mbed_official 85:e1a8e879a6a9 656
mbed_official 85:e1a8e879a6a9 657 /* Bits 1..0 : Enable or disable COMP. */
mbed_official 85:e1a8e879a6a9 658 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 659 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 660 #define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */
mbed_official 85:e1a8e879a6a9 661 #define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */
mbed_official 85:e1a8e879a6a9 662
mbed_official 85:e1a8e879a6a9 663 /* Register: COMP_PSEL */
mbed_official 85:e1a8e879a6a9 664 /* Description: Input pin select. */
mbed_official 85:e1a8e879a6a9 665
mbed_official 85:e1a8e879a6a9 666 /* Bits 2..0 : Analog input pin select. */
mbed_official 85:e1a8e879a6a9 667 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
mbed_official 85:e1a8e879a6a9 668 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
mbed_official 85:e1a8e879a6a9 669 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
mbed_official 85:e1a8e879a6a9 670 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
mbed_official 85:e1a8e879a6a9 671 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
mbed_official 85:e1a8e879a6a9 672 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
mbed_official 85:e1a8e879a6a9 673 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
mbed_official 85:e1a8e879a6a9 674 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
mbed_official 85:e1a8e879a6a9 675 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
mbed_official 85:e1a8e879a6a9 676 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
mbed_official 85:e1a8e879a6a9 677
mbed_official 85:e1a8e879a6a9 678 /* Register: COMP_REFSEL */
mbed_official 85:e1a8e879a6a9 679 /* Description: Reference select. */
mbed_official 85:e1a8e879a6a9 680
mbed_official 85:e1a8e879a6a9 681 /* Bits 2..0 : Reference select. */
mbed_official 85:e1a8e879a6a9 682 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
mbed_official 85:e1a8e879a6a9 683 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
mbed_official 85:e1a8e879a6a9 684 #define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */
mbed_official 85:e1a8e879a6a9 685 #define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */
mbed_official 85:e1a8e879a6a9 686 #define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */
mbed_official 85:e1a8e879a6a9 687 #define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */
mbed_official 85:e1a8e879a6a9 688 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */
mbed_official 85:e1a8e879a6a9 689
mbed_official 85:e1a8e879a6a9 690 /* Register: COMP_EXTREFSEL */
mbed_official 85:e1a8e879a6a9 691 /* Description: External reference select. */
mbed_official 85:e1a8e879a6a9 692
mbed_official 85:e1a8e879a6a9 693 /* Bit 0 : External analog reference pin selection. */
mbed_official 85:e1a8e879a6a9 694 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 695 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 696 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
mbed_official 85:e1a8e879a6a9 697 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
mbed_official 85:e1a8e879a6a9 698
mbed_official 85:e1a8e879a6a9 699 /* Register: COMP_TH */
mbed_official 85:e1a8e879a6a9 700 /* Description: Threshold configuration for hysteresis unit. */
mbed_official 85:e1a8e879a6a9 701
mbed_official 85:e1a8e879a6a9 702 /* Bits 13..8 : VDOWN configuration. */
mbed_official 85:e1a8e879a6a9 703 #define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */
mbed_official 85:e1a8e879a6a9 704 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
mbed_official 85:e1a8e879a6a9 705
mbed_official 85:e1a8e879a6a9 706 /* Bits 5..0 : VUP configuration. */
mbed_official 85:e1a8e879a6a9 707 #define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */
mbed_official 85:e1a8e879a6a9 708 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
mbed_official 85:e1a8e879a6a9 709
mbed_official 85:e1a8e879a6a9 710 /* Register: COMP_MODE */
mbed_official 85:e1a8e879a6a9 711 /* Description: Mode configuration. */
mbed_official 85:e1a8e879a6a9 712
mbed_official 85:e1a8e879a6a9 713 /* Bit 8 : Main operation mode. */
mbed_official 85:e1a8e879a6a9 714 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
mbed_official 85:e1a8e879a6a9 715 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
mbed_official 85:e1a8e879a6a9 716 #define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */
mbed_official 85:e1a8e879a6a9 717 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */
mbed_official 85:e1a8e879a6a9 718
mbed_official 85:e1a8e879a6a9 719 /* Bits 1..0 : Speed and power mode. */
mbed_official 85:e1a8e879a6a9 720 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
mbed_official 85:e1a8e879a6a9 721 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
mbed_official 85:e1a8e879a6a9 722 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */
mbed_official 85:e1a8e879a6a9 723 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */
mbed_official 85:e1a8e879a6a9 724 #define COMP_MODE_SP_High (2UL) /*!< High speed mode. */
mbed_official 85:e1a8e879a6a9 725
mbed_official 85:e1a8e879a6a9 726 /* Register: COMP_POWER */
mbed_official 85:e1a8e879a6a9 727 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 728
mbed_official 85:e1a8e879a6a9 729 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 730 #define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 731 #define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 732 #define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 733 #define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 734
mbed_official 85:e1a8e879a6a9 735
mbed_official 85:e1a8e879a6a9 736 /* Peripheral: ECB */
mbed_official 85:e1a8e879a6a9 737 /* Description: AES ECB Mode Encryption. */
mbed_official 85:e1a8e879a6a9 738
mbed_official 85:e1a8e879a6a9 739 /* Register: ECB_INTENSET */
mbed_official 85:e1a8e879a6a9 740 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 741
mbed_official 85:e1a8e879a6a9 742 /* Bit 1 : Enable interrupt on ERRORECB event. */
mbed_official 85:e1a8e879a6a9 743 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
mbed_official 85:e1a8e879a6a9 744 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
mbed_official 85:e1a8e879a6a9 745 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 746 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 747 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 748
mbed_official 85:e1a8e879a6a9 749 /* Bit 0 : Enable interrupt on ENDECB event. */
mbed_official 85:e1a8e879a6a9 750 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
mbed_official 85:e1a8e879a6a9 751 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
mbed_official 85:e1a8e879a6a9 752 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 753 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 754 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 755
mbed_official 85:e1a8e879a6a9 756 /* Register: ECB_INTENCLR */
mbed_official 85:e1a8e879a6a9 757 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 758
mbed_official 85:e1a8e879a6a9 759 /* Bit 1 : Disable interrupt on ERRORECB event. */
mbed_official 85:e1a8e879a6a9 760 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
mbed_official 85:e1a8e879a6a9 761 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
mbed_official 85:e1a8e879a6a9 762 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 763 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 764 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 765
mbed_official 85:e1a8e879a6a9 766 /* Bit 0 : Disable interrupt on ENDECB event. */
mbed_official 85:e1a8e879a6a9 767 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
mbed_official 85:e1a8e879a6a9 768 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
mbed_official 85:e1a8e879a6a9 769 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 770 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 771 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 772
mbed_official 85:e1a8e879a6a9 773 /* Register: ECB_POWER */
mbed_official 85:e1a8e879a6a9 774 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 775
mbed_official 85:e1a8e879a6a9 776 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 777 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 778 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 779 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 780 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 781
mbed_official 85:e1a8e879a6a9 782
mbed_official 85:e1a8e879a6a9 783 /* Peripheral: FICR */
mbed_official 85:e1a8e879a6a9 784 /* Description: Factory Information Configuration. */
mbed_official 85:e1a8e879a6a9 785
mbed_official 85:e1a8e879a6a9 786 /* Register: FICR_PPFC */
mbed_official 85:e1a8e879a6a9 787 /* Description: Pre-programmed factory code present. */
mbed_official 85:e1a8e879a6a9 788
mbed_official 85:e1a8e879a6a9 789 /* Bits 7..0 : Pre-programmed factory code present. */
mbed_official 85:e1a8e879a6a9 790 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
mbed_official 85:e1a8e879a6a9 791 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
mbed_official 85:e1a8e879a6a9 792 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
mbed_official 85:e1a8e879a6a9 793 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
mbed_official 85:e1a8e879a6a9 794
mbed_official 85:e1a8e879a6a9 795 /* Register: FICR_CONFIGID */
mbed_official 85:e1a8e879a6a9 796 /* Description: Configuration identifier. */
mbed_official 85:e1a8e879a6a9 797
mbed_official 85:e1a8e879a6a9 798 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
mbed_official 85:e1a8e879a6a9 799 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
mbed_official 85:e1a8e879a6a9 800 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
mbed_official 85:e1a8e879a6a9 801
mbed_official 85:e1a8e879a6a9 802 /* Bits 15..0 : Hardware Identification Number. */
mbed_official 85:e1a8e879a6a9 803 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
mbed_official 85:e1a8e879a6a9 804 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
mbed_official 85:e1a8e879a6a9 805
mbed_official 85:e1a8e879a6a9 806 /* Register: FICR_DEVICEADDRTYPE */
mbed_official 85:e1a8e879a6a9 807 /* Description: Device address type. */
mbed_official 85:e1a8e879a6a9 808
mbed_official 85:e1a8e879a6a9 809 /* Bit 0 : Device address type. */
mbed_official 85:e1a8e879a6a9 810 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
mbed_official 85:e1a8e879a6a9 811 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
mbed_official 85:e1a8e879a6a9 812 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
mbed_official 85:e1a8e879a6a9 813 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
mbed_official 85:e1a8e879a6a9 814
mbed_official 85:e1a8e879a6a9 815 /* Register: FICR_OVERRIDEEN */
mbed_official 85:e1a8e879a6a9 816 /* Description: Radio calibration override enable. */
mbed_official 85:e1a8e879a6a9 817
mbed_official 85:e1a8e879a6a9 818 /* Bit 3 : Override default values for BLE_1Mbit mode. */
mbed_official 85:e1a8e879a6a9 819 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
mbed_official 85:e1a8e879a6a9 820 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
mbed_official 85:e1a8e879a6a9 821 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
mbed_official 85:e1a8e879a6a9 822 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
mbed_official 85:e1a8e879a6a9 823
mbed_official 85:e1a8e879a6a9 824
mbed_official 85:e1a8e879a6a9 825 /* Peripheral: GPIO */
mbed_official 85:e1a8e879a6a9 826 /* Description: General purpose input and output. */
mbed_official 85:e1a8e879a6a9 827
mbed_official 85:e1a8e879a6a9 828 /* Register: GPIO_OUT */
mbed_official 85:e1a8e879a6a9 829 /* Description: Write GPIO port. */
mbed_official 85:e1a8e879a6a9 830
mbed_official 85:e1a8e879a6a9 831 /* Bit 31 : Pin 31. */
mbed_official 85:e1a8e879a6a9 832 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 833 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 834 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 835 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 836
mbed_official 85:e1a8e879a6a9 837 /* Bit 30 : Pin 30. */
mbed_official 85:e1a8e879a6a9 838 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 839 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 840 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 841 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 842
mbed_official 85:e1a8e879a6a9 843 /* Bit 29 : Pin 29. */
mbed_official 85:e1a8e879a6a9 844 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 845 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 846 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 847 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 848
mbed_official 85:e1a8e879a6a9 849 /* Bit 28 : Pin 28. */
mbed_official 85:e1a8e879a6a9 850 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 851 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 852 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 853 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 854
mbed_official 85:e1a8e879a6a9 855 /* Bit 27 : Pin 27. */
mbed_official 85:e1a8e879a6a9 856 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 857 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 858 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 859 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 860
mbed_official 85:e1a8e879a6a9 861 /* Bit 26 : Pin 26. */
mbed_official 85:e1a8e879a6a9 862 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 863 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 864 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 865 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 866
mbed_official 85:e1a8e879a6a9 867 /* Bit 25 : Pin 25. */
mbed_official 85:e1a8e879a6a9 868 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 869 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 870 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 871 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 872
mbed_official 85:e1a8e879a6a9 873 /* Bit 24 : Pin 24. */
mbed_official 85:e1a8e879a6a9 874 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 875 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 876 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 877 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 878
mbed_official 85:e1a8e879a6a9 879 /* Bit 23 : Pin 23. */
mbed_official 85:e1a8e879a6a9 880 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 881 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 882 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 883 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 884
mbed_official 85:e1a8e879a6a9 885 /* Bit 22 : Pin 22. */
mbed_official 85:e1a8e879a6a9 886 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 887 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 888 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 889 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 890
mbed_official 85:e1a8e879a6a9 891 /* Bit 21 : Pin 21. */
mbed_official 85:e1a8e879a6a9 892 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 893 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 894 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 895 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 896
mbed_official 85:e1a8e879a6a9 897 /* Bit 20 : Pin 20. */
mbed_official 85:e1a8e879a6a9 898 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 899 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 900 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 901 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 902
mbed_official 85:e1a8e879a6a9 903 /* Bit 19 : Pin 19. */
mbed_official 85:e1a8e879a6a9 904 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 905 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 906 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 907 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 908
mbed_official 85:e1a8e879a6a9 909 /* Bit 18 : Pin 18. */
mbed_official 85:e1a8e879a6a9 910 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 911 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 912 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 913 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 914
mbed_official 85:e1a8e879a6a9 915 /* Bit 17 : Pin 17. */
mbed_official 85:e1a8e879a6a9 916 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 917 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 918 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 919 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 920
mbed_official 85:e1a8e879a6a9 921 /* Bit 16 : Pin 16. */
mbed_official 85:e1a8e879a6a9 922 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 923 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 924 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 925 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 926
mbed_official 85:e1a8e879a6a9 927 /* Bit 15 : Pin 15. */
mbed_official 85:e1a8e879a6a9 928 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 929 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 930 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 931 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 932
mbed_official 85:e1a8e879a6a9 933 /* Bit 14 : Pin 14. */
mbed_official 85:e1a8e879a6a9 934 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 935 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 936 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 937 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 938
mbed_official 85:e1a8e879a6a9 939 /* Bit 13 : Pin 13. */
mbed_official 85:e1a8e879a6a9 940 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 941 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 942 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 943 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 944
mbed_official 85:e1a8e879a6a9 945 /* Bit 12 : Pin 12. */
mbed_official 85:e1a8e879a6a9 946 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 947 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 948 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 949 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 950
mbed_official 85:e1a8e879a6a9 951 /* Bit 11 : Pin 11. */
mbed_official 85:e1a8e879a6a9 952 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 953 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 954 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 955 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 956
mbed_official 85:e1a8e879a6a9 957 /* Bit 10 : Pin 10. */
mbed_official 85:e1a8e879a6a9 958 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 959 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 960 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 961 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 962
mbed_official 85:e1a8e879a6a9 963 /* Bit 9 : Pin 9. */
mbed_official 85:e1a8e879a6a9 964 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 965 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 966 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 967 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 968
mbed_official 85:e1a8e879a6a9 969 /* Bit 8 : Pin 8. */
mbed_official 85:e1a8e879a6a9 970 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 971 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 972 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 973 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 974
mbed_official 85:e1a8e879a6a9 975 /* Bit 7 : Pin 7. */
mbed_official 85:e1a8e879a6a9 976 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 977 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 978 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 979 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 980
mbed_official 85:e1a8e879a6a9 981 /* Bit 6 : Pin 6. */
mbed_official 85:e1a8e879a6a9 982 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 983 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 984 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 985 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 986
mbed_official 85:e1a8e879a6a9 987 /* Bit 5 : Pin 5. */
mbed_official 85:e1a8e879a6a9 988 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 989 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 990 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 991 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 992
mbed_official 85:e1a8e879a6a9 993 /* Bit 4 : Pin 4. */
mbed_official 85:e1a8e879a6a9 994 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 995 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 996 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 997 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 998
mbed_official 85:e1a8e879a6a9 999 /* Bit 3 : Pin 3. */
mbed_official 85:e1a8e879a6a9 1000 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1001 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1002 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1003 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1004
mbed_official 85:e1a8e879a6a9 1005 /* Bit 2 : Pin 2. */
mbed_official 85:e1a8e879a6a9 1006 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1007 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1008 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1009 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1010
mbed_official 85:e1a8e879a6a9 1011 /* Bit 1 : Pin 1. */
mbed_official 85:e1a8e879a6a9 1012 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1013 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1014 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1015 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1016
mbed_official 85:e1a8e879a6a9 1017 /* Bit 0 : Pin 0. */
mbed_official 85:e1a8e879a6a9 1018 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1019 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1020 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1021 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1022
mbed_official 85:e1a8e879a6a9 1023 /* Register: GPIO_OUTSET */
mbed_official 85:e1a8e879a6a9 1024 /* Description: Set individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1025
mbed_official 85:e1a8e879a6a9 1026 /* Bit 31 : Pin 31. */
mbed_official 85:e1a8e879a6a9 1027 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1028 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1029 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1030 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1031 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1032
mbed_official 85:e1a8e879a6a9 1033 /* Bit 30 : Pin 30. */
mbed_official 85:e1a8e879a6a9 1034 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1035 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1036 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1037 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1038 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1039
mbed_official 85:e1a8e879a6a9 1040 /* Bit 29 : Pin 29. */
mbed_official 85:e1a8e879a6a9 1041 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1042 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1043 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1044 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1045 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1046
mbed_official 85:e1a8e879a6a9 1047 /* Bit 28 : Pin 28. */
mbed_official 85:e1a8e879a6a9 1048 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1049 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1050 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1051 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1052 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1053
mbed_official 85:e1a8e879a6a9 1054 /* Bit 27 : Pin 27. */
mbed_official 85:e1a8e879a6a9 1055 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1056 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1057 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1058 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1059 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1060
mbed_official 85:e1a8e879a6a9 1061 /* Bit 26 : Pin 26. */
mbed_official 85:e1a8e879a6a9 1062 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1063 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1064 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1065 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1066 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1067
mbed_official 85:e1a8e879a6a9 1068 /* Bit 25 : Pin 25. */
mbed_official 85:e1a8e879a6a9 1069 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1070 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1071 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1072 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1073 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1074
mbed_official 85:e1a8e879a6a9 1075 /* Bit 24 : Pin 24. */
mbed_official 85:e1a8e879a6a9 1076 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1077 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1078 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1079 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1080 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1081
mbed_official 85:e1a8e879a6a9 1082 /* Bit 23 : Pin 23. */
mbed_official 85:e1a8e879a6a9 1083 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1084 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1085 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1086 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1087 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1088
mbed_official 85:e1a8e879a6a9 1089 /* Bit 22 : Pin 22. */
mbed_official 85:e1a8e879a6a9 1090 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1091 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1092 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1093 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1094 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1095
mbed_official 85:e1a8e879a6a9 1096 /* Bit 21 : Pin 21. */
mbed_official 85:e1a8e879a6a9 1097 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1098 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1099 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1100 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1101 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1102
mbed_official 85:e1a8e879a6a9 1103 /* Bit 20 : Pin 20. */
mbed_official 85:e1a8e879a6a9 1104 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1105 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1106 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1107 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1108 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1109
mbed_official 85:e1a8e879a6a9 1110 /* Bit 19 : Pin 19. */
mbed_official 85:e1a8e879a6a9 1111 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1112 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1113 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1114 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1115 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1116
mbed_official 85:e1a8e879a6a9 1117 /* Bit 18 : Pin 18. */
mbed_official 85:e1a8e879a6a9 1118 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1119 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1120 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1121 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1122 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1123
mbed_official 85:e1a8e879a6a9 1124 /* Bit 17 : Pin 17. */
mbed_official 85:e1a8e879a6a9 1125 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1126 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1127 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1128 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1129 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1130
mbed_official 85:e1a8e879a6a9 1131 /* Bit 16 : Pin 16. */
mbed_official 85:e1a8e879a6a9 1132 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1133 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1134 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1135 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1136 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1137
mbed_official 85:e1a8e879a6a9 1138 /* Bit 15 : Pin 15. */
mbed_official 85:e1a8e879a6a9 1139 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1140 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1141 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1142 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1143 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1144
mbed_official 85:e1a8e879a6a9 1145 /* Bit 14 : Pin 14. */
mbed_official 85:e1a8e879a6a9 1146 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1147 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1148 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1149 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1150 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1151
mbed_official 85:e1a8e879a6a9 1152 /* Bit 13 : Pin 13. */
mbed_official 85:e1a8e879a6a9 1153 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1154 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1155 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1156 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1157 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1158
mbed_official 85:e1a8e879a6a9 1159 /* Bit 12 : Pin 12. */
mbed_official 85:e1a8e879a6a9 1160 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1161 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1162 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1163 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1164 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1165
mbed_official 85:e1a8e879a6a9 1166 /* Bit 11 : Pin 11. */
mbed_official 85:e1a8e879a6a9 1167 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1168 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1169 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1170 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1171 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1172
mbed_official 85:e1a8e879a6a9 1173 /* Bit 10 : Pin 10. */
mbed_official 85:e1a8e879a6a9 1174 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1175 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1176 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1177 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1178 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1179
mbed_official 85:e1a8e879a6a9 1180 /* Bit 9 : Pin 9. */
mbed_official 85:e1a8e879a6a9 1181 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1182 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1183 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1184 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1185 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1186
mbed_official 85:e1a8e879a6a9 1187 /* Bit 8 : Pin 8. */
mbed_official 85:e1a8e879a6a9 1188 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1189 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1190 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1191 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1192 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1193
mbed_official 85:e1a8e879a6a9 1194 /* Bit 7 : Pin 7. */
mbed_official 85:e1a8e879a6a9 1195 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1196 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1197 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1198 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1199 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1200
mbed_official 85:e1a8e879a6a9 1201 /* Bit 6 : Pin 6. */
mbed_official 85:e1a8e879a6a9 1202 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1203 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1204 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1205 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1206 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1207
mbed_official 85:e1a8e879a6a9 1208 /* Bit 5 : Pin 5. */
mbed_official 85:e1a8e879a6a9 1209 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1210 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1211 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1212 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1213 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1214
mbed_official 85:e1a8e879a6a9 1215 /* Bit 4 : Pin 4. */
mbed_official 85:e1a8e879a6a9 1216 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1217 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1218 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1219 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1220 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1221
mbed_official 85:e1a8e879a6a9 1222 /* Bit 3 : Pin 3. */
mbed_official 85:e1a8e879a6a9 1223 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1224 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1225 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1226 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1227 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1228
mbed_official 85:e1a8e879a6a9 1229 /* Bit 2 : Pin 2. */
mbed_official 85:e1a8e879a6a9 1230 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1231 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1232 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1233 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1234 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1235
mbed_official 85:e1a8e879a6a9 1236 /* Bit 1 : Pin 1. */
mbed_official 85:e1a8e879a6a9 1237 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1238 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1239 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1240 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1241 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1242
mbed_official 85:e1a8e879a6a9 1243 /* Bit 0 : Pin 0. */
mbed_official 85:e1a8e879a6a9 1244 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1245 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1246 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1247 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1248 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
mbed_official 85:e1a8e879a6a9 1249
mbed_official 85:e1a8e879a6a9 1250 /* Register: GPIO_OUTCLR */
mbed_official 85:e1a8e879a6a9 1251 /* Description: Clear individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1252
mbed_official 85:e1a8e879a6a9 1253 /* Bit 31 : Pin 31. */
mbed_official 85:e1a8e879a6a9 1254 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1255 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1256 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1257 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1258 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1259
mbed_official 85:e1a8e879a6a9 1260 /* Bit 30 : Pin 30. */
mbed_official 85:e1a8e879a6a9 1261 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1262 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1263 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1264 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1265 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1266
mbed_official 85:e1a8e879a6a9 1267 /* Bit 29 : Pin 29. */
mbed_official 85:e1a8e879a6a9 1268 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1269 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1270 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1271 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1272 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1273
mbed_official 85:e1a8e879a6a9 1274 /* Bit 28 : Pin 28. */
mbed_official 85:e1a8e879a6a9 1275 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1276 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1277 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1278 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1279 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1280
mbed_official 85:e1a8e879a6a9 1281 /* Bit 27 : Pin 27. */
mbed_official 85:e1a8e879a6a9 1282 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1283 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1284 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1285 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1286 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1287
mbed_official 85:e1a8e879a6a9 1288 /* Bit 26 : Pin 26. */
mbed_official 85:e1a8e879a6a9 1289 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1290 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1291 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1292 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1293 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1294
mbed_official 85:e1a8e879a6a9 1295 /* Bit 25 : Pin 25. */
mbed_official 85:e1a8e879a6a9 1296 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1297 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1298 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1299 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1300 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1301
mbed_official 85:e1a8e879a6a9 1302 /* Bit 24 : Pin 24. */
mbed_official 85:e1a8e879a6a9 1303 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1304 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1305 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1306 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1307 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1308
mbed_official 85:e1a8e879a6a9 1309 /* Bit 23 : Pin 23. */
mbed_official 85:e1a8e879a6a9 1310 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1311 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1312 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1313 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1314 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1315
mbed_official 85:e1a8e879a6a9 1316 /* Bit 22 : Pin 22. */
mbed_official 85:e1a8e879a6a9 1317 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1318 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1319 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1320 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1321 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1322
mbed_official 85:e1a8e879a6a9 1323 /* Bit 21 : Pin 21. */
mbed_official 85:e1a8e879a6a9 1324 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1325 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1326 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1327 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1328 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1329
mbed_official 85:e1a8e879a6a9 1330 /* Bit 20 : Pin 20. */
mbed_official 85:e1a8e879a6a9 1331 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1332 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1333 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1334 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1335 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1336
mbed_official 85:e1a8e879a6a9 1337 /* Bit 19 : Pin 19. */
mbed_official 85:e1a8e879a6a9 1338 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1339 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1340 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1341 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1342 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1343
mbed_official 85:e1a8e879a6a9 1344 /* Bit 18 : Pin 18. */
mbed_official 85:e1a8e879a6a9 1345 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1346 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1347 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1348 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1349 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1350
mbed_official 85:e1a8e879a6a9 1351 /* Bit 17 : Pin 17. */
mbed_official 85:e1a8e879a6a9 1352 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1353 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1354 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1355 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1356 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1357
mbed_official 85:e1a8e879a6a9 1358 /* Bit 16 : Pin 16. */
mbed_official 85:e1a8e879a6a9 1359 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1360 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1361 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1362 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1363 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1364
mbed_official 85:e1a8e879a6a9 1365 /* Bit 15 : Pin 15. */
mbed_official 85:e1a8e879a6a9 1366 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1367 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1368 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1369 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1370 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1371
mbed_official 85:e1a8e879a6a9 1372 /* Bit 14 : Pin 14. */
mbed_official 85:e1a8e879a6a9 1373 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1374 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1375 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1376 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1377 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1378
mbed_official 85:e1a8e879a6a9 1379 /* Bit 13 : Pin 13. */
mbed_official 85:e1a8e879a6a9 1380 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1381 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1382 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1383 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1384 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1385
mbed_official 85:e1a8e879a6a9 1386 /* Bit 12 : Pin 12. */
mbed_official 85:e1a8e879a6a9 1387 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1388 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1389 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1390 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1391 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1392
mbed_official 85:e1a8e879a6a9 1393 /* Bit 11 : Pin 11. */
mbed_official 85:e1a8e879a6a9 1394 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1395 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1396 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1397 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1398 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1399
mbed_official 85:e1a8e879a6a9 1400 /* Bit 10 : Pin 10. */
mbed_official 85:e1a8e879a6a9 1401 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1402 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1403 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1404 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1405 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1406
mbed_official 85:e1a8e879a6a9 1407 /* Bit 9 : Pin 9. */
mbed_official 85:e1a8e879a6a9 1408 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1409 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1410 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1411 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1412 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1413
mbed_official 85:e1a8e879a6a9 1414 /* Bit 8 : Pin 8. */
mbed_official 85:e1a8e879a6a9 1415 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1416 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1417 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1418 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1419 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1420
mbed_official 85:e1a8e879a6a9 1421 /* Bit 7 : Pin 7. */
mbed_official 85:e1a8e879a6a9 1422 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1423 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1424 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1425 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1426 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1427
mbed_official 85:e1a8e879a6a9 1428 /* Bit 6 : Pin 6. */
mbed_official 85:e1a8e879a6a9 1429 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1430 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1431 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1432 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1433 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1434
mbed_official 85:e1a8e879a6a9 1435 /* Bit 5 : Pin 5. */
mbed_official 85:e1a8e879a6a9 1436 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1437 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1438 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1439 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1440 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1441
mbed_official 85:e1a8e879a6a9 1442 /* Bit 4 : Pin 4. */
mbed_official 85:e1a8e879a6a9 1443 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1444 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1445 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1446 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1447 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1448
mbed_official 85:e1a8e879a6a9 1449 /* Bit 3 : Pin 3. */
mbed_official 85:e1a8e879a6a9 1450 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1451 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1452 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1453 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1454 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1455
mbed_official 85:e1a8e879a6a9 1456 /* Bit 2 : Pin 2. */
mbed_official 85:e1a8e879a6a9 1457 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1458 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1459 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1460 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1461 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1462
mbed_official 85:e1a8e879a6a9 1463 /* Bit 1 : Pin 1. */
mbed_official 85:e1a8e879a6a9 1464 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1465 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1466 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1467 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1468 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1469
mbed_official 85:e1a8e879a6a9 1470 /* Bit 0 : Pin 0. */
mbed_official 85:e1a8e879a6a9 1471 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1472 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1473 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
mbed_official 85:e1a8e879a6a9 1474 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
mbed_official 85:e1a8e879a6a9 1475 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
mbed_official 85:e1a8e879a6a9 1476
mbed_official 85:e1a8e879a6a9 1477 /* Register: GPIO_IN */
mbed_official 85:e1a8e879a6a9 1478 /* Description: Read GPIO port. */
mbed_official 85:e1a8e879a6a9 1479
mbed_official 85:e1a8e879a6a9 1480 /* Bit 31 : Pin 31. */
mbed_official 85:e1a8e879a6a9 1481 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1482 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1483 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1484 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1485
mbed_official 85:e1a8e879a6a9 1486 /* Bit 30 : Pin 30. */
mbed_official 85:e1a8e879a6a9 1487 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1488 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1489 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1490 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1491
mbed_official 85:e1a8e879a6a9 1492 /* Bit 29 : Pin 29. */
mbed_official 85:e1a8e879a6a9 1493 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1494 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1495 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1496 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1497
mbed_official 85:e1a8e879a6a9 1498 /* Bit 28 : Pin 28. */
mbed_official 85:e1a8e879a6a9 1499 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1500 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1501 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1502 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1503
mbed_official 85:e1a8e879a6a9 1504 /* Bit 27 : Pin 27. */
mbed_official 85:e1a8e879a6a9 1505 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1506 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1507 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1508 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1509
mbed_official 85:e1a8e879a6a9 1510 /* Bit 26 : Pin 26. */
mbed_official 85:e1a8e879a6a9 1511 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1512 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1513 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1514 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1515
mbed_official 85:e1a8e879a6a9 1516 /* Bit 25 : Pin 25. */
mbed_official 85:e1a8e879a6a9 1517 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1518 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1519 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1520 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1521
mbed_official 85:e1a8e879a6a9 1522 /* Bit 24 : Pin 24. */
mbed_official 85:e1a8e879a6a9 1523 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1524 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1525 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1526 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1527
mbed_official 85:e1a8e879a6a9 1528 /* Bit 23 : Pin 23. */
mbed_official 85:e1a8e879a6a9 1529 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1530 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1531 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1532 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1533
mbed_official 85:e1a8e879a6a9 1534 /* Bit 22 : Pin 22. */
mbed_official 85:e1a8e879a6a9 1535 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1536 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1537 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1538 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1539
mbed_official 85:e1a8e879a6a9 1540 /* Bit 21 : Pin 21. */
mbed_official 85:e1a8e879a6a9 1541 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1542 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1543 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1544 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1545
mbed_official 85:e1a8e879a6a9 1546 /* Bit 20 : Pin 20. */
mbed_official 85:e1a8e879a6a9 1547 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1548 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1549 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1550 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1551
mbed_official 85:e1a8e879a6a9 1552 /* Bit 19 : Pin 19. */
mbed_official 85:e1a8e879a6a9 1553 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1554 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1555 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1556 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1557
mbed_official 85:e1a8e879a6a9 1558 /* Bit 18 : Pin 18. */
mbed_official 85:e1a8e879a6a9 1559 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1560 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1561 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1562 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1563
mbed_official 85:e1a8e879a6a9 1564 /* Bit 17 : Pin 17. */
mbed_official 85:e1a8e879a6a9 1565 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1566 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1567 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1568 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1569
mbed_official 85:e1a8e879a6a9 1570 /* Bit 16 : Pin 16. */
mbed_official 85:e1a8e879a6a9 1571 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1572 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1573 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1574 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1575
mbed_official 85:e1a8e879a6a9 1576 /* Bit 15 : Pin 15. */
mbed_official 85:e1a8e879a6a9 1577 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1578 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1579 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1580 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1581
mbed_official 85:e1a8e879a6a9 1582 /* Bit 14 : Pin 14. */
mbed_official 85:e1a8e879a6a9 1583 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1584 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1585 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1586 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1587
mbed_official 85:e1a8e879a6a9 1588 /* Bit 13 : Pin 13. */
mbed_official 85:e1a8e879a6a9 1589 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1590 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1591 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1592 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1593
mbed_official 85:e1a8e879a6a9 1594 /* Bit 12 : Pin 12. */
mbed_official 85:e1a8e879a6a9 1595 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1596 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1597 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1598 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1599
mbed_official 85:e1a8e879a6a9 1600 /* Bit 11 : Pin 11. */
mbed_official 85:e1a8e879a6a9 1601 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1602 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1603 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1604 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1605
mbed_official 85:e1a8e879a6a9 1606 /* Bit 10 : Pin 10. */
mbed_official 85:e1a8e879a6a9 1607 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1608 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1609 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1610 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1611
mbed_official 85:e1a8e879a6a9 1612 /* Bit 9 : Pin 9. */
mbed_official 85:e1a8e879a6a9 1613 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1614 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1615 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1616 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1617
mbed_official 85:e1a8e879a6a9 1618 /* Bit 8 : Pin 8. */
mbed_official 85:e1a8e879a6a9 1619 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1620 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1621 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1622 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1623
mbed_official 85:e1a8e879a6a9 1624 /* Bit 7 : Pin 7. */
mbed_official 85:e1a8e879a6a9 1625 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1626 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1627 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1628 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1629
mbed_official 85:e1a8e879a6a9 1630 /* Bit 6 : Pin 6. */
mbed_official 85:e1a8e879a6a9 1631 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1632 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1633 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1634 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1635
mbed_official 85:e1a8e879a6a9 1636 /* Bit 5 : Pin 5. */
mbed_official 85:e1a8e879a6a9 1637 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1638 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1639 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1640 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1641
mbed_official 85:e1a8e879a6a9 1642 /* Bit 4 : Pin 4. */
mbed_official 85:e1a8e879a6a9 1643 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1644 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1645 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1646 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1647
mbed_official 85:e1a8e879a6a9 1648 /* Bit 3 : Pin 3. */
mbed_official 85:e1a8e879a6a9 1649 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1650 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1651 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1652 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1653
mbed_official 85:e1a8e879a6a9 1654 /* Bit 2 : Pin 2. */
mbed_official 85:e1a8e879a6a9 1655 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1656 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1657 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1658 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1659
mbed_official 85:e1a8e879a6a9 1660 /* Bit 1 : Pin 1. */
mbed_official 85:e1a8e879a6a9 1661 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1662 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1663 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1664 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1665
mbed_official 85:e1a8e879a6a9 1666 /* Bit 0 : Pin 0. */
mbed_official 85:e1a8e879a6a9 1667 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1668 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1669 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
mbed_official 85:e1a8e879a6a9 1670 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
mbed_official 85:e1a8e879a6a9 1671
mbed_official 85:e1a8e879a6a9 1672 /* Register: GPIO_DIR */
mbed_official 85:e1a8e879a6a9 1673 /* Description: Direction of GPIO pins. */
mbed_official 85:e1a8e879a6a9 1674
mbed_official 85:e1a8e879a6a9 1675 /* Bit 31 : Pin 31. */
mbed_official 85:e1a8e879a6a9 1676 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1677 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1678 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1679 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1680
mbed_official 85:e1a8e879a6a9 1681 /* Bit 30 : Pin 30. */
mbed_official 85:e1a8e879a6a9 1682 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1683 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1684 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1685 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1686
mbed_official 85:e1a8e879a6a9 1687 /* Bit 29 : Pin 29. */
mbed_official 85:e1a8e879a6a9 1688 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1689 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1690 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1691 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1692
mbed_official 85:e1a8e879a6a9 1693 /* Bit 28 : Pin 28. */
mbed_official 85:e1a8e879a6a9 1694 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1695 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1696 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1697 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1698
mbed_official 85:e1a8e879a6a9 1699 /* Bit 27 : Pin 27. */
mbed_official 85:e1a8e879a6a9 1700 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1701 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1702 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1703 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1704
mbed_official 85:e1a8e879a6a9 1705 /* Bit 26 : Pin 26. */
mbed_official 85:e1a8e879a6a9 1706 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1707 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1708 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1709 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1710
mbed_official 85:e1a8e879a6a9 1711 /* Bit 25 : Pin 25. */
mbed_official 85:e1a8e879a6a9 1712 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1713 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1714 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1715 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1716
mbed_official 85:e1a8e879a6a9 1717 /* Bit 24 : Pin 24. */
mbed_official 85:e1a8e879a6a9 1718 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1719 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1720 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1721 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1722
mbed_official 85:e1a8e879a6a9 1723 /* Bit 23 : Pin 23. */
mbed_official 85:e1a8e879a6a9 1724 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1725 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1726 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1727 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1728
mbed_official 85:e1a8e879a6a9 1729 /* Bit 22 : Pin 22. */
mbed_official 85:e1a8e879a6a9 1730 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1731 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1732 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1733 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1734
mbed_official 85:e1a8e879a6a9 1735 /* Bit 21 : Pin 21. */
mbed_official 85:e1a8e879a6a9 1736 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1737 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1738 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1739 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1740
mbed_official 85:e1a8e879a6a9 1741 /* Bit 20 : Pin 20. */
mbed_official 85:e1a8e879a6a9 1742 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1743 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1744 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1745 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1746
mbed_official 85:e1a8e879a6a9 1747 /* Bit 19 : Pin 19. */
mbed_official 85:e1a8e879a6a9 1748 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1749 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1750 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1751 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1752
mbed_official 85:e1a8e879a6a9 1753 /* Bit 18 : Pin 18. */
mbed_official 85:e1a8e879a6a9 1754 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1755 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1756 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1757 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1758
mbed_official 85:e1a8e879a6a9 1759 /* Bit 17 : Pin 17. */
mbed_official 85:e1a8e879a6a9 1760 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1761 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1762 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1763 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1764
mbed_official 85:e1a8e879a6a9 1765 /* Bit 16 : Pin 16. */
mbed_official 85:e1a8e879a6a9 1766 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1767 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1768 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1769 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1770
mbed_official 85:e1a8e879a6a9 1771 /* Bit 15 : Pin 15. */
mbed_official 85:e1a8e879a6a9 1772 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1773 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1774 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1775 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1776
mbed_official 85:e1a8e879a6a9 1777 /* Bit 14 : Pin 14. */
mbed_official 85:e1a8e879a6a9 1778 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1779 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1780 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1781 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1782
mbed_official 85:e1a8e879a6a9 1783 /* Bit 13 : Pin 13. */
mbed_official 85:e1a8e879a6a9 1784 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1785 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1786 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1787 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1788
mbed_official 85:e1a8e879a6a9 1789 /* Bit 12 : Pin 12. */
mbed_official 85:e1a8e879a6a9 1790 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1791 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 1792 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1793 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1794
mbed_official 85:e1a8e879a6a9 1795 /* Bit 11 : Pin 11. */
mbed_official 85:e1a8e879a6a9 1796 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1797 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 1798 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1799 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1800
mbed_official 85:e1a8e879a6a9 1801 /* Bit 10 : Pin 10. */
mbed_official 85:e1a8e879a6a9 1802 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1803 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 1804 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1805 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1806
mbed_official 85:e1a8e879a6a9 1807 /* Bit 9 : Pin 9. */
mbed_official 85:e1a8e879a6a9 1808 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1809 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 1810 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1811 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1812
mbed_official 85:e1a8e879a6a9 1813 /* Bit 8 : Pin 8. */
mbed_official 85:e1a8e879a6a9 1814 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1815 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 1816 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1817 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1818
mbed_official 85:e1a8e879a6a9 1819 /* Bit 7 : Pin 7. */
mbed_official 85:e1a8e879a6a9 1820 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1821 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 1822 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1823 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1824
mbed_official 85:e1a8e879a6a9 1825 /* Bit 6 : Pin 6. */
mbed_official 85:e1a8e879a6a9 1826 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1827 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 1828 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1829 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1830
mbed_official 85:e1a8e879a6a9 1831 /* Bit 5 : Pin 5. */
mbed_official 85:e1a8e879a6a9 1832 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1833 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 1834 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1835 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1836
mbed_official 85:e1a8e879a6a9 1837 /* Bit 4 : Pin 4. */
mbed_official 85:e1a8e879a6a9 1838 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1839 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 1840 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1841 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1842
mbed_official 85:e1a8e879a6a9 1843 /* Bit 3 : Pin 3. */
mbed_official 85:e1a8e879a6a9 1844 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1845 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 1846 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1847 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1848
mbed_official 85:e1a8e879a6a9 1849 /* Bit 2 : Pin 2. */
mbed_official 85:e1a8e879a6a9 1850 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1851 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 1852 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1853 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1854
mbed_official 85:e1a8e879a6a9 1855 /* Bit 1 : Pin 1. */
mbed_official 85:e1a8e879a6a9 1856 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1857 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 1858 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1859 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1860
mbed_official 85:e1a8e879a6a9 1861 /* Bit 0 : Pin 0. */
mbed_official 85:e1a8e879a6a9 1862 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1863 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 1864 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1865 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1866
mbed_official 85:e1a8e879a6a9 1867 /* Register: GPIO_DIRSET */
mbed_official 85:e1a8e879a6a9 1868 /* Description: DIR set register. */
mbed_official 85:e1a8e879a6a9 1869
mbed_official 85:e1a8e879a6a9 1870 /* Bit 31 : Set as output pin 31. */
mbed_official 85:e1a8e879a6a9 1871 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1872 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 1873 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1874 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1875 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1876
mbed_official 85:e1a8e879a6a9 1877 /* Bit 30 : Set as output pin 30. */
mbed_official 85:e1a8e879a6a9 1878 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1879 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 1880 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1881 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1882 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1883
mbed_official 85:e1a8e879a6a9 1884 /* Bit 29 : Set as output pin 29. */
mbed_official 85:e1a8e879a6a9 1885 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1886 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 1887 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1888 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1889 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1890
mbed_official 85:e1a8e879a6a9 1891 /* Bit 28 : Set as output pin 28. */
mbed_official 85:e1a8e879a6a9 1892 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1893 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 1894 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1895 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1896 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1897
mbed_official 85:e1a8e879a6a9 1898 /* Bit 27 : Set as output pin 27. */
mbed_official 85:e1a8e879a6a9 1899 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1900 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 1901 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1902 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1903 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1904
mbed_official 85:e1a8e879a6a9 1905 /* Bit 26 : Set as output pin 26. */
mbed_official 85:e1a8e879a6a9 1906 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1907 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 1908 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1909 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1910 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1911
mbed_official 85:e1a8e879a6a9 1912 /* Bit 25 : Set as output pin 25. */
mbed_official 85:e1a8e879a6a9 1913 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1914 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 1915 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1916 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1917 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1918
mbed_official 85:e1a8e879a6a9 1919 /* Bit 24 : Set as output pin 24. */
mbed_official 85:e1a8e879a6a9 1920 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1921 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 1922 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1923 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1924 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1925
mbed_official 85:e1a8e879a6a9 1926 /* Bit 23 : Set as output pin 23. */
mbed_official 85:e1a8e879a6a9 1927 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1928 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 1929 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1930 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1931 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1932
mbed_official 85:e1a8e879a6a9 1933 /* Bit 22 : Set as output pin 22. */
mbed_official 85:e1a8e879a6a9 1934 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1935 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 1936 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1937 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1938 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1939
mbed_official 85:e1a8e879a6a9 1940 /* Bit 21 : Set as output pin 21. */
mbed_official 85:e1a8e879a6a9 1941 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1942 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 1943 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1944 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1945 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1946
mbed_official 85:e1a8e879a6a9 1947 /* Bit 20 : Set as output pin 20. */
mbed_official 85:e1a8e879a6a9 1948 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1949 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 1950 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1951 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1952 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1953
mbed_official 85:e1a8e879a6a9 1954 /* Bit 19 : Set as output pin 19. */
mbed_official 85:e1a8e879a6a9 1955 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1956 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 1957 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1958 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1959 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1960
mbed_official 85:e1a8e879a6a9 1961 /* Bit 18 : Set as output pin 18. */
mbed_official 85:e1a8e879a6a9 1962 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1963 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 1964 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1965 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1966 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1967
mbed_official 85:e1a8e879a6a9 1968 /* Bit 17 : Set as output pin 17. */
mbed_official 85:e1a8e879a6a9 1969 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1970 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 1971 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1972 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1973 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1974
mbed_official 85:e1a8e879a6a9 1975 /* Bit 16 : Set as output pin 16. */
mbed_official 85:e1a8e879a6a9 1976 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1977 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 1978 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1979 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1980 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1981
mbed_official 85:e1a8e879a6a9 1982 /* Bit 15 : Set as output pin 15. */
mbed_official 85:e1a8e879a6a9 1983 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1984 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 1985 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1986 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1987 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1988
mbed_official 85:e1a8e879a6a9 1989 /* Bit 14 : Set as output pin 14. */
mbed_official 85:e1a8e879a6a9 1990 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1991 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 1992 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 1993 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 1994 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 1995
mbed_official 85:e1a8e879a6a9 1996 /* Bit 13 : Set as output pin 13. */
mbed_official 85:e1a8e879a6a9 1997 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1998 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 1999 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2000 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2001 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2002
mbed_official 85:e1a8e879a6a9 2003 /* Bit 12 : Set as output pin 12. */
mbed_official 85:e1a8e879a6a9 2004 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 2005 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 2006 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2007 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2008 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2009
mbed_official 85:e1a8e879a6a9 2010 /* Bit 11 : Set as output pin 11. */
mbed_official 85:e1a8e879a6a9 2011 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 2012 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 2013 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2014 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2015 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2016
mbed_official 85:e1a8e879a6a9 2017 /* Bit 10 : Set as output pin 10. */
mbed_official 85:e1a8e879a6a9 2018 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 2019 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 2020 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2021 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2022 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2023
mbed_official 85:e1a8e879a6a9 2024 /* Bit 9 : Set as output pin 9. */
mbed_official 85:e1a8e879a6a9 2025 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 2026 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 2027 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2028 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2029 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2030
mbed_official 85:e1a8e879a6a9 2031 /* Bit 8 : Set as output pin 8. */
mbed_official 85:e1a8e879a6a9 2032 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 2033 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 2034 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2035 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2036 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2037
mbed_official 85:e1a8e879a6a9 2038 /* Bit 7 : Set as output pin 7. */
mbed_official 85:e1a8e879a6a9 2039 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 2040 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 2041 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2042 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2043 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2044
mbed_official 85:e1a8e879a6a9 2045 /* Bit 6 : Set as output pin 6. */
mbed_official 85:e1a8e879a6a9 2046 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 2047 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 2048 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2049 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2050 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2051
mbed_official 85:e1a8e879a6a9 2052 /* Bit 5 : Set as output pin 5. */
mbed_official 85:e1a8e879a6a9 2053 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 2054 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 2055 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2056 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2057 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2058
mbed_official 85:e1a8e879a6a9 2059 /* Bit 4 : Set as output pin 4. */
mbed_official 85:e1a8e879a6a9 2060 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 2061 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 2062 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2063 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2064 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2065
mbed_official 85:e1a8e879a6a9 2066 /* Bit 3 : Set as output pin 3. */
mbed_official 85:e1a8e879a6a9 2067 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 2068 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 2069 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2070 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2071 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2072
mbed_official 85:e1a8e879a6a9 2073 /* Bit 2 : Set as output pin 2. */
mbed_official 85:e1a8e879a6a9 2074 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 2075 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 2076 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2077 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2078 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2079
mbed_official 85:e1a8e879a6a9 2080 /* Bit 1 : Set as output pin 1. */
mbed_official 85:e1a8e879a6a9 2081 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 2082 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 2083 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2084 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2085 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2086
mbed_official 85:e1a8e879a6a9 2087 /* Bit 0 : Set as output pin 0. */
mbed_official 85:e1a8e879a6a9 2088 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 2089 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 2090 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2091 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2092 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
mbed_official 85:e1a8e879a6a9 2093
mbed_official 85:e1a8e879a6a9 2094 /* Register: GPIO_DIRCLR */
mbed_official 85:e1a8e879a6a9 2095 /* Description: DIR clear register. */
mbed_official 85:e1a8e879a6a9 2096
mbed_official 85:e1a8e879a6a9 2097 /* Bit 31 : Set as input pin 31. */
mbed_official 85:e1a8e879a6a9 2098 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
mbed_official 85:e1a8e879a6a9 2099 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
mbed_official 85:e1a8e879a6a9 2100 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2101 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2102 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2103
mbed_official 85:e1a8e879a6a9 2104 /* Bit 30 : Set as input pin 30. */
mbed_official 85:e1a8e879a6a9 2105 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
mbed_official 85:e1a8e879a6a9 2106 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
mbed_official 85:e1a8e879a6a9 2107 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2108 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2109 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2110
mbed_official 85:e1a8e879a6a9 2111 /* Bit 29 : Set as input pin 29. */
mbed_official 85:e1a8e879a6a9 2112 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
mbed_official 85:e1a8e879a6a9 2113 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
mbed_official 85:e1a8e879a6a9 2114 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2115 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2116 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2117
mbed_official 85:e1a8e879a6a9 2118 /* Bit 28 : Set as input pin 28. */
mbed_official 85:e1a8e879a6a9 2119 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
mbed_official 85:e1a8e879a6a9 2120 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
mbed_official 85:e1a8e879a6a9 2121 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2122 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2123 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2124
mbed_official 85:e1a8e879a6a9 2125 /* Bit 27 : Set as input pin 27. */
mbed_official 85:e1a8e879a6a9 2126 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
mbed_official 85:e1a8e879a6a9 2127 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
mbed_official 85:e1a8e879a6a9 2128 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2129 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2130 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2131
mbed_official 85:e1a8e879a6a9 2132 /* Bit 26 : Set as input pin 26. */
mbed_official 85:e1a8e879a6a9 2133 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
mbed_official 85:e1a8e879a6a9 2134 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
mbed_official 85:e1a8e879a6a9 2135 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2136 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2137 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2138
mbed_official 85:e1a8e879a6a9 2139 /* Bit 25 : Set as input pin 25. */
mbed_official 85:e1a8e879a6a9 2140 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
mbed_official 85:e1a8e879a6a9 2141 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
mbed_official 85:e1a8e879a6a9 2142 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2143 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2144 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2145
mbed_official 85:e1a8e879a6a9 2146 /* Bit 24 : Set as input pin 24. */
mbed_official 85:e1a8e879a6a9 2147 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
mbed_official 85:e1a8e879a6a9 2148 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
mbed_official 85:e1a8e879a6a9 2149 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2150 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2151 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2152
mbed_official 85:e1a8e879a6a9 2153 /* Bit 23 : Set as input pin 23. */
mbed_official 85:e1a8e879a6a9 2154 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
mbed_official 85:e1a8e879a6a9 2155 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
mbed_official 85:e1a8e879a6a9 2156 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2157 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2158 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2159
mbed_official 85:e1a8e879a6a9 2160 /* Bit 22 : Set as input pin 22. */
mbed_official 85:e1a8e879a6a9 2161 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
mbed_official 85:e1a8e879a6a9 2162 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
mbed_official 85:e1a8e879a6a9 2163 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2164 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2165 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2166
mbed_official 85:e1a8e879a6a9 2167 /* Bit 21 : Set as input pin 21. */
mbed_official 85:e1a8e879a6a9 2168 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
mbed_official 85:e1a8e879a6a9 2169 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
mbed_official 85:e1a8e879a6a9 2170 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2171 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2172 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2173
mbed_official 85:e1a8e879a6a9 2174 /* Bit 20 : Set as input pin 20. */
mbed_official 85:e1a8e879a6a9 2175 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
mbed_official 85:e1a8e879a6a9 2176 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
mbed_official 85:e1a8e879a6a9 2177 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2178 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2179 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2180
mbed_official 85:e1a8e879a6a9 2181 /* Bit 19 : Set as input pin 19. */
mbed_official 85:e1a8e879a6a9 2182 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
mbed_official 85:e1a8e879a6a9 2183 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
mbed_official 85:e1a8e879a6a9 2184 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2185 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2186 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2187
mbed_official 85:e1a8e879a6a9 2188 /* Bit 18 : Set as input pin 18. */
mbed_official 85:e1a8e879a6a9 2189 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
mbed_official 85:e1a8e879a6a9 2190 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
mbed_official 85:e1a8e879a6a9 2191 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2192 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2193 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2194
mbed_official 85:e1a8e879a6a9 2195 /* Bit 17 : Set as input pin 17. */
mbed_official 85:e1a8e879a6a9 2196 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
mbed_official 85:e1a8e879a6a9 2197 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
mbed_official 85:e1a8e879a6a9 2198 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2199 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2200 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2201
mbed_official 85:e1a8e879a6a9 2202 /* Bit 16 : Set as input pin 16. */
mbed_official 85:e1a8e879a6a9 2203 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
mbed_official 85:e1a8e879a6a9 2204 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
mbed_official 85:e1a8e879a6a9 2205 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2206 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2207 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2208
mbed_official 85:e1a8e879a6a9 2209 /* Bit 15 : Set as input pin 15. */
mbed_official 85:e1a8e879a6a9 2210 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
mbed_official 85:e1a8e879a6a9 2211 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
mbed_official 85:e1a8e879a6a9 2212 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2213 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2214 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2215
mbed_official 85:e1a8e879a6a9 2216 /* Bit 14 : Set as input pin 14. */
mbed_official 85:e1a8e879a6a9 2217 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
mbed_official 85:e1a8e879a6a9 2218 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
mbed_official 85:e1a8e879a6a9 2219 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2220 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2221 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2222
mbed_official 85:e1a8e879a6a9 2223 /* Bit 13 : Set as input pin 13. */
mbed_official 85:e1a8e879a6a9 2224 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
mbed_official 85:e1a8e879a6a9 2225 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
mbed_official 85:e1a8e879a6a9 2226 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2227 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2228 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2229
mbed_official 85:e1a8e879a6a9 2230 /* Bit 12 : Set as input pin 12. */
mbed_official 85:e1a8e879a6a9 2231 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
mbed_official 85:e1a8e879a6a9 2232 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
mbed_official 85:e1a8e879a6a9 2233 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2234 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2235 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2236
mbed_official 85:e1a8e879a6a9 2237 /* Bit 11 : Set as input pin 11. */
mbed_official 85:e1a8e879a6a9 2238 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
mbed_official 85:e1a8e879a6a9 2239 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
mbed_official 85:e1a8e879a6a9 2240 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2241 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2242 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2243
mbed_official 85:e1a8e879a6a9 2244 /* Bit 10 : Set as input pin 10. */
mbed_official 85:e1a8e879a6a9 2245 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
mbed_official 85:e1a8e879a6a9 2246 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
mbed_official 85:e1a8e879a6a9 2247 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2248 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2249 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2250
mbed_official 85:e1a8e879a6a9 2251 /* Bit 9 : Set as input pin 9. */
mbed_official 85:e1a8e879a6a9 2252 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
mbed_official 85:e1a8e879a6a9 2253 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
mbed_official 85:e1a8e879a6a9 2254 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2255 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2256 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2257
mbed_official 85:e1a8e879a6a9 2258 /* Bit 8 : Set as input pin 8. */
mbed_official 85:e1a8e879a6a9 2259 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
mbed_official 85:e1a8e879a6a9 2260 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
mbed_official 85:e1a8e879a6a9 2261 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2262 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2263 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2264
mbed_official 85:e1a8e879a6a9 2265 /* Bit 7 : Set as input pin 7. */
mbed_official 85:e1a8e879a6a9 2266 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
mbed_official 85:e1a8e879a6a9 2267 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
mbed_official 85:e1a8e879a6a9 2268 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2269 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2270 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2271
mbed_official 85:e1a8e879a6a9 2272 /* Bit 6 : Set as input pin 6. */
mbed_official 85:e1a8e879a6a9 2273 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
mbed_official 85:e1a8e879a6a9 2274 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
mbed_official 85:e1a8e879a6a9 2275 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2276 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2277 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2278
mbed_official 85:e1a8e879a6a9 2279 /* Bit 5 : Set as input pin 5. */
mbed_official 85:e1a8e879a6a9 2280 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
mbed_official 85:e1a8e879a6a9 2281 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
mbed_official 85:e1a8e879a6a9 2282 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2283 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2284 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2285
mbed_official 85:e1a8e879a6a9 2286 /* Bit 4 : Set as input pin 4. */
mbed_official 85:e1a8e879a6a9 2287 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
mbed_official 85:e1a8e879a6a9 2288 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
mbed_official 85:e1a8e879a6a9 2289 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2290 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2291 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2292
mbed_official 85:e1a8e879a6a9 2293 /* Bit 3 : Set as input pin 3. */
mbed_official 85:e1a8e879a6a9 2294 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
mbed_official 85:e1a8e879a6a9 2295 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
mbed_official 85:e1a8e879a6a9 2296 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2297 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2298 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2299
mbed_official 85:e1a8e879a6a9 2300 /* Bit 2 : Set as input pin 2. */
mbed_official 85:e1a8e879a6a9 2301 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
mbed_official 85:e1a8e879a6a9 2302 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
mbed_official 85:e1a8e879a6a9 2303 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2304 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2305 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2306
mbed_official 85:e1a8e879a6a9 2307 /* Bit 1 : Set as input pin 1. */
mbed_official 85:e1a8e879a6a9 2308 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
mbed_official 85:e1a8e879a6a9 2309 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
mbed_official 85:e1a8e879a6a9 2310 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2311 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2312 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2313
mbed_official 85:e1a8e879a6a9 2314 /* Bit 0 : Set as input pin 0. */
mbed_official 85:e1a8e879a6a9 2315 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
mbed_official 85:e1a8e879a6a9 2316 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
mbed_official 85:e1a8e879a6a9 2317 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
mbed_official 85:e1a8e879a6a9 2318 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
mbed_official 85:e1a8e879a6a9 2319 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
mbed_official 85:e1a8e879a6a9 2320
mbed_official 85:e1a8e879a6a9 2321 /* Register: GPIO_PIN_CNF */
mbed_official 85:e1a8e879a6a9 2322 /* Description: Configuration of GPIO pins. */
mbed_official 85:e1a8e879a6a9 2323
mbed_official 85:e1a8e879a6a9 2324 /* Bits 17..16 : Pin sensing mechanism. */
mbed_official 85:e1a8e879a6a9 2325 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
mbed_official 85:e1a8e879a6a9 2326 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
mbed_official 85:e1a8e879a6a9 2327 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 2328 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
mbed_official 85:e1a8e879a6a9 2329 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
mbed_official 85:e1a8e879a6a9 2330
mbed_official 85:e1a8e879a6a9 2331 /* Bits 10..8 : Drive configuration. */
mbed_official 85:e1a8e879a6a9 2332 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
mbed_official 85:e1a8e879a6a9 2333 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
mbed_official 85:e1a8e879a6a9 2334 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
mbed_official 85:e1a8e879a6a9 2335 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
mbed_official 85:e1a8e879a6a9 2336 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
mbed_official 85:e1a8e879a6a9 2337 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
mbed_official 85:e1a8e879a6a9 2338 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
mbed_official 85:e1a8e879a6a9 2339 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
mbed_official 85:e1a8e879a6a9 2340 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
mbed_official 85:e1a8e879a6a9 2341 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
mbed_official 85:e1a8e879a6a9 2342
mbed_official 85:e1a8e879a6a9 2343 /* Bits 3..2 : Pull-up or -down configuration. */
mbed_official 85:e1a8e879a6a9 2344 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
mbed_official 85:e1a8e879a6a9 2345 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
mbed_official 85:e1a8e879a6a9 2346 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
mbed_official 85:e1a8e879a6a9 2347 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
mbed_official 85:e1a8e879a6a9 2348 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
mbed_official 85:e1a8e879a6a9 2349
mbed_official 85:e1a8e879a6a9 2350 /* Bit 1 : Connect or disconnect input path. */
mbed_official 85:e1a8e879a6a9 2351 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
mbed_official 85:e1a8e879a6a9 2352 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
mbed_official 85:e1a8e879a6a9 2353 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
mbed_official 85:e1a8e879a6a9 2354 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
mbed_official 85:e1a8e879a6a9 2355
mbed_official 85:e1a8e879a6a9 2356 /* Bit 0 : Pin direction. */
mbed_official 85:e1a8e879a6a9 2357 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
mbed_official 85:e1a8e879a6a9 2358 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
mbed_official 85:e1a8e879a6a9 2359 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
mbed_official 85:e1a8e879a6a9 2360 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
mbed_official 85:e1a8e879a6a9 2361
mbed_official 85:e1a8e879a6a9 2362
mbed_official 85:e1a8e879a6a9 2363 /* Peripheral: GPIOTE */
mbed_official 85:e1a8e879a6a9 2364 /* Description: GPIO tasks and events. */
mbed_official 85:e1a8e879a6a9 2365
mbed_official 85:e1a8e879a6a9 2366 /* Register: GPIOTE_INTENSET */
mbed_official 85:e1a8e879a6a9 2367 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 2368
mbed_official 85:e1a8e879a6a9 2369 /* Bit 31 : Enable interrupt on PORT event. */
mbed_official 85:e1a8e879a6a9 2370 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
mbed_official 85:e1a8e879a6a9 2371 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
mbed_official 85:e1a8e879a6a9 2372 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2373 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2374 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2375
mbed_official 85:e1a8e879a6a9 2376 /* Bit 3 : Enable interrupt on IN[3] event. */
mbed_official 85:e1a8e879a6a9 2377 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
mbed_official 85:e1a8e879a6a9 2378 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
mbed_official 85:e1a8e879a6a9 2379 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2380 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2381 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2382
mbed_official 85:e1a8e879a6a9 2383 /* Bit 2 : Enable interrupt on IN[2] event. */
mbed_official 85:e1a8e879a6a9 2384 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
mbed_official 85:e1a8e879a6a9 2385 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
mbed_official 85:e1a8e879a6a9 2386 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2387 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2388 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2389
mbed_official 85:e1a8e879a6a9 2390 /* Bit 1 : Enable interrupt on IN[1] event. */
mbed_official 85:e1a8e879a6a9 2391 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
mbed_official 85:e1a8e879a6a9 2392 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
mbed_official 85:e1a8e879a6a9 2393 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2394 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2395 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2396
mbed_official 85:e1a8e879a6a9 2397 /* Bit 0 : Enable interrupt on IN[0] event. */
mbed_official 85:e1a8e879a6a9 2398 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
mbed_official 85:e1a8e879a6a9 2399 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
mbed_official 85:e1a8e879a6a9 2400 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2401 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2402 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2403
mbed_official 85:e1a8e879a6a9 2404 /* Register: GPIOTE_INTENCLR */
mbed_official 85:e1a8e879a6a9 2405 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 2406
mbed_official 85:e1a8e879a6a9 2407 /* Bit 31 : Disable interrupt on PORT event. */
mbed_official 85:e1a8e879a6a9 2408 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
mbed_official 85:e1a8e879a6a9 2409 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
mbed_official 85:e1a8e879a6a9 2410 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2411 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2412 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2413
mbed_official 85:e1a8e879a6a9 2414 /* Bit 3 : Disable interrupt on IN[3] event. */
mbed_official 85:e1a8e879a6a9 2415 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
mbed_official 85:e1a8e879a6a9 2416 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
mbed_official 85:e1a8e879a6a9 2417 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2418 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2419 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2420
mbed_official 85:e1a8e879a6a9 2421 /* Bit 2 : Disable interrupt on IN[2] event. */
mbed_official 85:e1a8e879a6a9 2422 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
mbed_official 85:e1a8e879a6a9 2423 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
mbed_official 85:e1a8e879a6a9 2424 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2425 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2426 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2427
mbed_official 85:e1a8e879a6a9 2428 /* Bit 1 : Disable interrupt on IN[1] event. */
mbed_official 85:e1a8e879a6a9 2429 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
mbed_official 85:e1a8e879a6a9 2430 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
mbed_official 85:e1a8e879a6a9 2431 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2432 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2433 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2434
mbed_official 85:e1a8e879a6a9 2435 /* Bit 0 : Disable interrupt on IN[0] event. */
mbed_official 85:e1a8e879a6a9 2436 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
mbed_official 85:e1a8e879a6a9 2437 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
mbed_official 85:e1a8e879a6a9 2438 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2439 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2440 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2441
mbed_official 85:e1a8e879a6a9 2442 /* Register: GPIOTE_CONFIG */
mbed_official 85:e1a8e879a6a9 2443 /* Description: Channel configuration registers. */
mbed_official 85:e1a8e879a6a9 2444
mbed_official 85:e1a8e879a6a9 2445 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
mbed_official 85:e1a8e879a6a9 2446 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
mbed_official 85:e1a8e879a6a9 2447 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
mbed_official 85:e1a8e879a6a9 2448 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
mbed_official 85:e1a8e879a6a9 2449 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
mbed_official 85:e1a8e879a6a9 2450
mbed_official 85:e1a8e879a6a9 2451 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
mbed_official 85:e1a8e879a6a9 2452 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
mbed_official 85:e1a8e879a6a9 2453 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
mbed_official 85:e1a8e879a6a9 2454 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
mbed_official 85:e1a8e879a6a9 2455 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
mbed_official 85:e1a8e879a6a9 2456 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
mbed_official 85:e1a8e879a6a9 2457
mbed_official 85:e1a8e879a6a9 2458 /* Bits 12..8 : Pin select. */
mbed_official 85:e1a8e879a6a9 2459 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
mbed_official 85:e1a8e879a6a9 2460 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
mbed_official 85:e1a8e879a6a9 2461
mbed_official 85:e1a8e879a6a9 2462 /* Bits 1..0 : Mode */
mbed_official 85:e1a8e879a6a9 2463 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
mbed_official 85:e1a8e879a6a9 2464 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
mbed_official 85:e1a8e879a6a9 2465 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 2466 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
mbed_official 85:e1a8e879a6a9 2467 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
mbed_official 85:e1a8e879a6a9 2468
mbed_official 85:e1a8e879a6a9 2469 /* Register: GPIOTE_POWER */
mbed_official 85:e1a8e879a6a9 2470 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 2471
mbed_official 85:e1a8e879a6a9 2472 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 2473 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 2474 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 2475 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 2476 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 2477
mbed_official 85:e1a8e879a6a9 2478
mbed_official 85:e1a8e879a6a9 2479 /* Peripheral: LPCOMP */
mbed_official 85:e1a8e879a6a9 2480 /* Description: Wakeup Comparator. */
mbed_official 85:e1a8e879a6a9 2481
mbed_official 85:e1a8e879a6a9 2482 /* Register: LPCOMP_SHORTS */
mbed_official 85:e1a8e879a6a9 2483 /* Description: Shortcut for the LPCOMP. */
mbed_official 85:e1a8e879a6a9 2484
mbed_official 85:e1a8e879a6a9 2485 /* Bit 4 : Short-cut between CROSS event and STOP task. */
mbed_official 85:e1a8e879a6a9 2486 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
mbed_official 85:e1a8e879a6a9 2487 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
mbed_official 85:e1a8e879a6a9 2488 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 2489 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 2490
mbed_official 85:e1a8e879a6a9 2491 /* Bit 3 : Short-cut between UP event and STOP task. */
mbed_official 85:e1a8e879a6a9 2492 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
mbed_official 85:e1a8e879a6a9 2493 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
mbed_official 85:e1a8e879a6a9 2494 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 2495 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 2496
mbed_official 85:e1a8e879a6a9 2497 /* Bit 2 : Short-cut between DOWN event and STOP task. */
mbed_official 85:e1a8e879a6a9 2498 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
mbed_official 85:e1a8e879a6a9 2499 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
mbed_official 85:e1a8e879a6a9 2500 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 2501 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 2502
mbed_official 85:e1a8e879a6a9 2503 /* Bit 1 : Short-cut between RADY event and STOP task. */
mbed_official 85:e1a8e879a6a9 2504 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
mbed_official 85:e1a8e879a6a9 2505 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
mbed_official 85:e1a8e879a6a9 2506 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 2507 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 2508
mbed_official 85:e1a8e879a6a9 2509 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
mbed_official 85:e1a8e879a6a9 2510 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
mbed_official 85:e1a8e879a6a9 2511 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
mbed_official 85:e1a8e879a6a9 2512 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 2513 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 2514
mbed_official 85:e1a8e879a6a9 2515 /* Register: LPCOMP_INTENSET */
mbed_official 85:e1a8e879a6a9 2516 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 2517
mbed_official 85:e1a8e879a6a9 2518 /* Bit 3 : Enable interrupt on CROSS event. */
mbed_official 85:e1a8e879a6a9 2519 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
mbed_official 85:e1a8e879a6a9 2520 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
mbed_official 85:e1a8e879a6a9 2521 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2522 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2523 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2524
mbed_official 85:e1a8e879a6a9 2525 /* Bit 2 : Enable interrupt on UP event. */
mbed_official 85:e1a8e879a6a9 2526 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
mbed_official 85:e1a8e879a6a9 2527 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
mbed_official 85:e1a8e879a6a9 2528 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2529 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2530 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2531
mbed_official 85:e1a8e879a6a9 2532 /* Bit 1 : Enable interrupt on DOWN event. */
mbed_official 85:e1a8e879a6a9 2533 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
mbed_official 85:e1a8e879a6a9 2534 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
mbed_official 85:e1a8e879a6a9 2535 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2536 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2537 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2538
mbed_official 85:e1a8e879a6a9 2539 /* Bit 0 : Enable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 2540 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 2541 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 2542 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2543 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2544 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2545
mbed_official 85:e1a8e879a6a9 2546 /* Register: LPCOMP_INTENCLR */
mbed_official 85:e1a8e879a6a9 2547 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 2548
mbed_official 85:e1a8e879a6a9 2549 /* Bit 3 : Disable interrupt on CROSS event. */
mbed_official 85:e1a8e879a6a9 2550 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
mbed_official 85:e1a8e879a6a9 2551 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
mbed_official 85:e1a8e879a6a9 2552 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2553 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2554 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2555
mbed_official 85:e1a8e879a6a9 2556 /* Bit 2 : Disable interrupt on UP event. */
mbed_official 85:e1a8e879a6a9 2557 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
mbed_official 85:e1a8e879a6a9 2558 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
mbed_official 85:e1a8e879a6a9 2559 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2560 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2561 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2562
mbed_official 85:e1a8e879a6a9 2563 /* Bit 1 : Disable interrupt on DOWN event. */
mbed_official 85:e1a8e879a6a9 2564 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
mbed_official 85:e1a8e879a6a9 2565 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
mbed_official 85:e1a8e879a6a9 2566 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2567 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2568 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2569
mbed_official 85:e1a8e879a6a9 2570 /* Bit 0 : Disable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 2571 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 2572 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 2573 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 2574 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 2575 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 2576
mbed_official 85:e1a8e879a6a9 2577 /* Register: LPCOMP_RESULT */
mbed_official 85:e1a8e879a6a9 2578 /* Description: Result of last compare. */
mbed_official 85:e1a8e879a6a9 2579
mbed_official 85:e1a8e879a6a9 2580 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
mbed_official 85:e1a8e879a6a9 2581 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
mbed_official 85:e1a8e879a6a9 2582 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
mbed_official 85:e1a8e879a6a9 2583 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
mbed_official 85:e1a8e879a6a9 2584 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
mbed_official 85:e1a8e879a6a9 2585
mbed_official 85:e1a8e879a6a9 2586 /* Register: LPCOMP_ENABLE */
mbed_official 85:e1a8e879a6a9 2587 /* Description: Enable the LPCOMP. */
mbed_official 85:e1a8e879a6a9 2588
mbed_official 85:e1a8e879a6a9 2589 /* Bits 1..0 : Enable or disable LPCOMP. */
mbed_official 85:e1a8e879a6a9 2590 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 2591 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 2592 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
mbed_official 85:e1a8e879a6a9 2593 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
mbed_official 85:e1a8e879a6a9 2594
mbed_official 85:e1a8e879a6a9 2595 /* Register: LPCOMP_PSEL */
mbed_official 85:e1a8e879a6a9 2596 /* Description: Input pin select. */
mbed_official 85:e1a8e879a6a9 2597
mbed_official 85:e1a8e879a6a9 2598 /* Bits 2..0 : Analog input pin select. */
mbed_official 85:e1a8e879a6a9 2599 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
mbed_official 85:e1a8e879a6a9 2600 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
mbed_official 85:e1a8e879a6a9 2601 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
mbed_official 85:e1a8e879a6a9 2602 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
mbed_official 85:e1a8e879a6a9 2603 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
mbed_official 85:e1a8e879a6a9 2604 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
mbed_official 85:e1a8e879a6a9 2605 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
mbed_official 85:e1a8e879a6a9 2606 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
mbed_official 85:e1a8e879a6a9 2607 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
mbed_official 85:e1a8e879a6a9 2608 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
mbed_official 85:e1a8e879a6a9 2609
mbed_official 85:e1a8e879a6a9 2610 /* Register: LPCOMP_REFSEL */
mbed_official 85:e1a8e879a6a9 2611 /* Description: Reference select. */
mbed_official 85:e1a8e879a6a9 2612
mbed_official 85:e1a8e879a6a9 2613 /* Bits 2..0 : Reference select. */
mbed_official 85:e1a8e879a6a9 2614 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
mbed_official 85:e1a8e879a6a9 2615 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
mbed_official 85:e1a8e879a6a9 2616 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2617 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2618 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2619 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2620 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2621 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2622 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */
mbed_official 85:e1a8e879a6a9 2623 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
mbed_official 85:e1a8e879a6a9 2624
mbed_official 85:e1a8e879a6a9 2625 /* Register: LPCOMP_EXTREFSEL */
mbed_official 85:e1a8e879a6a9 2626 /* Description: External reference select. */
mbed_official 85:e1a8e879a6a9 2627
mbed_official 85:e1a8e879a6a9 2628 /* Bit 0 : External analog reference pin selection. */
mbed_official 85:e1a8e879a6a9 2629 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 2630 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
mbed_official 85:e1a8e879a6a9 2631 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
mbed_official 85:e1a8e879a6a9 2632 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
mbed_official 85:e1a8e879a6a9 2633
mbed_official 85:e1a8e879a6a9 2634 /* Register: LPCOMP_ANADETECT */
mbed_official 85:e1a8e879a6a9 2635 /* Description: Analog detect configuration. */
mbed_official 85:e1a8e879a6a9 2636
mbed_official 85:e1a8e879a6a9 2637 /* Bits 1..0 : Analog detect configuration. */
mbed_official 85:e1a8e879a6a9 2638 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
mbed_official 85:e1a8e879a6a9 2639 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
mbed_official 85:e1a8e879a6a9 2640 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
mbed_official 85:e1a8e879a6a9 2641 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
mbed_official 85:e1a8e879a6a9 2642 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
mbed_official 85:e1a8e879a6a9 2643
mbed_official 85:e1a8e879a6a9 2644 /* Register: LPCOMP_POWER */
mbed_official 85:e1a8e879a6a9 2645 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 2646
mbed_official 85:e1a8e879a6a9 2647 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 2648 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 2649 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 2650 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 2651 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 2652
mbed_official 85:e1a8e879a6a9 2653
mbed_official 85:e1a8e879a6a9 2654 /* Peripheral: MPU */
mbed_official 85:e1a8e879a6a9 2655 /* Description: Memory Protection Unit. */
mbed_official 85:e1a8e879a6a9 2656
mbed_official 85:e1a8e879a6a9 2657 /* Register: MPU_PERR0 */
mbed_official 85:e1a8e879a6a9 2658 /* Description: Configuration of peripherals in mpu regions. */
mbed_official 85:e1a8e879a6a9 2659
mbed_official 85:e1a8e879a6a9 2660 /* Bit 31 : PPI region configuration. */
mbed_official 85:e1a8e879a6a9 2661 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
mbed_official 85:e1a8e879a6a9 2662 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
mbed_official 85:e1a8e879a6a9 2663 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2664 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2665
mbed_official 85:e1a8e879a6a9 2666 /* Bit 30 : NVMC region configuration. */
mbed_official 85:e1a8e879a6a9 2667 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
mbed_official 85:e1a8e879a6a9 2668 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
mbed_official 85:e1a8e879a6a9 2669 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2670 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2671
mbed_official 85:e1a8e879a6a9 2672 /* Bit 19 : LPCOMP_COMP region configuration. */
mbed_official 85:e1a8e879a6a9 2673 #define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */
mbed_official 85:e1a8e879a6a9 2674 #define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */
mbed_official 85:e1a8e879a6a9 2675 #define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2676 #define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2677
mbed_official 85:e1a8e879a6a9 2678 /* Bit 18 : QDEC region configuration. */
mbed_official 85:e1a8e879a6a9 2679 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
mbed_official 85:e1a8e879a6a9 2680 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
mbed_official 85:e1a8e879a6a9 2681 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2682 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2683
mbed_official 85:e1a8e879a6a9 2684 /* Bit 17 : RTC1 region configuration. */
mbed_official 85:e1a8e879a6a9 2685 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
mbed_official 85:e1a8e879a6a9 2686 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
mbed_official 85:e1a8e879a6a9 2687 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2688 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2689
mbed_official 85:e1a8e879a6a9 2690 /* Bit 16 : WDT region configuration. */
mbed_official 85:e1a8e879a6a9 2691 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
mbed_official 85:e1a8e879a6a9 2692 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
mbed_official 85:e1a8e879a6a9 2693 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2694 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2695
mbed_official 85:e1a8e879a6a9 2696 /* Bit 15 : CCM and AAR region configuration. */
mbed_official 85:e1a8e879a6a9 2697 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
mbed_official 85:e1a8e879a6a9 2698 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
mbed_official 85:e1a8e879a6a9 2699 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2700 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2701
mbed_official 85:e1a8e879a6a9 2702 /* Bit 14 : ECB region configuration. */
mbed_official 85:e1a8e879a6a9 2703 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
mbed_official 85:e1a8e879a6a9 2704 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
mbed_official 85:e1a8e879a6a9 2705 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2706 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2707
mbed_official 85:e1a8e879a6a9 2708 /* Bit 13 : RNG region configuration. */
mbed_official 85:e1a8e879a6a9 2709 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
mbed_official 85:e1a8e879a6a9 2710 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
mbed_official 85:e1a8e879a6a9 2711 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2712 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2713
mbed_official 85:e1a8e879a6a9 2714 /* Bit 12 : TEMP region configuration. */
mbed_official 85:e1a8e879a6a9 2715 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
mbed_official 85:e1a8e879a6a9 2716 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
mbed_official 85:e1a8e879a6a9 2717 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2718 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2719
mbed_official 85:e1a8e879a6a9 2720 /* Bit 11 : RTC0 region configuration. */
mbed_official 85:e1a8e879a6a9 2721 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
mbed_official 85:e1a8e879a6a9 2722 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
mbed_official 85:e1a8e879a6a9 2723 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2724 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2725
mbed_official 85:e1a8e879a6a9 2726 /* Bit 10 : TIMER2 region configuration. */
mbed_official 85:e1a8e879a6a9 2727 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
mbed_official 85:e1a8e879a6a9 2728 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
mbed_official 85:e1a8e879a6a9 2729 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2730 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2731
mbed_official 85:e1a8e879a6a9 2732 /* Bit 9 : TIMER1 region configuration. */
mbed_official 85:e1a8e879a6a9 2733 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
mbed_official 85:e1a8e879a6a9 2734 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
mbed_official 85:e1a8e879a6a9 2735 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2736 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2737
mbed_official 85:e1a8e879a6a9 2738 /* Bit 8 : TIMER0 region configuration. */
mbed_official 85:e1a8e879a6a9 2739 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
mbed_official 85:e1a8e879a6a9 2740 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
mbed_official 85:e1a8e879a6a9 2741 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2742 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2743
mbed_official 85:e1a8e879a6a9 2744 /* Bit 7 : ADC region configuration. */
mbed_official 85:e1a8e879a6a9 2745 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
mbed_official 85:e1a8e879a6a9 2746 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
mbed_official 85:e1a8e879a6a9 2747 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2748 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2749
mbed_official 85:e1a8e879a6a9 2750 /* Bit 6 : GPIOTE region configuration. */
mbed_official 85:e1a8e879a6a9 2751 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
mbed_official 85:e1a8e879a6a9 2752 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
mbed_official 85:e1a8e879a6a9 2753 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2754 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2755
mbed_official 85:e1a8e879a6a9 2756 /* Bit 4 : SPI1 and TWI1 region configuration. */
mbed_official 85:e1a8e879a6a9 2757 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
mbed_official 85:e1a8e879a6a9 2758 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
mbed_official 85:e1a8e879a6a9 2759 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2760 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2761
mbed_official 85:e1a8e879a6a9 2762 /* Bit 3 : SPI0 and TWI0 region configuration. */
mbed_official 85:e1a8e879a6a9 2763 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
mbed_official 85:e1a8e879a6a9 2764 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
mbed_official 85:e1a8e879a6a9 2765 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2766 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2767
mbed_official 85:e1a8e879a6a9 2768 /* Bit 2 : UART0 region configuration. */
mbed_official 85:e1a8e879a6a9 2769 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
mbed_official 85:e1a8e879a6a9 2770 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
mbed_official 85:e1a8e879a6a9 2771 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2772 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2773
mbed_official 85:e1a8e879a6a9 2774 /* Bit 1 : RADIO region configuration. */
mbed_official 85:e1a8e879a6a9 2775 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
mbed_official 85:e1a8e879a6a9 2776 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
mbed_official 85:e1a8e879a6a9 2777 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2778 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2779
mbed_official 85:e1a8e879a6a9 2780 /* Bit 0 : POWER_CLOCK region configuration. */
mbed_official 85:e1a8e879a6a9 2781 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
mbed_official 85:e1a8e879a6a9 2782 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
mbed_official 85:e1a8e879a6a9 2783 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
mbed_official 85:e1a8e879a6a9 2784 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
mbed_official 85:e1a8e879a6a9 2785
mbed_official 85:e1a8e879a6a9 2786 /* Register: MPU_PROTENSET0 */
mbed_official 85:e1a8e879a6a9 2787 /* Description: Protection bit enable set register for low addresses. */
mbed_official 85:e1a8e879a6a9 2788
mbed_official 85:e1a8e879a6a9 2789 /* Bit 31 : Protection enable for region 31. */
mbed_official 85:e1a8e879a6a9 2790 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
mbed_official 85:e1a8e879a6a9 2791 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
mbed_official 85:e1a8e879a6a9 2792 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2793 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2794 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2795
mbed_official 85:e1a8e879a6a9 2796 /* Bit 30 : Protection enable for region 30. */
mbed_official 85:e1a8e879a6a9 2797 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
mbed_official 85:e1a8e879a6a9 2798 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
mbed_official 85:e1a8e879a6a9 2799 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2800 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2801 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2802
mbed_official 85:e1a8e879a6a9 2803 /* Bit 29 : Protection enable for region 29. */
mbed_official 85:e1a8e879a6a9 2804 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
mbed_official 85:e1a8e879a6a9 2805 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
mbed_official 85:e1a8e879a6a9 2806 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2807 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2808 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2809
mbed_official 85:e1a8e879a6a9 2810 /* Bit 28 : Protection enable for region 28. */
mbed_official 85:e1a8e879a6a9 2811 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
mbed_official 85:e1a8e879a6a9 2812 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
mbed_official 85:e1a8e879a6a9 2813 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2814 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2815 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2816
mbed_official 85:e1a8e879a6a9 2817 /* Bit 27 : Protection enable for region 27. */
mbed_official 85:e1a8e879a6a9 2818 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
mbed_official 85:e1a8e879a6a9 2819 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
mbed_official 85:e1a8e879a6a9 2820 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2821 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2822 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2823
mbed_official 85:e1a8e879a6a9 2824 /* Bit 26 : Protection enable for region 26. */
mbed_official 85:e1a8e879a6a9 2825 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
mbed_official 85:e1a8e879a6a9 2826 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
mbed_official 85:e1a8e879a6a9 2827 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2828 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2829 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2830
mbed_official 85:e1a8e879a6a9 2831 /* Bit 25 : Protection enable for region 25. */
mbed_official 85:e1a8e879a6a9 2832 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
mbed_official 85:e1a8e879a6a9 2833 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
mbed_official 85:e1a8e879a6a9 2834 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2835 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2836 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2837
mbed_official 85:e1a8e879a6a9 2838 /* Bit 24 : Protection enable for region 24. */
mbed_official 85:e1a8e879a6a9 2839 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
mbed_official 85:e1a8e879a6a9 2840 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
mbed_official 85:e1a8e879a6a9 2841 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2842 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2843 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2844
mbed_official 85:e1a8e879a6a9 2845 /* Bit 23 : Protection enable for region 23. */
mbed_official 85:e1a8e879a6a9 2846 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
mbed_official 85:e1a8e879a6a9 2847 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
mbed_official 85:e1a8e879a6a9 2848 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2849 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2850 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2851
mbed_official 85:e1a8e879a6a9 2852 /* Bit 22 : Protection enable for region 22. */
mbed_official 85:e1a8e879a6a9 2853 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
mbed_official 85:e1a8e879a6a9 2854 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
mbed_official 85:e1a8e879a6a9 2855 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2856 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2857 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2858
mbed_official 85:e1a8e879a6a9 2859 /* Bit 21 : Protection enable for region 21. */
mbed_official 85:e1a8e879a6a9 2860 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
mbed_official 85:e1a8e879a6a9 2861 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
mbed_official 85:e1a8e879a6a9 2862 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2863 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2864 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2865
mbed_official 85:e1a8e879a6a9 2866 /* Bit 20 : Protection enable for region 20. */
mbed_official 85:e1a8e879a6a9 2867 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
mbed_official 85:e1a8e879a6a9 2868 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
mbed_official 85:e1a8e879a6a9 2869 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2870 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2871 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2872
mbed_official 85:e1a8e879a6a9 2873 /* Bit 19 : Protection enable for region 19. */
mbed_official 85:e1a8e879a6a9 2874 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
mbed_official 85:e1a8e879a6a9 2875 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
mbed_official 85:e1a8e879a6a9 2876 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2877 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2878 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2879
mbed_official 85:e1a8e879a6a9 2880 /* Bit 18 : Protection enable for region 18. */
mbed_official 85:e1a8e879a6a9 2881 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
mbed_official 85:e1a8e879a6a9 2882 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
mbed_official 85:e1a8e879a6a9 2883 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2884 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2885 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2886
mbed_official 85:e1a8e879a6a9 2887 /* Bit 17 : Protection enable for region 17. */
mbed_official 85:e1a8e879a6a9 2888 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
mbed_official 85:e1a8e879a6a9 2889 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
mbed_official 85:e1a8e879a6a9 2890 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2891 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2892 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2893
mbed_official 85:e1a8e879a6a9 2894 /* Bit 16 : Protection enable for region 16. */
mbed_official 85:e1a8e879a6a9 2895 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
mbed_official 85:e1a8e879a6a9 2896 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
mbed_official 85:e1a8e879a6a9 2897 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2898 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2899 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2900
mbed_official 85:e1a8e879a6a9 2901 /* Bit 15 : Protection enable for region 15. */
mbed_official 85:e1a8e879a6a9 2902 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
mbed_official 85:e1a8e879a6a9 2903 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
mbed_official 85:e1a8e879a6a9 2904 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2905 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2906 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2907
mbed_official 85:e1a8e879a6a9 2908 /* Bit 14 : Protection enable for region 14. */
mbed_official 85:e1a8e879a6a9 2909 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
mbed_official 85:e1a8e879a6a9 2910 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
mbed_official 85:e1a8e879a6a9 2911 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2912 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2913 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2914
mbed_official 85:e1a8e879a6a9 2915 /* Bit 13 : Protection enable for region 13. */
mbed_official 85:e1a8e879a6a9 2916 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
mbed_official 85:e1a8e879a6a9 2917 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
mbed_official 85:e1a8e879a6a9 2918 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2919 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2920 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2921
mbed_official 85:e1a8e879a6a9 2922 /* Bit 12 : Protection enable for region 12. */
mbed_official 85:e1a8e879a6a9 2923 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
mbed_official 85:e1a8e879a6a9 2924 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
mbed_official 85:e1a8e879a6a9 2925 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2926 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2927 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2928
mbed_official 85:e1a8e879a6a9 2929 /* Bit 11 : Protection enable for region 11. */
mbed_official 85:e1a8e879a6a9 2930 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
mbed_official 85:e1a8e879a6a9 2931 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
mbed_official 85:e1a8e879a6a9 2932 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2933 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2934 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2935
mbed_official 85:e1a8e879a6a9 2936 /* Bit 10 : Protection enable for region 10. */
mbed_official 85:e1a8e879a6a9 2937 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
mbed_official 85:e1a8e879a6a9 2938 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
mbed_official 85:e1a8e879a6a9 2939 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2940 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2941 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2942
mbed_official 85:e1a8e879a6a9 2943 /* Bit 9 : Protection enable for region 9. */
mbed_official 85:e1a8e879a6a9 2944 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
mbed_official 85:e1a8e879a6a9 2945 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
mbed_official 85:e1a8e879a6a9 2946 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2947 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2948 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2949
mbed_official 85:e1a8e879a6a9 2950 /* Bit 8 : Protection enable for region 8. */
mbed_official 85:e1a8e879a6a9 2951 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
mbed_official 85:e1a8e879a6a9 2952 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
mbed_official 85:e1a8e879a6a9 2953 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2954 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2955 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2956
mbed_official 85:e1a8e879a6a9 2957 /* Bit 7 : Protection enable for region 7. */
mbed_official 85:e1a8e879a6a9 2958 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
mbed_official 85:e1a8e879a6a9 2959 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
mbed_official 85:e1a8e879a6a9 2960 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2961 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2962 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2963
mbed_official 85:e1a8e879a6a9 2964 /* Bit 6 : Protection enable for region 6. */
mbed_official 85:e1a8e879a6a9 2965 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
mbed_official 85:e1a8e879a6a9 2966 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
mbed_official 85:e1a8e879a6a9 2967 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2968 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2969 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2970
mbed_official 85:e1a8e879a6a9 2971 /* Bit 5 : Protection enable for region 5. */
mbed_official 85:e1a8e879a6a9 2972 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
mbed_official 85:e1a8e879a6a9 2973 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
mbed_official 85:e1a8e879a6a9 2974 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2975 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2976 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2977
mbed_official 85:e1a8e879a6a9 2978 /* Bit 4 : Protection enable for region 4. */
mbed_official 85:e1a8e879a6a9 2979 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
mbed_official 85:e1a8e879a6a9 2980 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
mbed_official 85:e1a8e879a6a9 2981 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2982 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2983 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2984
mbed_official 85:e1a8e879a6a9 2985 /* Bit 3 : Protection enable for region 3. */
mbed_official 85:e1a8e879a6a9 2986 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
mbed_official 85:e1a8e879a6a9 2987 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
mbed_official 85:e1a8e879a6a9 2988 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2989 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2990 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2991
mbed_official 85:e1a8e879a6a9 2992 /* Bit 2 : Protection enable for region 2. */
mbed_official 85:e1a8e879a6a9 2993 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
mbed_official 85:e1a8e879a6a9 2994 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
mbed_official 85:e1a8e879a6a9 2995 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 2996 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 2997 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 2998
mbed_official 85:e1a8e879a6a9 2999 /* Bit 1 : Protection enable for region 1. */
mbed_official 85:e1a8e879a6a9 3000 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
mbed_official 85:e1a8e879a6a9 3001 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
mbed_official 85:e1a8e879a6a9 3002 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3003 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3004 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3005
mbed_official 85:e1a8e879a6a9 3006 /* Bit 0 : Protection enable for region 0. */
mbed_official 85:e1a8e879a6a9 3007 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
mbed_official 85:e1a8e879a6a9 3008 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
mbed_official 85:e1a8e879a6a9 3009 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3010 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3011 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3012
mbed_official 85:e1a8e879a6a9 3013 /* Register: MPU_PROTENSET1 */
mbed_official 85:e1a8e879a6a9 3014 /* Description: Protection bit enable set register for high addresses. */
mbed_official 85:e1a8e879a6a9 3015
mbed_official 85:e1a8e879a6a9 3016 /* Bit 31 : Protection enable for region 63. */
mbed_official 85:e1a8e879a6a9 3017 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
mbed_official 85:e1a8e879a6a9 3018 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
mbed_official 85:e1a8e879a6a9 3019 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3020 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3021 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3022
mbed_official 85:e1a8e879a6a9 3023 /* Bit 30 : Protection enable for region 62. */
mbed_official 85:e1a8e879a6a9 3024 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
mbed_official 85:e1a8e879a6a9 3025 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
mbed_official 85:e1a8e879a6a9 3026 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3027 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3028 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3029
mbed_official 85:e1a8e879a6a9 3030 /* Bit 29 : Protection enable for region 61. */
mbed_official 85:e1a8e879a6a9 3031 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
mbed_official 85:e1a8e879a6a9 3032 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
mbed_official 85:e1a8e879a6a9 3033 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3034 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3035 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3036
mbed_official 85:e1a8e879a6a9 3037 /* Bit 28 : Protection enable for region 60. */
mbed_official 85:e1a8e879a6a9 3038 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
mbed_official 85:e1a8e879a6a9 3039 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
mbed_official 85:e1a8e879a6a9 3040 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3041 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3042 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3043
mbed_official 85:e1a8e879a6a9 3044 /* Bit 27 : Protection enable for region 59. */
mbed_official 85:e1a8e879a6a9 3045 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
mbed_official 85:e1a8e879a6a9 3046 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
mbed_official 85:e1a8e879a6a9 3047 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3048 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3049 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3050
mbed_official 85:e1a8e879a6a9 3051 /* Bit 26 : Protection enable for region 58. */
mbed_official 85:e1a8e879a6a9 3052 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
mbed_official 85:e1a8e879a6a9 3053 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
mbed_official 85:e1a8e879a6a9 3054 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3055 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3056 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3057
mbed_official 85:e1a8e879a6a9 3058 /* Bit 25 : Protection enable for region 57. */
mbed_official 85:e1a8e879a6a9 3059 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
mbed_official 85:e1a8e879a6a9 3060 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
mbed_official 85:e1a8e879a6a9 3061 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3062 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3063 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3064
mbed_official 85:e1a8e879a6a9 3065 /* Bit 24 : Protection enable for region 56. */
mbed_official 85:e1a8e879a6a9 3066 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
mbed_official 85:e1a8e879a6a9 3067 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
mbed_official 85:e1a8e879a6a9 3068 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3069 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3070 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3071
mbed_official 85:e1a8e879a6a9 3072 /* Bit 23 : Protection enable for region 55. */
mbed_official 85:e1a8e879a6a9 3073 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
mbed_official 85:e1a8e879a6a9 3074 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
mbed_official 85:e1a8e879a6a9 3075 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3076 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3077 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3078
mbed_official 85:e1a8e879a6a9 3079 /* Bit 22 : Protection enable for region 54. */
mbed_official 85:e1a8e879a6a9 3080 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
mbed_official 85:e1a8e879a6a9 3081 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
mbed_official 85:e1a8e879a6a9 3082 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3083 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3084 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3085
mbed_official 85:e1a8e879a6a9 3086 /* Bit 21 : Protection enable for region 53. */
mbed_official 85:e1a8e879a6a9 3087 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
mbed_official 85:e1a8e879a6a9 3088 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
mbed_official 85:e1a8e879a6a9 3089 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3090 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3091 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3092
mbed_official 85:e1a8e879a6a9 3093 /* Bit 20 : Protection enable for region 52. */
mbed_official 85:e1a8e879a6a9 3094 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
mbed_official 85:e1a8e879a6a9 3095 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
mbed_official 85:e1a8e879a6a9 3096 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3097 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3098 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3099
mbed_official 85:e1a8e879a6a9 3100 /* Bit 19 : Protection enable for region 51. */
mbed_official 85:e1a8e879a6a9 3101 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
mbed_official 85:e1a8e879a6a9 3102 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
mbed_official 85:e1a8e879a6a9 3103 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3104 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3105 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3106
mbed_official 85:e1a8e879a6a9 3107 /* Bit 18 : Protection enable for region 50. */
mbed_official 85:e1a8e879a6a9 3108 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
mbed_official 85:e1a8e879a6a9 3109 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
mbed_official 85:e1a8e879a6a9 3110 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3111 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3112 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3113
mbed_official 85:e1a8e879a6a9 3114 /* Bit 17 : Protection enable for region 49. */
mbed_official 85:e1a8e879a6a9 3115 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
mbed_official 85:e1a8e879a6a9 3116 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
mbed_official 85:e1a8e879a6a9 3117 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3118 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3119 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3120
mbed_official 85:e1a8e879a6a9 3121 /* Bit 16 : Protection enable for region 48. */
mbed_official 85:e1a8e879a6a9 3122 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
mbed_official 85:e1a8e879a6a9 3123 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
mbed_official 85:e1a8e879a6a9 3124 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3125 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3126 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3127
mbed_official 85:e1a8e879a6a9 3128 /* Bit 15 : Protection enable for region 47. */
mbed_official 85:e1a8e879a6a9 3129 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
mbed_official 85:e1a8e879a6a9 3130 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
mbed_official 85:e1a8e879a6a9 3131 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3132 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3133 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3134
mbed_official 85:e1a8e879a6a9 3135 /* Bit 14 : Protection enable for region 46. */
mbed_official 85:e1a8e879a6a9 3136 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
mbed_official 85:e1a8e879a6a9 3137 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
mbed_official 85:e1a8e879a6a9 3138 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3139 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3140 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3141
mbed_official 85:e1a8e879a6a9 3142 /* Bit 13 : Protection enable for region 45. */
mbed_official 85:e1a8e879a6a9 3143 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
mbed_official 85:e1a8e879a6a9 3144 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
mbed_official 85:e1a8e879a6a9 3145 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3146 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3147 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3148
mbed_official 85:e1a8e879a6a9 3149 /* Bit 12 : Protection enable for region 44. */
mbed_official 85:e1a8e879a6a9 3150 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
mbed_official 85:e1a8e879a6a9 3151 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
mbed_official 85:e1a8e879a6a9 3152 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3153 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3154 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3155
mbed_official 85:e1a8e879a6a9 3156 /* Bit 11 : Protection enable for region 43. */
mbed_official 85:e1a8e879a6a9 3157 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
mbed_official 85:e1a8e879a6a9 3158 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
mbed_official 85:e1a8e879a6a9 3159 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3160 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3161 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3162
mbed_official 85:e1a8e879a6a9 3163 /* Bit 10 : Protection enable for region 42. */
mbed_official 85:e1a8e879a6a9 3164 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
mbed_official 85:e1a8e879a6a9 3165 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
mbed_official 85:e1a8e879a6a9 3166 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3167 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3168 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3169
mbed_official 85:e1a8e879a6a9 3170 /* Bit 9 : Protection enable for region 41. */
mbed_official 85:e1a8e879a6a9 3171 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
mbed_official 85:e1a8e879a6a9 3172 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
mbed_official 85:e1a8e879a6a9 3173 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3174 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3175 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3176
mbed_official 85:e1a8e879a6a9 3177 /* Bit 8 : Protection enable for region 40. */
mbed_official 85:e1a8e879a6a9 3178 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
mbed_official 85:e1a8e879a6a9 3179 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
mbed_official 85:e1a8e879a6a9 3180 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3181 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3182 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3183
mbed_official 85:e1a8e879a6a9 3184 /* Bit 7 : Protection enable for region 39. */
mbed_official 85:e1a8e879a6a9 3185 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
mbed_official 85:e1a8e879a6a9 3186 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
mbed_official 85:e1a8e879a6a9 3187 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3188 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3189 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3190
mbed_official 85:e1a8e879a6a9 3191 /* Bit 6 : Protection enable for region 38. */
mbed_official 85:e1a8e879a6a9 3192 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
mbed_official 85:e1a8e879a6a9 3193 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
mbed_official 85:e1a8e879a6a9 3194 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3195 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3196 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3197
mbed_official 85:e1a8e879a6a9 3198 /* Bit 5 : Protection enable for region 37. */
mbed_official 85:e1a8e879a6a9 3199 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
mbed_official 85:e1a8e879a6a9 3200 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
mbed_official 85:e1a8e879a6a9 3201 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3202 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3203 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3204
mbed_official 85:e1a8e879a6a9 3205 /* Bit 4 : Protection enable for region 36. */
mbed_official 85:e1a8e879a6a9 3206 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
mbed_official 85:e1a8e879a6a9 3207 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
mbed_official 85:e1a8e879a6a9 3208 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3209 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3210 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3211
mbed_official 85:e1a8e879a6a9 3212 /* Bit 3 : Protection enable for region 35. */
mbed_official 85:e1a8e879a6a9 3213 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
mbed_official 85:e1a8e879a6a9 3214 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
mbed_official 85:e1a8e879a6a9 3215 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3216 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3217 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3218
mbed_official 85:e1a8e879a6a9 3219 /* Bit 2 : Protection enable for region 34. */
mbed_official 85:e1a8e879a6a9 3220 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
mbed_official 85:e1a8e879a6a9 3221 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
mbed_official 85:e1a8e879a6a9 3222 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3223 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3224 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3225
mbed_official 85:e1a8e879a6a9 3226 /* Bit 1 : Protection enable for region 33. */
mbed_official 85:e1a8e879a6a9 3227 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
mbed_official 85:e1a8e879a6a9 3228 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
mbed_official 85:e1a8e879a6a9 3229 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3230 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3231 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3232
mbed_official 85:e1a8e879a6a9 3233 /* Bit 0 : Protection enable for region 32. */
mbed_official 85:e1a8e879a6a9 3234 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
mbed_official 85:e1a8e879a6a9 3235 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
mbed_official 85:e1a8e879a6a9 3236 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3237 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3238 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
mbed_official 85:e1a8e879a6a9 3239
mbed_official 85:e1a8e879a6a9 3240 /* Register: MPU_DISABLEINDEBUG */
mbed_official 85:e1a8e879a6a9 3241 /* Description: Disable protection mechanism in debug mode. */
mbed_official 85:e1a8e879a6a9 3242
mbed_official 85:e1a8e879a6a9 3243 /* Bit 0 : Disable protection mechanism in debug mode. */
mbed_official 85:e1a8e879a6a9 3244 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
mbed_official 85:e1a8e879a6a9 3245 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
mbed_official 85:e1a8e879a6a9 3246 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
mbed_official 85:e1a8e879a6a9 3247 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
mbed_official 85:e1a8e879a6a9 3248
mbed_official 85:e1a8e879a6a9 3249
mbed_official 85:e1a8e879a6a9 3250 /* Peripheral: NVMC */
mbed_official 85:e1a8e879a6a9 3251 /* Description: Non Volatile Memory Controller. */
mbed_official 85:e1a8e879a6a9 3252
mbed_official 85:e1a8e879a6a9 3253 /* Register: NVMC_READY */
mbed_official 85:e1a8e879a6a9 3254 /* Description: Ready flag. */
mbed_official 85:e1a8e879a6a9 3255
mbed_official 85:e1a8e879a6a9 3256 /* Bit 0 : NVMC ready. */
mbed_official 85:e1a8e879a6a9 3257 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 3258 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 3259 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
mbed_official 85:e1a8e879a6a9 3260 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
mbed_official 85:e1a8e879a6a9 3261
mbed_official 85:e1a8e879a6a9 3262 /* Register: NVMC_CONFIG */
mbed_official 85:e1a8e879a6a9 3263 /* Description: Configuration register. */
mbed_official 85:e1a8e879a6a9 3264
mbed_official 85:e1a8e879a6a9 3265 /* Bits 1..0 : Program write enable. */
mbed_official 85:e1a8e879a6a9 3266 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
mbed_official 85:e1a8e879a6a9 3267 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
mbed_official 85:e1a8e879a6a9 3268 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
mbed_official 85:e1a8e879a6a9 3269 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
mbed_official 85:e1a8e879a6a9 3270 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
mbed_official 85:e1a8e879a6a9 3271
mbed_official 85:e1a8e879a6a9 3272 /* Register: NVMC_ERASEALL */
mbed_official 85:e1a8e879a6a9 3273 /* Description: Register for erasing all non-volatile user memory. */
mbed_official 85:e1a8e879a6a9 3274
mbed_official 85:e1a8e879a6a9 3275 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
mbed_official 85:e1a8e879a6a9 3276 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
mbed_official 85:e1a8e879a6a9 3277 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
mbed_official 85:e1a8e879a6a9 3278 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
mbed_official 85:e1a8e879a6a9 3279 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
mbed_official 85:e1a8e879a6a9 3280
mbed_official 85:e1a8e879a6a9 3281 /* Register: NVMC_ERASEUICR */
mbed_official 85:e1a8e879a6a9 3282 /* Description: Register for start erasing User Information Congfiguration Registers. */
mbed_official 85:e1a8e879a6a9 3283
mbed_official 85:e1a8e879a6a9 3284 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
mbed_official 85:e1a8e879a6a9 3285 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
mbed_official 85:e1a8e879a6a9 3286 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
mbed_official 85:e1a8e879a6a9 3287 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
mbed_official 85:e1a8e879a6a9 3288 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
mbed_official 85:e1a8e879a6a9 3289
mbed_official 85:e1a8e879a6a9 3290
mbed_official 85:e1a8e879a6a9 3291 /* Peripheral: POWER */
mbed_official 85:e1a8e879a6a9 3292 /* Description: Power Control. */
mbed_official 85:e1a8e879a6a9 3293
mbed_official 85:e1a8e879a6a9 3294 /* Register: POWER_INTENSET */
mbed_official 85:e1a8e879a6a9 3295 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 3296
mbed_official 85:e1a8e879a6a9 3297 /* Bit 2 : Enable interrupt on POFWARN event. */
mbed_official 85:e1a8e879a6a9 3298 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
mbed_official 85:e1a8e879a6a9 3299 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
mbed_official 85:e1a8e879a6a9 3300 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 3301 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 3302 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 3303
mbed_official 85:e1a8e879a6a9 3304 /* Register: POWER_INTENCLR */
mbed_official 85:e1a8e879a6a9 3305 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 3306
mbed_official 85:e1a8e879a6a9 3307 /* Bit 2 : Disable interrupt on POFWARN event. */
mbed_official 85:e1a8e879a6a9 3308 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
mbed_official 85:e1a8e879a6a9 3309 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
mbed_official 85:e1a8e879a6a9 3310 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 3311 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 3312 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 3313
mbed_official 85:e1a8e879a6a9 3314 /* Register: POWER_RESETREAS */
mbed_official 85:e1a8e879a6a9 3315 /* Description: Reset reason. */
mbed_official 85:e1a8e879a6a9 3316
mbed_official 85:e1a8e879a6a9 3317 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
mbed_official 85:e1a8e879a6a9 3318 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
mbed_official 85:e1a8e879a6a9 3319 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
mbed_official 85:e1a8e879a6a9 3320
mbed_official 85:e1a8e879a6a9 3321 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
mbed_official 85:e1a8e879a6a9 3322 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
mbed_official 85:e1a8e879a6a9 3323 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
mbed_official 85:e1a8e879a6a9 3324
mbed_official 85:e1a8e879a6a9 3325 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
mbed_official 85:e1a8e879a6a9 3326 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
mbed_official 85:e1a8e879a6a9 3327 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
mbed_official 85:e1a8e879a6a9 3328
mbed_official 85:e1a8e879a6a9 3329 /* Bit 3 : Reset from CPU lock-up detected. */
mbed_official 85:e1a8e879a6a9 3330 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
mbed_official 85:e1a8e879a6a9 3331 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
mbed_official 85:e1a8e879a6a9 3332
mbed_official 85:e1a8e879a6a9 3333 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
mbed_official 85:e1a8e879a6a9 3334 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
mbed_official 85:e1a8e879a6a9 3335 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
mbed_official 85:e1a8e879a6a9 3336
mbed_official 85:e1a8e879a6a9 3337 /* Bit 1 : Reset from watchdog detected. */
mbed_official 85:e1a8e879a6a9 3338 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
mbed_official 85:e1a8e879a6a9 3339 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
mbed_official 85:e1a8e879a6a9 3340
mbed_official 85:e1a8e879a6a9 3341 /* Bit 0 : Reset from pin-reset detected. */
mbed_official 85:e1a8e879a6a9 3342 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
mbed_official 85:e1a8e879a6a9 3343 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
mbed_official 85:e1a8e879a6a9 3344
mbed_official 85:e1a8e879a6a9 3345 /* Register: POWER_SYSTEMOFF */
mbed_official 85:e1a8e879a6a9 3346 /* Description: System off register. */
mbed_official 85:e1a8e879a6a9 3347
mbed_official 85:e1a8e879a6a9 3348 /* Bit 0 : Enter system off mode. */
mbed_official 85:e1a8e879a6a9 3349 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
mbed_official 85:e1a8e879a6a9 3350 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
mbed_official 85:e1a8e879a6a9 3351 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
mbed_official 85:e1a8e879a6a9 3352
mbed_official 85:e1a8e879a6a9 3353 /* Register: POWER_POFCON */
mbed_official 85:e1a8e879a6a9 3354 /* Description: Power failure configuration. */
mbed_official 85:e1a8e879a6a9 3355
mbed_official 85:e1a8e879a6a9 3356 /* Bits 2..1 : Set threshold level. */
mbed_official 85:e1a8e879a6a9 3357 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
mbed_official 85:e1a8e879a6a9 3358 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
mbed_official 85:e1a8e879a6a9 3359 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
mbed_official 85:e1a8e879a6a9 3360 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
mbed_official 85:e1a8e879a6a9 3361 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
mbed_official 85:e1a8e879a6a9 3362 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
mbed_official 85:e1a8e879a6a9 3363
mbed_official 85:e1a8e879a6a9 3364 /* Bit 0 : Power failure comparator enable. */
mbed_official 85:e1a8e879a6a9 3365 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
mbed_official 85:e1a8e879a6a9 3366 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
mbed_official 85:e1a8e879a6a9 3367 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 3368 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 3369
mbed_official 85:e1a8e879a6a9 3370 /* Register: POWER_GPREGRET */
mbed_official 85:e1a8e879a6a9 3371 /* Description: General purpose retention register. This register is a retained register. */
mbed_official 85:e1a8e879a6a9 3372
mbed_official 85:e1a8e879a6a9 3373 /* Bits 7..0 : General purpose retention register. */
mbed_official 85:e1a8e879a6a9 3374 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
mbed_official 85:e1a8e879a6a9 3375 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
mbed_official 85:e1a8e879a6a9 3376
mbed_official 85:e1a8e879a6a9 3377 /* Register: POWER_RAMON */
mbed_official 85:e1a8e879a6a9 3378 /* Description: Ram on/off. */
mbed_official 85:e1a8e879a6a9 3379
mbed_official 85:e1a8e879a6a9 3380 /* Bit 19 : RAM block 3 behaviour in OFF mode. */
mbed_official 85:e1a8e879a6a9 3381 #define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */
mbed_official 85:e1a8e879a6a9 3382 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
mbed_official 85:e1a8e879a6a9 3383 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
mbed_official 85:e1a8e879a6a9 3384 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
mbed_official 85:e1a8e879a6a9 3385
mbed_official 85:e1a8e879a6a9 3386 /* Bit 18 : RAM block 2 behaviour in OFF mode. */
mbed_official 85:e1a8e879a6a9 3387 #define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */
mbed_official 85:e1a8e879a6a9 3388 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
mbed_official 85:e1a8e879a6a9 3389 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
mbed_official 85:e1a8e879a6a9 3390 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
mbed_official 85:e1a8e879a6a9 3391
mbed_official 85:e1a8e879a6a9 3392 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
mbed_official 85:e1a8e879a6a9 3393 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
mbed_official 85:e1a8e879a6a9 3394 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
mbed_official 85:e1a8e879a6a9 3395 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
mbed_official 85:e1a8e879a6a9 3396 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
mbed_official 85:e1a8e879a6a9 3397
mbed_official 85:e1a8e879a6a9 3398 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
mbed_official 85:e1a8e879a6a9 3399 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
mbed_official 85:e1a8e879a6a9 3400 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
mbed_official 85:e1a8e879a6a9 3401 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
mbed_official 85:e1a8e879a6a9 3402 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
mbed_official 85:e1a8e879a6a9 3403
mbed_official 85:e1a8e879a6a9 3404 /* Bit 3 : RAM block 3 behaviour in ON mode. */
mbed_official 85:e1a8e879a6a9 3405 #define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */
mbed_official 85:e1a8e879a6a9 3406 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
mbed_official 85:e1a8e879a6a9 3407 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */
mbed_official 85:e1a8e879a6a9 3408 #define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
mbed_official 85:e1a8e879a6a9 3409
mbed_official 85:e1a8e879a6a9 3410 /* Bit 2 : RAM block 2 behaviour in ON mode. */
mbed_official 85:e1a8e879a6a9 3411 #define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */
mbed_official 85:e1a8e879a6a9 3412 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
mbed_official 85:e1a8e879a6a9 3413 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
mbed_official 85:e1a8e879a6a9 3414 #define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
mbed_official 85:e1a8e879a6a9 3415
mbed_official 85:e1a8e879a6a9 3416 /* Bit 1 : RAM block 1 behaviour in ON mode. */
mbed_official 85:e1a8e879a6a9 3417 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
mbed_official 85:e1a8e879a6a9 3418 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
mbed_official 85:e1a8e879a6a9 3419 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
mbed_official 85:e1a8e879a6a9 3420 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
mbed_official 85:e1a8e879a6a9 3421
mbed_official 85:e1a8e879a6a9 3422 /* Bit 0 : RAM block 0 behaviour in ON mode. */
mbed_official 85:e1a8e879a6a9 3423 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
mbed_official 85:e1a8e879a6a9 3424 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
mbed_official 85:e1a8e879a6a9 3425 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
mbed_official 85:e1a8e879a6a9 3426 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
mbed_official 85:e1a8e879a6a9 3427
mbed_official 85:e1a8e879a6a9 3428 /* Register: POWER_RESET */
mbed_official 85:e1a8e879a6a9 3429 /* Description: Pin reset functionality configuration register. This register is a retained register. */
mbed_official 85:e1a8e879a6a9 3430
mbed_official 85:e1a8e879a6a9 3431 /* Bit 0 : Enable pin reset in debug interface mode. */
mbed_official 85:e1a8e879a6a9 3432 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
mbed_official 85:e1a8e879a6a9 3433 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
mbed_official 85:e1a8e879a6a9 3434 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
mbed_official 85:e1a8e879a6a9 3435 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
mbed_official 85:e1a8e879a6a9 3436
mbed_official 85:e1a8e879a6a9 3437 /* Register: POWER_DCDCEN */
mbed_official 85:e1a8e879a6a9 3438 /* Description: DCDC converter enable configuration register. */
mbed_official 85:e1a8e879a6a9 3439
mbed_official 85:e1a8e879a6a9 3440 /* Bit 0 : Enable DCDC converter. */
mbed_official 85:e1a8e879a6a9 3441 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
mbed_official 85:e1a8e879a6a9 3442 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
mbed_official 85:e1a8e879a6a9 3443 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
mbed_official 85:e1a8e879a6a9 3444 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
mbed_official 85:e1a8e879a6a9 3445
mbed_official 85:e1a8e879a6a9 3446
mbed_official 85:e1a8e879a6a9 3447 /* Peripheral: PPI */
mbed_official 85:e1a8e879a6a9 3448 /* Description: PPI controller. */
mbed_official 85:e1a8e879a6a9 3449
mbed_official 85:e1a8e879a6a9 3450 /* Register: PPI_CHEN */
mbed_official 85:e1a8e879a6a9 3451 /* Description: Channel enable. */
mbed_official 85:e1a8e879a6a9 3452
mbed_official 85:e1a8e879a6a9 3453 /* Bit 31 : Enable PPI channel 31. */
mbed_official 85:e1a8e879a6a9 3454 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
mbed_official 85:e1a8e879a6a9 3455 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
mbed_official 85:e1a8e879a6a9 3456 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3457 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3458
mbed_official 85:e1a8e879a6a9 3459 /* Bit 30 : Enable PPI channel 30. */
mbed_official 85:e1a8e879a6a9 3460 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
mbed_official 85:e1a8e879a6a9 3461 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
mbed_official 85:e1a8e879a6a9 3462 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3463 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3464
mbed_official 85:e1a8e879a6a9 3465 /* Bit 29 : Enable PPI channel 29. */
mbed_official 85:e1a8e879a6a9 3466 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
mbed_official 85:e1a8e879a6a9 3467 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
mbed_official 85:e1a8e879a6a9 3468 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3469 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3470
mbed_official 85:e1a8e879a6a9 3471 /* Bit 28 : Enable PPI channel 28. */
mbed_official 85:e1a8e879a6a9 3472 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
mbed_official 85:e1a8e879a6a9 3473 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
mbed_official 85:e1a8e879a6a9 3474 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3475 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3476
mbed_official 85:e1a8e879a6a9 3477 /* Bit 27 : Enable PPI channel 27. */
mbed_official 85:e1a8e879a6a9 3478 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
mbed_official 85:e1a8e879a6a9 3479 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
mbed_official 85:e1a8e879a6a9 3480 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3481 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3482
mbed_official 85:e1a8e879a6a9 3483 /* Bit 26 : Enable PPI channel 26. */
mbed_official 85:e1a8e879a6a9 3484 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
mbed_official 85:e1a8e879a6a9 3485 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
mbed_official 85:e1a8e879a6a9 3486 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3487 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3488
mbed_official 85:e1a8e879a6a9 3489 /* Bit 25 : Enable PPI channel 25. */
mbed_official 85:e1a8e879a6a9 3490 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
mbed_official 85:e1a8e879a6a9 3491 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
mbed_official 85:e1a8e879a6a9 3492 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3493 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3494
mbed_official 85:e1a8e879a6a9 3495 /* Bit 24 : Enable PPI channel 24. */
mbed_official 85:e1a8e879a6a9 3496 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
mbed_official 85:e1a8e879a6a9 3497 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
mbed_official 85:e1a8e879a6a9 3498 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3499 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3500
mbed_official 85:e1a8e879a6a9 3501 /* Bit 23 : Enable PPI channel 23. */
mbed_official 85:e1a8e879a6a9 3502 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
mbed_official 85:e1a8e879a6a9 3503 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
mbed_official 85:e1a8e879a6a9 3504 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3505 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3506
mbed_official 85:e1a8e879a6a9 3507 /* Bit 22 : Enable PPI channel 22. */
mbed_official 85:e1a8e879a6a9 3508 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
mbed_official 85:e1a8e879a6a9 3509 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
mbed_official 85:e1a8e879a6a9 3510 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3511 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3512
mbed_official 85:e1a8e879a6a9 3513 /* Bit 21 : Enable PPI channel 21. */
mbed_official 85:e1a8e879a6a9 3514 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
mbed_official 85:e1a8e879a6a9 3515 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
mbed_official 85:e1a8e879a6a9 3516 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3517 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3518
mbed_official 85:e1a8e879a6a9 3519 /* Bit 20 : Enable PPI channel 20. */
mbed_official 85:e1a8e879a6a9 3520 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
mbed_official 85:e1a8e879a6a9 3521 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
mbed_official 85:e1a8e879a6a9 3522 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3523 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3524
mbed_official 85:e1a8e879a6a9 3525 /* Bit 15 : Enable PPI channel 15. */
mbed_official 85:e1a8e879a6a9 3526 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
mbed_official 85:e1a8e879a6a9 3527 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
mbed_official 85:e1a8e879a6a9 3528 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3529 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3530
mbed_official 85:e1a8e879a6a9 3531 /* Bit 14 : Enable PPI channel 14. */
mbed_official 85:e1a8e879a6a9 3532 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
mbed_official 85:e1a8e879a6a9 3533 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
mbed_official 85:e1a8e879a6a9 3534 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3535 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3536
mbed_official 85:e1a8e879a6a9 3537 /* Bit 13 : Enable PPI channel 13. */
mbed_official 85:e1a8e879a6a9 3538 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
mbed_official 85:e1a8e879a6a9 3539 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
mbed_official 85:e1a8e879a6a9 3540 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3541 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3542
mbed_official 85:e1a8e879a6a9 3543 /* Bit 12 : Enable PPI channel 12. */
mbed_official 85:e1a8e879a6a9 3544 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
mbed_official 85:e1a8e879a6a9 3545 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
mbed_official 85:e1a8e879a6a9 3546 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3547 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3548
mbed_official 85:e1a8e879a6a9 3549 /* Bit 11 : Enable PPI channel 11. */
mbed_official 85:e1a8e879a6a9 3550 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
mbed_official 85:e1a8e879a6a9 3551 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
mbed_official 85:e1a8e879a6a9 3552 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3553 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3554
mbed_official 85:e1a8e879a6a9 3555 /* Bit 10 : Enable PPI channel 10. */
mbed_official 85:e1a8e879a6a9 3556 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
mbed_official 85:e1a8e879a6a9 3557 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
mbed_official 85:e1a8e879a6a9 3558 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3559 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3560
mbed_official 85:e1a8e879a6a9 3561 /* Bit 9 : Enable PPI channel 9. */
mbed_official 85:e1a8e879a6a9 3562 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
mbed_official 85:e1a8e879a6a9 3563 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
mbed_official 85:e1a8e879a6a9 3564 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3565 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3566
mbed_official 85:e1a8e879a6a9 3567 /* Bit 8 : Enable PPI channel 8. */
mbed_official 85:e1a8e879a6a9 3568 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
mbed_official 85:e1a8e879a6a9 3569 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
mbed_official 85:e1a8e879a6a9 3570 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3571 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3572
mbed_official 85:e1a8e879a6a9 3573 /* Bit 7 : Enable PPI channel 7. */
mbed_official 85:e1a8e879a6a9 3574 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
mbed_official 85:e1a8e879a6a9 3575 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
mbed_official 85:e1a8e879a6a9 3576 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3577 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3578
mbed_official 85:e1a8e879a6a9 3579 /* Bit 6 : Enable PPI channel 6. */
mbed_official 85:e1a8e879a6a9 3580 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
mbed_official 85:e1a8e879a6a9 3581 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
mbed_official 85:e1a8e879a6a9 3582 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3583 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3584
mbed_official 85:e1a8e879a6a9 3585 /* Bit 5 : Enable PPI channel 5. */
mbed_official 85:e1a8e879a6a9 3586 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
mbed_official 85:e1a8e879a6a9 3587 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
mbed_official 85:e1a8e879a6a9 3588 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3589 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3590
mbed_official 85:e1a8e879a6a9 3591 /* Bit 4 : Enable PPI channel 4. */
mbed_official 85:e1a8e879a6a9 3592 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
mbed_official 85:e1a8e879a6a9 3593 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
mbed_official 85:e1a8e879a6a9 3594 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3595 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3596
mbed_official 85:e1a8e879a6a9 3597 /* Bit 3 : Enable PPI channel 3. */
mbed_official 85:e1a8e879a6a9 3598 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
mbed_official 85:e1a8e879a6a9 3599 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
mbed_official 85:e1a8e879a6a9 3600 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
mbed_official 85:e1a8e879a6a9 3601 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
mbed_official 85:e1a8e879a6a9 3602
mbed_official 85:e1a8e879a6a9 3603 /* Bit 2 : Enable PPI channel 2. */
mbed_official 85:e1a8e879a6a9 3604 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
mbed_official 85:e1a8e879a6a9 3605 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
mbed_official 85:e1a8e879a6a9 3606 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3607 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3608
mbed_official 85:e1a8e879a6a9 3609 /* Bit 1 : Enable PPI channel 1. */
mbed_official 85:e1a8e879a6a9 3610 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
mbed_official 85:e1a8e879a6a9 3611 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
mbed_official 85:e1a8e879a6a9 3612 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3613 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3614
mbed_official 85:e1a8e879a6a9 3615 /* Bit 0 : Enable PPI channel 0. */
mbed_official 85:e1a8e879a6a9 3616 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
mbed_official 85:e1a8e879a6a9 3617 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
mbed_official 85:e1a8e879a6a9 3618 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3619 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3620
mbed_official 85:e1a8e879a6a9 3621 /* Register: PPI_CHENSET */
mbed_official 85:e1a8e879a6a9 3622 /* Description: Channel enable set. */
mbed_official 85:e1a8e879a6a9 3623
mbed_official 85:e1a8e879a6a9 3624 /* Bit 31 : Enable PPI channel 31. */
mbed_official 85:e1a8e879a6a9 3625 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
mbed_official 85:e1a8e879a6a9 3626 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
mbed_official 85:e1a8e879a6a9 3627 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3628 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3629 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3630
mbed_official 85:e1a8e879a6a9 3631 /* Bit 30 : Enable PPI channel 30. */
mbed_official 85:e1a8e879a6a9 3632 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
mbed_official 85:e1a8e879a6a9 3633 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
mbed_official 85:e1a8e879a6a9 3634 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3635 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3636 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3637
mbed_official 85:e1a8e879a6a9 3638 /* Bit 29 : Enable PPI channel 29. */
mbed_official 85:e1a8e879a6a9 3639 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
mbed_official 85:e1a8e879a6a9 3640 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
mbed_official 85:e1a8e879a6a9 3641 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3642 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3643 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3644
mbed_official 85:e1a8e879a6a9 3645 /* Bit 28 : Enable PPI channel 28. */
mbed_official 85:e1a8e879a6a9 3646 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
mbed_official 85:e1a8e879a6a9 3647 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
mbed_official 85:e1a8e879a6a9 3648 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3649 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3650 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3651
mbed_official 85:e1a8e879a6a9 3652 /* Bit 27 : Enable PPI channel 27. */
mbed_official 85:e1a8e879a6a9 3653 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
mbed_official 85:e1a8e879a6a9 3654 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
mbed_official 85:e1a8e879a6a9 3655 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3656 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3657 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3658
mbed_official 85:e1a8e879a6a9 3659 /* Bit 26 : Enable PPI channel 26. */
mbed_official 85:e1a8e879a6a9 3660 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
mbed_official 85:e1a8e879a6a9 3661 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
mbed_official 85:e1a8e879a6a9 3662 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3663 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3664 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3665
mbed_official 85:e1a8e879a6a9 3666 /* Bit 25 : Enable PPI channel 25. */
mbed_official 85:e1a8e879a6a9 3667 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
mbed_official 85:e1a8e879a6a9 3668 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
mbed_official 85:e1a8e879a6a9 3669 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3670 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3671 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3672
mbed_official 85:e1a8e879a6a9 3673 /* Bit 24 : Enable PPI channel 24. */
mbed_official 85:e1a8e879a6a9 3674 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
mbed_official 85:e1a8e879a6a9 3675 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
mbed_official 85:e1a8e879a6a9 3676 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3677 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3678 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3679
mbed_official 85:e1a8e879a6a9 3680 /* Bit 23 : Enable PPI channel 23. */
mbed_official 85:e1a8e879a6a9 3681 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
mbed_official 85:e1a8e879a6a9 3682 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
mbed_official 85:e1a8e879a6a9 3683 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3684 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3685 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3686
mbed_official 85:e1a8e879a6a9 3687 /* Bit 22 : Enable PPI channel 22. */
mbed_official 85:e1a8e879a6a9 3688 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
mbed_official 85:e1a8e879a6a9 3689 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
mbed_official 85:e1a8e879a6a9 3690 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3691 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3692 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3693
mbed_official 85:e1a8e879a6a9 3694 /* Bit 21 : Enable PPI channel 21. */
mbed_official 85:e1a8e879a6a9 3695 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
mbed_official 85:e1a8e879a6a9 3696 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
mbed_official 85:e1a8e879a6a9 3697 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3698 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3699 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3700
mbed_official 85:e1a8e879a6a9 3701 /* Bit 20 : Enable PPI channel 20. */
mbed_official 85:e1a8e879a6a9 3702 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
mbed_official 85:e1a8e879a6a9 3703 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
mbed_official 85:e1a8e879a6a9 3704 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3705 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3706 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3707
mbed_official 85:e1a8e879a6a9 3708 /* Bit 15 : Enable PPI channel 15. */
mbed_official 85:e1a8e879a6a9 3709 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
mbed_official 85:e1a8e879a6a9 3710 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
mbed_official 85:e1a8e879a6a9 3711 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3712 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3713 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3714
mbed_official 85:e1a8e879a6a9 3715 /* Bit 14 : Enable PPI channel 14. */
mbed_official 85:e1a8e879a6a9 3716 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
mbed_official 85:e1a8e879a6a9 3717 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
mbed_official 85:e1a8e879a6a9 3718 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3719 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3720 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3721
mbed_official 85:e1a8e879a6a9 3722 /* Bit 13 : Enable PPI channel 13. */
mbed_official 85:e1a8e879a6a9 3723 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
mbed_official 85:e1a8e879a6a9 3724 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
mbed_official 85:e1a8e879a6a9 3725 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3726 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3727 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3728
mbed_official 85:e1a8e879a6a9 3729 /* Bit 12 : Enable PPI channel 12. */
mbed_official 85:e1a8e879a6a9 3730 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
mbed_official 85:e1a8e879a6a9 3731 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
mbed_official 85:e1a8e879a6a9 3732 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3733 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3734 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3735
mbed_official 85:e1a8e879a6a9 3736 /* Bit 11 : Enable PPI channel 11. */
mbed_official 85:e1a8e879a6a9 3737 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
mbed_official 85:e1a8e879a6a9 3738 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
mbed_official 85:e1a8e879a6a9 3739 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3740 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3741 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3742
mbed_official 85:e1a8e879a6a9 3743 /* Bit 10 : Enable PPI channel 10. */
mbed_official 85:e1a8e879a6a9 3744 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
mbed_official 85:e1a8e879a6a9 3745 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
mbed_official 85:e1a8e879a6a9 3746 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3747 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3748 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3749
mbed_official 85:e1a8e879a6a9 3750 /* Bit 9 : Enable PPI channel 9. */
mbed_official 85:e1a8e879a6a9 3751 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
mbed_official 85:e1a8e879a6a9 3752 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
mbed_official 85:e1a8e879a6a9 3753 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3754 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3755 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3756
mbed_official 85:e1a8e879a6a9 3757 /* Bit 8 : Enable PPI channel 8. */
mbed_official 85:e1a8e879a6a9 3758 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
mbed_official 85:e1a8e879a6a9 3759 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
mbed_official 85:e1a8e879a6a9 3760 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3761 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3762 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3763
mbed_official 85:e1a8e879a6a9 3764 /* Bit 7 : Enable PPI channel 7. */
mbed_official 85:e1a8e879a6a9 3765 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
mbed_official 85:e1a8e879a6a9 3766 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
mbed_official 85:e1a8e879a6a9 3767 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3768 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3769 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3770
mbed_official 85:e1a8e879a6a9 3771 /* Bit 6 : Enable PPI channel 6. */
mbed_official 85:e1a8e879a6a9 3772 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
mbed_official 85:e1a8e879a6a9 3773 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
mbed_official 85:e1a8e879a6a9 3774 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3775 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3776 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3777
mbed_official 85:e1a8e879a6a9 3778 /* Bit 5 : Enable PPI channel 5. */
mbed_official 85:e1a8e879a6a9 3779 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
mbed_official 85:e1a8e879a6a9 3780 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
mbed_official 85:e1a8e879a6a9 3781 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3782 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3783 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3784
mbed_official 85:e1a8e879a6a9 3785 /* Bit 4 : Enable PPI channel 4. */
mbed_official 85:e1a8e879a6a9 3786 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
mbed_official 85:e1a8e879a6a9 3787 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
mbed_official 85:e1a8e879a6a9 3788 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3789 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3790 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3791
mbed_official 85:e1a8e879a6a9 3792 /* Bit 3 : Enable PPI channel 3. */
mbed_official 85:e1a8e879a6a9 3793 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
mbed_official 85:e1a8e879a6a9 3794 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
mbed_official 85:e1a8e879a6a9 3795 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3796 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3797 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3798
mbed_official 85:e1a8e879a6a9 3799 /* Bit 2 : Enable PPI channel 2. */
mbed_official 85:e1a8e879a6a9 3800 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
mbed_official 85:e1a8e879a6a9 3801 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
mbed_official 85:e1a8e879a6a9 3802 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3803 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3804 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3805
mbed_official 85:e1a8e879a6a9 3806 /* Bit 1 : Enable PPI channel 1. */
mbed_official 85:e1a8e879a6a9 3807 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
mbed_official 85:e1a8e879a6a9 3808 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
mbed_official 85:e1a8e879a6a9 3809 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3810 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3811 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3812
mbed_official 85:e1a8e879a6a9 3813 /* Bit 0 : Enable PPI channel 0. */
mbed_official 85:e1a8e879a6a9 3814 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
mbed_official 85:e1a8e879a6a9 3815 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
mbed_official 85:e1a8e879a6a9 3816 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3817 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3818 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
mbed_official 85:e1a8e879a6a9 3819
mbed_official 85:e1a8e879a6a9 3820 /* Register: PPI_CHENCLR */
mbed_official 85:e1a8e879a6a9 3821 /* Description: Channel enable clear. */
mbed_official 85:e1a8e879a6a9 3822
mbed_official 85:e1a8e879a6a9 3823 /* Bit 31 : Disable PPI channel 31. */
mbed_official 85:e1a8e879a6a9 3824 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
mbed_official 85:e1a8e879a6a9 3825 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
mbed_official 85:e1a8e879a6a9 3826 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3827 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3828 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3829
mbed_official 85:e1a8e879a6a9 3830 /* Bit 30 : Disable PPI channel 30. */
mbed_official 85:e1a8e879a6a9 3831 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
mbed_official 85:e1a8e879a6a9 3832 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
mbed_official 85:e1a8e879a6a9 3833 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3834 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3835 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3836
mbed_official 85:e1a8e879a6a9 3837 /* Bit 29 : Disable PPI channel 29. */
mbed_official 85:e1a8e879a6a9 3838 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
mbed_official 85:e1a8e879a6a9 3839 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
mbed_official 85:e1a8e879a6a9 3840 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3841 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3842 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3843
mbed_official 85:e1a8e879a6a9 3844 /* Bit 28 : Disable PPI channel 28. */
mbed_official 85:e1a8e879a6a9 3845 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
mbed_official 85:e1a8e879a6a9 3846 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
mbed_official 85:e1a8e879a6a9 3847 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3848 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3849 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3850
mbed_official 85:e1a8e879a6a9 3851 /* Bit 27 : Disable PPI channel 27. */
mbed_official 85:e1a8e879a6a9 3852 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
mbed_official 85:e1a8e879a6a9 3853 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
mbed_official 85:e1a8e879a6a9 3854 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3855 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3856 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3857
mbed_official 85:e1a8e879a6a9 3858 /* Bit 26 : Disable PPI channel 26. */
mbed_official 85:e1a8e879a6a9 3859 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
mbed_official 85:e1a8e879a6a9 3860 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
mbed_official 85:e1a8e879a6a9 3861 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3862 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3863 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3864
mbed_official 85:e1a8e879a6a9 3865 /* Bit 25 : Disable PPI channel 25. */
mbed_official 85:e1a8e879a6a9 3866 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
mbed_official 85:e1a8e879a6a9 3867 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
mbed_official 85:e1a8e879a6a9 3868 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3869 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3870 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3871
mbed_official 85:e1a8e879a6a9 3872 /* Bit 24 : Disable PPI channel 24. */
mbed_official 85:e1a8e879a6a9 3873 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
mbed_official 85:e1a8e879a6a9 3874 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
mbed_official 85:e1a8e879a6a9 3875 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3876 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3877 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3878
mbed_official 85:e1a8e879a6a9 3879 /* Bit 23 : Disable PPI channel 23. */
mbed_official 85:e1a8e879a6a9 3880 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
mbed_official 85:e1a8e879a6a9 3881 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
mbed_official 85:e1a8e879a6a9 3882 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3883 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3884 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3885
mbed_official 85:e1a8e879a6a9 3886 /* Bit 22 : Disable PPI channel 22. */
mbed_official 85:e1a8e879a6a9 3887 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
mbed_official 85:e1a8e879a6a9 3888 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
mbed_official 85:e1a8e879a6a9 3889 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3890 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3891 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3892
mbed_official 85:e1a8e879a6a9 3893 /* Bit 21 : Disable PPI channel 21. */
mbed_official 85:e1a8e879a6a9 3894 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
mbed_official 85:e1a8e879a6a9 3895 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
mbed_official 85:e1a8e879a6a9 3896 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3897 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3898 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3899
mbed_official 85:e1a8e879a6a9 3900 /* Bit 20 : Disable PPI channel 20. */
mbed_official 85:e1a8e879a6a9 3901 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
mbed_official 85:e1a8e879a6a9 3902 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
mbed_official 85:e1a8e879a6a9 3903 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3904 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3905 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3906
mbed_official 85:e1a8e879a6a9 3907 /* Bit 15 : Disable PPI channel 15. */
mbed_official 85:e1a8e879a6a9 3908 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
mbed_official 85:e1a8e879a6a9 3909 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
mbed_official 85:e1a8e879a6a9 3910 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3911 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3912 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3913
mbed_official 85:e1a8e879a6a9 3914 /* Bit 14 : Disable PPI channel 14. */
mbed_official 85:e1a8e879a6a9 3915 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
mbed_official 85:e1a8e879a6a9 3916 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
mbed_official 85:e1a8e879a6a9 3917 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3918 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3919 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3920
mbed_official 85:e1a8e879a6a9 3921 /* Bit 13 : Disable PPI channel 13. */
mbed_official 85:e1a8e879a6a9 3922 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
mbed_official 85:e1a8e879a6a9 3923 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
mbed_official 85:e1a8e879a6a9 3924 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3925 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3926 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3927
mbed_official 85:e1a8e879a6a9 3928 /* Bit 12 : Disable PPI channel 12. */
mbed_official 85:e1a8e879a6a9 3929 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
mbed_official 85:e1a8e879a6a9 3930 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
mbed_official 85:e1a8e879a6a9 3931 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3932 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3933 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3934
mbed_official 85:e1a8e879a6a9 3935 /* Bit 11 : Disable PPI channel 11. */
mbed_official 85:e1a8e879a6a9 3936 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
mbed_official 85:e1a8e879a6a9 3937 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
mbed_official 85:e1a8e879a6a9 3938 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3939 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3940 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3941
mbed_official 85:e1a8e879a6a9 3942 /* Bit 10 : Disable PPI channel 10. */
mbed_official 85:e1a8e879a6a9 3943 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
mbed_official 85:e1a8e879a6a9 3944 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
mbed_official 85:e1a8e879a6a9 3945 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3946 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3947 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3948
mbed_official 85:e1a8e879a6a9 3949 /* Bit 9 : Disable PPI channel 9. */
mbed_official 85:e1a8e879a6a9 3950 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
mbed_official 85:e1a8e879a6a9 3951 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
mbed_official 85:e1a8e879a6a9 3952 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3953 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3954 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3955
mbed_official 85:e1a8e879a6a9 3956 /* Bit 8 : Disable PPI channel 8. */
mbed_official 85:e1a8e879a6a9 3957 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
mbed_official 85:e1a8e879a6a9 3958 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
mbed_official 85:e1a8e879a6a9 3959 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3960 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3961 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3962
mbed_official 85:e1a8e879a6a9 3963 /* Bit 7 : Disable PPI channel 7. */
mbed_official 85:e1a8e879a6a9 3964 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
mbed_official 85:e1a8e879a6a9 3965 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
mbed_official 85:e1a8e879a6a9 3966 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3967 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3968 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3969
mbed_official 85:e1a8e879a6a9 3970 /* Bit 6 : Disable PPI channel 6. */
mbed_official 85:e1a8e879a6a9 3971 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
mbed_official 85:e1a8e879a6a9 3972 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
mbed_official 85:e1a8e879a6a9 3973 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3974 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3975 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3976
mbed_official 85:e1a8e879a6a9 3977 /* Bit 5 : Disable PPI channel 5. */
mbed_official 85:e1a8e879a6a9 3978 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
mbed_official 85:e1a8e879a6a9 3979 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
mbed_official 85:e1a8e879a6a9 3980 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3981 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3982 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3983
mbed_official 85:e1a8e879a6a9 3984 /* Bit 4 : Disable PPI channel 4. */
mbed_official 85:e1a8e879a6a9 3985 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
mbed_official 85:e1a8e879a6a9 3986 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
mbed_official 85:e1a8e879a6a9 3987 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3988 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3989 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3990
mbed_official 85:e1a8e879a6a9 3991 /* Bit 3 : Disable PPI channel 3. */
mbed_official 85:e1a8e879a6a9 3992 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
mbed_official 85:e1a8e879a6a9 3993 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
mbed_official 85:e1a8e879a6a9 3994 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 3995 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 3996 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 3997
mbed_official 85:e1a8e879a6a9 3998 /* Bit 2 : Disable PPI channel 2. */
mbed_official 85:e1a8e879a6a9 3999 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
mbed_official 85:e1a8e879a6a9 4000 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
mbed_official 85:e1a8e879a6a9 4001 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 4002 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 4003 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 4004
mbed_official 85:e1a8e879a6a9 4005 /* Bit 1 : Disable PPI channel 1. */
mbed_official 85:e1a8e879a6a9 4006 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
mbed_official 85:e1a8e879a6a9 4007 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
mbed_official 85:e1a8e879a6a9 4008 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 4009 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 4010 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 4011
mbed_official 85:e1a8e879a6a9 4012 /* Bit 0 : Disable PPI channel 0. */
mbed_official 85:e1a8e879a6a9 4013 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
mbed_official 85:e1a8e879a6a9 4014 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
mbed_official 85:e1a8e879a6a9 4015 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
mbed_official 85:e1a8e879a6a9 4016 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
mbed_official 85:e1a8e879a6a9 4017 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
mbed_official 85:e1a8e879a6a9 4018
mbed_official 85:e1a8e879a6a9 4019 /* Register: PPI_CHG */
mbed_official 85:e1a8e879a6a9 4020 /* Description: Channel group configuration. */
mbed_official 85:e1a8e879a6a9 4021
mbed_official 85:e1a8e879a6a9 4022 /* Bit 31 : Include CH31 in channel group. */
mbed_official 85:e1a8e879a6a9 4023 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
mbed_official 85:e1a8e879a6a9 4024 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
mbed_official 85:e1a8e879a6a9 4025 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4026 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4027
mbed_official 85:e1a8e879a6a9 4028 /* Bit 30 : Include CH30 in channel group. */
mbed_official 85:e1a8e879a6a9 4029 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
mbed_official 85:e1a8e879a6a9 4030 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
mbed_official 85:e1a8e879a6a9 4031 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4032 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4033
mbed_official 85:e1a8e879a6a9 4034 /* Bit 29 : Include CH29 in channel group. */
mbed_official 85:e1a8e879a6a9 4035 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
mbed_official 85:e1a8e879a6a9 4036 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
mbed_official 85:e1a8e879a6a9 4037 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4038 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4039
mbed_official 85:e1a8e879a6a9 4040 /* Bit 28 : Include CH28 in channel group. */
mbed_official 85:e1a8e879a6a9 4041 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
mbed_official 85:e1a8e879a6a9 4042 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
mbed_official 85:e1a8e879a6a9 4043 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4044 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4045
mbed_official 85:e1a8e879a6a9 4046 /* Bit 27 : Include CH27 in channel group. */
mbed_official 85:e1a8e879a6a9 4047 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
mbed_official 85:e1a8e879a6a9 4048 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
mbed_official 85:e1a8e879a6a9 4049 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4050 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4051
mbed_official 85:e1a8e879a6a9 4052 /* Bit 26 : Include CH26 in channel group. */
mbed_official 85:e1a8e879a6a9 4053 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
mbed_official 85:e1a8e879a6a9 4054 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
mbed_official 85:e1a8e879a6a9 4055 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4056 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4057
mbed_official 85:e1a8e879a6a9 4058 /* Bit 25 : Include CH25 in channel group. */
mbed_official 85:e1a8e879a6a9 4059 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
mbed_official 85:e1a8e879a6a9 4060 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
mbed_official 85:e1a8e879a6a9 4061 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4062 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4063
mbed_official 85:e1a8e879a6a9 4064 /* Bit 24 : Include CH24 in channel group. */
mbed_official 85:e1a8e879a6a9 4065 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
mbed_official 85:e1a8e879a6a9 4066 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
mbed_official 85:e1a8e879a6a9 4067 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4068 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4069
mbed_official 85:e1a8e879a6a9 4070 /* Bit 23 : Include CH23 in channel group. */
mbed_official 85:e1a8e879a6a9 4071 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
mbed_official 85:e1a8e879a6a9 4072 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
mbed_official 85:e1a8e879a6a9 4073 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4074 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4075
mbed_official 85:e1a8e879a6a9 4076 /* Bit 22 : Include CH22 in channel group. */
mbed_official 85:e1a8e879a6a9 4077 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
mbed_official 85:e1a8e879a6a9 4078 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
mbed_official 85:e1a8e879a6a9 4079 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4080 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4081
mbed_official 85:e1a8e879a6a9 4082 /* Bit 21 : Include CH21 in channel group. */
mbed_official 85:e1a8e879a6a9 4083 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
mbed_official 85:e1a8e879a6a9 4084 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
mbed_official 85:e1a8e879a6a9 4085 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4086 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4087
mbed_official 85:e1a8e879a6a9 4088 /* Bit 20 : Include CH20 in channel group. */
mbed_official 85:e1a8e879a6a9 4089 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
mbed_official 85:e1a8e879a6a9 4090 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
mbed_official 85:e1a8e879a6a9 4091 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4092 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4093
mbed_official 85:e1a8e879a6a9 4094 /* Bit 15 : Include CH15 in channel group. */
mbed_official 85:e1a8e879a6a9 4095 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
mbed_official 85:e1a8e879a6a9 4096 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
mbed_official 85:e1a8e879a6a9 4097 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4098 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4099
mbed_official 85:e1a8e879a6a9 4100 /* Bit 14 : Include CH14 in channel group. */
mbed_official 85:e1a8e879a6a9 4101 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
mbed_official 85:e1a8e879a6a9 4102 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
mbed_official 85:e1a8e879a6a9 4103 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4104 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4105
mbed_official 85:e1a8e879a6a9 4106 /* Bit 13 : Include CH13 in channel group. */
mbed_official 85:e1a8e879a6a9 4107 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
mbed_official 85:e1a8e879a6a9 4108 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
mbed_official 85:e1a8e879a6a9 4109 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4110 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4111
mbed_official 85:e1a8e879a6a9 4112 /* Bit 12 : Include CH12 in channel group. */
mbed_official 85:e1a8e879a6a9 4113 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
mbed_official 85:e1a8e879a6a9 4114 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
mbed_official 85:e1a8e879a6a9 4115 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4116 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4117
mbed_official 85:e1a8e879a6a9 4118 /* Bit 11 : Include CH11 in channel group. */
mbed_official 85:e1a8e879a6a9 4119 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
mbed_official 85:e1a8e879a6a9 4120 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
mbed_official 85:e1a8e879a6a9 4121 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4122 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4123
mbed_official 85:e1a8e879a6a9 4124 /* Bit 10 : Include CH10 in channel group. */
mbed_official 85:e1a8e879a6a9 4125 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
mbed_official 85:e1a8e879a6a9 4126 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
mbed_official 85:e1a8e879a6a9 4127 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4128 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4129
mbed_official 85:e1a8e879a6a9 4130 /* Bit 9 : Include CH9 in channel group. */
mbed_official 85:e1a8e879a6a9 4131 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
mbed_official 85:e1a8e879a6a9 4132 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
mbed_official 85:e1a8e879a6a9 4133 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4134 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4135
mbed_official 85:e1a8e879a6a9 4136 /* Bit 8 : Include CH8 in channel group. */
mbed_official 85:e1a8e879a6a9 4137 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
mbed_official 85:e1a8e879a6a9 4138 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
mbed_official 85:e1a8e879a6a9 4139 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4140 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4141
mbed_official 85:e1a8e879a6a9 4142 /* Bit 7 : Include CH7 in channel group. */
mbed_official 85:e1a8e879a6a9 4143 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
mbed_official 85:e1a8e879a6a9 4144 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
mbed_official 85:e1a8e879a6a9 4145 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4146 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4147
mbed_official 85:e1a8e879a6a9 4148 /* Bit 6 : Include CH6 in channel group. */
mbed_official 85:e1a8e879a6a9 4149 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
mbed_official 85:e1a8e879a6a9 4150 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
mbed_official 85:e1a8e879a6a9 4151 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4152 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4153
mbed_official 85:e1a8e879a6a9 4154 /* Bit 5 : Include CH5 in channel group. */
mbed_official 85:e1a8e879a6a9 4155 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
mbed_official 85:e1a8e879a6a9 4156 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
mbed_official 85:e1a8e879a6a9 4157 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4158 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4159
mbed_official 85:e1a8e879a6a9 4160 /* Bit 4 : Include CH4 in channel group. */
mbed_official 85:e1a8e879a6a9 4161 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
mbed_official 85:e1a8e879a6a9 4162 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
mbed_official 85:e1a8e879a6a9 4163 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4164 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4165
mbed_official 85:e1a8e879a6a9 4166 /* Bit 3 : Include CH3 in channel group. */
mbed_official 85:e1a8e879a6a9 4167 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
mbed_official 85:e1a8e879a6a9 4168 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
mbed_official 85:e1a8e879a6a9 4169 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4170 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4171
mbed_official 85:e1a8e879a6a9 4172 /* Bit 2 : Include CH2 in channel group. */
mbed_official 85:e1a8e879a6a9 4173 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
mbed_official 85:e1a8e879a6a9 4174 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
mbed_official 85:e1a8e879a6a9 4175 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4176 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4177
mbed_official 85:e1a8e879a6a9 4178 /* Bit 1 : Include CH1 in channel group. */
mbed_official 85:e1a8e879a6a9 4179 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
mbed_official 85:e1a8e879a6a9 4180 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
mbed_official 85:e1a8e879a6a9 4181 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4182 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4183
mbed_official 85:e1a8e879a6a9 4184 /* Bit 0 : Include CH0 in channel group. */
mbed_official 85:e1a8e879a6a9 4185 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
mbed_official 85:e1a8e879a6a9 4186 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
mbed_official 85:e1a8e879a6a9 4187 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
mbed_official 85:e1a8e879a6a9 4188 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
mbed_official 85:e1a8e879a6a9 4189
mbed_official 85:e1a8e879a6a9 4190
mbed_official 85:e1a8e879a6a9 4191 /* Peripheral: PU */
mbed_official 85:e1a8e879a6a9 4192 /* Description: Patch unit. */
mbed_official 85:e1a8e879a6a9 4193
mbed_official 85:e1a8e879a6a9 4194 /* Register: PU_PATCHADDR */
mbed_official 85:e1a8e879a6a9 4195 /* Description: Relative address of patch instructions. */
mbed_official 85:e1a8e879a6a9 4196
mbed_official 85:e1a8e879a6a9 4197 /* Bits 24..0 : Relative address of patch instructions. */
mbed_official 85:e1a8e879a6a9 4198 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
mbed_official 85:e1a8e879a6a9 4199 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
mbed_official 85:e1a8e879a6a9 4200
mbed_official 85:e1a8e879a6a9 4201 /* Register: PU_PATCHEN */
mbed_official 85:e1a8e879a6a9 4202 /* Description: Patch enable register. */
mbed_official 85:e1a8e879a6a9 4203
mbed_official 85:e1a8e879a6a9 4204 /* Bit 7 : Patch 7 enabled. */
mbed_official 85:e1a8e879a6a9 4205 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4206 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4207 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4208 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4209
mbed_official 85:e1a8e879a6a9 4210 /* Bit 6 : Patch 6 enabled. */
mbed_official 85:e1a8e879a6a9 4211 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4212 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4213 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4214 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4215
mbed_official 85:e1a8e879a6a9 4216 /* Bit 5 : Patch 5 enabled. */
mbed_official 85:e1a8e879a6a9 4217 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4218 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4219 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4220 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4221
mbed_official 85:e1a8e879a6a9 4222 /* Bit 4 : Patch 4 enabled. */
mbed_official 85:e1a8e879a6a9 4223 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4224 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4225 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4226 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4227
mbed_official 85:e1a8e879a6a9 4228 /* Bit 3 : Patch 3 enabled. */
mbed_official 85:e1a8e879a6a9 4229 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4230 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4231 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4232 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4233
mbed_official 85:e1a8e879a6a9 4234 /* Bit 2 : Patch 2 enabled. */
mbed_official 85:e1a8e879a6a9 4235 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4236 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4237 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4238 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4239
mbed_official 85:e1a8e879a6a9 4240 /* Bit 1 : Patch 1 enabled. */
mbed_official 85:e1a8e879a6a9 4241 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4242 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4243 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4244 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4245
mbed_official 85:e1a8e879a6a9 4246 /* Bit 0 : Patch 0 enabled. */
mbed_official 85:e1a8e879a6a9 4247 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4248 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4249 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4250 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4251
mbed_official 85:e1a8e879a6a9 4252 /* Register: PU_PATCHENSET */
mbed_official 85:e1a8e879a6a9 4253 /* Description: Patch enable register. */
mbed_official 85:e1a8e879a6a9 4254
mbed_official 85:e1a8e879a6a9 4255 /* Bit 7 : Patch 7 enabled. */
mbed_official 85:e1a8e879a6a9 4256 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4257 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4258 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4259 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4260 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4261
mbed_official 85:e1a8e879a6a9 4262 /* Bit 6 : Patch 6 enabled. */
mbed_official 85:e1a8e879a6a9 4263 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4264 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4265 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4266 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4267 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4268
mbed_official 85:e1a8e879a6a9 4269 /* Bit 5 : Patch 5 enabled. */
mbed_official 85:e1a8e879a6a9 4270 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4271 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4272 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4273 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4274 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4275
mbed_official 85:e1a8e879a6a9 4276 /* Bit 4 : Patch 4 enabled. */
mbed_official 85:e1a8e879a6a9 4277 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4278 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4279 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4280 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4281 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4282
mbed_official 85:e1a8e879a6a9 4283 /* Bit 3 : Patch 3 enabled. */
mbed_official 85:e1a8e879a6a9 4284 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4285 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4286 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4287 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4288 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4289
mbed_official 85:e1a8e879a6a9 4290 /* Bit 2 : Patch 2 enabled. */
mbed_official 85:e1a8e879a6a9 4291 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4292 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4293 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4294 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4295 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4296
mbed_official 85:e1a8e879a6a9 4297 /* Bit 1 : Patch 1 enabled. */
mbed_official 85:e1a8e879a6a9 4298 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4299 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4300 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4301 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4302 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4303
mbed_official 85:e1a8e879a6a9 4304 /* Bit 0 : Patch 0 enabled. */
mbed_official 85:e1a8e879a6a9 4305 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4306 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4307 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4308 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4309 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
mbed_official 85:e1a8e879a6a9 4310
mbed_official 85:e1a8e879a6a9 4311 /* Register: PU_PATCHENCLR */
mbed_official 85:e1a8e879a6a9 4312 /* Description: Patch disable register. */
mbed_official 85:e1a8e879a6a9 4313
mbed_official 85:e1a8e879a6a9 4314 /* Bit 7 : Patch 7 enabled. */
mbed_official 85:e1a8e879a6a9 4315 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4316 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
mbed_official 85:e1a8e879a6a9 4317 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4318 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4319 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4320
mbed_official 85:e1a8e879a6a9 4321 /* Bit 6 : Patch 6 enabled. */
mbed_official 85:e1a8e879a6a9 4322 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4323 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
mbed_official 85:e1a8e879a6a9 4324 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4325 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4326 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4327
mbed_official 85:e1a8e879a6a9 4328 /* Bit 5 : Patch 5 enabled. */
mbed_official 85:e1a8e879a6a9 4329 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4330 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
mbed_official 85:e1a8e879a6a9 4331 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4332 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4333 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4334
mbed_official 85:e1a8e879a6a9 4335 /* Bit 4 : Patch 4 enabled. */
mbed_official 85:e1a8e879a6a9 4336 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4337 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
mbed_official 85:e1a8e879a6a9 4338 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4339 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4340 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4341
mbed_official 85:e1a8e879a6a9 4342 /* Bit 3 : Patch 3 enabled. */
mbed_official 85:e1a8e879a6a9 4343 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4344 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
mbed_official 85:e1a8e879a6a9 4345 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4346 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4347 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4348
mbed_official 85:e1a8e879a6a9 4349 /* Bit 2 : Patch 2 enabled. */
mbed_official 85:e1a8e879a6a9 4350 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4351 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
mbed_official 85:e1a8e879a6a9 4352 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4353 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4354 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4355
mbed_official 85:e1a8e879a6a9 4356 /* Bit 1 : Patch 1 enabled. */
mbed_official 85:e1a8e879a6a9 4357 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4358 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
mbed_official 85:e1a8e879a6a9 4359 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4360 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4361 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4362
mbed_official 85:e1a8e879a6a9 4363 /* Bit 0 : Patch 0 enabled. */
mbed_official 85:e1a8e879a6a9 4364 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4365 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
mbed_official 85:e1a8e879a6a9 4366 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
mbed_official 85:e1a8e879a6a9 4367 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
mbed_official 85:e1a8e879a6a9 4368 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
mbed_official 85:e1a8e879a6a9 4369
mbed_official 85:e1a8e879a6a9 4370
mbed_official 85:e1a8e879a6a9 4371 /* Peripheral: QDEC */
mbed_official 85:e1a8e879a6a9 4372 /* Description: Rotary decoder. */
mbed_official 85:e1a8e879a6a9 4373
mbed_official 85:e1a8e879a6a9 4374 /* Register: QDEC_SHORTS */
mbed_official 85:e1a8e879a6a9 4375 /* Description: Shortcut for the QDEC. */
mbed_official 85:e1a8e879a6a9 4376
mbed_official 85:e1a8e879a6a9 4377 /* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
mbed_official 85:e1a8e879a6a9 4378 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
mbed_official 85:e1a8e879a6a9 4379 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
mbed_official 85:e1a8e879a6a9 4380 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4381 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4382
mbed_official 85:e1a8e879a6a9 4383 /* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
mbed_official 85:e1a8e879a6a9 4384 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
mbed_official 85:e1a8e879a6a9 4385 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
mbed_official 85:e1a8e879a6a9 4386 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4387 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4388
mbed_official 85:e1a8e879a6a9 4389 /* Register: QDEC_INTENSET */
mbed_official 85:e1a8e879a6a9 4390 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 4391
mbed_official 85:e1a8e879a6a9 4392 /* Bit 2 : Enable interrupt on ACCOF event. */
mbed_official 85:e1a8e879a6a9 4393 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
mbed_official 85:e1a8e879a6a9 4394 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
mbed_official 85:e1a8e879a6a9 4395 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4396 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4397 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4398
mbed_official 85:e1a8e879a6a9 4399 /* Bit 1 : Enable interrupt on REPORTRDY event. */
mbed_official 85:e1a8e879a6a9 4400 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
mbed_official 85:e1a8e879a6a9 4401 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
mbed_official 85:e1a8e879a6a9 4402 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4403 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4404 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4405
mbed_official 85:e1a8e879a6a9 4406 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
mbed_official 85:e1a8e879a6a9 4407 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
mbed_official 85:e1a8e879a6a9 4408 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
mbed_official 85:e1a8e879a6a9 4409 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4410 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4411 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4412
mbed_official 85:e1a8e879a6a9 4413 /* Register: QDEC_INTENCLR */
mbed_official 85:e1a8e879a6a9 4414 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 4415
mbed_official 85:e1a8e879a6a9 4416 /* Bit 2 : Disable interrupt on ACCOF event. */
mbed_official 85:e1a8e879a6a9 4417 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
mbed_official 85:e1a8e879a6a9 4418 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
mbed_official 85:e1a8e879a6a9 4419 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4420 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4421 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4422
mbed_official 85:e1a8e879a6a9 4423 /* Bit 1 : Disable interrupt on REPORTRDY event. */
mbed_official 85:e1a8e879a6a9 4424 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
mbed_official 85:e1a8e879a6a9 4425 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
mbed_official 85:e1a8e879a6a9 4426 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4427 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4428 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4429
mbed_official 85:e1a8e879a6a9 4430 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
mbed_official 85:e1a8e879a6a9 4431 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
mbed_official 85:e1a8e879a6a9 4432 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
mbed_official 85:e1a8e879a6a9 4433 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4434 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4435 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4436
mbed_official 85:e1a8e879a6a9 4437 /* Register: QDEC_ENABLE */
mbed_official 85:e1a8e879a6a9 4438 /* Description: Enable the QDEC. */
mbed_official 85:e1a8e879a6a9 4439
mbed_official 85:e1a8e879a6a9 4440 /* Bit 0 : Enable or disable QDEC. */
mbed_official 85:e1a8e879a6a9 4441 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 4442 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 4443 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
mbed_official 85:e1a8e879a6a9 4444 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
mbed_official 85:e1a8e879a6a9 4445
mbed_official 85:e1a8e879a6a9 4446 /* Register: QDEC_LEDPOL */
mbed_official 85:e1a8e879a6a9 4447 /* Description: LED output pin polarity. */
mbed_official 85:e1a8e879a6a9 4448
mbed_official 85:e1a8e879a6a9 4449 /* Bit 0 : LED output pin polarity. */
mbed_official 85:e1a8e879a6a9 4450 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
mbed_official 85:e1a8e879a6a9 4451 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
mbed_official 85:e1a8e879a6a9 4452 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
mbed_official 85:e1a8e879a6a9 4453 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
mbed_official 85:e1a8e879a6a9 4454
mbed_official 85:e1a8e879a6a9 4455 /* Register: QDEC_SAMPLEPER */
mbed_official 85:e1a8e879a6a9 4456 /* Description: Sample period. */
mbed_official 85:e1a8e879a6a9 4457
mbed_official 85:e1a8e879a6a9 4458 /* Bits 2..0 : Sample period. */
mbed_official 85:e1a8e879a6a9 4459 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
mbed_official 85:e1a8e879a6a9 4460 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
mbed_official 85:e1a8e879a6a9 4461 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
mbed_official 85:e1a8e879a6a9 4462 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
mbed_official 85:e1a8e879a6a9 4463 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
mbed_official 85:e1a8e879a6a9 4464 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
mbed_official 85:e1a8e879a6a9 4465 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
mbed_official 85:e1a8e879a6a9 4466 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
mbed_official 85:e1a8e879a6a9 4467 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
mbed_official 85:e1a8e879a6a9 4468 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
mbed_official 85:e1a8e879a6a9 4469
mbed_official 85:e1a8e879a6a9 4470 /* Register: QDEC_SAMPLE */
mbed_official 85:e1a8e879a6a9 4471 /* Description: Motion sample value. */
mbed_official 85:e1a8e879a6a9 4472
mbed_official 85:e1a8e879a6a9 4473 /* Bits 31..0 : Last sample taken in compliment to 2. */
mbed_official 85:e1a8e879a6a9 4474 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
mbed_official 85:e1a8e879a6a9 4475 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
mbed_official 85:e1a8e879a6a9 4476
mbed_official 85:e1a8e879a6a9 4477 /* Register: QDEC_REPORTPER */
mbed_official 85:e1a8e879a6a9 4478 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
mbed_official 85:e1a8e879a6a9 4479
mbed_official 85:e1a8e879a6a9 4480 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
mbed_official 85:e1a8e879a6a9 4481 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
mbed_official 85:e1a8e879a6a9 4482 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
mbed_official 85:e1a8e879a6a9 4483 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
mbed_official 85:e1a8e879a6a9 4484 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
mbed_official 85:e1a8e879a6a9 4485 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
mbed_official 85:e1a8e879a6a9 4486 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
mbed_official 85:e1a8e879a6a9 4487 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
mbed_official 85:e1a8e879a6a9 4488 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
mbed_official 85:e1a8e879a6a9 4489 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
mbed_official 85:e1a8e879a6a9 4490 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
mbed_official 85:e1a8e879a6a9 4491
mbed_official 85:e1a8e879a6a9 4492 /* Register: QDEC_DBFEN */
mbed_official 85:e1a8e879a6a9 4493 /* Description: Enable debouncer input filters. */
mbed_official 85:e1a8e879a6a9 4494
mbed_official 85:e1a8e879a6a9 4495 /* Bit 0 : Enable debounce input filters. */
mbed_official 85:e1a8e879a6a9 4496 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
mbed_official 85:e1a8e879a6a9 4497 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
mbed_official 85:e1a8e879a6a9 4498 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
mbed_official 85:e1a8e879a6a9 4499 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
mbed_official 85:e1a8e879a6a9 4500
mbed_official 85:e1a8e879a6a9 4501 /* Register: QDEC_LEDPRE */
mbed_official 85:e1a8e879a6a9 4502 /* Description: Time LED is switched ON before the sample. */
mbed_official 85:e1a8e879a6a9 4503
mbed_official 85:e1a8e879a6a9 4504 /* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
mbed_official 85:e1a8e879a6a9 4505 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
mbed_official 85:e1a8e879a6a9 4506 #define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
mbed_official 85:e1a8e879a6a9 4507
mbed_official 85:e1a8e879a6a9 4508 /* Register: QDEC_ACCDBL */
mbed_official 85:e1a8e879a6a9 4509 /* Description: Accumulated double (error) transitions register. */
mbed_official 85:e1a8e879a6a9 4510
mbed_official 85:e1a8e879a6a9 4511 /* Bits 3..0 : Accumulated double (error) transitions. */
mbed_official 85:e1a8e879a6a9 4512 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
mbed_official 85:e1a8e879a6a9 4513 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
mbed_official 85:e1a8e879a6a9 4514
mbed_official 85:e1a8e879a6a9 4515 /* Register: QDEC_ACCDBLREAD */
mbed_official 85:e1a8e879a6a9 4516 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
mbed_official 85:e1a8e879a6a9 4517
mbed_official 85:e1a8e879a6a9 4518 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
mbed_official 85:e1a8e879a6a9 4519 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
mbed_official 85:e1a8e879a6a9 4520 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
mbed_official 85:e1a8e879a6a9 4521
mbed_official 85:e1a8e879a6a9 4522 /* Register: QDEC_POWER */
mbed_official 85:e1a8e879a6a9 4523 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 4524
mbed_official 85:e1a8e879a6a9 4525 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 4526 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 4527 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 4528 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 4529 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 4530
mbed_official 85:e1a8e879a6a9 4531
mbed_official 85:e1a8e879a6a9 4532 /* Peripheral: RADIO */
mbed_official 85:e1a8e879a6a9 4533 /* Description: The radio. */
mbed_official 85:e1a8e879a6a9 4534
mbed_official 85:e1a8e879a6a9 4535 /* Register: RADIO_SHORTS */
mbed_official 85:e1a8e879a6a9 4536 /* Description: Shortcut for the radio. */
mbed_official 85:e1a8e879a6a9 4537
mbed_official 85:e1a8e879a6a9 4538 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
mbed_official 85:e1a8e879a6a9 4539 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
mbed_official 85:e1a8e879a6a9 4540 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
mbed_official 85:e1a8e879a6a9 4541 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4542 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4543
mbed_official 85:e1a8e879a6a9 4544 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
mbed_official 85:e1a8e879a6a9 4545 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
mbed_official 85:e1a8e879a6a9 4546 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
mbed_official 85:e1a8e879a6a9 4547 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4548 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4549
mbed_official 85:e1a8e879a6a9 4550 /* Bit 5 : Shortcut between END event and START task. */
mbed_official 85:e1a8e879a6a9 4551 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
mbed_official 85:e1a8e879a6a9 4552 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
mbed_official 85:e1a8e879a6a9 4553 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4554 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4555
mbed_official 85:e1a8e879a6a9 4556 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
mbed_official 85:e1a8e879a6a9 4557 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
mbed_official 85:e1a8e879a6a9 4558 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
mbed_official 85:e1a8e879a6a9 4559 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4560 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4561
mbed_official 85:e1a8e879a6a9 4562 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
mbed_official 85:e1a8e879a6a9 4563 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
mbed_official 85:e1a8e879a6a9 4564 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
mbed_official 85:e1a8e879a6a9 4565 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4566 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4567
mbed_official 85:e1a8e879a6a9 4568 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
mbed_official 85:e1a8e879a6a9 4569 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
mbed_official 85:e1a8e879a6a9 4570 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
mbed_official 85:e1a8e879a6a9 4571 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4572 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4573
mbed_official 85:e1a8e879a6a9 4574 /* Bit 1 : Shortcut between END event and DISABLE task. */
mbed_official 85:e1a8e879a6a9 4575 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
mbed_official 85:e1a8e879a6a9 4576 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
mbed_official 85:e1a8e879a6a9 4577 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4578 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4579
mbed_official 85:e1a8e879a6a9 4580 /* Bit 0 : Shortcut between READY event and START task. */
mbed_official 85:e1a8e879a6a9 4581 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
mbed_official 85:e1a8e879a6a9 4582 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
mbed_official 85:e1a8e879a6a9 4583 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 4584 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 4585
mbed_official 85:e1a8e879a6a9 4586 /* Register: RADIO_INTENSET */
mbed_official 85:e1a8e879a6a9 4587 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 4588
mbed_official 85:e1a8e879a6a9 4589 /* Bit 10 : Enable interrupt on BCMATCH event. */
mbed_official 85:e1a8e879a6a9 4590 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
mbed_official 85:e1a8e879a6a9 4591 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
mbed_official 85:e1a8e879a6a9 4592 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4593 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4594 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4595
mbed_official 85:e1a8e879a6a9 4596 /* Bit 7 : Enable interrupt on RSSIEND event. */
mbed_official 85:e1a8e879a6a9 4597 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
mbed_official 85:e1a8e879a6a9 4598 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
mbed_official 85:e1a8e879a6a9 4599 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4600 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4601 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4602
mbed_official 85:e1a8e879a6a9 4603 /* Bit 6 : Enable interrupt on DEVMISS event. */
mbed_official 85:e1a8e879a6a9 4604 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
mbed_official 85:e1a8e879a6a9 4605 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
mbed_official 85:e1a8e879a6a9 4606 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4607 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4608 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4609
mbed_official 85:e1a8e879a6a9 4610 /* Bit 5 : Enable interrupt on DEVMATCH event. */
mbed_official 85:e1a8e879a6a9 4611 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
mbed_official 85:e1a8e879a6a9 4612 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
mbed_official 85:e1a8e879a6a9 4613 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4614 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4615 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4616
mbed_official 85:e1a8e879a6a9 4617 /* Bit 4 : Enable interrupt on DISABLED event. */
mbed_official 85:e1a8e879a6a9 4618 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
mbed_official 85:e1a8e879a6a9 4619 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
mbed_official 85:e1a8e879a6a9 4620 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4621 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4622 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4623
mbed_official 85:e1a8e879a6a9 4624 /* Bit 3 : Enable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 4625 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 4626 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 4627 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4628 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4629 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4630
mbed_official 85:e1a8e879a6a9 4631 /* Bit 2 : Enable interrupt on PAYLOAD event. */
mbed_official 85:e1a8e879a6a9 4632 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
mbed_official 85:e1a8e879a6a9 4633 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
mbed_official 85:e1a8e879a6a9 4634 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4635 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4636 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4637
mbed_official 85:e1a8e879a6a9 4638 /* Bit 1 : Enable interrupt on ADDRESS event. */
mbed_official 85:e1a8e879a6a9 4639 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 4640 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 4641 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4642 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4643 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4644
mbed_official 85:e1a8e879a6a9 4645 /* Bit 0 : Enable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 4646 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 4647 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 4648 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4649 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4650 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4651
mbed_official 85:e1a8e879a6a9 4652 /* Register: RADIO_INTENCLR */
mbed_official 85:e1a8e879a6a9 4653 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 4654
mbed_official 85:e1a8e879a6a9 4655 /* Bit 10 : Disable interrupt on BCMATCH event. */
mbed_official 85:e1a8e879a6a9 4656 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
mbed_official 85:e1a8e879a6a9 4657 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
mbed_official 85:e1a8e879a6a9 4658 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4659 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4660 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4661
mbed_official 85:e1a8e879a6a9 4662 /* Bit 7 : Disable interrupt on RSSIEND event. */
mbed_official 85:e1a8e879a6a9 4663 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
mbed_official 85:e1a8e879a6a9 4664 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
mbed_official 85:e1a8e879a6a9 4665 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4666 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4667 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4668
mbed_official 85:e1a8e879a6a9 4669 /* Bit 6 : Disable interrupt on DEVMISS event. */
mbed_official 85:e1a8e879a6a9 4670 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
mbed_official 85:e1a8e879a6a9 4671 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
mbed_official 85:e1a8e879a6a9 4672 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4673 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4674 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4675
mbed_official 85:e1a8e879a6a9 4676 /* Bit 5 : Disable interrupt on DEVMATCH event. */
mbed_official 85:e1a8e879a6a9 4677 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
mbed_official 85:e1a8e879a6a9 4678 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
mbed_official 85:e1a8e879a6a9 4679 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4680 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4681 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4682
mbed_official 85:e1a8e879a6a9 4683 /* Bit 4 : Disable interrupt on DISABLED event. */
mbed_official 85:e1a8e879a6a9 4684 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
mbed_official 85:e1a8e879a6a9 4685 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
mbed_official 85:e1a8e879a6a9 4686 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4687 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4688 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4689
mbed_official 85:e1a8e879a6a9 4690 /* Bit 3 : Disable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 4691 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 4692 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 4693 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4694 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4695 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4696
mbed_official 85:e1a8e879a6a9 4697 /* Bit 2 : Disable interrupt on PAYLOAD event. */
mbed_official 85:e1a8e879a6a9 4698 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
mbed_official 85:e1a8e879a6a9 4699 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
mbed_official 85:e1a8e879a6a9 4700 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4701 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4702 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4703
mbed_official 85:e1a8e879a6a9 4704 /* Bit 1 : Disable interrupt on ADDRESS event. */
mbed_official 85:e1a8e879a6a9 4705 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 4706 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 4707 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4708 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4709 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4710
mbed_official 85:e1a8e879a6a9 4711 /* Bit 0 : Disable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 4712 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 4713 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 4714 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 4715 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 4716 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 4717
mbed_official 85:e1a8e879a6a9 4718 /* Register: RADIO_CRCSTATUS */
mbed_official 85:e1a8e879a6a9 4719 /* Description: CRC status of received packet. */
mbed_official 85:e1a8e879a6a9 4720
mbed_official 85:e1a8e879a6a9 4721 /* Bit 0 : CRC status of received packet. */
mbed_official 85:e1a8e879a6a9 4722 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
mbed_official 85:e1a8e879a6a9 4723 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
mbed_official 85:e1a8e879a6a9 4724 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
mbed_official 85:e1a8e879a6a9 4725 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
mbed_official 85:e1a8e879a6a9 4726
mbed_official 85:e1a8e879a6a9 4727 /* Register: RADIO_RXMATCH */
mbed_official 85:e1a8e879a6a9 4728 /* Description: Received address. */
mbed_official 85:e1a8e879a6a9 4729
mbed_official 85:e1a8e879a6a9 4730 /* Bits 2..0 : Logical address in which previous packet was received. */
mbed_official 85:e1a8e879a6a9 4731 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
mbed_official 85:e1a8e879a6a9 4732 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
mbed_official 85:e1a8e879a6a9 4733
mbed_official 85:e1a8e879a6a9 4734 /* Register: RADIO_RXCRC */
mbed_official 85:e1a8e879a6a9 4735 /* Description: Received CRC. */
mbed_official 85:e1a8e879a6a9 4736
mbed_official 85:e1a8e879a6a9 4737 /* Bits 23..0 : CRC field of previously received packet. */
mbed_official 85:e1a8e879a6a9 4738 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
mbed_official 85:e1a8e879a6a9 4739 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
mbed_official 85:e1a8e879a6a9 4740
mbed_official 85:e1a8e879a6a9 4741 /* Register: RADIO_DAI */
mbed_official 85:e1a8e879a6a9 4742 /* Description: Device address match index. */
mbed_official 85:e1a8e879a6a9 4743
mbed_official 85:e1a8e879a6a9 4744 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
mbed_official 85:e1a8e879a6a9 4745 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
mbed_official 85:e1a8e879a6a9 4746 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
mbed_official 85:e1a8e879a6a9 4747
mbed_official 85:e1a8e879a6a9 4748 /* Register: RADIO_FREQUENCY */
mbed_official 85:e1a8e879a6a9 4749 /* Description: Frequency. */
mbed_official 85:e1a8e879a6a9 4750
mbed_official 85:e1a8e879a6a9 4751 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
mbed_official 85:e1a8e879a6a9 4752 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 4753 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 4754
mbed_official 85:e1a8e879a6a9 4755 /* Register: RADIO_TXPOWER */
mbed_official 85:e1a8e879a6a9 4756 /* Description: Output power. */
mbed_official 85:e1a8e879a6a9 4757
mbed_official 85:e1a8e879a6a9 4758 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
mbed_official 85:e1a8e879a6a9 4759 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
mbed_official 85:e1a8e879a6a9 4760 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
mbed_official 85:e1a8e879a6a9 4761 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
mbed_official 85:e1a8e879a6a9 4762 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
mbed_official 85:e1a8e879a6a9 4763 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
mbed_official 85:e1a8e879a6a9 4764 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
mbed_official 85:e1a8e879a6a9 4765 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
mbed_official 85:e1a8e879a6a9 4766 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
mbed_official 85:e1a8e879a6a9 4767 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
mbed_official 85:e1a8e879a6a9 4768 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
mbed_official 85:e1a8e879a6a9 4769
mbed_official 85:e1a8e879a6a9 4770 /* Register: RADIO_MODE */
mbed_official 85:e1a8e879a6a9 4771 /* Description: Data rate and modulation. */
mbed_official 85:e1a8e879a6a9 4772
mbed_official 85:e1a8e879a6a9 4773 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
mbed_official 85:e1a8e879a6a9 4774 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
mbed_official 85:e1a8e879a6a9 4775 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
mbed_official 85:e1a8e879a6a9 4776 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
mbed_official 85:e1a8e879a6a9 4777 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
mbed_official 85:e1a8e879a6a9 4778 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
mbed_official 85:e1a8e879a6a9 4779 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
mbed_official 85:e1a8e879a6a9 4780
mbed_official 85:e1a8e879a6a9 4781 /* Register: RADIO_PCNF0 */
mbed_official 85:e1a8e879a6a9 4782 /* Description: Packet configuration 0. */
mbed_official 85:e1a8e879a6a9 4783
mbed_official 85:e1a8e879a6a9 4784 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4785 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
mbed_official 85:e1a8e879a6a9 4786 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
mbed_official 85:e1a8e879a6a9 4787
mbed_official 85:e1a8e879a6a9 4788 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4789 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
mbed_official 85:e1a8e879a6a9 4790 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
mbed_official 85:e1a8e879a6a9 4791
mbed_official 85:e1a8e879a6a9 4792 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4793 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
mbed_official 85:e1a8e879a6a9 4794 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
mbed_official 85:e1a8e879a6a9 4795
mbed_official 85:e1a8e879a6a9 4796 /* Register: RADIO_PCNF1 */
mbed_official 85:e1a8e879a6a9 4797 /* Description: Packet configuration 1. */
mbed_official 85:e1a8e879a6a9 4798
mbed_official 85:e1a8e879a6a9 4799 /* Bit 25 : Packet whitening enable. */
mbed_official 85:e1a8e879a6a9 4800 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
mbed_official 85:e1a8e879a6a9 4801 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
mbed_official 85:e1a8e879a6a9 4802 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
mbed_official 85:e1a8e879a6a9 4803 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
mbed_official 85:e1a8e879a6a9 4804
mbed_official 85:e1a8e879a6a9 4805 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4806 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
mbed_official 85:e1a8e879a6a9 4807 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
mbed_official 85:e1a8e879a6a9 4808 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
mbed_official 85:e1a8e879a6a9 4809 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
mbed_official 85:e1a8e879a6a9 4810
mbed_official 85:e1a8e879a6a9 4811 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4812 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
mbed_official 85:e1a8e879a6a9 4813 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
mbed_official 85:e1a8e879a6a9 4814
mbed_official 85:e1a8e879a6a9 4815 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4816 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
mbed_official 85:e1a8e879a6a9 4817 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
mbed_official 85:e1a8e879a6a9 4818
mbed_official 85:e1a8e879a6a9 4819 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
mbed_official 85:e1a8e879a6a9 4820 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
mbed_official 85:e1a8e879a6a9 4821 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
mbed_official 85:e1a8e879a6a9 4822
mbed_official 85:e1a8e879a6a9 4823 /* Register: RADIO_PREFIX0 */
mbed_official 85:e1a8e879a6a9 4824 /* Description: Prefixes bytes for logical addresses 0 to 3. */
mbed_official 85:e1a8e879a6a9 4825
mbed_official 85:e1a8e879a6a9 4826 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4827 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
mbed_official 85:e1a8e879a6a9 4828 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
mbed_official 85:e1a8e879a6a9 4829
mbed_official 85:e1a8e879a6a9 4830 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4831 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
mbed_official 85:e1a8e879a6a9 4832 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
mbed_official 85:e1a8e879a6a9 4833
mbed_official 85:e1a8e879a6a9 4834 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4835 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
mbed_official 85:e1a8e879a6a9 4836 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
mbed_official 85:e1a8e879a6a9 4837
mbed_official 85:e1a8e879a6a9 4838 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4839 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
mbed_official 85:e1a8e879a6a9 4840 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
mbed_official 85:e1a8e879a6a9 4841
mbed_official 85:e1a8e879a6a9 4842 /* Register: RADIO_PREFIX1 */
mbed_official 85:e1a8e879a6a9 4843 /* Description: Prefixes bytes for logical addresses 4 to 7. */
mbed_official 85:e1a8e879a6a9 4844
mbed_official 85:e1a8e879a6a9 4845 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4846 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
mbed_official 85:e1a8e879a6a9 4847 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
mbed_official 85:e1a8e879a6a9 4848
mbed_official 85:e1a8e879a6a9 4849 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4850 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
mbed_official 85:e1a8e879a6a9 4851 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
mbed_official 85:e1a8e879a6a9 4852
mbed_official 85:e1a8e879a6a9 4853 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4854 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
mbed_official 85:e1a8e879a6a9 4855 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
mbed_official 85:e1a8e879a6a9 4856
mbed_official 85:e1a8e879a6a9 4857 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4858 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
mbed_official 85:e1a8e879a6a9 4859 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
mbed_official 85:e1a8e879a6a9 4860
mbed_official 85:e1a8e879a6a9 4861 /* Register: RADIO_TXADDRESS */
mbed_official 85:e1a8e879a6a9 4862 /* Description: Transmit address select. */
mbed_official 85:e1a8e879a6a9 4863
mbed_official 85:e1a8e879a6a9 4864 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4865 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
mbed_official 85:e1a8e879a6a9 4866 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
mbed_official 85:e1a8e879a6a9 4867
mbed_official 85:e1a8e879a6a9 4868 /* Register: RADIO_RXADDRESSES */
mbed_official 85:e1a8e879a6a9 4869 /* Description: Receive address select. */
mbed_official 85:e1a8e879a6a9 4870
mbed_official 85:e1a8e879a6a9 4871 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4872 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
mbed_official 85:e1a8e879a6a9 4873 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
mbed_official 85:e1a8e879a6a9 4874 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4875 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4876
mbed_official 85:e1a8e879a6a9 4877 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4878 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
mbed_official 85:e1a8e879a6a9 4879 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
mbed_official 85:e1a8e879a6a9 4880 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4881 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4882
mbed_official 85:e1a8e879a6a9 4883 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4884 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
mbed_official 85:e1a8e879a6a9 4885 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
mbed_official 85:e1a8e879a6a9 4886 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4887 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4888
mbed_official 85:e1a8e879a6a9 4889 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4890 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
mbed_official 85:e1a8e879a6a9 4891 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
mbed_official 85:e1a8e879a6a9 4892 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4893 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4894
mbed_official 85:e1a8e879a6a9 4895 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4896 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
mbed_official 85:e1a8e879a6a9 4897 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
mbed_official 85:e1a8e879a6a9 4898 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4899 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4900
mbed_official 85:e1a8e879a6a9 4901 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4902 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
mbed_official 85:e1a8e879a6a9 4903 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
mbed_official 85:e1a8e879a6a9 4904 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4905 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4906
mbed_official 85:e1a8e879a6a9 4907 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4908 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
mbed_official 85:e1a8e879a6a9 4909 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
mbed_official 85:e1a8e879a6a9 4910 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4911 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4912
mbed_official 85:e1a8e879a6a9 4913 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4914 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
mbed_official 85:e1a8e879a6a9 4915 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
mbed_official 85:e1a8e879a6a9 4916 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
mbed_official 85:e1a8e879a6a9 4917 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
mbed_official 85:e1a8e879a6a9 4918
mbed_official 85:e1a8e879a6a9 4919 /* Register: RADIO_CRCCNF */
mbed_official 85:e1a8e879a6a9 4920 /* Description: CRC configuration. */
mbed_official 85:e1a8e879a6a9 4921
mbed_official 85:e1a8e879a6a9 4922 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4923 #define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */
mbed_official 85:e1a8e879a6a9 4924 #define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */
mbed_official 85:e1a8e879a6a9 4925 #define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
mbed_official 85:e1a8e879a6a9 4926 #define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
mbed_official 85:e1a8e879a6a9 4927
mbed_official 85:e1a8e879a6a9 4928 /* Bits 1..0 : CRC length. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4929 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
mbed_official 85:e1a8e879a6a9 4930 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
mbed_official 85:e1a8e879a6a9 4931 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
mbed_official 85:e1a8e879a6a9 4932 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
mbed_official 85:e1a8e879a6a9 4933 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
mbed_official 85:e1a8e879a6a9 4934 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
mbed_official 85:e1a8e879a6a9 4935
mbed_official 85:e1a8e879a6a9 4936 /* Register: RADIO_CRCPOLY */
mbed_official 85:e1a8e879a6a9 4937 /* Description: CRC polynomial. */
mbed_official 85:e1a8e879a6a9 4938
mbed_official 85:e1a8e879a6a9 4939 /* Bits 23..1 : CRC polynomial. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4940 #define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */
mbed_official 85:e1a8e879a6a9 4941 #define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
mbed_official 85:e1a8e879a6a9 4942
mbed_official 85:e1a8e879a6a9 4943 /* Register: RADIO_CRCINIT */
mbed_official 85:e1a8e879a6a9 4944 /* Description: CRC initial value. */
mbed_official 85:e1a8e879a6a9 4945
mbed_official 85:e1a8e879a6a9 4946 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 4947 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
mbed_official 85:e1a8e879a6a9 4948 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
mbed_official 85:e1a8e879a6a9 4949
mbed_official 85:e1a8e879a6a9 4950 /* Register: RADIO_TEST */
mbed_official 85:e1a8e879a6a9 4951 /* Description: Test features enable register. */
mbed_official 85:e1a8e879a6a9 4952
mbed_official 85:e1a8e879a6a9 4953 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
mbed_official 85:e1a8e879a6a9 4954 #define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */
mbed_official 85:e1a8e879a6a9 4955 #define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */
mbed_official 85:e1a8e879a6a9 4956 #define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */
mbed_official 85:e1a8e879a6a9 4957 #define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */
mbed_official 85:e1a8e879a6a9 4958
mbed_official 85:e1a8e879a6a9 4959 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
mbed_official 85:e1a8e879a6a9 4960 #define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */
mbed_official 85:e1a8e879a6a9 4961 #define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */
mbed_official 85:e1a8e879a6a9 4962 #define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
mbed_official 85:e1a8e879a6a9 4963 #define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
mbed_official 85:e1a8e879a6a9 4964
mbed_official 85:e1a8e879a6a9 4965 /* Register: RADIO_TIFS */
mbed_official 85:e1a8e879a6a9 4966 /* Description: Inter Frame Spacing in microseconds. */
mbed_official 85:e1a8e879a6a9 4967
mbed_official 85:e1a8e879a6a9 4968 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
mbed_official 85:e1a8e879a6a9 4969 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
mbed_official 85:e1a8e879a6a9 4970 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
mbed_official 85:e1a8e879a6a9 4971
mbed_official 85:e1a8e879a6a9 4972 /* Register: RADIO_RSSISAMPLE */
mbed_official 85:e1a8e879a6a9 4973 /* Description: RSSI sample. */
mbed_official 85:e1a8e879a6a9 4974
mbed_official 85:e1a8e879a6a9 4975 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
mbed_official 85:e1a8e879a6a9 4976 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
mbed_official 85:e1a8e879a6a9 4977 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
mbed_official 85:e1a8e879a6a9 4978
mbed_official 85:e1a8e879a6a9 4979 /* Register: RADIO_STATE */
mbed_official 85:e1a8e879a6a9 4980 /* Description: Current radio state. */
mbed_official 85:e1a8e879a6a9 4981
mbed_official 85:e1a8e879a6a9 4982 /* Bits 3..0 : Current radio state. */
mbed_official 85:e1a8e879a6a9 4983 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
mbed_official 85:e1a8e879a6a9 4984 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
mbed_official 85:e1a8e879a6a9 4985 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
mbed_official 85:e1a8e879a6a9 4986 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
mbed_official 85:e1a8e879a6a9 4987 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
mbed_official 85:e1a8e879a6a9 4988 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
mbed_official 85:e1a8e879a6a9 4989 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
mbed_official 85:e1a8e879a6a9 4990 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
mbed_official 85:e1a8e879a6a9 4991 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
mbed_official 85:e1a8e879a6a9 4992 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
mbed_official 85:e1a8e879a6a9 4993 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
mbed_official 85:e1a8e879a6a9 4994
mbed_official 85:e1a8e879a6a9 4995 /* Register: RADIO_DATAWHITEIV */
mbed_official 85:e1a8e879a6a9 4996 /* Description: Data whitening initial value. */
mbed_official 85:e1a8e879a6a9 4997
mbed_official 85:e1a8e879a6a9 4998 /* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
mbed_official 85:e1a8e879a6a9 4999 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
mbed_official 85:e1a8e879a6a9 5000 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
mbed_official 85:e1a8e879a6a9 5001
mbed_official 85:e1a8e879a6a9 5002 /* Register: RADIO_DAP */
mbed_official 85:e1a8e879a6a9 5003 /* Description: Device address prefix. */
mbed_official 85:e1a8e879a6a9 5004
mbed_official 85:e1a8e879a6a9 5005 /* Bits 15..0 : Device address prefix. */
mbed_official 85:e1a8e879a6a9 5006 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
mbed_official 85:e1a8e879a6a9 5007 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
mbed_official 85:e1a8e879a6a9 5008
mbed_official 85:e1a8e879a6a9 5009 /* Register: RADIO_DACNF */
mbed_official 85:e1a8e879a6a9 5010 /* Description: Device address match configuration. */
mbed_official 85:e1a8e879a6a9 5011
mbed_official 85:e1a8e879a6a9 5012 /* Bit 15 : TxAdd for device address 7. */
mbed_official 85:e1a8e879a6a9 5013 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
mbed_official 85:e1a8e879a6a9 5014 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
mbed_official 85:e1a8e879a6a9 5015
mbed_official 85:e1a8e879a6a9 5016 /* Bit 14 : TxAdd for device address 6. */
mbed_official 85:e1a8e879a6a9 5017 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
mbed_official 85:e1a8e879a6a9 5018 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
mbed_official 85:e1a8e879a6a9 5019
mbed_official 85:e1a8e879a6a9 5020 /* Bit 13 : TxAdd for device address 5. */
mbed_official 85:e1a8e879a6a9 5021 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
mbed_official 85:e1a8e879a6a9 5022 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
mbed_official 85:e1a8e879a6a9 5023
mbed_official 85:e1a8e879a6a9 5024 /* Bit 12 : TxAdd for device address 4. */
mbed_official 85:e1a8e879a6a9 5025 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
mbed_official 85:e1a8e879a6a9 5026 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
mbed_official 85:e1a8e879a6a9 5027
mbed_official 85:e1a8e879a6a9 5028 /* Bit 11 : TxAdd for device address 3. */
mbed_official 85:e1a8e879a6a9 5029 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
mbed_official 85:e1a8e879a6a9 5030 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
mbed_official 85:e1a8e879a6a9 5031
mbed_official 85:e1a8e879a6a9 5032 /* Bit 10 : TxAdd for device address 2. */
mbed_official 85:e1a8e879a6a9 5033 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
mbed_official 85:e1a8e879a6a9 5034 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
mbed_official 85:e1a8e879a6a9 5035
mbed_official 85:e1a8e879a6a9 5036 /* Bit 9 : TxAdd for device address 1. */
mbed_official 85:e1a8e879a6a9 5037 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
mbed_official 85:e1a8e879a6a9 5038 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
mbed_official 85:e1a8e879a6a9 5039
mbed_official 85:e1a8e879a6a9 5040 /* Bit 8 : TxAdd for device address 0. */
mbed_official 85:e1a8e879a6a9 5041 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
mbed_official 85:e1a8e879a6a9 5042 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
mbed_official 85:e1a8e879a6a9 5043
mbed_official 85:e1a8e879a6a9 5044 /* Bit 7 : Enable or disable device address matching using device address 7. */
mbed_official 85:e1a8e879a6a9 5045 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
mbed_official 85:e1a8e879a6a9 5046 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
mbed_official 85:e1a8e879a6a9 5047 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5048 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5049
mbed_official 85:e1a8e879a6a9 5050 /* Bit 6 : Enable or disable device address matching using device address 6. */
mbed_official 85:e1a8e879a6a9 5051 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
mbed_official 85:e1a8e879a6a9 5052 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
mbed_official 85:e1a8e879a6a9 5053 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5054 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5055
mbed_official 85:e1a8e879a6a9 5056 /* Bit 5 : Enable or disable device address matching using device address 5. */
mbed_official 85:e1a8e879a6a9 5057 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
mbed_official 85:e1a8e879a6a9 5058 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
mbed_official 85:e1a8e879a6a9 5059 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5060 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5061
mbed_official 85:e1a8e879a6a9 5062 /* Bit 4 : Enable or disable device address matching using device address 4. */
mbed_official 85:e1a8e879a6a9 5063 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
mbed_official 85:e1a8e879a6a9 5064 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
mbed_official 85:e1a8e879a6a9 5065 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5066 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5067
mbed_official 85:e1a8e879a6a9 5068 /* Bit 3 : Enable or disable device address matching using device address 3. */
mbed_official 85:e1a8e879a6a9 5069 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
mbed_official 85:e1a8e879a6a9 5070 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
mbed_official 85:e1a8e879a6a9 5071 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5072 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5073
mbed_official 85:e1a8e879a6a9 5074 /* Bit 2 : Enable or disable device address matching using device address 2. */
mbed_official 85:e1a8e879a6a9 5075 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
mbed_official 85:e1a8e879a6a9 5076 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
mbed_official 85:e1a8e879a6a9 5077 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5078 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5079
mbed_official 85:e1a8e879a6a9 5080 /* Bit 1 : Enable or disable device address matching using device address 1. */
mbed_official 85:e1a8e879a6a9 5081 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
mbed_official 85:e1a8e879a6a9 5082 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
mbed_official 85:e1a8e879a6a9 5083 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5084 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5085
mbed_official 85:e1a8e879a6a9 5086 /* Bit 0 : Enable or disable device address matching using device address 0. */
mbed_official 85:e1a8e879a6a9 5087 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
mbed_official 85:e1a8e879a6a9 5088 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
mbed_official 85:e1a8e879a6a9 5089 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 5090 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 5091
mbed_official 85:e1a8e879a6a9 5092 /* Register: RADIO_OVERRIDE0 */
mbed_official 85:e1a8e879a6a9 5093 /* Description: Trim value override register 0. */
mbed_official 85:e1a8e879a6a9 5094
mbed_official 85:e1a8e879a6a9 5095 /* Bits 31..0 : Trim value override register 0. */
mbed_official 85:e1a8e879a6a9 5096 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
mbed_official 85:e1a8e879a6a9 5097 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
mbed_official 85:e1a8e879a6a9 5098
mbed_official 85:e1a8e879a6a9 5099 /* Register: RADIO_OVERRIDE1 */
mbed_official 85:e1a8e879a6a9 5100 /* Description: Trim value override register 1. */
mbed_official 85:e1a8e879a6a9 5101
mbed_official 85:e1a8e879a6a9 5102 /* Bits 31..0 : Trim value override register 1. */
mbed_official 85:e1a8e879a6a9 5103 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
mbed_official 85:e1a8e879a6a9 5104 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
mbed_official 85:e1a8e879a6a9 5105
mbed_official 85:e1a8e879a6a9 5106 /* Register: RADIO_OVERRIDE2 */
mbed_official 85:e1a8e879a6a9 5107 /* Description: Trim value override register 2. */
mbed_official 85:e1a8e879a6a9 5108
mbed_official 85:e1a8e879a6a9 5109 /* Bits 31..0 : Trim value override register 2. */
mbed_official 85:e1a8e879a6a9 5110 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
mbed_official 85:e1a8e879a6a9 5111 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
mbed_official 85:e1a8e879a6a9 5112
mbed_official 85:e1a8e879a6a9 5113 /* Register: RADIO_OVERRIDE3 */
mbed_official 85:e1a8e879a6a9 5114 /* Description: Trim value override register 3. */
mbed_official 85:e1a8e879a6a9 5115
mbed_official 85:e1a8e879a6a9 5116 /* Bits 31..0 : Trim value override register 3. */
mbed_official 85:e1a8e879a6a9 5117 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
mbed_official 85:e1a8e879a6a9 5118 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
mbed_official 85:e1a8e879a6a9 5119
mbed_official 85:e1a8e879a6a9 5120 /* Register: RADIO_OVERRIDE4 */
mbed_official 85:e1a8e879a6a9 5121 /* Description: Trim value override register 4. */
mbed_official 85:e1a8e879a6a9 5122
mbed_official 85:e1a8e879a6a9 5123 /* Bit 31 : Enable or disable override of default trim values. */
mbed_official 85:e1a8e879a6a9 5124 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5125 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5126 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
mbed_official 85:e1a8e879a6a9 5127 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
mbed_official 85:e1a8e879a6a9 5128
mbed_official 85:e1a8e879a6a9 5129 /* Bits 27..0 : Trim value override register 4. */
mbed_official 85:e1a8e879a6a9 5130 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
mbed_official 85:e1a8e879a6a9 5131 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
mbed_official 85:e1a8e879a6a9 5132
mbed_official 85:e1a8e879a6a9 5133 /* Register: RADIO_POWER */
mbed_official 85:e1a8e879a6a9 5134 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5135
mbed_official 85:e1a8e879a6a9 5136 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5137 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5138 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5139 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5140 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5141
mbed_official 85:e1a8e879a6a9 5142
mbed_official 85:e1a8e879a6a9 5143 /* Peripheral: RNG */
mbed_official 85:e1a8e879a6a9 5144 /* Description: Random Number Generator. */
mbed_official 85:e1a8e879a6a9 5145
mbed_official 85:e1a8e879a6a9 5146 /* Register: RNG_SHORTS */
mbed_official 85:e1a8e879a6a9 5147 /* Description: Shortcut for the RNG. */
mbed_official 85:e1a8e879a6a9 5148
mbed_official 85:e1a8e879a6a9 5149 /* Bit 0 : Short-cut between VALRDY event and STOP task. */
mbed_official 85:e1a8e879a6a9 5150 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
mbed_official 85:e1a8e879a6a9 5151 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
mbed_official 85:e1a8e879a6a9 5152 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5153 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5154
mbed_official 85:e1a8e879a6a9 5155 /* Register: RNG_INTENSET */
mbed_official 85:e1a8e879a6a9 5156 /* Description: Interrupt enable set register */
mbed_official 85:e1a8e879a6a9 5157
mbed_official 85:e1a8e879a6a9 5158 /* Bit 0 : Enable interrupt on VALRDY event. */
mbed_official 85:e1a8e879a6a9 5159 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
mbed_official 85:e1a8e879a6a9 5160 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
mbed_official 85:e1a8e879a6a9 5161 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5162 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5163 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5164
mbed_official 85:e1a8e879a6a9 5165 /* Register: RNG_INTENCLR */
mbed_official 85:e1a8e879a6a9 5166 /* Description: Interrupt enable clear register */
mbed_official 85:e1a8e879a6a9 5167
mbed_official 85:e1a8e879a6a9 5168 /* Bit 0 : Disable interrupt on VALRDY event. */
mbed_official 85:e1a8e879a6a9 5169 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
mbed_official 85:e1a8e879a6a9 5170 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
mbed_official 85:e1a8e879a6a9 5171 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5172 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5173 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5174
mbed_official 85:e1a8e879a6a9 5175 /* Register: RNG_CONFIG */
mbed_official 85:e1a8e879a6a9 5176 /* Description: Configuration register. */
mbed_official 85:e1a8e879a6a9 5177
mbed_official 85:e1a8e879a6a9 5178 /* Bit 0 : Digital error correction enable. */
mbed_official 85:e1a8e879a6a9 5179 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
mbed_official 85:e1a8e879a6a9 5180 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
mbed_official 85:e1a8e879a6a9 5181 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
mbed_official 85:e1a8e879a6a9 5182 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
mbed_official 85:e1a8e879a6a9 5183
mbed_official 85:e1a8e879a6a9 5184 /* Register: RNG_VALUE */
mbed_official 85:e1a8e879a6a9 5185 /* Description: RNG random number. */
mbed_official 85:e1a8e879a6a9 5186
mbed_official 85:e1a8e879a6a9 5187 /* Bits 7..0 : Generated random number. */
mbed_official 85:e1a8e879a6a9 5188 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
mbed_official 85:e1a8e879a6a9 5189 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
mbed_official 85:e1a8e879a6a9 5190
mbed_official 85:e1a8e879a6a9 5191 /* Register: RNG_POWER */
mbed_official 85:e1a8e879a6a9 5192 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5193
mbed_official 85:e1a8e879a6a9 5194 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5195 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5196 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5197 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5198 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5199
mbed_official 85:e1a8e879a6a9 5200
mbed_official 85:e1a8e879a6a9 5201 /* Peripheral: RTC */
mbed_official 85:e1a8e879a6a9 5202 /* Description: Real time counter 0. */
mbed_official 85:e1a8e879a6a9 5203
mbed_official 85:e1a8e879a6a9 5204 /* Register: RTC_INTENSET */
mbed_official 85:e1a8e879a6a9 5205 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5206
mbed_official 85:e1a8e879a6a9 5207 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
mbed_official 85:e1a8e879a6a9 5208 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5209 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5210 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5211 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5212 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5213
mbed_official 85:e1a8e879a6a9 5214 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
mbed_official 85:e1a8e879a6a9 5215 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5216 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5217 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5218 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5219 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5220
mbed_official 85:e1a8e879a6a9 5221 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
mbed_official 85:e1a8e879a6a9 5222 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5223 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5224 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5225 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5226 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5227
mbed_official 85:e1a8e879a6a9 5228 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
mbed_official 85:e1a8e879a6a9 5229 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5230 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5231 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5232 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5233 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5234
mbed_official 85:e1a8e879a6a9 5235 /* Bit 1 : Enable interrupt on OVRFLW event. */
mbed_official 85:e1a8e879a6a9 5236 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5237 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5238 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5239 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5240 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5241
mbed_official 85:e1a8e879a6a9 5242 /* Bit 0 : Enable interrupt on TICK event. */
mbed_official 85:e1a8e879a6a9 5243 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
mbed_official 85:e1a8e879a6a9 5244 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
mbed_official 85:e1a8e879a6a9 5245 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5246 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5247 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5248
mbed_official 85:e1a8e879a6a9 5249 /* Register: RTC_INTENCLR */
mbed_official 85:e1a8e879a6a9 5250 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5251
mbed_official 85:e1a8e879a6a9 5252 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
mbed_official 85:e1a8e879a6a9 5253 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5254 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5255 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5256 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5257 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5258
mbed_official 85:e1a8e879a6a9 5259 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
mbed_official 85:e1a8e879a6a9 5260 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5261 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5262 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5263 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5264 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5265
mbed_official 85:e1a8e879a6a9 5266 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
mbed_official 85:e1a8e879a6a9 5267 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5268 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5269 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5270 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5271 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5272
mbed_official 85:e1a8e879a6a9 5273 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
mbed_official 85:e1a8e879a6a9 5274 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5275 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5276 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5277 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5278 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5279
mbed_official 85:e1a8e879a6a9 5280 /* Bit 1 : Disable interrupt on OVRFLW event. */
mbed_official 85:e1a8e879a6a9 5281 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5282 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5283 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5284 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5285 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5286
mbed_official 85:e1a8e879a6a9 5287 /* Bit 0 : Disable interrupt on TICK event. */
mbed_official 85:e1a8e879a6a9 5288 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
mbed_official 85:e1a8e879a6a9 5289 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
mbed_official 85:e1a8e879a6a9 5290 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5291 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5292 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5293
mbed_official 85:e1a8e879a6a9 5294 /* Register: RTC_EVTEN */
mbed_official 85:e1a8e879a6a9 5295 /* Description: Configures event enable routing to PPI for each RTC event. */
mbed_official 85:e1a8e879a6a9 5296
mbed_official 85:e1a8e879a6a9 5297 /* Bit 19 : COMPARE[3] event enable. */
mbed_official 85:e1a8e879a6a9 5298 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5299 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5300 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5301 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5302
mbed_official 85:e1a8e879a6a9 5303 /* Bit 18 : COMPARE[2] event enable. */
mbed_official 85:e1a8e879a6a9 5304 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5305 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5306 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5307 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5308
mbed_official 85:e1a8e879a6a9 5309 /* Bit 17 : COMPARE[1] event enable. */
mbed_official 85:e1a8e879a6a9 5310 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5311 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5312 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5313 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5314
mbed_official 85:e1a8e879a6a9 5315 /* Bit 16 : COMPARE[0] event enable. */
mbed_official 85:e1a8e879a6a9 5316 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5317 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5318 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5319 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5320
mbed_official 85:e1a8e879a6a9 5321 /* Bit 1 : OVRFLW event enable. */
mbed_official 85:e1a8e879a6a9 5322 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5323 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5324 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5325 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5326
mbed_official 85:e1a8e879a6a9 5327 /* Bit 0 : TICK event enable. */
mbed_official 85:e1a8e879a6a9 5328 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
mbed_official 85:e1a8e879a6a9 5329 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
mbed_official 85:e1a8e879a6a9 5330 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5331 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5332
mbed_official 85:e1a8e879a6a9 5333 /* Register: RTC_EVTENSET */
mbed_official 85:e1a8e879a6a9 5334 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 5335
mbed_official 85:e1a8e879a6a9 5336 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
mbed_official 85:e1a8e879a6a9 5337 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5338 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5339 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5340 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5341 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5342
mbed_official 85:e1a8e879a6a9 5343 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
mbed_official 85:e1a8e879a6a9 5344 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5345 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5346 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5347 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5348 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5349
mbed_official 85:e1a8e879a6a9 5350 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
mbed_official 85:e1a8e879a6a9 5351 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5352 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5353 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5354 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5355 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5356
mbed_official 85:e1a8e879a6a9 5357 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
mbed_official 85:e1a8e879a6a9 5358 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5359 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5360 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5361 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5362 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5363
mbed_official 85:e1a8e879a6a9 5364 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
mbed_official 85:e1a8e879a6a9 5365 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5366 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5367 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5368 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5369 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5370
mbed_official 85:e1a8e879a6a9 5371 /* Bit 0 : Enable routing to PPI of TICK event. */
mbed_official 85:e1a8e879a6a9 5372 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
mbed_official 85:e1a8e879a6a9 5373 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
mbed_official 85:e1a8e879a6a9 5374 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5375 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5376 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
mbed_official 85:e1a8e879a6a9 5377
mbed_official 85:e1a8e879a6a9 5378 /* Register: RTC_EVTENCLR */
mbed_official 85:e1a8e879a6a9 5379 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 5380
mbed_official 85:e1a8e879a6a9 5381 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
mbed_official 85:e1a8e879a6a9 5382 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5383 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5384 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5385 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5386 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5387
mbed_official 85:e1a8e879a6a9 5388 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
mbed_official 85:e1a8e879a6a9 5389 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5390 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5391 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5392 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5393 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5394
mbed_official 85:e1a8e879a6a9 5395 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
mbed_official 85:e1a8e879a6a9 5396 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5397 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5398 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5399 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5400 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5401
mbed_official 85:e1a8e879a6a9 5402 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
mbed_official 85:e1a8e879a6a9 5403 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5404 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5405 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5406 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5407 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5408
mbed_official 85:e1a8e879a6a9 5409 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
mbed_official 85:e1a8e879a6a9 5410 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5411 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
mbed_official 85:e1a8e879a6a9 5412 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5413 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5414 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5415
mbed_official 85:e1a8e879a6a9 5416 /* Bit 0 : Disable routing to PPI of TICK event. */
mbed_official 85:e1a8e879a6a9 5417 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
mbed_official 85:e1a8e879a6a9 5418 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
mbed_official 85:e1a8e879a6a9 5419 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
mbed_official 85:e1a8e879a6a9 5420 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
mbed_official 85:e1a8e879a6a9 5421 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
mbed_official 85:e1a8e879a6a9 5422
mbed_official 85:e1a8e879a6a9 5423 /* Register: RTC_COUNTER */
mbed_official 85:e1a8e879a6a9 5424 /* Description: Current COUNTER value. */
mbed_official 85:e1a8e879a6a9 5425
mbed_official 85:e1a8e879a6a9 5426 /* Bits 23..0 : Counter value. */
mbed_official 85:e1a8e879a6a9 5427 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
mbed_official 85:e1a8e879a6a9 5428 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
mbed_official 85:e1a8e879a6a9 5429
mbed_official 85:e1a8e879a6a9 5430 /* Register: RTC_PRESCALER */
mbed_official 85:e1a8e879a6a9 5431 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
mbed_official 85:e1a8e879a6a9 5432
mbed_official 85:e1a8e879a6a9 5433 /* Bits 11..0 : RTC PRESCALER value. */
mbed_official 85:e1a8e879a6a9 5434 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
mbed_official 85:e1a8e879a6a9 5435 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
mbed_official 85:e1a8e879a6a9 5436
mbed_official 85:e1a8e879a6a9 5437 /* Register: RTC_CC */
mbed_official 85:e1a8e879a6a9 5438 /* Description: Capture/compare registers. */
mbed_official 85:e1a8e879a6a9 5439
mbed_official 85:e1a8e879a6a9 5440 /* Bits 23..0 : Compare value. */
mbed_official 85:e1a8e879a6a9 5441 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
mbed_official 85:e1a8e879a6a9 5442 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
mbed_official 85:e1a8e879a6a9 5443
mbed_official 85:e1a8e879a6a9 5444 /* Register: RTC_POWER */
mbed_official 85:e1a8e879a6a9 5445 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5446
mbed_official 85:e1a8e879a6a9 5447 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5448 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5449 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5450 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5451 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5452
mbed_official 85:e1a8e879a6a9 5453
mbed_official 85:e1a8e879a6a9 5454 /* Peripheral: SPI */
mbed_official 85:e1a8e879a6a9 5455 /* Description: SPI master 0. */
mbed_official 85:e1a8e879a6a9 5456
mbed_official 85:e1a8e879a6a9 5457 /* Register: SPI_INTENSET */
mbed_official 85:e1a8e879a6a9 5458 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5459
mbed_official 85:e1a8e879a6a9 5460 /* Bit 2 : Enable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 5461 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 5462 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 5463 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5464 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5465 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5466
mbed_official 85:e1a8e879a6a9 5467 /* Register: SPI_INTENCLR */
mbed_official 85:e1a8e879a6a9 5468 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5469
mbed_official 85:e1a8e879a6a9 5470 /* Bit 2 : Disable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 5471 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
mbed_official 85:e1a8e879a6a9 5472 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
mbed_official 85:e1a8e879a6a9 5473 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5474 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5475 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5476
mbed_official 85:e1a8e879a6a9 5477 /* Register: SPI_ENABLE */
mbed_official 85:e1a8e879a6a9 5478 /* Description: Enable SPI. */
mbed_official 85:e1a8e879a6a9 5479
mbed_official 85:e1a8e879a6a9 5480 /* Bits 2..0 : Enable or disable SPI. */
mbed_official 85:e1a8e879a6a9 5481 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5482 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5483 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
mbed_official 85:e1a8e879a6a9 5484 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
mbed_official 85:e1a8e879a6a9 5485
mbed_official 85:e1a8e879a6a9 5486 /* Register: SPI_RXD */
mbed_official 85:e1a8e879a6a9 5487 /* Description: RX data. */
mbed_official 85:e1a8e879a6a9 5488
mbed_official 85:e1a8e879a6a9 5489 /* Bits 7..0 : RX data from last transfer. */
mbed_official 85:e1a8e879a6a9 5490 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
mbed_official 85:e1a8e879a6a9 5491 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
mbed_official 85:e1a8e879a6a9 5492
mbed_official 85:e1a8e879a6a9 5493 /* Register: SPI_TXD */
mbed_official 85:e1a8e879a6a9 5494 /* Description: TX data. */
mbed_official 85:e1a8e879a6a9 5495
mbed_official 85:e1a8e879a6a9 5496 /* Bits 7..0 : TX data for next transfer. */
mbed_official 85:e1a8e879a6a9 5497 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
mbed_official 85:e1a8e879a6a9 5498 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
mbed_official 85:e1a8e879a6a9 5499
mbed_official 85:e1a8e879a6a9 5500 /* Register: SPI_FREQUENCY */
mbed_official 85:e1a8e879a6a9 5501 /* Description: SPI frequency */
mbed_official 85:e1a8e879a6a9 5502
mbed_official 85:e1a8e879a6a9 5503 /* Bits 31..0 : SPI data rate. */
mbed_official 85:e1a8e879a6a9 5504 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 5505 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 5506 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
mbed_official 85:e1a8e879a6a9 5507 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
mbed_official 85:e1a8e879a6a9 5508 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
mbed_official 85:e1a8e879a6a9 5509 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
mbed_official 85:e1a8e879a6a9 5510 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
mbed_official 85:e1a8e879a6a9 5511 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
mbed_official 85:e1a8e879a6a9 5512 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
mbed_official 85:e1a8e879a6a9 5513
mbed_official 85:e1a8e879a6a9 5514 /* Register: SPI_CONFIG */
mbed_official 85:e1a8e879a6a9 5515 /* Description: Configuration register. */
mbed_official 85:e1a8e879a6a9 5516
mbed_official 85:e1a8e879a6a9 5517 /* Bit 2 : Serial clock (SCK) polarity. */
mbed_official 85:e1a8e879a6a9 5518 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
mbed_official 85:e1a8e879a6a9 5519 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
mbed_official 85:e1a8e879a6a9 5520 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
mbed_official 85:e1a8e879a6a9 5521 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
mbed_official 85:e1a8e879a6a9 5522
mbed_official 85:e1a8e879a6a9 5523 /* Bit 1 : Serial clock (SCK) phase. */
mbed_official 85:e1a8e879a6a9 5524 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
mbed_official 85:e1a8e879a6a9 5525 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
mbed_official 85:e1a8e879a6a9 5526 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
mbed_official 85:e1a8e879a6a9 5527 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
mbed_official 85:e1a8e879a6a9 5528
mbed_official 85:e1a8e879a6a9 5529 /* Bit 0 : Bit order. */
mbed_official 85:e1a8e879a6a9 5530 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
mbed_official 85:e1a8e879a6a9 5531 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
mbed_official 85:e1a8e879a6a9 5532 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
mbed_official 85:e1a8e879a6a9 5533 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
mbed_official 85:e1a8e879a6a9 5534
mbed_official 85:e1a8e879a6a9 5535 /* Register: SPI_POWER */
mbed_official 85:e1a8e879a6a9 5536 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5537
mbed_official 85:e1a8e879a6a9 5538 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5539 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5540 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5541 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5542 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5543
mbed_official 85:e1a8e879a6a9 5544
mbed_official 85:e1a8e879a6a9 5545 /* Peripheral: SPIS */
mbed_official 85:e1a8e879a6a9 5546 /* Description: SPI slave 1. */
mbed_official 85:e1a8e879a6a9 5547
mbed_official 85:e1a8e879a6a9 5548 /* Register: SPIS_SHORTS */
mbed_official 85:e1a8e879a6a9 5549 /* Description: Shortcuts for SPIS. */
mbed_official 85:e1a8e879a6a9 5550
mbed_official 85:e1a8e879a6a9 5551 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
mbed_official 85:e1a8e879a6a9 5552 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
mbed_official 85:e1a8e879a6a9 5553 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
mbed_official 85:e1a8e879a6a9 5554 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5555 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5556
mbed_official 85:e1a8e879a6a9 5557 /* Register: SPIS_INTENSET */
mbed_official 85:e1a8e879a6a9 5558 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5559
mbed_official 85:e1a8e879a6a9 5560 /* Bit 10 : Enable interrupt on ACQUIRED event. */
mbed_official 85:e1a8e879a6a9 5561 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
mbed_official 85:e1a8e879a6a9 5562 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
mbed_official 85:e1a8e879a6a9 5563 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5564 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5565 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5566
mbed_official 85:e1a8e879a6a9 5567 /* Bit 1 : Enable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 5568 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 5569 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 5570 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5571 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5572 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5573
mbed_official 85:e1a8e879a6a9 5574 /* Register: SPIS_INTENCLR */
mbed_official 85:e1a8e879a6a9 5575 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5576
mbed_official 85:e1a8e879a6a9 5577 /* Bit 10 : Disable interrupt on ACQUIRED event. */
mbed_official 85:e1a8e879a6a9 5578 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
mbed_official 85:e1a8e879a6a9 5579 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
mbed_official 85:e1a8e879a6a9 5580 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5581 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5582 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5583
mbed_official 85:e1a8e879a6a9 5584 /* Bit 1 : Disable interrupt on END event. */
mbed_official 85:e1a8e879a6a9 5585 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
mbed_official 85:e1a8e879a6a9 5586 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
mbed_official 85:e1a8e879a6a9 5587 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5588 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5589 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5590
mbed_official 85:e1a8e879a6a9 5591 /* Register: SPIS_SEMSTAT */
mbed_official 85:e1a8e879a6a9 5592 /* Description: Semaphore status. */
mbed_official 85:e1a8e879a6a9 5593
mbed_official 85:e1a8e879a6a9 5594 /* Bits 1..0 : Semaphore status. */
mbed_official 85:e1a8e879a6a9 5595 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
mbed_official 85:e1a8e879a6a9 5596 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
mbed_official 85:e1a8e879a6a9 5597 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
mbed_official 85:e1a8e879a6a9 5598 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
mbed_official 85:e1a8e879a6a9 5599 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
mbed_official 85:e1a8e879a6a9 5600 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
mbed_official 85:e1a8e879a6a9 5601
mbed_official 85:e1a8e879a6a9 5602 /* Register: SPIS_STATUS */
mbed_official 85:e1a8e879a6a9 5603 /* Description: Status from last transaction. */
mbed_official 85:e1a8e879a6a9 5604
mbed_official 85:e1a8e879a6a9 5605 /* Bit 1 : RX buffer overflow detected, and prevented. */
mbed_official 85:e1a8e879a6a9 5606 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
mbed_official 85:e1a8e879a6a9 5607 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
mbed_official 85:e1a8e879a6a9 5608 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 5609 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 5610 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
mbed_official 85:e1a8e879a6a9 5611
mbed_official 85:e1a8e879a6a9 5612 /* Bit 0 : TX buffer overread detected, and prevented. */
mbed_official 85:e1a8e879a6a9 5613 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
mbed_official 85:e1a8e879a6a9 5614 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
mbed_official 85:e1a8e879a6a9 5615 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 5616 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 5617 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
mbed_official 85:e1a8e879a6a9 5618
mbed_official 85:e1a8e879a6a9 5619 /* Register: SPIS_ENABLE */
mbed_official 85:e1a8e879a6a9 5620 /* Description: Enable SPIS. */
mbed_official 85:e1a8e879a6a9 5621
mbed_official 85:e1a8e879a6a9 5622 /* Bits 2..0 : Enable or disable SPIS. */
mbed_official 85:e1a8e879a6a9 5623 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5624 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 5625 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
mbed_official 85:e1a8e879a6a9 5626 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
mbed_official 85:e1a8e879a6a9 5627
mbed_official 85:e1a8e879a6a9 5628 /* Register: SPIS_MAXRX */
mbed_official 85:e1a8e879a6a9 5629 /* Description: Maximum number of bytes in the receive buffer. */
mbed_official 85:e1a8e879a6a9 5630
mbed_official 85:e1a8e879a6a9 5631 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
mbed_official 85:e1a8e879a6a9 5632 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
mbed_official 85:e1a8e879a6a9 5633 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
mbed_official 85:e1a8e879a6a9 5634
mbed_official 85:e1a8e879a6a9 5635 /* Register: SPIS_AMOUNTRX */
mbed_official 85:e1a8e879a6a9 5636 /* Description: Number of bytes received in last granted transaction. */
mbed_official 85:e1a8e879a6a9 5637
mbed_official 85:e1a8e879a6a9 5638 /* Bits 7..0 : Number of bytes received in last granted transaction. */
mbed_official 85:e1a8e879a6a9 5639 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
mbed_official 85:e1a8e879a6a9 5640 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
mbed_official 85:e1a8e879a6a9 5641
mbed_official 85:e1a8e879a6a9 5642 /* Register: SPIS_MAXTX */
mbed_official 85:e1a8e879a6a9 5643 /* Description: Maximum number of bytes in the transmit buffer. */
mbed_official 85:e1a8e879a6a9 5644
mbed_official 85:e1a8e879a6a9 5645 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
mbed_official 85:e1a8e879a6a9 5646 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
mbed_official 85:e1a8e879a6a9 5647 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
mbed_official 85:e1a8e879a6a9 5648
mbed_official 85:e1a8e879a6a9 5649 /* Register: SPIS_AMOUNTTX */
mbed_official 85:e1a8e879a6a9 5650 /* Description: Number of bytes transmitted in last granted transaction. */
mbed_official 85:e1a8e879a6a9 5651
mbed_official 85:e1a8e879a6a9 5652 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
mbed_official 85:e1a8e879a6a9 5653 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
mbed_official 85:e1a8e879a6a9 5654 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
mbed_official 85:e1a8e879a6a9 5655
mbed_official 85:e1a8e879a6a9 5656 /* Register: SPIS_CONFIG */
mbed_official 85:e1a8e879a6a9 5657 /* Description: Configuration register. */
mbed_official 85:e1a8e879a6a9 5658
mbed_official 85:e1a8e879a6a9 5659 /* Bit 2 : Serial clock (SCK) polarity. */
mbed_official 85:e1a8e879a6a9 5660 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
mbed_official 85:e1a8e879a6a9 5661 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
mbed_official 85:e1a8e879a6a9 5662 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
mbed_official 85:e1a8e879a6a9 5663 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
mbed_official 85:e1a8e879a6a9 5664
mbed_official 85:e1a8e879a6a9 5665 /* Bit 1 : Serial clock (SCK) phase. */
mbed_official 85:e1a8e879a6a9 5666 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
mbed_official 85:e1a8e879a6a9 5667 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
mbed_official 85:e1a8e879a6a9 5668 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
mbed_official 85:e1a8e879a6a9 5669 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
mbed_official 85:e1a8e879a6a9 5670
mbed_official 85:e1a8e879a6a9 5671 /* Bit 0 : Bit order. */
mbed_official 85:e1a8e879a6a9 5672 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
mbed_official 85:e1a8e879a6a9 5673 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
mbed_official 85:e1a8e879a6a9 5674 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
mbed_official 85:e1a8e879a6a9 5675 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
mbed_official 85:e1a8e879a6a9 5676
mbed_official 85:e1a8e879a6a9 5677 /* Register: SPIS_DEF */
mbed_official 85:e1a8e879a6a9 5678 /* Description: Default character. */
mbed_official 85:e1a8e879a6a9 5679
mbed_official 85:e1a8e879a6a9 5680 /* Bits 7..0 : Default character. */
mbed_official 85:e1a8e879a6a9 5681 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
mbed_official 85:e1a8e879a6a9 5682 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
mbed_official 85:e1a8e879a6a9 5683
mbed_official 85:e1a8e879a6a9 5684 /* Register: SPIS_ORC */
mbed_official 85:e1a8e879a6a9 5685 /* Description: Over-read character. */
mbed_official 85:e1a8e879a6a9 5686
mbed_official 85:e1a8e879a6a9 5687 /* Bits 7..0 : Over-read character. */
mbed_official 85:e1a8e879a6a9 5688 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
mbed_official 85:e1a8e879a6a9 5689 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
mbed_official 85:e1a8e879a6a9 5690
mbed_official 85:e1a8e879a6a9 5691 /* Register: SPIS_POWER */
mbed_official 85:e1a8e879a6a9 5692 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5693
mbed_official 85:e1a8e879a6a9 5694 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5695 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5696 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5697 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5698 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5699
mbed_official 85:e1a8e879a6a9 5700
mbed_official 85:e1a8e879a6a9 5701 /* Peripheral: TEMP */
mbed_official 85:e1a8e879a6a9 5702 /* Description: Temperature Sensor. */
mbed_official 85:e1a8e879a6a9 5703
mbed_official 85:e1a8e879a6a9 5704 /* Register: TEMP_INTENSET */
mbed_official 85:e1a8e879a6a9 5705 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5706
mbed_official 85:e1a8e879a6a9 5707 /* Bit 0 : Enable interrupt on DATARDY event. */
mbed_official 85:e1a8e879a6a9 5708 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
mbed_official 85:e1a8e879a6a9 5709 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
mbed_official 85:e1a8e879a6a9 5710 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5711 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5712 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5713
mbed_official 85:e1a8e879a6a9 5714 /* Register: TEMP_INTENCLR */
mbed_official 85:e1a8e879a6a9 5715 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5716
mbed_official 85:e1a8e879a6a9 5717 /* Bit 0 : Disable interrupt on DATARDY event. */
mbed_official 85:e1a8e879a6a9 5718 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
mbed_official 85:e1a8e879a6a9 5719 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
mbed_official 85:e1a8e879a6a9 5720 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5721 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5722 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5723
mbed_official 85:e1a8e879a6a9 5724 /* Register: TEMP_POWER */
mbed_official 85:e1a8e879a6a9 5725 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5726
mbed_official 85:e1a8e879a6a9 5727 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5728 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5729 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5730 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5731 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5732
mbed_official 85:e1a8e879a6a9 5733
mbed_official 85:e1a8e879a6a9 5734 /* Peripheral: TIMER */
mbed_official 85:e1a8e879a6a9 5735 /* Description: Timer 0. */
mbed_official 85:e1a8e879a6a9 5736
mbed_official 85:e1a8e879a6a9 5737 /* Register: TIMER_SHORTS */
mbed_official 85:e1a8e879a6a9 5738 /* Description: Shortcuts for Timer. */
mbed_official 85:e1a8e879a6a9 5739
mbed_official 85:e1a8e879a6a9 5740 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
mbed_official 85:e1a8e879a6a9 5741 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
mbed_official 85:e1a8e879a6a9 5742 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
mbed_official 85:e1a8e879a6a9 5743 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5744 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5745
mbed_official 85:e1a8e879a6a9 5746 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
mbed_official 85:e1a8e879a6a9 5747 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
mbed_official 85:e1a8e879a6a9 5748 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
mbed_official 85:e1a8e879a6a9 5749 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5750 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5751
mbed_official 85:e1a8e879a6a9 5752 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
mbed_official 85:e1a8e879a6a9 5753 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
mbed_official 85:e1a8e879a6a9 5754 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
mbed_official 85:e1a8e879a6a9 5755 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5756 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5757
mbed_official 85:e1a8e879a6a9 5758 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
mbed_official 85:e1a8e879a6a9 5759 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
mbed_official 85:e1a8e879a6a9 5760 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
mbed_official 85:e1a8e879a6a9 5761 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5762 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5763
mbed_official 85:e1a8e879a6a9 5764 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
mbed_official 85:e1a8e879a6a9 5765 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5766 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5767 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5768 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5769
mbed_official 85:e1a8e879a6a9 5770 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
mbed_official 85:e1a8e879a6a9 5771 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5772 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5773 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5774 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5775
mbed_official 85:e1a8e879a6a9 5776 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
mbed_official 85:e1a8e879a6a9 5777 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5778 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5779 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5780 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5781
mbed_official 85:e1a8e879a6a9 5782 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
mbed_official 85:e1a8e879a6a9 5783 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5784 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
mbed_official 85:e1a8e879a6a9 5785 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5786 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5787
mbed_official 85:e1a8e879a6a9 5788 /* Register: TIMER_INTENSET */
mbed_official 85:e1a8e879a6a9 5789 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5790
mbed_official 85:e1a8e879a6a9 5791 /* Bit 19 : Enable interrupt on COMPARE[3] */
mbed_official 85:e1a8e879a6a9 5792 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5793 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5794 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5795 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5796 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5797
mbed_official 85:e1a8e879a6a9 5798 /* Bit 18 : Enable interrupt on COMPARE[2] */
mbed_official 85:e1a8e879a6a9 5799 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5800 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5801 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5802 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5803 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5804
mbed_official 85:e1a8e879a6a9 5805 /* Bit 17 : Enable interrupt on COMPARE[1] */
mbed_official 85:e1a8e879a6a9 5806 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5807 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5808 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5809 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5810 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5811
mbed_official 85:e1a8e879a6a9 5812 /* Bit 16 : Enable interrupt on COMPARE[0] */
mbed_official 85:e1a8e879a6a9 5813 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5814 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5815 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5816 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5817 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5818
mbed_official 85:e1a8e879a6a9 5819 /* Register: TIMER_INTENCLR */
mbed_official 85:e1a8e879a6a9 5820 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5821
mbed_official 85:e1a8e879a6a9 5822 /* Bit 19 : Disable interrupt on COMPARE[3] */
mbed_official 85:e1a8e879a6a9 5823 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5824 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
mbed_official 85:e1a8e879a6a9 5825 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5826 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5827 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5828
mbed_official 85:e1a8e879a6a9 5829 /* Bit 18 : Disable interrupt on COMPARE[2] */
mbed_official 85:e1a8e879a6a9 5830 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5831 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
mbed_official 85:e1a8e879a6a9 5832 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5833 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5834 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5835
mbed_official 85:e1a8e879a6a9 5836 /* Bit 17 : Disable interrupt on COMPARE[1] */
mbed_official 85:e1a8e879a6a9 5837 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5838 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
mbed_official 85:e1a8e879a6a9 5839 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5840 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5841 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5842
mbed_official 85:e1a8e879a6a9 5843 /* Bit 16 : Disable interrupt on COMPARE[0] */
mbed_official 85:e1a8e879a6a9 5844 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5845 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
mbed_official 85:e1a8e879a6a9 5846 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5847 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5848 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5849
mbed_official 85:e1a8e879a6a9 5850 /* Register: TIMER_MODE */
mbed_official 85:e1a8e879a6a9 5851 /* Description: Timer Mode selection. */
mbed_official 85:e1a8e879a6a9 5852
mbed_official 85:e1a8e879a6a9 5853 /* Bit 0 : Select Normal or Counter mode. */
mbed_official 85:e1a8e879a6a9 5854 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
mbed_official 85:e1a8e879a6a9 5855 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
mbed_official 85:e1a8e879a6a9 5856 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
mbed_official 85:e1a8e879a6a9 5857 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
mbed_official 85:e1a8e879a6a9 5858
mbed_official 85:e1a8e879a6a9 5859 /* Register: TIMER_BITMODE */
mbed_official 85:e1a8e879a6a9 5860 /* Description: Sets timer behaviour. */
mbed_official 85:e1a8e879a6a9 5861
mbed_official 85:e1a8e879a6a9 5862 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
mbed_official 85:e1a8e879a6a9 5863 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
mbed_official 85:e1a8e879a6a9 5864 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
mbed_official 85:e1a8e879a6a9 5865 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
mbed_official 85:e1a8e879a6a9 5866 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
mbed_official 85:e1a8e879a6a9 5867 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
mbed_official 85:e1a8e879a6a9 5868 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
mbed_official 85:e1a8e879a6a9 5869
mbed_official 85:e1a8e879a6a9 5870 /* Register: TIMER_PRESCALER */
mbed_official 85:e1a8e879a6a9 5871 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
mbed_official 85:e1a8e879a6a9 5872
mbed_official 85:e1a8e879a6a9 5873 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
mbed_official 85:e1a8e879a6a9 5874 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
mbed_official 85:e1a8e879a6a9 5875 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
mbed_official 85:e1a8e879a6a9 5876
mbed_official 85:e1a8e879a6a9 5877 /* Register: TIMER_POWER */
mbed_official 85:e1a8e879a6a9 5878 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5879
mbed_official 85:e1a8e879a6a9 5880 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 5881 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 5882 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 5883 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 5884 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 5885
mbed_official 85:e1a8e879a6a9 5886
mbed_official 85:e1a8e879a6a9 5887 /* Peripheral: TWI */
mbed_official 85:e1a8e879a6a9 5888 /* Description: Two-wire interface master 0. */
mbed_official 85:e1a8e879a6a9 5889
mbed_official 85:e1a8e879a6a9 5890 /* Register: TWI_SHORTS */
mbed_official 85:e1a8e879a6a9 5891 /* Description: Shortcuts for TWI. */
mbed_official 85:e1a8e879a6a9 5892
mbed_official 85:e1a8e879a6a9 5893 /* Bit 1 : Shortcut between BB event and the STOP task. */
mbed_official 85:e1a8e879a6a9 5894 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
mbed_official 85:e1a8e879a6a9 5895 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
mbed_official 85:e1a8e879a6a9 5896 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5897 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5898
mbed_official 85:e1a8e879a6a9 5899 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
mbed_official 85:e1a8e879a6a9 5900 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
mbed_official 85:e1a8e879a6a9 5901 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
mbed_official 85:e1a8e879a6a9 5902 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 5903 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 5904
mbed_official 85:e1a8e879a6a9 5905 /* Register: TWI_INTENSET */
mbed_official 85:e1a8e879a6a9 5906 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 5907
mbed_official 85:e1a8e879a6a9 5908 /* Bit 14 : Enable interrupt on BB event. */
mbed_official 85:e1a8e879a6a9 5909 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
mbed_official 85:e1a8e879a6a9 5910 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
mbed_official 85:e1a8e879a6a9 5911 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5912 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5913 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5914
mbed_official 85:e1a8e879a6a9 5915 /* Bit 9 : Enable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 5916 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 5917 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 5918 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5919 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5920 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5921
mbed_official 85:e1a8e879a6a9 5922 /* Bit 7 : Enable interrupt on TXDSENT event. */
mbed_official 85:e1a8e879a6a9 5923 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
mbed_official 85:e1a8e879a6a9 5924 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
mbed_official 85:e1a8e879a6a9 5925 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5926 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5927 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5928
mbed_official 85:e1a8e879a6a9 5929 /* Bit 2 : Enable interrupt on READY event. */
mbed_official 85:e1a8e879a6a9 5930 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
mbed_official 85:e1a8e879a6a9 5931 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
mbed_official 85:e1a8e879a6a9 5932 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5933 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5934 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5935
mbed_official 85:e1a8e879a6a9 5936 /* Bit 1 : Enable interrupt on STOPPED event. */
mbed_official 85:e1a8e879a6a9 5937 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
mbed_official 85:e1a8e879a6a9 5938 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
mbed_official 85:e1a8e879a6a9 5939 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5940 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5941 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5942
mbed_official 85:e1a8e879a6a9 5943 /* Register: TWI_INTENCLR */
mbed_official 85:e1a8e879a6a9 5944 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 5945
mbed_official 85:e1a8e879a6a9 5946 /* Bit 14 : Disable interrupt on BB event. */
mbed_official 85:e1a8e879a6a9 5947 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
mbed_official 85:e1a8e879a6a9 5948 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
mbed_official 85:e1a8e879a6a9 5949 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5950 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5951 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5952
mbed_official 85:e1a8e879a6a9 5953 /* Bit 9 : Disable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 5954 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 5955 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 5956 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5957 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5958 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5959
mbed_official 85:e1a8e879a6a9 5960 /* Bit 7 : Disable interrupt on TXDSENT event. */
mbed_official 85:e1a8e879a6a9 5961 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
mbed_official 85:e1a8e879a6a9 5962 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
mbed_official 85:e1a8e879a6a9 5963 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5964 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5965 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5966
mbed_official 85:e1a8e879a6a9 5967 /* Bit 2 : Disable interrupt on RXDREADY event. */
mbed_official 85:e1a8e879a6a9 5968 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
mbed_official 85:e1a8e879a6a9 5969 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
mbed_official 85:e1a8e879a6a9 5970 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5971 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5972 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5973
mbed_official 85:e1a8e879a6a9 5974 /* Bit 1 : Disable interrupt on STOPPED event. */
mbed_official 85:e1a8e879a6a9 5975 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
mbed_official 85:e1a8e879a6a9 5976 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
mbed_official 85:e1a8e879a6a9 5977 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 5978 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 5979 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 5980
mbed_official 85:e1a8e879a6a9 5981 /* Register: TWI_ERRORSRC */
mbed_official 85:e1a8e879a6a9 5982 /* Description: Two-wire error source. Write error field to 1 to clear error. */
mbed_official 85:e1a8e879a6a9 5983
mbed_official 85:e1a8e879a6a9 5984 /* Bit 2 : NACK received after sending a data byte. */
mbed_official 85:e1a8e879a6a9 5985 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
mbed_official 85:e1a8e879a6a9 5986 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
mbed_official 85:e1a8e879a6a9 5987 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 5988 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 5989 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 5990
mbed_official 85:e1a8e879a6a9 5991 /* Bit 1 : NACK received after sending the address. */
mbed_official 85:e1a8e879a6a9 5992 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
mbed_official 85:e1a8e879a6a9 5993 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
mbed_official 85:e1a8e879a6a9 5994 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 5995 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 5996 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 5997
mbed_official 85:e1a8e879a6a9 5998 /* Register: TWI_ENABLE */
mbed_official 85:e1a8e879a6a9 5999 /* Description: Enable two-wire master. */
mbed_official 85:e1a8e879a6a9 6000
mbed_official 85:e1a8e879a6a9 6001 /* Bits 2..0 : Enable or disable W2M */
mbed_official 85:e1a8e879a6a9 6002 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 6003 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 6004 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 6005 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 6006
mbed_official 85:e1a8e879a6a9 6007 /* Register: TWI_RXD */
mbed_official 85:e1a8e879a6a9 6008 /* Description: RX data register. */
mbed_official 85:e1a8e879a6a9 6009
mbed_official 85:e1a8e879a6a9 6010 /* Bits 7..0 : RX data from last transfer. */
mbed_official 85:e1a8e879a6a9 6011 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
mbed_official 85:e1a8e879a6a9 6012 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
mbed_official 85:e1a8e879a6a9 6013
mbed_official 85:e1a8e879a6a9 6014 /* Register: TWI_TXD */
mbed_official 85:e1a8e879a6a9 6015 /* Description: TX data register. */
mbed_official 85:e1a8e879a6a9 6016
mbed_official 85:e1a8e879a6a9 6017 /* Bits 7..0 : TX data for next transfer. */
mbed_official 85:e1a8e879a6a9 6018 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
mbed_official 85:e1a8e879a6a9 6019 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
mbed_official 85:e1a8e879a6a9 6020
mbed_official 85:e1a8e879a6a9 6021 /* Register: TWI_FREQUENCY */
mbed_official 85:e1a8e879a6a9 6022 /* Description: Two-wire frequency. */
mbed_official 85:e1a8e879a6a9 6023
mbed_official 85:e1a8e879a6a9 6024 /* Bits 31..0 : Two-wire master clock frequency. */
mbed_official 85:e1a8e879a6a9 6025 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 6026 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
mbed_official 85:e1a8e879a6a9 6027 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
mbed_official 85:e1a8e879a6a9 6028 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
mbed_official 85:e1a8e879a6a9 6029 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
mbed_official 85:e1a8e879a6a9 6030
mbed_official 85:e1a8e879a6a9 6031 /* Register: TWI_ADDRESS */
mbed_official 85:e1a8e879a6a9 6032 /* Description: Address used in the two-wire transfer. */
mbed_official 85:e1a8e879a6a9 6033
mbed_official 85:e1a8e879a6a9 6034 /* Bits 6..0 : Two-wire address. */
mbed_official 85:e1a8e879a6a9 6035 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 6036 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
mbed_official 85:e1a8e879a6a9 6037
mbed_official 85:e1a8e879a6a9 6038 /* Register: TWI_POWER */
mbed_official 85:e1a8e879a6a9 6039 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6040
mbed_official 85:e1a8e879a6a9 6041 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6042 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 6043 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 6044 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 6045 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 6046
mbed_official 85:e1a8e879a6a9 6047
mbed_official 85:e1a8e879a6a9 6048 /* Peripheral: UART */
mbed_official 85:e1a8e879a6a9 6049 /* Description: Universal Asynchronous Receiver/Transmitter. */
mbed_official 85:e1a8e879a6a9 6050
mbed_official 85:e1a8e879a6a9 6051 /* Register: UART_SHORTS */
mbed_official 85:e1a8e879a6a9 6052 /* Description: Shortcuts for TWI. */
mbed_official 85:e1a8e879a6a9 6053
mbed_official 85:e1a8e879a6a9 6054 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
mbed_official 85:e1a8e879a6a9 6055 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
mbed_official 85:e1a8e879a6a9 6056 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
mbed_official 85:e1a8e879a6a9 6057 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 6058 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 6059
mbed_official 85:e1a8e879a6a9 6060 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
mbed_official 85:e1a8e879a6a9 6061 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
mbed_official 85:e1a8e879a6a9 6062 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
mbed_official 85:e1a8e879a6a9 6063 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
mbed_official 85:e1a8e879a6a9 6064 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
mbed_official 85:e1a8e879a6a9 6065
mbed_official 85:e1a8e879a6a9 6066 /* Register: UART_INTENSET */
mbed_official 85:e1a8e879a6a9 6067 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 6068
mbed_official 85:e1a8e879a6a9 6069 /* Bit 17 : Enable interrupt on RXTO event. */
mbed_official 85:e1a8e879a6a9 6070 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
mbed_official 85:e1a8e879a6a9 6071 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
mbed_official 85:e1a8e879a6a9 6072 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6073 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6074 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6075
mbed_official 85:e1a8e879a6a9 6076 /* Bit 9 : Enable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 6077 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 6078 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 6079 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6080 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6081 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6082
mbed_official 85:e1a8e879a6a9 6083 /* Bit 7 : Enable interrupt on TXRDY event. */
mbed_official 85:e1a8e879a6a9 6084 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
mbed_official 85:e1a8e879a6a9 6085 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
mbed_official 85:e1a8e879a6a9 6086 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6087 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6088 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6089
mbed_official 85:e1a8e879a6a9 6090 /* Bit 2 : Enable interrupt on RXRDY event. */
mbed_official 85:e1a8e879a6a9 6091 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
mbed_official 85:e1a8e879a6a9 6092 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
mbed_official 85:e1a8e879a6a9 6093 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6094 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6095 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6096
mbed_official 85:e1a8e879a6a9 6097 /* Bit 1 : Enable interrupt on NCTS event. */
mbed_official 85:e1a8e879a6a9 6098 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
mbed_official 85:e1a8e879a6a9 6099 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
mbed_official 85:e1a8e879a6a9 6100 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6101 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6102 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6103
mbed_official 85:e1a8e879a6a9 6104 /* Bit 0 : Enable interrupt on CTS event. */
mbed_official 85:e1a8e879a6a9 6105 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
mbed_official 85:e1a8e879a6a9 6106 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
mbed_official 85:e1a8e879a6a9 6107 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6108 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6109 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6110
mbed_official 85:e1a8e879a6a9 6111 /* Register: UART_INTENCLR */
mbed_official 85:e1a8e879a6a9 6112 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 6113
mbed_official 85:e1a8e879a6a9 6114 /* Bit 17 : Disable interrupt on RXTO event. */
mbed_official 85:e1a8e879a6a9 6115 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
mbed_official 85:e1a8e879a6a9 6116 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
mbed_official 85:e1a8e879a6a9 6117 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6118 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6119 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6120
mbed_official 85:e1a8e879a6a9 6121 /* Bit 9 : Disable interrupt on ERROR event. */
mbed_official 85:e1a8e879a6a9 6122 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
mbed_official 85:e1a8e879a6a9 6123 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
mbed_official 85:e1a8e879a6a9 6124 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6125 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6126 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6127
mbed_official 85:e1a8e879a6a9 6128 /* Bit 7 : Disable interrupt on TXRDY event. */
mbed_official 85:e1a8e879a6a9 6129 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
mbed_official 85:e1a8e879a6a9 6130 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
mbed_official 85:e1a8e879a6a9 6131 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6132 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6133 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6134
mbed_official 85:e1a8e879a6a9 6135 /* Bit 2 : Disable interrupt on RXRDY event. */
mbed_official 85:e1a8e879a6a9 6136 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
mbed_official 85:e1a8e879a6a9 6137 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
mbed_official 85:e1a8e879a6a9 6138 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6139 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6140 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6141
mbed_official 85:e1a8e879a6a9 6142 /* Bit 1 : Disable interrupt on NCTS event. */
mbed_official 85:e1a8e879a6a9 6143 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
mbed_official 85:e1a8e879a6a9 6144 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
mbed_official 85:e1a8e879a6a9 6145 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6146 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6147 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6148
mbed_official 85:e1a8e879a6a9 6149 /* Bit 0 : Disable interrupt on CTS event. */
mbed_official 85:e1a8e879a6a9 6150 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
mbed_official 85:e1a8e879a6a9 6151 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
mbed_official 85:e1a8e879a6a9 6152 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6153 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6154 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6155
mbed_official 85:e1a8e879a6a9 6156 /* Register: UART_ERRORSRC */
mbed_official 85:e1a8e879a6a9 6157 /* Description: Error source. Write error field to 1 to clear error. */
mbed_official 85:e1a8e879a6a9 6158
mbed_official 85:e1a8e879a6a9 6159 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
mbed_official 85:e1a8e879a6a9 6160 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
mbed_official 85:e1a8e879a6a9 6161 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
mbed_official 85:e1a8e879a6a9 6162 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 6163 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 6164 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 6165
mbed_official 85:e1a8e879a6a9 6166 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
mbed_official 85:e1a8e879a6a9 6167 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
mbed_official 85:e1a8e879a6a9 6168 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
mbed_official 85:e1a8e879a6a9 6169 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 6170 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 6171 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 6172
mbed_official 85:e1a8e879a6a9 6173 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
mbed_official 85:e1a8e879a6a9 6174 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
mbed_official 85:e1a8e879a6a9 6175 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
mbed_official 85:e1a8e879a6a9 6176 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 6177 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 6178 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 6179
mbed_official 85:e1a8e879a6a9 6180 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
mbed_official 85:e1a8e879a6a9 6181 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
mbed_official 85:e1a8e879a6a9 6182 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
mbed_official 85:e1a8e879a6a9 6183 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
mbed_official 85:e1a8e879a6a9 6184 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
mbed_official 85:e1a8e879a6a9 6185 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
mbed_official 85:e1a8e879a6a9 6186
mbed_official 85:e1a8e879a6a9 6187 /* Register: UART_ENABLE */
mbed_official 85:e1a8e879a6a9 6188 /* Description: Enable UART and acquire IOs. */
mbed_official 85:e1a8e879a6a9 6189
mbed_official 85:e1a8e879a6a9 6190 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
mbed_official 85:e1a8e879a6a9 6191 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
mbed_official 85:e1a8e879a6a9 6192 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
mbed_official 85:e1a8e879a6a9 6193 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
mbed_official 85:e1a8e879a6a9 6194 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
mbed_official 85:e1a8e879a6a9 6195
mbed_official 85:e1a8e879a6a9 6196 /* Register: UART_RXD */
mbed_official 85:e1a8e879a6a9 6197 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
mbed_official 85:e1a8e879a6a9 6198
mbed_official 85:e1a8e879a6a9 6199 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
mbed_official 85:e1a8e879a6a9 6200 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
mbed_official 85:e1a8e879a6a9 6201 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
mbed_official 85:e1a8e879a6a9 6202
mbed_official 85:e1a8e879a6a9 6203 /* Register: UART_TXD */
mbed_official 85:e1a8e879a6a9 6204 /* Description: TXD register. */
mbed_official 85:e1a8e879a6a9 6205
mbed_official 85:e1a8e879a6a9 6206 /* Bits 7..0 : TX data for transfer. */
mbed_official 85:e1a8e879a6a9 6207 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
mbed_official 85:e1a8e879a6a9 6208 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
mbed_official 85:e1a8e879a6a9 6209
mbed_official 85:e1a8e879a6a9 6210 /* Register: UART_BAUDRATE */
mbed_official 85:e1a8e879a6a9 6211 /* Description: UART Baudrate. */
mbed_official 85:e1a8e879a6a9 6212
mbed_official 85:e1a8e879a6a9 6213 /* Bits 31..0 : UART baudrate. */
mbed_official 85:e1a8e879a6a9 6214 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
mbed_official 85:e1a8e879a6a9 6215 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
mbed_official 85:e1a8e879a6a9 6216 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
mbed_official 85:e1a8e879a6a9 6217 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
mbed_official 85:e1a8e879a6a9 6218 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
mbed_official 85:e1a8e879a6a9 6219 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
mbed_official 85:e1a8e879a6a9 6220 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
mbed_official 85:e1a8e879a6a9 6221 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
mbed_official 85:e1a8e879a6a9 6222 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
mbed_official 85:e1a8e879a6a9 6223 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
mbed_official 85:e1a8e879a6a9 6224 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
mbed_official 85:e1a8e879a6a9 6225 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
mbed_official 85:e1a8e879a6a9 6226 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
mbed_official 85:e1a8e879a6a9 6227 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
mbed_official 85:e1a8e879a6a9 6228 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
mbed_official 85:e1a8e879a6a9 6229 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
mbed_official 85:e1a8e879a6a9 6230 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
mbed_official 85:e1a8e879a6a9 6231 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
mbed_official 85:e1a8e879a6a9 6232
mbed_official 85:e1a8e879a6a9 6233 /* Register: UART_CONFIG */
mbed_official 85:e1a8e879a6a9 6234 /* Description: Configuration of parity and hardware flow control register. */
mbed_official 85:e1a8e879a6a9 6235
mbed_official 85:e1a8e879a6a9 6236 /* Bits 3..1 : Include parity bit. */
mbed_official 85:e1a8e879a6a9 6237 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
mbed_official 85:e1a8e879a6a9 6238 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
mbed_official 85:e1a8e879a6a9 6239 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
mbed_official 85:e1a8e879a6a9 6240 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
mbed_official 85:e1a8e879a6a9 6241
mbed_official 85:e1a8e879a6a9 6242 /* Bit 0 : Hardware flow control. */
mbed_official 85:e1a8e879a6a9 6243 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
mbed_official 85:e1a8e879a6a9 6244 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
mbed_official 85:e1a8e879a6a9 6245 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
mbed_official 85:e1a8e879a6a9 6246 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
mbed_official 85:e1a8e879a6a9 6247
mbed_official 85:e1a8e879a6a9 6248 /* Register: UART_POWER */
mbed_official 85:e1a8e879a6a9 6249 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6250
mbed_official 85:e1a8e879a6a9 6251 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6252 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 6253 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 6254 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 6255 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 6256
mbed_official 85:e1a8e879a6a9 6257
mbed_official 85:e1a8e879a6a9 6258 /* Peripheral: UICR */
mbed_official 85:e1a8e879a6a9 6259 /* Description: User Information Configuration. */
mbed_official 85:e1a8e879a6a9 6260
mbed_official 85:e1a8e879a6a9 6261 /* Register: UICR_RBPCONF */
mbed_official 85:e1a8e879a6a9 6262 /* Description: Readback protection configuration. */
mbed_official 85:e1a8e879a6a9 6263
mbed_official 85:e1a8e879a6a9 6264 /* Bits 15..8 : Readback protect all code in the device. */
mbed_official 85:e1a8e879a6a9 6265 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
mbed_official 85:e1a8e879a6a9 6266 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
mbed_official 85:e1a8e879a6a9 6267 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 6268 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 6269
mbed_official 85:e1a8e879a6a9 6270 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
mbed_official 85:e1a8e879a6a9 6271 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
mbed_official 85:e1a8e879a6a9 6272 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
mbed_official 85:e1a8e879a6a9 6273 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
mbed_official 85:e1a8e879a6a9 6274 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
mbed_official 85:e1a8e879a6a9 6275
mbed_official 85:e1a8e879a6a9 6276 /* Register: UICR_XTALFREQ */
mbed_official 85:e1a8e879a6a9 6277 /* Description: Reset value for CLOCK XTALFREQ register. */
mbed_official 85:e1a8e879a6a9 6278
mbed_official 85:e1a8e879a6a9 6279 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
mbed_official 85:e1a8e879a6a9 6280 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
mbed_official 85:e1a8e879a6a9 6281 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
mbed_official 85:e1a8e879a6a9 6282 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
mbed_official 85:e1a8e879a6a9 6283 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
mbed_official 85:e1a8e879a6a9 6284
mbed_official 85:e1a8e879a6a9 6285 /* Register: UICR_FWID */
mbed_official 85:e1a8e879a6a9 6286 /* Description: Firmware ID. */
mbed_official 85:e1a8e879a6a9 6287
mbed_official 85:e1a8e879a6a9 6288 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
mbed_official 85:e1a8e879a6a9 6289 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
mbed_official 85:e1a8e879a6a9 6290 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
mbed_official 85:e1a8e879a6a9 6291
mbed_official 85:e1a8e879a6a9 6292
mbed_official 85:e1a8e879a6a9 6293 /* Peripheral: WDT */
mbed_official 85:e1a8e879a6a9 6294 /* Description: Watchdog Timer. */
mbed_official 85:e1a8e879a6a9 6295
mbed_official 85:e1a8e879a6a9 6296 /* Register: WDT_INTENSET */
mbed_official 85:e1a8e879a6a9 6297 /* Description: Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 6298
mbed_official 85:e1a8e879a6a9 6299 /* Bit 0 : Enable interrupt on TIMEOUT event. */
mbed_official 85:e1a8e879a6a9 6300 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
mbed_official 85:e1a8e879a6a9 6301 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
mbed_official 85:e1a8e879a6a9 6302 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6303 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6304 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6305
mbed_official 85:e1a8e879a6a9 6306 /* Register: WDT_INTENCLR */
mbed_official 85:e1a8e879a6a9 6307 /* Description: Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 6308
mbed_official 85:e1a8e879a6a9 6309 /* Bit 0 : Disable interrupt on TIMEOUT event. */
mbed_official 85:e1a8e879a6a9 6310 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
mbed_official 85:e1a8e879a6a9 6311 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
mbed_official 85:e1a8e879a6a9 6312 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
mbed_official 85:e1a8e879a6a9 6313 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
mbed_official 85:e1a8e879a6a9 6314 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
mbed_official 85:e1a8e879a6a9 6315
mbed_official 85:e1a8e879a6a9 6316 /* Register: WDT_RUNSTATUS */
mbed_official 85:e1a8e879a6a9 6317 /* Description: Watchdog running status. */
mbed_official 85:e1a8e879a6a9 6318
mbed_official 85:e1a8e879a6a9 6319 /* Bit 0 : Watchdog running status. */
mbed_official 85:e1a8e879a6a9 6320 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
mbed_official 85:e1a8e879a6a9 6321 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
mbed_official 85:e1a8e879a6a9 6322 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
mbed_official 85:e1a8e879a6a9 6323 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
mbed_official 85:e1a8e879a6a9 6324
mbed_official 85:e1a8e879a6a9 6325 /* Register: WDT_REQSTATUS */
mbed_official 85:e1a8e879a6a9 6326 /* Description: Request status. */
mbed_official 85:e1a8e879a6a9 6327
mbed_official 85:e1a8e879a6a9 6328 /* Bit 7 : Request status for RR[7]. */
mbed_official 85:e1a8e879a6a9 6329 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
mbed_official 85:e1a8e879a6a9 6330 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
mbed_official 85:e1a8e879a6a9 6331 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6332 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6333
mbed_official 85:e1a8e879a6a9 6334 /* Bit 6 : Request status for RR[6]. */
mbed_official 85:e1a8e879a6a9 6335 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
mbed_official 85:e1a8e879a6a9 6336 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
mbed_official 85:e1a8e879a6a9 6337 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6338 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6339
mbed_official 85:e1a8e879a6a9 6340 /* Bit 5 : Request status for RR[5]. */
mbed_official 85:e1a8e879a6a9 6341 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
mbed_official 85:e1a8e879a6a9 6342 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
mbed_official 85:e1a8e879a6a9 6343 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6344 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6345
mbed_official 85:e1a8e879a6a9 6346 /* Bit 4 : Request status for RR[4]. */
mbed_official 85:e1a8e879a6a9 6347 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
mbed_official 85:e1a8e879a6a9 6348 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
mbed_official 85:e1a8e879a6a9 6349 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6350 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6351
mbed_official 85:e1a8e879a6a9 6352 /* Bit 3 : Request status for RR[3]. */
mbed_official 85:e1a8e879a6a9 6353 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
mbed_official 85:e1a8e879a6a9 6354 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
mbed_official 85:e1a8e879a6a9 6355 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6356 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6357
mbed_official 85:e1a8e879a6a9 6358 /* Bit 2 : Request status for RR[2]. */
mbed_official 85:e1a8e879a6a9 6359 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
mbed_official 85:e1a8e879a6a9 6360 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
mbed_official 85:e1a8e879a6a9 6361 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6362 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6363
mbed_official 85:e1a8e879a6a9 6364 /* Bit 1 : Request status for RR[1]. */
mbed_official 85:e1a8e879a6a9 6365 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
mbed_official 85:e1a8e879a6a9 6366 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
mbed_official 85:e1a8e879a6a9 6367 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6368 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6369
mbed_official 85:e1a8e879a6a9 6370 /* Bit 0 : Request status for RR[0]. */
mbed_official 85:e1a8e879a6a9 6371 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
mbed_official 85:e1a8e879a6a9 6372 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
mbed_official 85:e1a8e879a6a9 6373 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
mbed_official 85:e1a8e879a6a9 6374 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
mbed_official 85:e1a8e879a6a9 6375
mbed_official 85:e1a8e879a6a9 6376 /* Register: WDT_RREN */
mbed_official 85:e1a8e879a6a9 6377 /* Description: Reload request enable. */
mbed_official 85:e1a8e879a6a9 6378
mbed_official 85:e1a8e879a6a9 6379 /* Bit 7 : Enable or disable RR[7] register. */
mbed_official 85:e1a8e879a6a9 6380 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
mbed_official 85:e1a8e879a6a9 6381 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
mbed_official 85:e1a8e879a6a9 6382 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
mbed_official 85:e1a8e879a6a9 6383 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
mbed_official 85:e1a8e879a6a9 6384
mbed_official 85:e1a8e879a6a9 6385 /* Bit 6 : Enable or disable RR[6] register. */
mbed_official 85:e1a8e879a6a9 6386 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
mbed_official 85:e1a8e879a6a9 6387 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
mbed_official 85:e1a8e879a6a9 6388 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
mbed_official 85:e1a8e879a6a9 6389 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
mbed_official 85:e1a8e879a6a9 6390
mbed_official 85:e1a8e879a6a9 6391 /* Bit 5 : Enable or disable RR[5] register. */
mbed_official 85:e1a8e879a6a9 6392 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
mbed_official 85:e1a8e879a6a9 6393 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
mbed_official 85:e1a8e879a6a9 6394 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
mbed_official 85:e1a8e879a6a9 6395 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
mbed_official 85:e1a8e879a6a9 6396
mbed_official 85:e1a8e879a6a9 6397 /* Bit 4 : Enable or disable RR[4] register. */
mbed_official 85:e1a8e879a6a9 6398 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
mbed_official 85:e1a8e879a6a9 6399 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
mbed_official 85:e1a8e879a6a9 6400 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
mbed_official 85:e1a8e879a6a9 6401 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
mbed_official 85:e1a8e879a6a9 6402
mbed_official 85:e1a8e879a6a9 6403 /* Bit 3 : Enable or disable RR[3] register. */
mbed_official 85:e1a8e879a6a9 6404 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
mbed_official 85:e1a8e879a6a9 6405 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
mbed_official 85:e1a8e879a6a9 6406 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
mbed_official 85:e1a8e879a6a9 6407 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
mbed_official 85:e1a8e879a6a9 6408
mbed_official 85:e1a8e879a6a9 6409 /* Bit 2 : Enable or disable RR[2] register. */
mbed_official 85:e1a8e879a6a9 6410 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
mbed_official 85:e1a8e879a6a9 6411 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
mbed_official 85:e1a8e879a6a9 6412 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
mbed_official 85:e1a8e879a6a9 6413 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
mbed_official 85:e1a8e879a6a9 6414
mbed_official 85:e1a8e879a6a9 6415 /* Bit 1 : Enable or disable RR[1] register. */
mbed_official 85:e1a8e879a6a9 6416 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
mbed_official 85:e1a8e879a6a9 6417 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
mbed_official 85:e1a8e879a6a9 6418 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
mbed_official 85:e1a8e879a6a9 6419 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
mbed_official 85:e1a8e879a6a9 6420
mbed_official 85:e1a8e879a6a9 6421 /* Bit 0 : Enable or disable RR[0] register. */
mbed_official 85:e1a8e879a6a9 6422 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
mbed_official 85:e1a8e879a6a9 6423 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
mbed_official 85:e1a8e879a6a9 6424 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
mbed_official 85:e1a8e879a6a9 6425 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
mbed_official 85:e1a8e879a6a9 6426
mbed_official 85:e1a8e879a6a9 6427 /* Register: WDT_CONFIG */
mbed_official 85:e1a8e879a6a9 6428 /* Description: Configuration register. */
mbed_official 85:e1a8e879a6a9 6429
mbed_official 85:e1a8e879a6a9 6430 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
mbed_official 85:e1a8e879a6a9 6431 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
mbed_official 85:e1a8e879a6a9 6432 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
mbed_official 85:e1a8e879a6a9 6433 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
mbed_official 85:e1a8e879a6a9 6434 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
mbed_official 85:e1a8e879a6a9 6435
mbed_official 85:e1a8e879a6a9 6436 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
mbed_official 85:e1a8e879a6a9 6437 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
mbed_official 85:e1a8e879a6a9 6438 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
mbed_official 85:e1a8e879a6a9 6439 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
mbed_official 85:e1a8e879a6a9 6440 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
mbed_official 85:e1a8e879a6a9 6441
mbed_official 85:e1a8e879a6a9 6442 /* Register: WDT_RR */
mbed_official 85:e1a8e879a6a9 6443 /* Description: Reload requests registers. */
mbed_official 85:e1a8e879a6a9 6444
mbed_official 85:e1a8e879a6a9 6445 /* Bits 31..0 : Reload register. */
mbed_official 85:e1a8e879a6a9 6446 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
mbed_official 85:e1a8e879a6a9 6447 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
mbed_official 85:e1a8e879a6a9 6448 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
mbed_official 85:e1a8e879a6a9 6449
mbed_official 85:e1a8e879a6a9 6450 /* Register: WDT_POWER */
mbed_official 85:e1a8e879a6a9 6451 /* Description: Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6452
mbed_official 85:e1a8e879a6a9 6453 /* Bit 0 : Peripheral power control. */
mbed_official 85:e1a8e879a6a9 6454 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
mbed_official 85:e1a8e879a6a9 6455 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
mbed_official 85:e1a8e879a6a9 6456 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
mbed_official 85:e1a8e879a6a9 6457 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
mbed_official 85:e1a8e879a6a9 6458
mbed_official 85:e1a8e879a6a9 6459
mbed_official 85:e1a8e879a6a9 6460 /*lint --flb "Leave library region" */
mbed_official 85:e1a8e879a6a9 6461 #endif