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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c@392:2b59412bb664, 2014-11-07 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Nov 07 08:15:08 2014 +0000
- Revision:
- 392:2b59412bb664
- Parent:
- targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_smbus.c@340:28d1f895c6fe
- Child:
- 441:d2c15dda23c1
Synchronized with git revision eec0be05cd92349bee83c65f9e1302b25b5badf4
Full URL: https://github.com/mbedmicro/mbed/commit/eec0be05cd92349bee83c65f9e1302b25b5badf4/
Targets: STM32F0 - Factorisation of NUCLEO_F030R8/F072RB/F091RC cmsis folders
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 340:28d1f895c6fe | 1 | /** |
mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_smbus.c |
mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
mbed_official | 340:28d1f895c6fe | 5 | * @version V1.1.0 |
mbed_official | 340:28d1f895c6fe | 6 | * @date 03-Oct-2014 |
mbed_official | 340:28d1f895c6fe | 7 | * @brief SMBUS HAL module driver. |
mbed_official | 340:28d1f895c6fe | 8 | * |
mbed_official | 340:28d1f895c6fe | 9 | * This file provides firmware functions to manage the following |
mbed_official | 340:28d1f895c6fe | 10 | * functionalities of the System Management Bus (SMBus) peripheral, |
mbed_official | 340:28d1f895c6fe | 11 | * based on I2C principales of operation : |
mbed_official | 340:28d1f895c6fe | 12 | * + Initialization and de-initialization functions |
mbed_official | 340:28d1f895c6fe | 13 | * + IO operation functions |
mbed_official | 340:28d1f895c6fe | 14 | * + Peripheral State and Errors functions |
mbed_official | 340:28d1f895c6fe | 15 | * |
mbed_official | 340:28d1f895c6fe | 16 | @verbatim |
mbed_official | 340:28d1f895c6fe | 17 | ============================================================================== |
mbed_official | 340:28d1f895c6fe | 18 | ##### How to use this driver ##### |
mbed_official | 340:28d1f895c6fe | 19 | ============================================================================== |
mbed_official | 340:28d1f895c6fe | 20 | [..] |
mbed_official | 340:28d1f895c6fe | 21 | The SMBUS HAL driver can be used as follows: |
mbed_official | 340:28d1f895c6fe | 22 | |
mbed_official | 340:28d1f895c6fe | 23 | (#) Declare a SMBUS_HandleTypeDef handle structure, for example: |
mbed_official | 340:28d1f895c6fe | 24 | SMBUS_HandleTypeDef hsmbus; |
mbed_official | 340:28d1f895c6fe | 25 | |
mbed_official | 340:28d1f895c6fe | 26 | (#)Initialize the SMBUS low level resources by implement the HAL_SMBUS_MspInit ()API: |
mbed_official | 340:28d1f895c6fe | 27 | (##) Enable the SMBUSx interface clock |
mbed_official | 340:28d1f895c6fe | 28 | (##) SMBUS pins configuration |
mbed_official | 340:28d1f895c6fe | 29 | (+++) Enable the clock for the SMBUS GPIOs |
mbed_official | 340:28d1f895c6fe | 30 | (+++) Configure SMBUS pins as alternate function open-drain |
mbed_official | 340:28d1f895c6fe | 31 | (##) NVIC configuration if you need to use interrupt process |
mbed_official | 340:28d1f895c6fe | 32 | (+++) Configure the SMBUSx interrupt priority |
mbed_official | 340:28d1f895c6fe | 33 | (+++) Enable the NVIC SMBUS IRQ Channel |
mbed_official | 340:28d1f895c6fe | 34 | |
mbed_official | 340:28d1f895c6fe | 35 | (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Adressing Mode, |
mbed_official | 340:28d1f895c6fe | 36 | Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, |
mbed_official | 340:28d1f895c6fe | 37 | Peripheral mode and Packet Error Check mode in the hsmbus Init structure. |
mbed_official | 340:28d1f895c6fe | 38 | |
mbed_official | 340:28d1f895c6fe | 39 | (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: |
mbed_official | 340:28d1f895c6fe | 40 | (++) These API s configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) |
mbed_official | 340:28d1f895c6fe | 41 | by calling the customed HAL_SMBUS_MspInit(&hsmbus) API. |
mbed_official | 340:28d1f895c6fe | 42 | |
mbed_official | 340:28d1f895c6fe | 43 | (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() |
mbed_official | 340:28d1f895c6fe | 44 | |
mbed_official | 340:28d1f895c6fe | 45 | (#) For SMBUS IO operations, only one mode of operations is available within this driver : |
mbed_official | 340:28d1f895c6fe | 46 | |
mbed_official | 340:28d1f895c6fe | 47 | *** Interrupt mode IO operation *** |
mbed_official | 340:28d1f895c6fe | 48 | =================================== |
mbed_official | 340:28d1f895c6fe | 49 | [..] |
mbed_official | 340:28d1f895c6fe | 50 | (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT() |
mbed_official | 340:28d1f895c6fe | 51 | (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 52 | add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback |
mbed_official | 340:28d1f895c6fe | 53 | (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT() |
mbed_official | 340:28d1f895c6fe | 54 | (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 55 | add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback |
mbed_official | 340:28d1f895c6fe | 56 | (+) Abort a master/host SMBUS process commnunication with Interrupt using HAL_SMBUS_Master_Abort_IT() |
mbed_official | 340:28d1f895c6fe | 57 | (++) The associated previous transfer callback is called at the end of abort process |
mbed_official | 340:28d1f895c6fe | 58 | (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit |
mbed_official | 340:28d1f895c6fe | 59 | (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive |
mbed_official | 340:28d1f895c6fe | 60 | (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode |
mbed_official | 340:28d1f895c6fe | 61 | using HAL_SMBUS_Slave_Listen_IT() HAL_SMBUS_DisableListen_IT() |
mbed_official | 340:28d1f895c6fe | 62 | (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 63 | add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). |
mbed_official | 340:28d1f895c6fe | 64 | (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 65 | add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback |
mbed_official | 340:28d1f895c6fe | 66 | (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() |
mbed_official | 340:28d1f895c6fe | 67 | (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 68 | add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback |
mbed_official | 340:28d1f895c6fe | 69 | (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT() |
mbed_official | 340:28d1f895c6fe | 70 | (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback is executed and user can |
mbed_official | 340:28d1f895c6fe | 71 | add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback |
mbed_official | 340:28d1f895c6fe | 72 | (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT() |
mbed_official | 340:28d1f895c6fe | 73 | (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can |
mbed_official | 340:28d1f895c6fe | 74 | add his own code by customization of function pointer HAL_SMBUS_ErrorCallback |
mbed_official | 340:28d1f895c6fe | 75 | to check the Alert Error Code using function HAL_SMBUS_GetError() |
mbed_official | 340:28d1f895c6fe | 76 | (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() |
mbed_official | 340:28d1f895c6fe | 77 | (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can |
mbed_official | 340:28d1f895c6fe | 78 | add his own code by customization of function pointer HAL_SMBUS_ErrorCallback |
mbed_official | 340:28d1f895c6fe | 79 | to check the Error Code using function HAL_SMBUS_GetError() |
mbed_official | 340:28d1f895c6fe | 80 | |
mbed_official | 340:28d1f895c6fe | 81 | *** SMBUS HAL driver macros list *** |
mbed_official | 340:28d1f895c6fe | 82 | ================================== |
mbed_official | 340:28d1f895c6fe | 83 | [..] |
mbed_official | 340:28d1f895c6fe | 84 | Below the list of most used macros in SMBUS HAL driver. |
mbed_official | 340:28d1f895c6fe | 85 | |
mbed_official | 340:28d1f895c6fe | 86 | (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral |
mbed_official | 340:28d1f895c6fe | 87 | (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral |
mbed_official | 340:28d1f895c6fe | 88 | (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not |
mbed_official | 340:28d1f895c6fe | 89 | (+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag |
mbed_official | 340:28d1f895c6fe | 90 | (+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt |
mbed_official | 340:28d1f895c6fe | 91 | (+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt |
mbed_official | 340:28d1f895c6fe | 92 | |
mbed_official | 340:28d1f895c6fe | 93 | [..] |
mbed_official | 340:28d1f895c6fe | 94 | (@) You can refer to the SMBUS HAL driver header file for more useful macros |
mbed_official | 340:28d1f895c6fe | 95 | |
mbed_official | 340:28d1f895c6fe | 96 | |
mbed_official | 340:28d1f895c6fe | 97 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 98 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 99 | * @attention |
mbed_official | 340:28d1f895c6fe | 100 | * |
mbed_official | 340:28d1f895c6fe | 101 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 340:28d1f895c6fe | 102 | * |
mbed_official | 340:28d1f895c6fe | 103 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 340:28d1f895c6fe | 104 | * are permitted provided that the following conditions are met: |
mbed_official | 340:28d1f895c6fe | 105 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 106 | * this list of conditions and the following disclaimer. |
mbed_official | 340:28d1f895c6fe | 107 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 340:28d1f895c6fe | 108 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 340:28d1f895c6fe | 109 | * and/or other materials provided with the distribution. |
mbed_official | 340:28d1f895c6fe | 110 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 340:28d1f895c6fe | 111 | * may be used to endorse or promote products derived from this software |
mbed_official | 340:28d1f895c6fe | 112 | * without specific prior written permission. |
mbed_official | 340:28d1f895c6fe | 113 | * |
mbed_official | 340:28d1f895c6fe | 114 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 340:28d1f895c6fe | 115 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 340:28d1f895c6fe | 116 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 340:28d1f895c6fe | 117 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 340:28d1f895c6fe | 118 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 340:28d1f895c6fe | 119 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 340:28d1f895c6fe | 120 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 340:28d1f895c6fe | 121 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 340:28d1f895c6fe | 122 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 340:28d1f895c6fe | 123 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 340:28d1f895c6fe | 124 | * |
mbed_official | 340:28d1f895c6fe | 125 | ****************************************************************************** |
mbed_official | 340:28d1f895c6fe | 126 | */ |
mbed_official | 340:28d1f895c6fe | 127 | |
mbed_official | 340:28d1f895c6fe | 128 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 129 | #include "stm32f0xx_hal.h" |
mbed_official | 340:28d1f895c6fe | 130 | |
mbed_official | 340:28d1f895c6fe | 131 | /** @addtogroup STM32F0xx_HAL_Driver |
mbed_official | 340:28d1f895c6fe | 132 | * @{ |
mbed_official | 340:28d1f895c6fe | 133 | */ |
mbed_official | 340:28d1f895c6fe | 134 | |
mbed_official | 340:28d1f895c6fe | 135 | /** @defgroup SMBUS SMBUS HAL module driver |
mbed_official | 340:28d1f895c6fe | 136 | * @brief SMBUS HAL module driver |
mbed_official | 340:28d1f895c6fe | 137 | * @{ |
mbed_official | 340:28d1f895c6fe | 138 | */ |
mbed_official | 340:28d1f895c6fe | 139 | |
mbed_official | 340:28d1f895c6fe | 140 | #ifdef HAL_SMBUS_MODULE_ENABLED |
mbed_official | 340:28d1f895c6fe | 141 | |
mbed_official | 340:28d1f895c6fe | 142 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 143 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 144 | /** @defgroup SMBUS_Private_Define SMBUS Private Define |
mbed_official | 340:28d1f895c6fe | 145 | * @{ |
mbed_official | 340:28d1f895c6fe | 146 | */ |
mbed_official | 340:28d1f895c6fe | 147 | #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! SMBUS TIMING clear register Mask */ |
mbed_official | 340:28d1f895c6fe | 148 | #define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */ |
mbed_official | 340:28d1f895c6fe | 149 | #define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 150 | #define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 151 | #define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 152 | #define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 153 | #define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 154 | #define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 155 | #define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */ |
mbed_official | 340:28d1f895c6fe | 156 | #define MAX_NBYTE_SIZE 255 |
mbed_official | 340:28d1f895c6fe | 157 | /** |
mbed_official | 340:28d1f895c6fe | 158 | * @} |
mbed_official | 340:28d1f895c6fe | 159 | */ |
mbed_official | 340:28d1f895c6fe | 160 | |
mbed_official | 340:28d1f895c6fe | 161 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 162 | /** @defgroup SMBUS_Private_Macros SMBUS Private Macros |
mbed_official | 340:28d1f895c6fe | 163 | * @{ |
mbed_official | 340:28d1f895c6fe | 164 | */ |
mbed_official | 340:28d1f895c6fe | 165 | #define __SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) |
mbed_official | 340:28d1f895c6fe | 166 | #define __SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
mbed_official | 340:28d1f895c6fe | 167 | /** |
mbed_official | 340:28d1f895c6fe | 168 | * @} |
mbed_official | 340:28d1f895c6fe | 169 | */ |
mbed_official | 340:28d1f895c6fe | 170 | |
mbed_official | 340:28d1f895c6fe | 171 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 172 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 173 | /** @defgroup SMBUS_Private_Functions SMBUS Private Functions |
mbed_official | 340:28d1f895c6fe | 174 | * @{ |
mbed_official | 340:28d1f895c6fe | 175 | */ |
mbed_official | 340:28d1f895c6fe | 176 | static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); |
mbed_official | 340:28d1f895c6fe | 177 | |
mbed_official | 340:28d1f895c6fe | 178 | static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); |
mbed_official | 340:28d1f895c6fe | 179 | static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest); |
mbed_official | 340:28d1f895c6fe | 180 | static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus); |
mbed_official | 340:28d1f895c6fe | 181 | static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus); |
mbed_official | 340:28d1f895c6fe | 182 | |
mbed_official | 340:28d1f895c6fe | 183 | static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); |
mbed_official | 340:28d1f895c6fe | 184 | /** |
mbed_official | 340:28d1f895c6fe | 185 | * @} |
mbed_official | 340:28d1f895c6fe | 186 | */ |
mbed_official | 340:28d1f895c6fe | 187 | |
mbed_official | 340:28d1f895c6fe | 188 | /* Exported functions ---------------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 189 | |
mbed_official | 340:28d1f895c6fe | 190 | /** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions |
mbed_official | 340:28d1f895c6fe | 191 | * @{ |
mbed_official | 340:28d1f895c6fe | 192 | */ |
mbed_official | 340:28d1f895c6fe | 193 | |
mbed_official | 340:28d1f895c6fe | 194 | /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
mbed_official | 340:28d1f895c6fe | 195 | * @brief Initialization and Configuration functions |
mbed_official | 340:28d1f895c6fe | 196 | * |
mbed_official | 340:28d1f895c6fe | 197 | @verbatim |
mbed_official | 340:28d1f895c6fe | 198 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 199 | ##### Initialization and de-initialization functions ##### |
mbed_official | 340:28d1f895c6fe | 200 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 201 | [..] This subsection provides a set of functions allowing to initialize and |
mbed_official | 340:28d1f895c6fe | 202 | de-initialiaze the SMBUSx peripheral: |
mbed_official | 340:28d1f895c6fe | 203 | |
mbed_official | 340:28d1f895c6fe | 204 | (+) User must Implement HAL_SMBUS_MspInit() function in which he configures |
mbed_official | 340:28d1f895c6fe | 205 | all related peripherals resources (CLOCK, GPIO, IT and NVIC ). |
mbed_official | 340:28d1f895c6fe | 206 | |
mbed_official | 340:28d1f895c6fe | 207 | (+) Call the function HAL_SMBUS_Init() to configure the selected device with |
mbed_official | 340:28d1f895c6fe | 208 | the selected configuration: |
mbed_official | 340:28d1f895c6fe | 209 | (++) Clock Timing |
mbed_official | 340:28d1f895c6fe | 210 | (++) Bus Timeout |
mbed_official | 340:28d1f895c6fe | 211 | (++) Analog Filer mode |
mbed_official | 340:28d1f895c6fe | 212 | (++) Own Address 1 |
mbed_official | 340:28d1f895c6fe | 213 | (++) Addressing mode (Master, Slave) |
mbed_official | 340:28d1f895c6fe | 214 | (++) Dual Addressing mode |
mbed_official | 340:28d1f895c6fe | 215 | (++) Own Address 2 |
mbed_official | 340:28d1f895c6fe | 216 | (++) Own Address 2 Mask |
mbed_official | 340:28d1f895c6fe | 217 | (++) General call mode |
mbed_official | 340:28d1f895c6fe | 218 | (++) Nostretch mode |
mbed_official | 340:28d1f895c6fe | 219 | (++) Packet Error Check mode |
mbed_official | 340:28d1f895c6fe | 220 | (++) Peripheral mode |
mbed_official | 340:28d1f895c6fe | 221 | |
mbed_official | 340:28d1f895c6fe | 222 | |
mbed_official | 340:28d1f895c6fe | 223 | (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration |
mbed_official | 340:28d1f895c6fe | 224 | of the selected SMBUSx periperal. |
mbed_official | 340:28d1f895c6fe | 225 | |
mbed_official | 340:28d1f895c6fe | 226 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 227 | * @{ |
mbed_official | 340:28d1f895c6fe | 228 | */ |
mbed_official | 340:28d1f895c6fe | 229 | |
mbed_official | 340:28d1f895c6fe | 230 | /** |
mbed_official | 340:28d1f895c6fe | 231 | * @brief Initializes the SMBUS according to the specified parameters |
mbed_official | 340:28d1f895c6fe | 232 | * in the SMBUS_InitTypeDef and create the associated handle. |
mbed_official | 340:28d1f895c6fe | 233 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 234 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 235 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 236 | */ |
mbed_official | 340:28d1f895c6fe | 237 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 238 | { |
mbed_official | 340:28d1f895c6fe | 239 | /* Check the SMBUS handle allocation */ |
mbed_official | 340:28d1f895c6fe | 240 | if(hsmbus == HAL_NULL) |
mbed_official | 340:28d1f895c6fe | 241 | { |
mbed_official | 340:28d1f895c6fe | 242 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 243 | } |
mbed_official | 340:28d1f895c6fe | 244 | |
mbed_official | 340:28d1f895c6fe | 245 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 246 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
mbed_official | 340:28d1f895c6fe | 247 | assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); |
mbed_official | 340:28d1f895c6fe | 248 | assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); |
mbed_official | 340:28d1f895c6fe | 249 | assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); |
mbed_official | 340:28d1f895c6fe | 250 | assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); |
mbed_official | 340:28d1f895c6fe | 251 | assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); |
mbed_official | 340:28d1f895c6fe | 252 | assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); |
mbed_official | 340:28d1f895c6fe | 253 | assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); |
mbed_official | 340:28d1f895c6fe | 254 | assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); |
mbed_official | 340:28d1f895c6fe | 255 | assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); |
mbed_official | 340:28d1f895c6fe | 256 | assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); |
mbed_official | 340:28d1f895c6fe | 257 | |
mbed_official | 340:28d1f895c6fe | 258 | if(hsmbus->State == HAL_SMBUS_STATE_RESET) |
mbed_official | 340:28d1f895c6fe | 259 | { |
mbed_official | 340:28d1f895c6fe | 260 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
mbed_official | 340:28d1f895c6fe | 261 | HAL_SMBUS_MspInit(hsmbus); |
mbed_official | 340:28d1f895c6fe | 262 | } |
mbed_official | 340:28d1f895c6fe | 263 | |
mbed_official | 340:28d1f895c6fe | 264 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
mbed_official | 340:28d1f895c6fe | 265 | |
mbed_official | 340:28d1f895c6fe | 266 | /* Disable the selected SMBUS peripheral */ |
mbed_official | 340:28d1f895c6fe | 267 | __HAL_SMBUS_DISABLE(hsmbus); |
mbed_official | 340:28d1f895c6fe | 268 | |
mbed_official | 340:28d1f895c6fe | 269 | /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 270 | /* Configure SMBUSx: Frequency range */ |
mbed_official | 340:28d1f895c6fe | 271 | hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; |
mbed_official | 340:28d1f895c6fe | 272 | |
mbed_official | 340:28d1f895c6fe | 273 | /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 274 | /* Configure SMBUSx: Bus Timeout */ |
mbed_official | 340:28d1f895c6fe | 275 | hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; |
mbed_official | 340:28d1f895c6fe | 276 | hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; |
mbed_official | 340:28d1f895c6fe | 277 | hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; |
mbed_official | 340:28d1f895c6fe | 278 | |
mbed_official | 340:28d1f895c6fe | 279 | /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ |
mbed_official | 340:28d1f895c6fe | 280 | /* Configure SMBUSx: Own Address1 and ack own address1 mode */ |
mbed_official | 340:28d1f895c6fe | 281 | hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; |
mbed_official | 340:28d1f895c6fe | 282 | |
mbed_official | 340:28d1f895c6fe | 283 | if(hsmbus->Init.OwnAddress1 != 0) |
mbed_official | 340:28d1f895c6fe | 284 | { |
mbed_official | 340:28d1f895c6fe | 285 | if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) |
mbed_official | 340:28d1f895c6fe | 286 | { |
mbed_official | 340:28d1f895c6fe | 287 | hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); |
mbed_official | 340:28d1f895c6fe | 288 | } |
mbed_official | 340:28d1f895c6fe | 289 | else /* SMBUS_ADDRESSINGMODE_10BIT */ |
mbed_official | 340:28d1f895c6fe | 290 | { |
mbed_official | 340:28d1f895c6fe | 291 | hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); |
mbed_official | 340:28d1f895c6fe | 292 | } |
mbed_official | 340:28d1f895c6fe | 293 | } |
mbed_official | 340:28d1f895c6fe | 294 | |
mbed_official | 340:28d1f895c6fe | 295 | /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 296 | /* Configure SMBUSx: Addressing Master mode */ |
mbed_official | 340:28d1f895c6fe | 297 | if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) |
mbed_official | 340:28d1f895c6fe | 298 | { |
mbed_official | 340:28d1f895c6fe | 299 | hsmbus->Instance->CR2 = (I2C_CR2_ADD10); |
mbed_official | 340:28d1f895c6fe | 300 | } |
mbed_official | 340:28d1f895c6fe | 301 | /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ |
mbed_official | 340:28d1f895c6fe | 302 | /* AUTOEND and NACK bit will be manage during Transfer process */ |
mbed_official | 340:28d1f895c6fe | 303 | hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); |
mbed_official | 340:28d1f895c6fe | 304 | |
mbed_official | 340:28d1f895c6fe | 305 | /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ |
mbed_official | 340:28d1f895c6fe | 306 | /* Configure SMBUSx: Dual mode and Own Address2 */ |
mbed_official | 340:28d1f895c6fe | 307 | hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8)); |
mbed_official | 340:28d1f895c6fe | 308 | |
mbed_official | 340:28d1f895c6fe | 309 | /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ |
mbed_official | 340:28d1f895c6fe | 310 | /* Configure SMBUSx: Generalcall and NoStretch mode */ |
mbed_official | 340:28d1f895c6fe | 311 | hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); |
mbed_official | 340:28d1f895c6fe | 312 | |
mbed_official | 340:28d1f895c6fe | 313 | /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ |
mbed_official | 340:28d1f895c6fe | 314 | if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED) |
mbed_official | 340:28d1f895c6fe | 315 | && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) |
mbed_official | 340:28d1f895c6fe | 316 | { |
mbed_official | 340:28d1f895c6fe | 317 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
mbed_official | 340:28d1f895c6fe | 318 | } |
mbed_official | 340:28d1f895c6fe | 319 | |
mbed_official | 340:28d1f895c6fe | 320 | /* Enable the selected SMBUS peripheral */ |
mbed_official | 340:28d1f895c6fe | 321 | __HAL_SMBUS_ENABLE(hsmbus); |
mbed_official | 340:28d1f895c6fe | 322 | |
mbed_official | 340:28d1f895c6fe | 323 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 324 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 325 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 326 | |
mbed_official | 340:28d1f895c6fe | 327 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 328 | } |
mbed_official | 340:28d1f895c6fe | 329 | |
mbed_official | 340:28d1f895c6fe | 330 | /** |
mbed_official | 340:28d1f895c6fe | 331 | * @brief DeInitializes the SMBUS peripheral. |
mbed_official | 340:28d1f895c6fe | 332 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 333 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 334 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 335 | */ |
mbed_official | 340:28d1f895c6fe | 336 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 337 | { |
mbed_official | 340:28d1f895c6fe | 338 | /* Check the SMBUS handle allocation */ |
mbed_official | 340:28d1f895c6fe | 339 | if(hsmbus == HAL_NULL) |
mbed_official | 340:28d1f895c6fe | 340 | { |
mbed_official | 340:28d1f895c6fe | 341 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 342 | } |
mbed_official | 340:28d1f895c6fe | 343 | |
mbed_official | 340:28d1f895c6fe | 344 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 345 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
mbed_official | 340:28d1f895c6fe | 346 | |
mbed_official | 340:28d1f895c6fe | 347 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
mbed_official | 340:28d1f895c6fe | 348 | |
mbed_official | 340:28d1f895c6fe | 349 | /* Disable the SMBUS Peripheral Clock */ |
mbed_official | 340:28d1f895c6fe | 350 | __HAL_SMBUS_DISABLE(hsmbus); |
mbed_official | 340:28d1f895c6fe | 351 | |
mbed_official | 340:28d1f895c6fe | 352 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
mbed_official | 340:28d1f895c6fe | 353 | HAL_SMBUS_MspDeInit(hsmbus); |
mbed_official | 340:28d1f895c6fe | 354 | |
mbed_official | 340:28d1f895c6fe | 355 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 356 | hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; |
mbed_official | 340:28d1f895c6fe | 357 | hsmbus->State = HAL_SMBUS_STATE_RESET; |
mbed_official | 340:28d1f895c6fe | 358 | |
mbed_official | 340:28d1f895c6fe | 359 | /* Release Lock */ |
mbed_official | 340:28d1f895c6fe | 360 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 361 | |
mbed_official | 340:28d1f895c6fe | 362 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 363 | } |
mbed_official | 340:28d1f895c6fe | 364 | |
mbed_official | 340:28d1f895c6fe | 365 | /** |
mbed_official | 340:28d1f895c6fe | 366 | * @brief SMBUS MSP Init. |
mbed_official | 340:28d1f895c6fe | 367 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 368 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 369 | * @retval None |
mbed_official | 340:28d1f895c6fe | 370 | */ |
mbed_official | 340:28d1f895c6fe | 371 | __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 372 | { |
mbed_official | 340:28d1f895c6fe | 373 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 374 | the HAL_SMBUS_MspInit could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 375 | */ |
mbed_official | 340:28d1f895c6fe | 376 | } |
mbed_official | 340:28d1f895c6fe | 377 | |
mbed_official | 340:28d1f895c6fe | 378 | /** |
mbed_official | 340:28d1f895c6fe | 379 | * @brief SMBUS MSP DeInit |
mbed_official | 340:28d1f895c6fe | 380 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 381 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 382 | * @retval None |
mbed_official | 340:28d1f895c6fe | 383 | */ |
mbed_official | 340:28d1f895c6fe | 384 | __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 385 | { |
mbed_official | 340:28d1f895c6fe | 386 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 387 | the HAL_SMBUS_MspDeInit could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 388 | */ |
mbed_official | 340:28d1f895c6fe | 389 | } |
mbed_official | 340:28d1f895c6fe | 390 | |
mbed_official | 340:28d1f895c6fe | 391 | /** |
mbed_official | 340:28d1f895c6fe | 392 | * @} |
mbed_official | 340:28d1f895c6fe | 393 | */ |
mbed_official | 340:28d1f895c6fe | 394 | |
mbed_official | 340:28d1f895c6fe | 395 | /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
mbed_official | 340:28d1f895c6fe | 396 | * @brief Data transfers functions |
mbed_official | 340:28d1f895c6fe | 397 | * |
mbed_official | 340:28d1f895c6fe | 398 | @verbatim |
mbed_official | 340:28d1f895c6fe | 399 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 400 | ##### IO operation functions ##### |
mbed_official | 340:28d1f895c6fe | 401 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 402 | [..] |
mbed_official | 340:28d1f895c6fe | 403 | This subsection provides a set of functions allowing to manage the SMBUS data |
mbed_official | 340:28d1f895c6fe | 404 | transfers. |
mbed_official | 340:28d1f895c6fe | 405 | |
mbed_official | 340:28d1f895c6fe | 406 | (#) Blocking mode function to check if device is ready for usage is : |
mbed_official | 340:28d1f895c6fe | 407 | (++) HAL_SMBUS_IsDeviceReady() |
mbed_official | 340:28d1f895c6fe | 408 | |
mbed_official | 340:28d1f895c6fe | 409 | (#) There is only one mode of transfer: |
mbed_official | 340:28d1f895c6fe | 410 | (++) No-Blocking mode : The communication is performed using Interrupts. |
mbed_official | 340:28d1f895c6fe | 411 | These functions return the status of the transfer startup. |
mbed_official | 340:28d1f895c6fe | 412 | The end of the data processing will be indicated through the |
mbed_official | 340:28d1f895c6fe | 413 | dedicated SMBUS IRQ when using Interrupt mode. |
mbed_official | 340:28d1f895c6fe | 414 | |
mbed_official | 340:28d1f895c6fe | 415 | (#) No-Blocking mode functions with Interrupt are : |
mbed_official | 340:28d1f895c6fe | 416 | (++) HAL_SMBUS_Master_Transmit_IT() |
mbed_official | 340:28d1f895c6fe | 417 | (++) HAL_SMBUS_Master_Receive_IT() |
mbed_official | 340:28d1f895c6fe | 418 | (++) HAL_SMBUS_Slave_Transmit_IT() |
mbed_official | 340:28d1f895c6fe | 419 | (++) HAL_SMBUS_Slave_Receive_IT() |
mbed_official | 340:28d1f895c6fe | 420 | (++) HAL_SMBUS_Slave_Listen_IT() or alias HAL_SMBUS_EnableListen_IT() |
mbed_official | 340:28d1f895c6fe | 421 | (++) HAL_SMBUS_DisableListen_IT() |
mbed_official | 340:28d1f895c6fe | 422 | (++) HAL_SMBUS_EnableAlert_IT() |
mbed_official | 340:28d1f895c6fe | 423 | (++) HAL_SMBUS_DisableAlert_IT() |
mbed_official | 340:28d1f895c6fe | 424 | |
mbed_official | 340:28d1f895c6fe | 425 | (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: |
mbed_official | 340:28d1f895c6fe | 426 | (++) HAL_SMBUS_MasterTxCpltCallback() |
mbed_official | 340:28d1f895c6fe | 427 | (++) HAL_SMBUS_MasterRxCpltCallback() |
mbed_official | 340:28d1f895c6fe | 428 | (++) HAL_SMBUS_SlaveTxCpltCallback() |
mbed_official | 340:28d1f895c6fe | 429 | (++) HAL_SMBUS_SlaveRxCpltCallback() |
mbed_official | 340:28d1f895c6fe | 430 | (++) HAL_SMBUS_SlaveAddrCallback() or alias HAL_SMBUS_AddrCallback() |
mbed_official | 340:28d1f895c6fe | 431 | (++) HAL_SMBUS_SlaveListenCpltCallback() or alias HAL_SMBUS_ListenCpltCallback() |
mbed_official | 340:28d1f895c6fe | 432 | (++) HAL_SMBUS_ErrorCallback() |
mbed_official | 340:28d1f895c6fe | 433 | |
mbed_official | 340:28d1f895c6fe | 434 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 435 | * @{ |
mbed_official | 340:28d1f895c6fe | 436 | */ |
mbed_official | 340:28d1f895c6fe | 437 | |
mbed_official | 340:28d1f895c6fe | 438 | /** |
mbed_official | 340:28d1f895c6fe | 439 | * @brief Transmit in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt |
mbed_official | 340:28d1f895c6fe | 440 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 441 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 442 | * @param DevAddress: Target device address |
mbed_official | 340:28d1f895c6fe | 443 | * @param pData: Pointer to data buffer |
mbed_official | 340:28d1f895c6fe | 444 | * @param Size: Amount of data to be sent |
mbed_official | 340:28d1f895c6fe | 445 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
mbed_official | 340:28d1f895c6fe | 446 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 447 | */ |
mbed_official | 340:28d1f895c6fe | 448 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
mbed_official | 340:28d1f895c6fe | 449 | { |
mbed_official | 340:28d1f895c6fe | 450 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 451 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
mbed_official | 340:28d1f895c6fe | 452 | |
mbed_official | 340:28d1f895c6fe | 453 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
mbed_official | 340:28d1f895c6fe | 454 | { |
mbed_official | 340:28d1f895c6fe | 455 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 456 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 457 | |
mbed_official | 340:28d1f895c6fe | 458 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; |
mbed_official | 340:28d1f895c6fe | 459 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 460 | /* Prepare transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 461 | hsmbus->pBuffPtr = pData; |
mbed_official | 340:28d1f895c6fe | 462 | hsmbus->XferCount = Size; |
mbed_official | 340:28d1f895c6fe | 463 | hsmbus->XferOptions = XferOptions; |
mbed_official | 340:28d1f895c6fe | 464 | |
mbed_official | 340:28d1f895c6fe | 465 | /* In case of Quick command, remove autoend mode */ |
mbed_official | 340:28d1f895c6fe | 466 | /* Manage the stop generation by software */ |
mbed_official | 340:28d1f895c6fe | 467 | if(hsmbus->pBuffPtr == HAL_NULL) |
mbed_official | 340:28d1f895c6fe | 468 | { |
mbed_official | 340:28d1f895c6fe | 469 | hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; |
mbed_official | 340:28d1f895c6fe | 470 | } |
mbed_official | 340:28d1f895c6fe | 471 | |
mbed_official | 340:28d1f895c6fe | 472 | if(Size > MAX_NBYTE_SIZE) |
mbed_official | 340:28d1f895c6fe | 473 | { |
mbed_official | 340:28d1f895c6fe | 474 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
mbed_official | 340:28d1f895c6fe | 475 | } |
mbed_official | 340:28d1f895c6fe | 476 | else |
mbed_official | 340:28d1f895c6fe | 477 | { |
mbed_official | 340:28d1f895c6fe | 478 | hsmbus->XferSize = Size; |
mbed_official | 340:28d1f895c6fe | 479 | } |
mbed_official | 340:28d1f895c6fe | 480 | |
mbed_official | 340:28d1f895c6fe | 481 | /* Send Slave Address */ |
mbed_official | 340:28d1f895c6fe | 482 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
mbed_official | 340:28d1f895c6fe | 483 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
mbed_official | 340:28d1f895c6fe | 484 | { |
mbed_official | 340:28d1f895c6fe | 485 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); |
mbed_official | 340:28d1f895c6fe | 486 | } |
mbed_official | 340:28d1f895c6fe | 487 | else |
mbed_official | 340:28d1f895c6fe | 488 | { |
mbed_official | 340:28d1f895c6fe | 489 | /* If transfer direction not change, do not generate Restart Condition */ |
mbed_official | 340:28d1f895c6fe | 490 | /* Mean Previous state is same as current state */ |
mbed_official | 340:28d1f895c6fe | 491 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 492 | { |
mbed_official | 340:28d1f895c6fe | 493 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 494 | } |
mbed_official | 340:28d1f895c6fe | 495 | /* Else transfer direction change, so generate Restart with new transfer direction */ |
mbed_official | 340:28d1f895c6fe | 496 | else |
mbed_official | 340:28d1f895c6fe | 497 | { |
mbed_official | 340:28d1f895c6fe | 498 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); |
mbed_official | 340:28d1f895c6fe | 499 | } |
mbed_official | 340:28d1f895c6fe | 500 | |
mbed_official | 340:28d1f895c6fe | 501 | /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ |
mbed_official | 340:28d1f895c6fe | 502 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
mbed_official | 340:28d1f895c6fe | 503 | if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
mbed_official | 340:28d1f895c6fe | 504 | { |
mbed_official | 340:28d1f895c6fe | 505 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 506 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 507 | } |
mbed_official | 340:28d1f895c6fe | 508 | } |
mbed_official | 340:28d1f895c6fe | 509 | |
mbed_official | 340:28d1f895c6fe | 510 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 511 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 512 | |
mbed_official | 340:28d1f895c6fe | 513 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
mbed_official | 340:28d1f895c6fe | 514 | to avoid the risk of SMBUS interrupt handle execution before current |
mbed_official | 340:28d1f895c6fe | 515 | process unlock */ |
mbed_official | 340:28d1f895c6fe | 516 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 517 | |
mbed_official | 340:28d1f895c6fe | 518 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 519 | } |
mbed_official | 340:28d1f895c6fe | 520 | else |
mbed_official | 340:28d1f895c6fe | 521 | { |
mbed_official | 340:28d1f895c6fe | 522 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 523 | } |
mbed_official | 340:28d1f895c6fe | 524 | } |
mbed_official | 340:28d1f895c6fe | 525 | |
mbed_official | 340:28d1f895c6fe | 526 | /** |
mbed_official | 340:28d1f895c6fe | 527 | * @brief Receive in master/host SMBUS mode an amount of data in no-blocking mode with Interrupt |
mbed_official | 340:28d1f895c6fe | 528 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 529 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 530 | * @param DevAddress: Target device address |
mbed_official | 340:28d1f895c6fe | 531 | * @param pData: Pointer to data buffer |
mbed_official | 340:28d1f895c6fe | 532 | * @param Size: Amount of data to be sent |
mbed_official | 340:28d1f895c6fe | 533 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
mbed_official | 340:28d1f895c6fe | 534 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 535 | */ |
mbed_official | 340:28d1f895c6fe | 536 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
mbed_official | 340:28d1f895c6fe | 537 | { |
mbed_official | 340:28d1f895c6fe | 538 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 539 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
mbed_official | 340:28d1f895c6fe | 540 | |
mbed_official | 340:28d1f895c6fe | 541 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
mbed_official | 340:28d1f895c6fe | 542 | { |
mbed_official | 340:28d1f895c6fe | 543 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 544 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 545 | |
mbed_official | 340:28d1f895c6fe | 546 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; |
mbed_official | 340:28d1f895c6fe | 547 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 548 | |
mbed_official | 340:28d1f895c6fe | 549 | /* Prepare transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 550 | hsmbus->pBuffPtr = pData; |
mbed_official | 340:28d1f895c6fe | 551 | hsmbus->XferCount = Size; |
mbed_official | 340:28d1f895c6fe | 552 | hsmbus->XferOptions = XferOptions; |
mbed_official | 340:28d1f895c6fe | 553 | |
mbed_official | 340:28d1f895c6fe | 554 | /* In case of Quick command, remove autoend mode */ |
mbed_official | 340:28d1f895c6fe | 555 | /* Manage the stop generation by software */ |
mbed_official | 340:28d1f895c6fe | 556 | if(hsmbus->pBuffPtr == HAL_NULL) |
mbed_official | 340:28d1f895c6fe | 557 | { |
mbed_official | 340:28d1f895c6fe | 558 | hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; |
mbed_official | 340:28d1f895c6fe | 559 | } |
mbed_official | 340:28d1f895c6fe | 560 | |
mbed_official | 340:28d1f895c6fe | 561 | if(Size > MAX_NBYTE_SIZE) |
mbed_official | 340:28d1f895c6fe | 562 | { |
mbed_official | 340:28d1f895c6fe | 563 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
mbed_official | 340:28d1f895c6fe | 564 | } |
mbed_official | 340:28d1f895c6fe | 565 | else |
mbed_official | 340:28d1f895c6fe | 566 | { |
mbed_official | 340:28d1f895c6fe | 567 | hsmbus->XferSize = Size; |
mbed_official | 340:28d1f895c6fe | 568 | } |
mbed_official | 340:28d1f895c6fe | 569 | |
mbed_official | 340:28d1f895c6fe | 570 | /* Send Slave Address */ |
mbed_official | 340:28d1f895c6fe | 571 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
mbed_official | 340:28d1f895c6fe | 572 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
mbed_official | 340:28d1f895c6fe | 573 | { |
mbed_official | 340:28d1f895c6fe | 574 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); |
mbed_official | 340:28d1f895c6fe | 575 | } |
mbed_official | 340:28d1f895c6fe | 576 | else |
mbed_official | 340:28d1f895c6fe | 577 | { |
mbed_official | 340:28d1f895c6fe | 578 | /* If transfer direction not change, do not generate Restart Condition */ |
mbed_official | 340:28d1f895c6fe | 579 | /* Mean Previous state is same as current state */ |
mbed_official | 340:28d1f895c6fe | 580 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 581 | { |
mbed_official | 340:28d1f895c6fe | 582 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 583 | } |
mbed_official | 340:28d1f895c6fe | 584 | /* Else transfer direction change, so generate Restart with new transfer direction */ |
mbed_official | 340:28d1f895c6fe | 585 | else |
mbed_official | 340:28d1f895c6fe | 586 | { |
mbed_official | 340:28d1f895c6fe | 587 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); |
mbed_official | 340:28d1f895c6fe | 588 | } |
mbed_official | 340:28d1f895c6fe | 589 | } |
mbed_official | 340:28d1f895c6fe | 590 | |
mbed_official | 340:28d1f895c6fe | 591 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 592 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 593 | |
mbed_official | 340:28d1f895c6fe | 594 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
mbed_official | 340:28d1f895c6fe | 595 | to avoid the risk of SMBUS interrupt handle execution before current |
mbed_official | 340:28d1f895c6fe | 596 | process unlock */ |
mbed_official | 340:28d1f895c6fe | 597 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 598 | |
mbed_official | 340:28d1f895c6fe | 599 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 600 | } |
mbed_official | 340:28d1f895c6fe | 601 | else |
mbed_official | 340:28d1f895c6fe | 602 | { |
mbed_official | 340:28d1f895c6fe | 603 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 604 | } |
mbed_official | 340:28d1f895c6fe | 605 | } |
mbed_official | 340:28d1f895c6fe | 606 | |
mbed_official | 340:28d1f895c6fe | 607 | /** |
mbed_official | 340:28d1f895c6fe | 608 | * @brief Abort a master/host SMBUS process commnunication with Interrupt |
mbed_official | 340:28d1f895c6fe | 609 | * @note : This abort can be called only if state is ready |
mbed_official | 340:28d1f895c6fe | 610 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 611 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 612 | * @param DevAddress: Target device address |
mbed_official | 340:28d1f895c6fe | 613 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 614 | */ |
mbed_official | 340:28d1f895c6fe | 615 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) |
mbed_official | 340:28d1f895c6fe | 616 | { |
mbed_official | 340:28d1f895c6fe | 617 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
mbed_official | 340:28d1f895c6fe | 618 | { |
mbed_official | 340:28d1f895c6fe | 619 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 620 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 621 | |
mbed_official | 340:28d1f895c6fe | 622 | /* Keep the same state as previous */ |
mbed_official | 340:28d1f895c6fe | 623 | /* to perform as well the call of the corresponding end of transfer callback */ |
mbed_official | 340:28d1f895c6fe | 624 | if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 625 | { |
mbed_official | 340:28d1f895c6fe | 626 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; |
mbed_official | 340:28d1f895c6fe | 627 | } |
mbed_official | 340:28d1f895c6fe | 628 | else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 629 | { |
mbed_official | 340:28d1f895c6fe | 630 | hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; |
mbed_official | 340:28d1f895c6fe | 631 | } |
mbed_official | 340:28d1f895c6fe | 632 | else |
mbed_official | 340:28d1f895c6fe | 633 | { |
mbed_official | 340:28d1f895c6fe | 634 | /* Wrong usage of abort function */ |
mbed_official | 340:28d1f895c6fe | 635 | /* This function should be used only in case of abort monitored by master device */ |
mbed_official | 340:28d1f895c6fe | 636 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 637 | } |
mbed_official | 340:28d1f895c6fe | 638 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 639 | |
mbed_official | 340:28d1f895c6fe | 640 | /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ |
mbed_official | 340:28d1f895c6fe | 641 | /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ |
mbed_official | 340:28d1f895c6fe | 642 | SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 643 | |
mbed_official | 340:28d1f895c6fe | 644 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 645 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 646 | |
mbed_official | 340:28d1f895c6fe | 647 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
mbed_official | 340:28d1f895c6fe | 648 | to avoid the risk of SMBUS interrupt handle execution before current |
mbed_official | 340:28d1f895c6fe | 649 | process unlock */ |
mbed_official | 340:28d1f895c6fe | 650 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 651 | { |
mbed_official | 340:28d1f895c6fe | 652 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 653 | } |
mbed_official | 340:28d1f895c6fe | 654 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 655 | { |
mbed_official | 340:28d1f895c6fe | 656 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 657 | } |
mbed_official | 340:28d1f895c6fe | 658 | |
mbed_official | 340:28d1f895c6fe | 659 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 660 | } |
mbed_official | 340:28d1f895c6fe | 661 | else |
mbed_official | 340:28d1f895c6fe | 662 | { |
mbed_official | 340:28d1f895c6fe | 663 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 664 | } |
mbed_official | 340:28d1f895c6fe | 665 | } |
mbed_official | 340:28d1f895c6fe | 666 | |
mbed_official | 340:28d1f895c6fe | 667 | /** |
mbed_official | 340:28d1f895c6fe | 668 | * @brief Transmit in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt |
mbed_official | 340:28d1f895c6fe | 669 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 670 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 671 | * @param pData: Pointer to data buffer |
mbed_official | 340:28d1f895c6fe | 672 | * @param Size: Amount of data to be sent |
mbed_official | 340:28d1f895c6fe | 673 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
mbed_official | 340:28d1f895c6fe | 674 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 675 | */ |
mbed_official | 340:28d1f895c6fe | 676 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
mbed_official | 340:28d1f895c6fe | 677 | { |
mbed_official | 340:28d1f895c6fe | 678 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 679 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
mbed_official | 340:28d1f895c6fe | 680 | |
mbed_official | 340:28d1f895c6fe | 681 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 682 | { |
mbed_official | 340:28d1f895c6fe | 683 | if((pData == HAL_NULL) || (Size == 0)) |
mbed_official | 340:28d1f895c6fe | 684 | { |
mbed_official | 340:28d1f895c6fe | 685 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 686 | } |
mbed_official | 340:28d1f895c6fe | 687 | |
mbed_official | 340:28d1f895c6fe | 688 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
mbed_official | 340:28d1f895c6fe | 689 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 690 | |
mbed_official | 340:28d1f895c6fe | 691 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 692 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 693 | |
mbed_official | 340:28d1f895c6fe | 694 | hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX; |
mbed_official | 340:28d1f895c6fe | 695 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 696 | |
mbed_official | 340:28d1f895c6fe | 697 | /* Set SBC bit to manage Acknowledge at each bit */ |
mbed_official | 340:28d1f895c6fe | 698 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
mbed_official | 340:28d1f895c6fe | 699 | |
mbed_official | 340:28d1f895c6fe | 700 | /* Enable Address Acknowledge */ |
mbed_official | 340:28d1f895c6fe | 701 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
mbed_official | 340:28d1f895c6fe | 702 | |
mbed_official | 340:28d1f895c6fe | 703 | /* Prepare transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 704 | hsmbus->pBuffPtr = pData; |
mbed_official | 340:28d1f895c6fe | 705 | hsmbus->XferSize = Size; |
mbed_official | 340:28d1f895c6fe | 706 | hsmbus->XferCount = Size; |
mbed_official | 340:28d1f895c6fe | 707 | hsmbus->XferOptions = XferOptions; |
mbed_official | 340:28d1f895c6fe | 708 | |
mbed_official | 340:28d1f895c6fe | 709 | if(Size > MAX_NBYTE_SIZE) |
mbed_official | 340:28d1f895c6fe | 710 | { |
mbed_official | 340:28d1f895c6fe | 711 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
mbed_official | 340:28d1f895c6fe | 712 | } |
mbed_official | 340:28d1f895c6fe | 713 | else |
mbed_official | 340:28d1f895c6fe | 714 | { |
mbed_official | 340:28d1f895c6fe | 715 | hsmbus->XferSize = Size; |
mbed_official | 340:28d1f895c6fe | 716 | } |
mbed_official | 340:28d1f895c6fe | 717 | |
mbed_official | 340:28d1f895c6fe | 718 | /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ |
mbed_official | 340:28d1f895c6fe | 719 | if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) ) |
mbed_official | 340:28d1f895c6fe | 720 | { |
mbed_official | 340:28d1f895c6fe | 721 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 722 | } |
mbed_official | 340:28d1f895c6fe | 723 | else |
mbed_official | 340:28d1f895c6fe | 724 | { |
mbed_official | 340:28d1f895c6fe | 725 | /* Set NBYTE to transmit */ |
mbed_official | 340:28d1f895c6fe | 726 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 727 | |
mbed_official | 340:28d1f895c6fe | 728 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
mbed_official | 340:28d1f895c6fe | 729 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
mbed_official | 340:28d1f895c6fe | 730 | if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
mbed_official | 340:28d1f895c6fe | 731 | { |
mbed_official | 340:28d1f895c6fe | 732 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 733 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 734 | } |
mbed_official | 340:28d1f895c6fe | 735 | } |
mbed_official | 340:28d1f895c6fe | 736 | |
mbed_official | 340:28d1f895c6fe | 737 | /* Clear ADDR flag after prepare the transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 738 | /* This action will generate an acknowledge to the HOST */ |
mbed_official | 340:28d1f895c6fe | 739 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
mbed_official | 340:28d1f895c6fe | 740 | |
mbed_official | 340:28d1f895c6fe | 741 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 742 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 743 | |
mbed_official | 340:28d1f895c6fe | 744 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
mbed_official | 340:28d1f895c6fe | 745 | to avoid the risk of SMBUS interrupt handle execution before current |
mbed_official | 340:28d1f895c6fe | 746 | process unlock */ |
mbed_official | 340:28d1f895c6fe | 747 | /* REnable ADDR interrupt */ |
mbed_official | 340:28d1f895c6fe | 748 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); |
mbed_official | 340:28d1f895c6fe | 749 | |
mbed_official | 340:28d1f895c6fe | 750 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 751 | } |
mbed_official | 340:28d1f895c6fe | 752 | else |
mbed_official | 340:28d1f895c6fe | 753 | { |
mbed_official | 340:28d1f895c6fe | 754 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 755 | } |
mbed_official | 340:28d1f895c6fe | 756 | } |
mbed_official | 340:28d1f895c6fe | 757 | |
mbed_official | 340:28d1f895c6fe | 758 | /** |
mbed_official | 340:28d1f895c6fe | 759 | * @brief Receive in slave/device SMBUS mode an amount of data in no-blocking mode with Interrupt |
mbed_official | 340:28d1f895c6fe | 760 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 761 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 762 | * @param pData: Pointer to data buffer |
mbed_official | 340:28d1f895c6fe | 763 | * @param Size: Amount of data to be sent |
mbed_official | 340:28d1f895c6fe | 764 | * @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition |
mbed_official | 340:28d1f895c6fe | 765 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 766 | */ |
mbed_official | 340:28d1f895c6fe | 767 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
mbed_official | 340:28d1f895c6fe | 768 | { |
mbed_official | 340:28d1f895c6fe | 769 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 770 | assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
mbed_official | 340:28d1f895c6fe | 771 | |
mbed_official | 340:28d1f895c6fe | 772 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 773 | { |
mbed_official | 340:28d1f895c6fe | 774 | if((pData == HAL_NULL) || (Size == 0)) |
mbed_official | 340:28d1f895c6fe | 775 | { |
mbed_official | 340:28d1f895c6fe | 776 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 777 | } |
mbed_official | 340:28d1f895c6fe | 778 | |
mbed_official | 340:28d1f895c6fe | 779 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
mbed_official | 340:28d1f895c6fe | 780 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 781 | |
mbed_official | 340:28d1f895c6fe | 782 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 783 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 784 | |
mbed_official | 340:28d1f895c6fe | 785 | hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX; |
mbed_official | 340:28d1f895c6fe | 786 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 787 | |
mbed_official | 340:28d1f895c6fe | 788 | /* Set SBC bit to manage Acknowledge at each bit */ |
mbed_official | 340:28d1f895c6fe | 789 | hsmbus->Instance->CR1 |= I2C_CR1_SBC; |
mbed_official | 340:28d1f895c6fe | 790 | |
mbed_official | 340:28d1f895c6fe | 791 | /* Enable Address Acknowledge */ |
mbed_official | 340:28d1f895c6fe | 792 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
mbed_official | 340:28d1f895c6fe | 793 | |
mbed_official | 340:28d1f895c6fe | 794 | /* Prepare transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 795 | hsmbus->pBuffPtr = pData; |
mbed_official | 340:28d1f895c6fe | 796 | hsmbus->XferSize = Size; |
mbed_official | 340:28d1f895c6fe | 797 | hsmbus->XferCount = Size; |
mbed_official | 340:28d1f895c6fe | 798 | hsmbus->XferOptions = XferOptions; |
mbed_official | 340:28d1f895c6fe | 799 | |
mbed_official | 340:28d1f895c6fe | 800 | /* Set NBYTE to receive */ |
mbed_official | 340:28d1f895c6fe | 801 | /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ |
mbed_official | 340:28d1f895c6fe | 802 | /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ |
mbed_official | 340:28d1f895c6fe | 803 | /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ |
mbed_official | 340:28d1f895c6fe | 804 | /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ |
mbed_official | 340:28d1f895c6fe | 805 | if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET))) |
mbed_official | 340:28d1f895c6fe | 806 | { |
mbed_official | 340:28d1f895c6fe | 807 | SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 808 | } |
mbed_official | 340:28d1f895c6fe | 809 | else |
mbed_official | 340:28d1f895c6fe | 810 | { |
mbed_official | 340:28d1f895c6fe | 811 | SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 812 | } |
mbed_official | 340:28d1f895c6fe | 813 | |
mbed_official | 340:28d1f895c6fe | 814 | /* Clear ADDR flag after prepare the transfer parameters */ |
mbed_official | 340:28d1f895c6fe | 815 | /* This action will generate an acknowledge to the HOST */ |
mbed_official | 340:28d1f895c6fe | 816 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
mbed_official | 340:28d1f895c6fe | 817 | |
mbed_official | 340:28d1f895c6fe | 818 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 819 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 820 | |
mbed_official | 340:28d1f895c6fe | 821 | /* Note : The SMBUS interrupts must be enabled after unlocking current process |
mbed_official | 340:28d1f895c6fe | 822 | to avoid the risk of SMBUS interrupt handle execution before current |
mbed_official | 340:28d1f895c6fe | 823 | process unlock */ |
mbed_official | 340:28d1f895c6fe | 824 | /* REnable ADDR interrupt */ |
mbed_official | 340:28d1f895c6fe | 825 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); |
mbed_official | 340:28d1f895c6fe | 826 | |
mbed_official | 340:28d1f895c6fe | 827 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 828 | } |
mbed_official | 340:28d1f895c6fe | 829 | else |
mbed_official | 340:28d1f895c6fe | 830 | { |
mbed_official | 340:28d1f895c6fe | 831 | return HAL_ERROR; |
mbed_official | 340:28d1f895c6fe | 832 | } |
mbed_official | 340:28d1f895c6fe | 833 | } |
mbed_official | 340:28d1f895c6fe | 834 | |
mbed_official | 340:28d1f895c6fe | 835 | /** |
mbed_official | 340:28d1f895c6fe | 836 | * @brief This function enable the Address listen mode |
mbed_official | 340:28d1f895c6fe | 837 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 838 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 839 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 840 | */ |
mbed_official | 340:28d1f895c6fe | 841 | HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 842 | { |
mbed_official | 340:28d1f895c6fe | 843 | hsmbus->State = HAL_SMBUS_STATE_LISTEN; |
mbed_official | 340:28d1f895c6fe | 844 | |
mbed_official | 340:28d1f895c6fe | 845 | /* Enable the Address Match interrupt */ |
mbed_official | 340:28d1f895c6fe | 846 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); |
mbed_official | 340:28d1f895c6fe | 847 | |
mbed_official | 340:28d1f895c6fe | 848 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 849 | } |
mbed_official | 340:28d1f895c6fe | 850 | |
mbed_official | 340:28d1f895c6fe | 851 | /** |
mbed_official | 340:28d1f895c6fe | 852 | * @brief This function disable the Address listen mode |
mbed_official | 340:28d1f895c6fe | 853 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 854 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 855 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 856 | */ |
mbed_official | 340:28d1f895c6fe | 857 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 858 | { |
mbed_official | 340:28d1f895c6fe | 859 | /* Disable Address listen mode only if a transfer is not ongoing */ |
mbed_official | 340:28d1f895c6fe | 860 | if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 861 | { |
mbed_official | 340:28d1f895c6fe | 862 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 863 | |
mbed_official | 340:28d1f895c6fe | 864 | /* Disable the Address Match interrupt */ |
mbed_official | 340:28d1f895c6fe | 865 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); |
mbed_official | 340:28d1f895c6fe | 866 | |
mbed_official | 340:28d1f895c6fe | 867 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 868 | } |
mbed_official | 340:28d1f895c6fe | 869 | else |
mbed_official | 340:28d1f895c6fe | 870 | { |
mbed_official | 340:28d1f895c6fe | 871 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 872 | } |
mbed_official | 340:28d1f895c6fe | 873 | } |
mbed_official | 340:28d1f895c6fe | 874 | |
mbed_official | 340:28d1f895c6fe | 875 | /** |
mbed_official | 340:28d1f895c6fe | 876 | * @brief This function enable the SMBUS alert mode. |
mbed_official | 340:28d1f895c6fe | 877 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 878 | * the configuration information for the specified SMBUSx peripheral. |
mbed_official | 340:28d1f895c6fe | 879 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 880 | */ |
mbed_official | 340:28d1f895c6fe | 881 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 882 | { |
mbed_official | 340:28d1f895c6fe | 883 | /* Enable SMBus alert */ |
mbed_official | 340:28d1f895c6fe | 884 | hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; |
mbed_official | 340:28d1f895c6fe | 885 | |
mbed_official | 340:28d1f895c6fe | 886 | /* Clear ALERT flag */ |
mbed_official | 340:28d1f895c6fe | 887 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); |
mbed_official | 340:28d1f895c6fe | 888 | |
mbed_official | 340:28d1f895c6fe | 889 | /* Enable Alert Interrupt */ |
mbed_official | 340:28d1f895c6fe | 890 | SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); |
mbed_official | 340:28d1f895c6fe | 891 | |
mbed_official | 340:28d1f895c6fe | 892 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 893 | } |
mbed_official | 340:28d1f895c6fe | 894 | /** |
mbed_official | 340:28d1f895c6fe | 895 | * @brief This function disable the SMBUS alert mode. |
mbed_official | 340:28d1f895c6fe | 896 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 897 | * the configuration information for the specified SMBUSx peripheral. |
mbed_official | 340:28d1f895c6fe | 898 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 899 | */ |
mbed_official | 340:28d1f895c6fe | 900 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 901 | { |
mbed_official | 340:28d1f895c6fe | 902 | /* Enable SMBus alert */ |
mbed_official | 340:28d1f895c6fe | 903 | hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; |
mbed_official | 340:28d1f895c6fe | 904 | |
mbed_official | 340:28d1f895c6fe | 905 | /* Disable Alert Interrupt */ |
mbed_official | 340:28d1f895c6fe | 906 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); |
mbed_official | 340:28d1f895c6fe | 907 | |
mbed_official | 340:28d1f895c6fe | 908 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 909 | } |
mbed_official | 340:28d1f895c6fe | 910 | |
mbed_official | 340:28d1f895c6fe | 911 | /** |
mbed_official | 340:28d1f895c6fe | 912 | * @brief Checks if target device is ready for communication. |
mbed_official | 340:28d1f895c6fe | 913 | * @note This function is used with Memory devices |
mbed_official | 340:28d1f895c6fe | 914 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 915 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 916 | * @param DevAddress: Target device address |
mbed_official | 340:28d1f895c6fe | 917 | * @param Trials: Number of trials |
mbed_official | 340:28d1f895c6fe | 918 | * @param Timeout: Timeout duration |
mbed_official | 340:28d1f895c6fe | 919 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 920 | */ |
mbed_official | 340:28d1f895c6fe | 921 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
mbed_official | 340:28d1f895c6fe | 922 | { |
mbed_official | 340:28d1f895c6fe | 923 | uint32_t tickstart = 0; |
mbed_official | 340:28d1f895c6fe | 924 | |
mbed_official | 340:28d1f895c6fe | 925 | __IO uint32_t SMBUS_Trials = 0; |
mbed_official | 340:28d1f895c6fe | 926 | |
mbed_official | 340:28d1f895c6fe | 927 | if(hsmbus->State == HAL_SMBUS_STATE_READY) |
mbed_official | 340:28d1f895c6fe | 928 | { |
mbed_official | 340:28d1f895c6fe | 929 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) |
mbed_official | 340:28d1f895c6fe | 930 | { |
mbed_official | 340:28d1f895c6fe | 931 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 932 | } |
mbed_official | 340:28d1f895c6fe | 933 | |
mbed_official | 340:28d1f895c6fe | 934 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 935 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 936 | |
mbed_official | 340:28d1f895c6fe | 937 | hsmbus->State = HAL_SMBUS_STATE_BUSY; |
mbed_official | 340:28d1f895c6fe | 938 | hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; |
mbed_official | 340:28d1f895c6fe | 939 | |
mbed_official | 340:28d1f895c6fe | 940 | do |
mbed_official | 340:28d1f895c6fe | 941 | { |
mbed_official | 340:28d1f895c6fe | 942 | /* Generate Start */ |
mbed_official | 340:28d1f895c6fe | 943 | hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); |
mbed_official | 340:28d1f895c6fe | 944 | |
mbed_official | 340:28d1f895c6fe | 945 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
mbed_official | 340:28d1f895c6fe | 946 | /* Wait until STOPF flag is set or a NACK flag is set*/ |
mbed_official | 340:28d1f895c6fe | 947 | tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 948 | while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT)) |
mbed_official | 340:28d1f895c6fe | 949 | { |
mbed_official | 340:28d1f895c6fe | 950 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 340:28d1f895c6fe | 951 | { |
mbed_official | 340:28d1f895c6fe | 952 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
mbed_official | 340:28d1f895c6fe | 953 | { |
mbed_official | 340:28d1f895c6fe | 954 | /* Device is ready */ |
mbed_official | 340:28d1f895c6fe | 955 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 956 | |
mbed_official | 340:28d1f895c6fe | 957 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 958 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 959 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 960 | } |
mbed_official | 340:28d1f895c6fe | 961 | } |
mbed_official | 340:28d1f895c6fe | 962 | } |
mbed_official | 340:28d1f895c6fe | 963 | |
mbed_official | 340:28d1f895c6fe | 964 | /* Check if the NACKF flag has not been set */ |
mbed_official | 340:28d1f895c6fe | 965 | if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) |
mbed_official | 340:28d1f895c6fe | 966 | { |
mbed_official | 340:28d1f895c6fe | 967 | /* Wait until STOPF flag is reset */ |
mbed_official | 340:28d1f895c6fe | 968 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
mbed_official | 340:28d1f895c6fe | 969 | { |
mbed_official | 340:28d1f895c6fe | 970 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 971 | } |
mbed_official | 340:28d1f895c6fe | 972 | |
mbed_official | 340:28d1f895c6fe | 973 | /* Clear STOP Flag */ |
mbed_official | 340:28d1f895c6fe | 974 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 975 | |
mbed_official | 340:28d1f895c6fe | 976 | /* Device is ready */ |
mbed_official | 340:28d1f895c6fe | 977 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 978 | |
mbed_official | 340:28d1f895c6fe | 979 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 980 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 981 | |
mbed_official | 340:28d1f895c6fe | 982 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 983 | } |
mbed_official | 340:28d1f895c6fe | 984 | else |
mbed_official | 340:28d1f895c6fe | 985 | { |
mbed_official | 340:28d1f895c6fe | 986 | /* Wait until STOPF flag is reset */ |
mbed_official | 340:28d1f895c6fe | 987 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
mbed_official | 340:28d1f895c6fe | 988 | { |
mbed_official | 340:28d1f895c6fe | 989 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 990 | } |
mbed_official | 340:28d1f895c6fe | 991 | |
mbed_official | 340:28d1f895c6fe | 992 | /* Clear NACK Flag */ |
mbed_official | 340:28d1f895c6fe | 993 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
mbed_official | 340:28d1f895c6fe | 994 | |
mbed_official | 340:28d1f895c6fe | 995 | /* Clear STOP Flag, auto generated with autoend*/ |
mbed_official | 340:28d1f895c6fe | 996 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 997 | } |
mbed_official | 340:28d1f895c6fe | 998 | |
mbed_official | 340:28d1f895c6fe | 999 | /* Check if the maximum allowed number of trials has been reached */ |
mbed_official | 340:28d1f895c6fe | 1000 | if (SMBUS_Trials++ == Trials) |
mbed_official | 340:28d1f895c6fe | 1001 | { |
mbed_official | 340:28d1f895c6fe | 1002 | /* Generate Stop */ |
mbed_official | 340:28d1f895c6fe | 1003 | hsmbus->Instance->CR2 |= I2C_CR2_STOP; |
mbed_official | 340:28d1f895c6fe | 1004 | |
mbed_official | 340:28d1f895c6fe | 1005 | /* Wait until STOPF flag is reset */ |
mbed_official | 340:28d1f895c6fe | 1006 | if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) |
mbed_official | 340:28d1f895c6fe | 1007 | { |
mbed_official | 340:28d1f895c6fe | 1008 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1009 | } |
mbed_official | 340:28d1f895c6fe | 1010 | |
mbed_official | 340:28d1f895c6fe | 1011 | /* Clear STOP Flag */ |
mbed_official | 340:28d1f895c6fe | 1012 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 1013 | } |
mbed_official | 340:28d1f895c6fe | 1014 | }while(SMBUS_Trials < Trials); |
mbed_official | 340:28d1f895c6fe | 1015 | |
mbed_official | 340:28d1f895c6fe | 1016 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1017 | |
mbed_official | 340:28d1f895c6fe | 1018 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1019 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1020 | |
mbed_official | 340:28d1f895c6fe | 1021 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1022 | } |
mbed_official | 340:28d1f895c6fe | 1023 | else |
mbed_official | 340:28d1f895c6fe | 1024 | { |
mbed_official | 340:28d1f895c6fe | 1025 | return HAL_BUSY; |
mbed_official | 340:28d1f895c6fe | 1026 | } |
mbed_official | 340:28d1f895c6fe | 1027 | } |
mbed_official | 340:28d1f895c6fe | 1028 | |
mbed_official | 340:28d1f895c6fe | 1029 | /** |
mbed_official | 340:28d1f895c6fe | 1030 | * @brief This function handles SMBUS event interrupt request. |
mbed_official | 340:28d1f895c6fe | 1031 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1032 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1033 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1034 | */ |
mbed_official | 340:28d1f895c6fe | 1035 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1036 | { |
mbed_official | 340:28d1f895c6fe | 1037 | uint32_t tmpisrvalue = 0; |
mbed_official | 340:28d1f895c6fe | 1038 | |
mbed_official | 340:28d1f895c6fe | 1039 | /* Use a local variable to store the current ISR flags */ |
mbed_official | 340:28d1f895c6fe | 1040 | /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ |
mbed_official | 340:28d1f895c6fe | 1041 | tmpisrvalue = __SMBUS_GET_ISR_REG(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1042 | |
mbed_official | 340:28d1f895c6fe | 1043 | /* SMBUS in mode Transmitter ---------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1044 | if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1045 | { |
mbed_official | 340:28d1f895c6fe | 1046 | /* Slave mode selected */ |
mbed_official | 340:28d1f895c6fe | 1047 | if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1048 | { |
mbed_official | 340:28d1f895c6fe | 1049 | SMBUS_Slave_ISR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1050 | } |
mbed_official | 340:28d1f895c6fe | 1051 | /* Master mode selected */ |
mbed_official | 340:28d1f895c6fe | 1052 | else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1053 | { |
mbed_official | 340:28d1f895c6fe | 1054 | SMBUS_Master_ISR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1055 | } |
mbed_official | 340:28d1f895c6fe | 1056 | } |
mbed_official | 340:28d1f895c6fe | 1057 | |
mbed_official | 340:28d1f895c6fe | 1058 | /* SMBUS in mode Receiver ----------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1059 | if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1060 | { |
mbed_official | 340:28d1f895c6fe | 1061 | /* Slave mode selected */ |
mbed_official | 340:28d1f895c6fe | 1062 | if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1063 | { |
mbed_official | 340:28d1f895c6fe | 1064 | SMBUS_Slave_ISR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1065 | } |
mbed_official | 340:28d1f895c6fe | 1066 | /* Master mode selected */ |
mbed_official | 340:28d1f895c6fe | 1067 | else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1068 | { |
mbed_official | 340:28d1f895c6fe | 1069 | SMBUS_Master_ISR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1070 | } |
mbed_official | 340:28d1f895c6fe | 1071 | } |
mbed_official | 340:28d1f895c6fe | 1072 | |
mbed_official | 340:28d1f895c6fe | 1073 | /* SMBUS in mode Listener Only --------------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1074 | if (((__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (__SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1075 | && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET))) |
mbed_official | 340:28d1f895c6fe | 1076 | { |
mbed_official | 340:28d1f895c6fe | 1077 | if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 1078 | { |
mbed_official | 340:28d1f895c6fe | 1079 | SMBUS_Slave_ISR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1080 | } |
mbed_official | 340:28d1f895c6fe | 1081 | } |
mbed_official | 340:28d1f895c6fe | 1082 | } |
mbed_official | 340:28d1f895c6fe | 1083 | |
mbed_official | 340:28d1f895c6fe | 1084 | /** |
mbed_official | 340:28d1f895c6fe | 1085 | * @brief This function handles SMBUS error interrupt request. |
mbed_official | 340:28d1f895c6fe | 1086 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1087 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1088 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1089 | */ |
mbed_official | 340:28d1f895c6fe | 1090 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1091 | { |
mbed_official | 340:28d1f895c6fe | 1092 | /* SMBUS Bus error interrupt occurred ------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1093 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1094 | { |
mbed_official | 340:28d1f895c6fe | 1095 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; |
mbed_official | 340:28d1f895c6fe | 1096 | |
mbed_official | 340:28d1f895c6fe | 1097 | /* Clear BERR flag */ |
mbed_official | 340:28d1f895c6fe | 1098 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); |
mbed_official | 340:28d1f895c6fe | 1099 | } |
mbed_official | 340:28d1f895c6fe | 1100 | |
mbed_official | 340:28d1f895c6fe | 1101 | /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1102 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1103 | { |
mbed_official | 340:28d1f895c6fe | 1104 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; |
mbed_official | 340:28d1f895c6fe | 1105 | |
mbed_official | 340:28d1f895c6fe | 1106 | /* Clear OVR flag */ |
mbed_official | 340:28d1f895c6fe | 1107 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); |
mbed_official | 340:28d1f895c6fe | 1108 | } |
mbed_official | 340:28d1f895c6fe | 1109 | |
mbed_official | 340:28d1f895c6fe | 1110 | /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1111 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1112 | { |
mbed_official | 340:28d1f895c6fe | 1113 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; |
mbed_official | 340:28d1f895c6fe | 1114 | |
mbed_official | 340:28d1f895c6fe | 1115 | /* Clear ARLO flag */ |
mbed_official | 340:28d1f895c6fe | 1116 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); |
mbed_official | 340:28d1f895c6fe | 1117 | } |
mbed_official | 340:28d1f895c6fe | 1118 | |
mbed_official | 340:28d1f895c6fe | 1119 | /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1120 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1121 | { |
mbed_official | 340:28d1f895c6fe | 1122 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1123 | |
mbed_official | 340:28d1f895c6fe | 1124 | /* Clear TIMEOUT flag */ |
mbed_official | 340:28d1f895c6fe | 1125 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); |
mbed_official | 340:28d1f895c6fe | 1126 | } |
mbed_official | 340:28d1f895c6fe | 1127 | |
mbed_official | 340:28d1f895c6fe | 1128 | /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1129 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1130 | { |
mbed_official | 340:28d1f895c6fe | 1131 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; |
mbed_official | 340:28d1f895c6fe | 1132 | |
mbed_official | 340:28d1f895c6fe | 1133 | /* Clear ALERT flag */ |
mbed_official | 340:28d1f895c6fe | 1134 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); |
mbed_official | 340:28d1f895c6fe | 1135 | } |
mbed_official | 340:28d1f895c6fe | 1136 | |
mbed_official | 340:28d1f895c6fe | 1137 | /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ |
mbed_official | 340:28d1f895c6fe | 1138 | if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1139 | { |
mbed_official | 340:28d1f895c6fe | 1140 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; |
mbed_official | 340:28d1f895c6fe | 1141 | |
mbed_official | 340:28d1f895c6fe | 1142 | /* Clear PEC error flag */ |
mbed_official | 340:28d1f895c6fe | 1143 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); |
mbed_official | 340:28d1f895c6fe | 1144 | } |
mbed_official | 340:28d1f895c6fe | 1145 | |
mbed_official | 340:28d1f895c6fe | 1146 | /* Call the Error Callback in case of Error detected */ |
mbed_official | 340:28d1f895c6fe | 1147 | if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF)) |
mbed_official | 340:28d1f895c6fe | 1148 | { |
mbed_official | 340:28d1f895c6fe | 1149 | /* Do not Reset the the HAL state in case of ALERT error */ |
mbed_official | 340:28d1f895c6fe | 1150 | if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) |
mbed_official | 340:28d1f895c6fe | 1151 | { |
mbed_official | 340:28d1f895c6fe | 1152 | if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1153 | || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) |
mbed_official | 340:28d1f895c6fe | 1154 | { |
mbed_official | 340:28d1f895c6fe | 1155 | /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ |
mbed_official | 340:28d1f895c6fe | 1156 | /* keep HAL_SMBUS_STATE_LISTEN if set */ |
mbed_official | 340:28d1f895c6fe | 1157 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1158 | hsmbus->State = HAL_SMBUS_STATE_LISTEN; |
mbed_official | 340:28d1f895c6fe | 1159 | } |
mbed_official | 340:28d1f895c6fe | 1160 | } |
mbed_official | 340:28d1f895c6fe | 1161 | |
mbed_official | 340:28d1f895c6fe | 1162 | /* Call the Error callback to prevent upper layer */ |
mbed_official | 340:28d1f895c6fe | 1163 | HAL_SMBUS_ErrorCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1164 | } |
mbed_official | 340:28d1f895c6fe | 1165 | } |
mbed_official | 340:28d1f895c6fe | 1166 | |
mbed_official | 340:28d1f895c6fe | 1167 | /** |
mbed_official | 340:28d1f895c6fe | 1168 | * @brief Master Tx Transfer completed callbacks. |
mbed_official | 340:28d1f895c6fe | 1169 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1170 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1171 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1172 | */ |
mbed_official | 340:28d1f895c6fe | 1173 | __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1174 | { |
mbed_official | 340:28d1f895c6fe | 1175 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1176 | the HAL_SMBUS_TxCpltCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1177 | */ |
mbed_official | 340:28d1f895c6fe | 1178 | } |
mbed_official | 340:28d1f895c6fe | 1179 | |
mbed_official | 340:28d1f895c6fe | 1180 | /** |
mbed_official | 340:28d1f895c6fe | 1181 | * @brief Master Rx Transfer completed callbacks. |
mbed_official | 340:28d1f895c6fe | 1182 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1183 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1184 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1185 | */ |
mbed_official | 340:28d1f895c6fe | 1186 | __weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1187 | { |
mbed_official | 340:28d1f895c6fe | 1188 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1189 | the HAL_SMBUS_TxCpltCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1190 | */ |
mbed_official | 340:28d1f895c6fe | 1191 | } |
mbed_official | 340:28d1f895c6fe | 1192 | |
mbed_official | 340:28d1f895c6fe | 1193 | /** @brief Slave Tx Transfer completed callbacks. |
mbed_official | 340:28d1f895c6fe | 1194 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1195 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1196 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1197 | */ |
mbed_official | 340:28d1f895c6fe | 1198 | __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1199 | { |
mbed_official | 340:28d1f895c6fe | 1200 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1201 | the HAL_SMBUS_TxCpltCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1202 | */ |
mbed_official | 340:28d1f895c6fe | 1203 | } |
mbed_official | 340:28d1f895c6fe | 1204 | |
mbed_official | 340:28d1f895c6fe | 1205 | /** |
mbed_official | 340:28d1f895c6fe | 1206 | * @brief Slave Rx Transfer completed callbacks. |
mbed_official | 340:28d1f895c6fe | 1207 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1208 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1209 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1210 | */ |
mbed_official | 340:28d1f895c6fe | 1211 | __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1212 | { |
mbed_official | 340:28d1f895c6fe | 1213 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1214 | the HAL_SMBUS_TxCpltCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1215 | */ |
mbed_official | 340:28d1f895c6fe | 1216 | } |
mbed_official | 340:28d1f895c6fe | 1217 | |
mbed_official | 340:28d1f895c6fe | 1218 | /** |
mbed_official | 340:28d1f895c6fe | 1219 | * @brief Slave Address Match callbacks. |
mbed_official | 340:28d1f895c6fe | 1220 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1221 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1222 | * @param TransferDirection: Master request Transfer Direction (Write/Read) |
mbed_official | 340:28d1f895c6fe | 1223 | * @param AddrMatchCode: Address Match Code |
mbed_official | 340:28d1f895c6fe | 1224 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1225 | */ |
mbed_official | 340:28d1f895c6fe | 1226 | __weak void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) |
mbed_official | 340:28d1f895c6fe | 1227 | { |
mbed_official | 340:28d1f895c6fe | 1228 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1229 | the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1230 | */ |
mbed_official | 340:28d1f895c6fe | 1231 | } |
mbed_official | 340:28d1f895c6fe | 1232 | |
mbed_official | 340:28d1f895c6fe | 1233 | /** |
mbed_official | 340:28d1f895c6fe | 1234 | * @brief Listen Complete callbacks. |
mbed_official | 340:28d1f895c6fe | 1235 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1236 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1237 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1238 | */ |
mbed_official | 340:28d1f895c6fe | 1239 | __weak void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1240 | { |
mbed_official | 340:28d1f895c6fe | 1241 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1242 | the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1243 | */ |
mbed_official | 340:28d1f895c6fe | 1244 | } |
mbed_official | 340:28d1f895c6fe | 1245 | |
mbed_official | 340:28d1f895c6fe | 1246 | /** |
mbed_official | 340:28d1f895c6fe | 1247 | * @brief SMBUS error callbacks. |
mbed_official | 340:28d1f895c6fe | 1248 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1249 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1250 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1251 | */ |
mbed_official | 340:28d1f895c6fe | 1252 | __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1253 | { |
mbed_official | 340:28d1f895c6fe | 1254 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 340:28d1f895c6fe | 1255 | the HAL_SMBUS_ErrorCallback could be implemented in the user file |
mbed_official | 340:28d1f895c6fe | 1256 | */ |
mbed_official | 340:28d1f895c6fe | 1257 | } |
mbed_official | 340:28d1f895c6fe | 1258 | |
mbed_official | 340:28d1f895c6fe | 1259 | /** |
mbed_official | 340:28d1f895c6fe | 1260 | * @} |
mbed_official | 340:28d1f895c6fe | 1261 | */ |
mbed_official | 340:28d1f895c6fe | 1262 | |
mbed_official | 340:28d1f895c6fe | 1263 | /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
mbed_official | 340:28d1f895c6fe | 1264 | * @brief Peripheral State and Errors functions |
mbed_official | 340:28d1f895c6fe | 1265 | * |
mbed_official | 340:28d1f895c6fe | 1266 | @verbatim |
mbed_official | 340:28d1f895c6fe | 1267 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 1268 | ##### Peripheral State and Errors functions ##### |
mbed_official | 340:28d1f895c6fe | 1269 | =============================================================================== |
mbed_official | 340:28d1f895c6fe | 1270 | [..] |
mbed_official | 340:28d1f895c6fe | 1271 | This subsection permit to get in run-time the status of the peripheral |
mbed_official | 340:28d1f895c6fe | 1272 | and the data flow. |
mbed_official | 340:28d1f895c6fe | 1273 | |
mbed_official | 340:28d1f895c6fe | 1274 | @endverbatim |
mbed_official | 340:28d1f895c6fe | 1275 | * @{ |
mbed_official | 340:28d1f895c6fe | 1276 | */ |
mbed_official | 340:28d1f895c6fe | 1277 | |
mbed_official | 340:28d1f895c6fe | 1278 | /** |
mbed_official | 340:28d1f895c6fe | 1279 | * @brief Returns the SMBUS state. |
mbed_official | 340:28d1f895c6fe | 1280 | * @param hsmbus : SMBUS handle |
mbed_official | 340:28d1f895c6fe | 1281 | * @retval HAL state |
mbed_official | 340:28d1f895c6fe | 1282 | */ |
mbed_official | 340:28d1f895c6fe | 1283 | HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1284 | { |
mbed_official | 340:28d1f895c6fe | 1285 | return hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1286 | } |
mbed_official | 340:28d1f895c6fe | 1287 | |
mbed_official | 340:28d1f895c6fe | 1288 | /** |
mbed_official | 340:28d1f895c6fe | 1289 | * @brief Return the SMBUS error code |
mbed_official | 340:28d1f895c6fe | 1290 | * @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1291 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1292 | * @retval SMBUS Error Code |
mbed_official | 340:28d1f895c6fe | 1293 | */ |
mbed_official | 340:28d1f895c6fe | 1294 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1295 | { |
mbed_official | 340:28d1f895c6fe | 1296 | return hsmbus->ErrorCode; |
mbed_official | 340:28d1f895c6fe | 1297 | } |
mbed_official | 340:28d1f895c6fe | 1298 | |
mbed_official | 340:28d1f895c6fe | 1299 | /** |
mbed_official | 340:28d1f895c6fe | 1300 | * @} |
mbed_official | 340:28d1f895c6fe | 1301 | */ |
mbed_official | 340:28d1f895c6fe | 1302 | |
mbed_official | 340:28d1f895c6fe | 1303 | /** |
mbed_official | 340:28d1f895c6fe | 1304 | * @} |
mbed_official | 340:28d1f895c6fe | 1305 | */ |
mbed_official | 340:28d1f895c6fe | 1306 | |
mbed_official | 340:28d1f895c6fe | 1307 | /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions |
mbed_official | 340:28d1f895c6fe | 1308 | * @brief Data transfers Private functions |
mbed_official | 340:28d1f895c6fe | 1309 | * @{ |
mbed_official | 340:28d1f895c6fe | 1310 | */ |
mbed_official | 340:28d1f895c6fe | 1311 | |
mbed_official | 340:28d1f895c6fe | 1312 | /** |
mbed_official | 340:28d1f895c6fe | 1313 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode |
mbed_official | 340:28d1f895c6fe | 1314 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1315 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1316 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 1317 | */ |
mbed_official | 340:28d1f895c6fe | 1318 | static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1319 | { |
mbed_official | 340:28d1f895c6fe | 1320 | uint16_t DevAddress; |
mbed_official | 340:28d1f895c6fe | 1321 | |
mbed_official | 340:28d1f895c6fe | 1322 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 1323 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1324 | |
mbed_official | 340:28d1f895c6fe | 1325 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) |
mbed_official | 340:28d1f895c6fe | 1326 | { |
mbed_official | 340:28d1f895c6fe | 1327 | /* Clear NACK Flag */ |
mbed_official | 340:28d1f895c6fe | 1328 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
mbed_official | 340:28d1f895c6fe | 1329 | |
mbed_official | 340:28d1f895c6fe | 1330 | /* Set corresponding Error Code */ |
mbed_official | 340:28d1f895c6fe | 1331 | /* No need to generate STOP, it is automatically done */ |
mbed_official | 340:28d1f895c6fe | 1332 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; |
mbed_official | 340:28d1f895c6fe | 1333 | |
mbed_official | 340:28d1f895c6fe | 1334 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1335 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1336 | |
mbed_official | 340:28d1f895c6fe | 1337 | /* Call the Error callback to prevent upper layer */ |
mbed_official | 340:28d1f895c6fe | 1338 | HAL_SMBUS_ErrorCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1339 | } |
mbed_official | 340:28d1f895c6fe | 1340 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) |
mbed_official | 340:28d1f895c6fe | 1341 | { |
mbed_official | 340:28d1f895c6fe | 1342 | |
mbed_official | 340:28d1f895c6fe | 1343 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
mbed_official | 340:28d1f895c6fe | 1344 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1345 | { |
mbed_official | 340:28d1f895c6fe | 1346 | /* Disable Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1347 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1348 | |
mbed_official | 340:28d1f895c6fe | 1349 | /* Clear STOP Flag */ |
mbed_official | 340:28d1f895c6fe | 1350 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 1351 | |
mbed_official | 340:28d1f895c6fe | 1352 | /* Clear Configuration Register 2 */ |
mbed_official | 340:28d1f895c6fe | 1353 | __HAL_SMBUS_RESET_CR2(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1354 | |
mbed_official | 340:28d1f895c6fe | 1355 | /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ |
mbed_official | 340:28d1f895c6fe | 1356 | /* Disable the selected SMBUS peripheral */ |
mbed_official | 340:28d1f895c6fe | 1357 | __HAL_SMBUS_DISABLE(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1358 | |
mbed_official | 340:28d1f895c6fe | 1359 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1360 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1361 | |
mbed_official | 340:28d1f895c6fe | 1362 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1363 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1364 | |
mbed_official | 340:28d1f895c6fe | 1365 | /* REenable the selected SMBUS peripheral */ |
mbed_official | 340:28d1f895c6fe | 1366 | __HAL_SMBUS_ENABLE(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1367 | |
mbed_official | 340:28d1f895c6fe | 1368 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1369 | } |
mbed_official | 340:28d1f895c6fe | 1370 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1371 | { |
mbed_official | 340:28d1f895c6fe | 1372 | /* Disable Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1373 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 1374 | |
mbed_official | 340:28d1f895c6fe | 1375 | /* Clear STOP Flag */ |
mbed_official | 340:28d1f895c6fe | 1376 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 1377 | |
mbed_official | 340:28d1f895c6fe | 1378 | /* Clear Configuration Register 2 */ |
mbed_official | 340:28d1f895c6fe | 1379 | __HAL_SMBUS_RESET_CR2(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1380 | |
mbed_official | 340:28d1f895c6fe | 1381 | hsmbus->PreviousState = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1382 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1383 | |
mbed_official | 340:28d1f895c6fe | 1384 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1385 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1386 | |
mbed_official | 340:28d1f895c6fe | 1387 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1388 | } |
mbed_official | 340:28d1f895c6fe | 1389 | } |
mbed_official | 340:28d1f895c6fe | 1390 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) |
mbed_official | 340:28d1f895c6fe | 1391 | { |
mbed_official | 340:28d1f895c6fe | 1392 | /* Read data from RXDR */ |
mbed_official | 340:28d1f895c6fe | 1393 | (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; |
mbed_official | 340:28d1f895c6fe | 1394 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1395 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1396 | } |
mbed_official | 340:28d1f895c6fe | 1397 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) |
mbed_official | 340:28d1f895c6fe | 1398 | { |
mbed_official | 340:28d1f895c6fe | 1399 | /* Write data to TXDR */ |
mbed_official | 340:28d1f895c6fe | 1400 | hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); |
mbed_official | 340:28d1f895c6fe | 1401 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1402 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1403 | } |
mbed_official | 340:28d1f895c6fe | 1404 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET) |
mbed_official | 340:28d1f895c6fe | 1405 | { |
mbed_official | 340:28d1f895c6fe | 1406 | if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) |
mbed_official | 340:28d1f895c6fe | 1407 | { |
mbed_official | 340:28d1f895c6fe | 1408 | DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD); |
mbed_official | 340:28d1f895c6fe | 1409 | |
mbed_official | 340:28d1f895c6fe | 1410 | if(hsmbus->XferCount > MAX_NBYTE_SIZE) |
mbed_official | 340:28d1f895c6fe | 1411 | { |
mbed_official | 340:28d1f895c6fe | 1412 | SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1413 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
mbed_official | 340:28d1f895c6fe | 1414 | } |
mbed_official | 340:28d1f895c6fe | 1415 | else |
mbed_official | 340:28d1f895c6fe | 1416 | { |
mbed_official | 340:28d1f895c6fe | 1417 | hsmbus->XferSize = hsmbus->XferCount; |
mbed_official | 340:28d1f895c6fe | 1418 | SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1419 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
mbed_official | 340:28d1f895c6fe | 1420 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
mbed_official | 340:28d1f895c6fe | 1421 | if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
mbed_official | 340:28d1f895c6fe | 1422 | { |
mbed_official | 340:28d1f895c6fe | 1423 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1424 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1425 | } |
mbed_official | 340:28d1f895c6fe | 1426 | } |
mbed_official | 340:28d1f895c6fe | 1427 | } |
mbed_official | 340:28d1f895c6fe | 1428 | else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) |
mbed_official | 340:28d1f895c6fe | 1429 | { |
mbed_official | 340:28d1f895c6fe | 1430 | /* Call TxCpltCallback if no stop mode is set */ |
mbed_official | 340:28d1f895c6fe | 1431 | if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) |
mbed_official | 340:28d1f895c6fe | 1432 | { |
mbed_official | 340:28d1f895c6fe | 1433 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
mbed_official | 340:28d1f895c6fe | 1434 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1435 | { |
mbed_official | 340:28d1f895c6fe | 1436 | /* Disable Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1437 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1438 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1439 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1440 | |
mbed_official | 340:28d1f895c6fe | 1441 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1442 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1443 | |
mbed_official | 340:28d1f895c6fe | 1444 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1445 | } |
mbed_official | 340:28d1f895c6fe | 1446 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1447 | { |
mbed_official | 340:28d1f895c6fe | 1448 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 1449 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1450 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1451 | |
mbed_official | 340:28d1f895c6fe | 1452 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1453 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1454 | |
mbed_official | 340:28d1f895c6fe | 1455 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1456 | } |
mbed_official | 340:28d1f895c6fe | 1457 | } |
mbed_official | 340:28d1f895c6fe | 1458 | } |
mbed_official | 340:28d1f895c6fe | 1459 | } |
mbed_official | 340:28d1f895c6fe | 1460 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET) |
mbed_official | 340:28d1f895c6fe | 1461 | { |
mbed_official | 340:28d1f895c6fe | 1462 | if(hsmbus->XferCount == 0) |
mbed_official | 340:28d1f895c6fe | 1463 | { |
mbed_official | 340:28d1f895c6fe | 1464 | /* Specific use case for Quick command */ |
mbed_official | 340:28d1f895c6fe | 1465 | if(hsmbus->pBuffPtr == HAL_NULL) |
mbed_official | 340:28d1f895c6fe | 1466 | { |
mbed_official | 340:28d1f895c6fe | 1467 | /* Generate a Stop command */ |
mbed_official | 340:28d1f895c6fe | 1468 | hsmbus->Instance->CR2 |= I2C_CR2_STOP; |
mbed_official | 340:28d1f895c6fe | 1469 | } |
mbed_official | 340:28d1f895c6fe | 1470 | /* Call TxCpltCallback if no stop mode is set */ |
mbed_official | 340:28d1f895c6fe | 1471 | else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) |
mbed_official | 340:28d1f895c6fe | 1472 | { |
mbed_official | 340:28d1f895c6fe | 1473 | /* No Generate Stop, to permit restart mode */ |
mbed_official | 340:28d1f895c6fe | 1474 | /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ |
mbed_official | 340:28d1f895c6fe | 1475 | |
mbed_official | 340:28d1f895c6fe | 1476 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
mbed_official | 340:28d1f895c6fe | 1477 | if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1478 | { |
mbed_official | 340:28d1f895c6fe | 1479 | /* Disable Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1480 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1481 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1482 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1483 | |
mbed_official | 340:28d1f895c6fe | 1484 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1485 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1486 | |
mbed_official | 340:28d1f895c6fe | 1487 | HAL_SMBUS_MasterTxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1488 | } |
mbed_official | 340:28d1f895c6fe | 1489 | else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1490 | { |
mbed_official | 340:28d1f895c6fe | 1491 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 1492 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1493 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1494 | |
mbed_official | 340:28d1f895c6fe | 1495 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1496 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1497 | |
mbed_official | 340:28d1f895c6fe | 1498 | HAL_SMBUS_MasterRxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1499 | } |
mbed_official | 340:28d1f895c6fe | 1500 | } |
mbed_official | 340:28d1f895c6fe | 1501 | } |
mbed_official | 340:28d1f895c6fe | 1502 | } |
mbed_official | 340:28d1f895c6fe | 1503 | |
mbed_official | 340:28d1f895c6fe | 1504 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1505 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1506 | |
mbed_official | 340:28d1f895c6fe | 1507 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1508 | } |
mbed_official | 340:28d1f895c6fe | 1509 | /** |
mbed_official | 340:28d1f895c6fe | 1510 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode |
mbed_official | 340:28d1f895c6fe | 1511 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1512 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1513 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 1514 | */ |
mbed_official | 340:28d1f895c6fe | 1515 | static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) |
mbed_official | 340:28d1f895c6fe | 1516 | { |
mbed_official | 340:28d1f895c6fe | 1517 | uint8_t TransferDirection = 0; |
mbed_official | 340:28d1f895c6fe | 1518 | uint16_t SlaveAddrCode = 0; |
mbed_official | 340:28d1f895c6fe | 1519 | |
mbed_official | 340:28d1f895c6fe | 1520 | /* Process Locked */ |
mbed_official | 340:28d1f895c6fe | 1521 | __HAL_LOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1522 | |
mbed_official | 340:28d1f895c6fe | 1523 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET) |
mbed_official | 340:28d1f895c6fe | 1524 | { |
mbed_official | 340:28d1f895c6fe | 1525 | /* Check that SMBUS transfer finished */ |
mbed_official | 340:28d1f895c6fe | 1526 | /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ |
mbed_official | 340:28d1f895c6fe | 1527 | /* Mean XferCount == 0*/ |
mbed_official | 340:28d1f895c6fe | 1528 | /* So clear Flag NACKF only */ |
mbed_official | 340:28d1f895c6fe | 1529 | if(hsmbus->XferCount == 0) |
mbed_official | 340:28d1f895c6fe | 1530 | { |
mbed_official | 340:28d1f895c6fe | 1531 | /* Clear NACK Flag */ |
mbed_official | 340:28d1f895c6fe | 1532 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
mbed_official | 340:28d1f895c6fe | 1533 | |
mbed_official | 340:28d1f895c6fe | 1534 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1535 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1536 | } |
mbed_official | 340:28d1f895c6fe | 1537 | else |
mbed_official | 340:28d1f895c6fe | 1538 | { |
mbed_official | 340:28d1f895c6fe | 1539 | /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ |
mbed_official | 340:28d1f895c6fe | 1540 | /* Clear NACK Flag */ |
mbed_official | 340:28d1f895c6fe | 1541 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); |
mbed_official | 340:28d1f895c6fe | 1542 | |
mbed_official | 340:28d1f895c6fe | 1543 | /* Set HAL State to "Idle" State, mean to LISTEN state */ |
mbed_official | 340:28d1f895c6fe | 1544 | /* So reset Slave Busy state */ |
mbed_official | 340:28d1f895c6fe | 1545 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1546 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); |
mbed_official | 340:28d1f895c6fe | 1547 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); |
mbed_official | 340:28d1f895c6fe | 1548 | |
mbed_official | 340:28d1f895c6fe | 1549 | /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1550 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1551 | |
mbed_official | 340:28d1f895c6fe | 1552 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
mbed_official | 340:28d1f895c6fe | 1553 | hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; |
mbed_official | 340:28d1f895c6fe | 1554 | |
mbed_official | 340:28d1f895c6fe | 1555 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1556 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1557 | |
mbed_official | 340:28d1f895c6fe | 1558 | /* Call the Error callback to prevent upper layer */ |
mbed_official | 340:28d1f895c6fe | 1559 | HAL_SMBUS_ErrorCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1560 | } |
mbed_official | 340:28d1f895c6fe | 1561 | } |
mbed_official | 340:28d1f895c6fe | 1562 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) |
mbed_official | 340:28d1f895c6fe | 1563 | { |
mbed_official | 340:28d1f895c6fe | 1564 | TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1565 | SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1566 | |
mbed_official | 340:28d1f895c6fe | 1567 | /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ |
mbed_official | 340:28d1f895c6fe | 1568 | /* Other ADDRInterrupt will be treat in next Listen usecase */ |
mbed_official | 340:28d1f895c6fe | 1569 | __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); |
mbed_official | 340:28d1f895c6fe | 1570 | |
mbed_official | 340:28d1f895c6fe | 1571 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1572 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1573 | |
mbed_official | 340:28d1f895c6fe | 1574 | /* Call Slave Addr callback */ |
mbed_official | 340:28d1f895c6fe | 1575 | HAL_SMBUS_SlaveAddrCallback(hsmbus, TransferDirection, SlaveAddrCode); |
mbed_official | 340:28d1f895c6fe | 1576 | } |
mbed_official | 340:28d1f895c6fe | 1577 | else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)) |
mbed_official | 340:28d1f895c6fe | 1578 | { |
mbed_official | 340:28d1f895c6fe | 1579 | if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) |
mbed_official | 340:28d1f895c6fe | 1580 | { |
mbed_official | 340:28d1f895c6fe | 1581 | /* Read data from RXDR */ |
mbed_official | 340:28d1f895c6fe | 1582 | (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR; |
mbed_official | 340:28d1f895c6fe | 1583 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1584 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1585 | |
mbed_official | 340:28d1f895c6fe | 1586 | if(hsmbus->XferCount == 1) |
mbed_official | 340:28d1f895c6fe | 1587 | { |
mbed_official | 340:28d1f895c6fe | 1588 | /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ |
mbed_official | 340:28d1f895c6fe | 1589 | /* or only the last Byte of Transfer */ |
mbed_official | 340:28d1f895c6fe | 1590 | /* So reset the RELOAD bit mode */ |
mbed_official | 340:28d1f895c6fe | 1591 | hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; |
mbed_official | 340:28d1f895c6fe | 1592 | SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1593 | } |
mbed_official | 340:28d1f895c6fe | 1594 | else if(hsmbus->XferCount == 0) |
mbed_official | 340:28d1f895c6fe | 1595 | { |
mbed_official | 340:28d1f895c6fe | 1596 | /* Last Byte is received, disable Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1597 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); |
mbed_official | 340:28d1f895c6fe | 1598 | |
mbed_official | 340:28d1f895c6fe | 1599 | /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ |
mbed_official | 340:28d1f895c6fe | 1600 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1601 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); |
mbed_official | 340:28d1f895c6fe | 1602 | |
mbed_official | 340:28d1f895c6fe | 1603 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1604 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1605 | |
mbed_official | 340:28d1f895c6fe | 1606 | /* Call the Rx complete callback to inform upper layer of the end of receive process */ |
mbed_official | 340:28d1f895c6fe | 1607 | HAL_SMBUS_SlaveRxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1608 | } |
mbed_official | 340:28d1f895c6fe | 1609 | else |
mbed_official | 340:28d1f895c6fe | 1610 | { |
mbed_official | 340:28d1f895c6fe | 1611 | /* Set Reload for next Bytes */ |
mbed_official | 340:28d1f895c6fe | 1612 | SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1613 | |
mbed_official | 340:28d1f895c6fe | 1614 | /* Ack last Byte Read */ |
mbed_official | 340:28d1f895c6fe | 1615 | hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; |
mbed_official | 340:28d1f895c6fe | 1616 | } |
mbed_official | 340:28d1f895c6fe | 1617 | } |
mbed_official | 340:28d1f895c6fe | 1618 | else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) |
mbed_official | 340:28d1f895c6fe | 1619 | { |
mbed_official | 340:28d1f895c6fe | 1620 | if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0)) |
mbed_official | 340:28d1f895c6fe | 1621 | { |
mbed_official | 340:28d1f895c6fe | 1622 | if(hsmbus->XferCount > MAX_NBYTE_SIZE) |
mbed_official | 340:28d1f895c6fe | 1623 | { |
mbed_official | 340:28d1f895c6fe | 1624 | SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1625 | hsmbus->XferSize = MAX_NBYTE_SIZE; |
mbed_official | 340:28d1f895c6fe | 1626 | } |
mbed_official | 340:28d1f895c6fe | 1627 | else |
mbed_official | 340:28d1f895c6fe | 1628 | { |
mbed_official | 340:28d1f895c6fe | 1629 | hsmbus->XferSize = hsmbus->XferCount; |
mbed_official | 340:28d1f895c6fe | 1630 | SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); |
mbed_official | 340:28d1f895c6fe | 1631 | /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ |
mbed_official | 340:28d1f895c6fe | 1632 | /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ |
mbed_official | 340:28d1f895c6fe | 1633 | if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) |
mbed_official | 340:28d1f895c6fe | 1634 | { |
mbed_official | 340:28d1f895c6fe | 1635 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1636 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1637 | } |
mbed_official | 340:28d1f895c6fe | 1638 | } |
mbed_official | 340:28d1f895c6fe | 1639 | } |
mbed_official | 340:28d1f895c6fe | 1640 | } |
mbed_official | 340:28d1f895c6fe | 1641 | } |
mbed_official | 340:28d1f895c6fe | 1642 | else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) |
mbed_official | 340:28d1f895c6fe | 1643 | { |
mbed_official | 340:28d1f895c6fe | 1644 | /* Write data to TXDR only if XferCount not reach "0" */ |
mbed_official | 340:28d1f895c6fe | 1645 | /* A TXIS flag can be set, during STOP treatment */ |
mbed_official | 340:28d1f895c6fe | 1646 | /* Check if all Datas have already been sent */ |
mbed_official | 340:28d1f895c6fe | 1647 | /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ |
mbed_official | 340:28d1f895c6fe | 1648 | if(hsmbus->XferCount > 0) |
mbed_official | 340:28d1f895c6fe | 1649 | { |
mbed_official | 340:28d1f895c6fe | 1650 | /* Write data to TXDR */ |
mbed_official | 340:28d1f895c6fe | 1651 | hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++); |
mbed_official | 340:28d1f895c6fe | 1652 | hsmbus->XferCount--; |
mbed_official | 340:28d1f895c6fe | 1653 | hsmbus->XferSize--; |
mbed_official | 340:28d1f895c6fe | 1654 | } |
mbed_official | 340:28d1f895c6fe | 1655 | |
mbed_official | 340:28d1f895c6fe | 1656 | if(hsmbus->XferCount == 0) |
mbed_official | 340:28d1f895c6fe | 1657 | { |
mbed_official | 340:28d1f895c6fe | 1658 | /* Last Byte is Transmitted */ |
mbed_official | 340:28d1f895c6fe | 1659 | /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ |
mbed_official | 340:28d1f895c6fe | 1660 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1661 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1662 | hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); |
mbed_official | 340:28d1f895c6fe | 1663 | |
mbed_official | 340:28d1f895c6fe | 1664 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1665 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1666 | |
mbed_official | 340:28d1f895c6fe | 1667 | /* Call the Tx complete callback to inform upper layer of the end of transmit process */ |
mbed_official | 340:28d1f895c6fe | 1668 | HAL_SMBUS_SlaveTxCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1669 | } |
mbed_official | 340:28d1f895c6fe | 1670 | } |
mbed_official | 340:28d1f895c6fe | 1671 | |
mbed_official | 340:28d1f895c6fe | 1672 | /* Check if STOPF is set */ |
mbed_official | 340:28d1f895c6fe | 1673 | if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET) |
mbed_official | 340:28d1f895c6fe | 1674 | { |
mbed_official | 340:28d1f895c6fe | 1675 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 1676 | { |
mbed_official | 340:28d1f895c6fe | 1677 | /* Disable RX and TX Interrupts */ |
mbed_official | 340:28d1f895c6fe | 1678 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); |
mbed_official | 340:28d1f895c6fe | 1679 | |
mbed_official | 340:28d1f895c6fe | 1680 | /* Disable ADDR Interrupt */ |
mbed_official | 340:28d1f895c6fe | 1681 | SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); |
mbed_official | 340:28d1f895c6fe | 1682 | |
mbed_official | 340:28d1f895c6fe | 1683 | /* Disable Address Acknowledge */ |
mbed_official | 340:28d1f895c6fe | 1684 | hsmbus->Instance->CR2 |= I2C_CR2_NACK; |
mbed_official | 340:28d1f895c6fe | 1685 | |
mbed_official | 340:28d1f895c6fe | 1686 | /* Clear Configuration Register 2 */ |
mbed_official | 340:28d1f895c6fe | 1687 | __HAL_SMBUS_RESET_CR2(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1688 | |
mbed_official | 340:28d1f895c6fe | 1689 | /* Clear STOP Flag */ |
mbed_official | 340:28d1f895c6fe | 1690 | __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); |
mbed_official | 340:28d1f895c6fe | 1691 | |
mbed_official | 340:28d1f895c6fe | 1692 | /* Clear ADDR flag */ |
mbed_official | 340:28d1f895c6fe | 1693 | __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR); |
mbed_official | 340:28d1f895c6fe | 1694 | |
mbed_official | 340:28d1f895c6fe | 1695 | hsmbus->XferOptions = 0; |
mbed_official | 340:28d1f895c6fe | 1696 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1697 | hsmbus->State = HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1698 | |
mbed_official | 340:28d1f895c6fe | 1699 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1700 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1701 | |
mbed_official | 340:28d1f895c6fe | 1702 | /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */ |
mbed_official | 340:28d1f895c6fe | 1703 | HAL_SMBUS_SlaveListenCpltCallback(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1704 | } |
mbed_official | 340:28d1f895c6fe | 1705 | } |
mbed_official | 340:28d1f895c6fe | 1706 | |
mbed_official | 340:28d1f895c6fe | 1707 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1708 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1709 | |
mbed_official | 340:28d1f895c6fe | 1710 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1711 | } |
mbed_official | 340:28d1f895c6fe | 1712 | /** |
mbed_official | 340:28d1f895c6fe | 1713 | * @brief Manage the enabling of Interrupts |
mbed_official | 340:28d1f895c6fe | 1714 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1715 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1716 | * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. |
mbed_official | 340:28d1f895c6fe | 1717 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 1718 | */ |
mbed_official | 340:28d1f895c6fe | 1719 | static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) |
mbed_official | 340:28d1f895c6fe | 1720 | { |
mbed_official | 340:28d1f895c6fe | 1721 | uint32_t tmpisr = 0; |
mbed_official | 340:28d1f895c6fe | 1722 | |
mbed_official | 340:28d1f895c6fe | 1723 | if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) |
mbed_official | 340:28d1f895c6fe | 1724 | { |
mbed_official | 340:28d1f895c6fe | 1725 | /* Enable ERR interrupt */ |
mbed_official | 340:28d1f895c6fe | 1726 | tmpisr |= SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1727 | } |
mbed_official | 340:28d1f895c6fe | 1728 | |
mbed_official | 340:28d1f895c6fe | 1729 | if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) |
mbed_official | 340:28d1f895c6fe | 1730 | { |
mbed_official | 340:28d1f895c6fe | 1731 | /* Enable ADDR, STOP interrupt */ |
mbed_official | 340:28d1f895c6fe | 1732 | tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1733 | } |
mbed_official | 340:28d1f895c6fe | 1734 | |
mbed_official | 340:28d1f895c6fe | 1735 | if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) |
mbed_official | 340:28d1f895c6fe | 1736 | { |
mbed_official | 340:28d1f895c6fe | 1737 | /* Enable ERR, TC, STOP, NACK, RXI interrupt */ |
mbed_official | 340:28d1f895c6fe | 1738 | tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; |
mbed_official | 340:28d1f895c6fe | 1739 | } |
mbed_official | 340:28d1f895c6fe | 1740 | |
mbed_official | 340:28d1f895c6fe | 1741 | if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) |
mbed_official | 340:28d1f895c6fe | 1742 | { |
mbed_official | 340:28d1f895c6fe | 1743 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
mbed_official | 340:28d1f895c6fe | 1744 | tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; |
mbed_official | 340:28d1f895c6fe | 1745 | } |
mbed_official | 340:28d1f895c6fe | 1746 | |
mbed_official | 340:28d1f895c6fe | 1747 | /* Enable interrupts only at the end */ |
mbed_official | 340:28d1f895c6fe | 1748 | /* to avoid the risk of SMBUS interrupt handle execution before */ |
mbed_official | 340:28d1f895c6fe | 1749 | /* all interrupts requested done */ |
mbed_official | 340:28d1f895c6fe | 1750 | __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); |
mbed_official | 340:28d1f895c6fe | 1751 | |
mbed_official | 340:28d1f895c6fe | 1752 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1753 | } |
mbed_official | 340:28d1f895c6fe | 1754 | /** |
mbed_official | 340:28d1f895c6fe | 1755 | * @brief Manage the disabling of Interrupts |
mbed_official | 340:28d1f895c6fe | 1756 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1757 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1758 | * @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition. |
mbed_official | 340:28d1f895c6fe | 1759 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 1760 | */ |
mbed_official | 340:28d1f895c6fe | 1761 | static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest) |
mbed_official | 340:28d1f895c6fe | 1762 | { |
mbed_official | 340:28d1f895c6fe | 1763 | uint32_t tmpisr = 0; |
mbed_official | 340:28d1f895c6fe | 1764 | |
mbed_official | 340:28d1f895c6fe | 1765 | if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) ) |
mbed_official | 340:28d1f895c6fe | 1766 | { |
mbed_official | 340:28d1f895c6fe | 1767 | /* Disable ERR interrupt */ |
mbed_official | 340:28d1f895c6fe | 1768 | tmpisr |= SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1769 | } |
mbed_official | 340:28d1f895c6fe | 1770 | |
mbed_official | 340:28d1f895c6fe | 1771 | if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) |
mbed_official | 340:28d1f895c6fe | 1772 | { |
mbed_official | 340:28d1f895c6fe | 1773 | /* Disable TC, STOP, NACK, TXI interrupt */ |
mbed_official | 340:28d1f895c6fe | 1774 | tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; |
mbed_official | 340:28d1f895c6fe | 1775 | |
mbed_official | 340:28d1f895c6fe | 1776 | if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
mbed_official | 340:28d1f895c6fe | 1777 | && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) |
mbed_official | 340:28d1f895c6fe | 1778 | { |
mbed_official | 340:28d1f895c6fe | 1779 | /* Disable ERR interrupt */ |
mbed_official | 340:28d1f895c6fe | 1780 | tmpisr |= SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1781 | } |
mbed_official | 340:28d1f895c6fe | 1782 | |
mbed_official | 340:28d1f895c6fe | 1783 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 1784 | { |
mbed_official | 340:28d1f895c6fe | 1785 | /* Disable STOPI, NACKI */ |
mbed_official | 340:28d1f895c6fe | 1786 | tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
mbed_official | 340:28d1f895c6fe | 1787 | } |
mbed_official | 340:28d1f895c6fe | 1788 | } |
mbed_official | 340:28d1f895c6fe | 1789 | |
mbed_official | 340:28d1f895c6fe | 1790 | if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) |
mbed_official | 340:28d1f895c6fe | 1791 | { |
mbed_official | 340:28d1f895c6fe | 1792 | /* Disable TC, STOP, NACK, RXI interrupt */ |
mbed_official | 340:28d1f895c6fe | 1793 | tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; |
mbed_official | 340:28d1f895c6fe | 1794 | |
mbed_official | 340:28d1f895c6fe | 1795 | if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
mbed_official | 340:28d1f895c6fe | 1796 | && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) |
mbed_official | 340:28d1f895c6fe | 1797 | { |
mbed_official | 340:28d1f895c6fe | 1798 | /* Disable ERR interrupt */ |
mbed_official | 340:28d1f895c6fe | 1799 | tmpisr |= SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1800 | } |
mbed_official | 340:28d1f895c6fe | 1801 | |
mbed_official | 340:28d1f895c6fe | 1802 | if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) |
mbed_official | 340:28d1f895c6fe | 1803 | { |
mbed_official | 340:28d1f895c6fe | 1804 | /* Disable STOPI, NACKI */ |
mbed_official | 340:28d1f895c6fe | 1805 | tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
mbed_official | 340:28d1f895c6fe | 1806 | } |
mbed_official | 340:28d1f895c6fe | 1807 | } |
mbed_official | 340:28d1f895c6fe | 1808 | |
mbed_official | 340:28d1f895c6fe | 1809 | if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) |
mbed_official | 340:28d1f895c6fe | 1810 | { |
mbed_official | 340:28d1f895c6fe | 1811 | /* Enable ADDR, STOP interrupt */ |
mbed_official | 340:28d1f895c6fe | 1812 | tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; |
mbed_official | 340:28d1f895c6fe | 1813 | |
mbed_official | 340:28d1f895c6fe | 1814 | if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) |
mbed_official | 340:28d1f895c6fe | 1815 | { |
mbed_official | 340:28d1f895c6fe | 1816 | /* Disable ERR interrupt */ |
mbed_official | 340:28d1f895c6fe | 1817 | tmpisr |= SMBUS_IT_ERRI; |
mbed_official | 340:28d1f895c6fe | 1818 | } |
mbed_official | 340:28d1f895c6fe | 1819 | } |
mbed_official | 340:28d1f895c6fe | 1820 | |
mbed_official | 340:28d1f895c6fe | 1821 | /* Disable interrupts only at the end */ |
mbed_official | 340:28d1f895c6fe | 1822 | /* to avoid a breaking situation like at "t" time */ |
mbed_official | 340:28d1f895c6fe | 1823 | /* all disable interrupts request are not done */ |
mbed_official | 340:28d1f895c6fe | 1824 | __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); |
mbed_official | 340:28d1f895c6fe | 1825 | |
mbed_official | 340:28d1f895c6fe | 1826 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1827 | } |
mbed_official | 340:28d1f895c6fe | 1828 | /** |
mbed_official | 340:28d1f895c6fe | 1829 | * @brief This function handles SMBUS Communication Timeout. |
mbed_official | 340:28d1f895c6fe | 1830 | * @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains |
mbed_official | 340:28d1f895c6fe | 1831 | * the configuration information for the specified SMBUS. |
mbed_official | 340:28d1f895c6fe | 1832 | * @param Flag: specifies the SMBUS flag to check. |
mbed_official | 340:28d1f895c6fe | 1833 | * @param Status: The new Flag status (SET or RESET). |
mbed_official | 340:28d1f895c6fe | 1834 | * @param Timeout: Timeout duration |
mbed_official | 340:28d1f895c6fe | 1835 | * @retval HAL status |
mbed_official | 340:28d1f895c6fe | 1836 | */ |
mbed_official | 340:28d1f895c6fe | 1837 | static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) |
mbed_official | 340:28d1f895c6fe | 1838 | { |
mbed_official | 340:28d1f895c6fe | 1839 | uint32_t tickstart = HAL_GetTick(); |
mbed_official | 340:28d1f895c6fe | 1840 | |
mbed_official | 340:28d1f895c6fe | 1841 | /* Wait until flag is set */ |
mbed_official | 340:28d1f895c6fe | 1842 | if(Status == RESET) |
mbed_official | 340:28d1f895c6fe | 1843 | { |
mbed_official | 340:28d1f895c6fe | 1844 | while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET) |
mbed_official | 340:28d1f895c6fe | 1845 | { |
mbed_official | 340:28d1f895c6fe | 1846 | /* Check for the Timeout */ |
mbed_official | 340:28d1f895c6fe | 1847 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 340:28d1f895c6fe | 1848 | { |
mbed_official | 340:28d1f895c6fe | 1849 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
mbed_official | 340:28d1f895c6fe | 1850 | { |
mbed_official | 340:28d1f895c6fe | 1851 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1852 | hsmbus->State= HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1853 | |
mbed_official | 340:28d1f895c6fe | 1854 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1855 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1856 | |
mbed_official | 340:28d1f895c6fe | 1857 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1858 | } |
mbed_official | 340:28d1f895c6fe | 1859 | } |
mbed_official | 340:28d1f895c6fe | 1860 | } |
mbed_official | 340:28d1f895c6fe | 1861 | } |
mbed_official | 340:28d1f895c6fe | 1862 | else |
mbed_official | 340:28d1f895c6fe | 1863 | { |
mbed_official | 340:28d1f895c6fe | 1864 | while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET) |
mbed_official | 340:28d1f895c6fe | 1865 | { |
mbed_official | 340:28d1f895c6fe | 1866 | /* Check for the Timeout */ |
mbed_official | 340:28d1f895c6fe | 1867 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 340:28d1f895c6fe | 1868 | { |
mbed_official | 340:28d1f895c6fe | 1869 | if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
mbed_official | 340:28d1f895c6fe | 1870 | { |
mbed_official | 340:28d1f895c6fe | 1871 | hsmbus->PreviousState = hsmbus->State; |
mbed_official | 340:28d1f895c6fe | 1872 | hsmbus->State= HAL_SMBUS_STATE_READY; |
mbed_official | 340:28d1f895c6fe | 1873 | |
mbed_official | 340:28d1f895c6fe | 1874 | /* Process Unlocked */ |
mbed_official | 340:28d1f895c6fe | 1875 | __HAL_UNLOCK(hsmbus); |
mbed_official | 340:28d1f895c6fe | 1876 | |
mbed_official | 340:28d1f895c6fe | 1877 | return HAL_TIMEOUT; |
mbed_official | 340:28d1f895c6fe | 1878 | } |
mbed_official | 340:28d1f895c6fe | 1879 | } |
mbed_official | 340:28d1f895c6fe | 1880 | } |
mbed_official | 340:28d1f895c6fe | 1881 | } |
mbed_official | 340:28d1f895c6fe | 1882 | return HAL_OK; |
mbed_official | 340:28d1f895c6fe | 1883 | } |
mbed_official | 340:28d1f895c6fe | 1884 | |
mbed_official | 340:28d1f895c6fe | 1885 | /** |
mbed_official | 340:28d1f895c6fe | 1886 | * @brief Handles SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). |
mbed_official | 340:28d1f895c6fe | 1887 | * @param hsmbus: SMBUS handle. |
mbed_official | 340:28d1f895c6fe | 1888 | * @param DevAddress: specifies the slave address to be programmed. |
mbed_official | 340:28d1f895c6fe | 1889 | * @param Size: specifies the number of bytes to be programmed. |
mbed_official | 340:28d1f895c6fe | 1890 | * This parameter must be a value between 0 and 255. |
mbed_official | 340:28d1f895c6fe | 1891 | * @param Mode: new state of the SMBUS START condition generation. |
mbed_official | 340:28d1f895c6fe | 1892 | * This parameter can be one or a combination of the following values: |
mbed_official | 340:28d1f895c6fe | 1893 | * @arg SMBUS_NO_MODE: No specific mode enabled. |
mbed_official | 340:28d1f895c6fe | 1894 | * @arg SMBUS_RELOAD_MODE: Enable Reload mode. |
mbed_official | 340:28d1f895c6fe | 1895 | * @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode. |
mbed_official | 340:28d1f895c6fe | 1896 | * @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode. |
mbed_official | 340:28d1f895c6fe | 1897 | * @param Request: new state of the SMBUS START condition generation. |
mbed_official | 340:28d1f895c6fe | 1898 | * This parameter can be one of the following values: |
mbed_official | 340:28d1f895c6fe | 1899 | * @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition. |
mbed_official | 340:28d1f895c6fe | 1900 | * @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0). |
mbed_official | 340:28d1f895c6fe | 1901 | * @arg SMBUS_GENERATE_START_READ: Generate Restart for read request. |
mbed_official | 340:28d1f895c6fe | 1902 | * @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request. |
mbed_official | 340:28d1f895c6fe | 1903 | * @retval None |
mbed_official | 340:28d1f895c6fe | 1904 | */ |
mbed_official | 340:28d1f895c6fe | 1905 | static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) |
mbed_official | 340:28d1f895c6fe | 1906 | { |
mbed_official | 340:28d1f895c6fe | 1907 | uint32_t tmpreg = 0; |
mbed_official | 340:28d1f895c6fe | 1908 | |
mbed_official | 340:28d1f895c6fe | 1909 | /* Check the parameters */ |
mbed_official | 340:28d1f895c6fe | 1910 | assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); |
mbed_official | 340:28d1f895c6fe | 1911 | assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); |
mbed_official | 340:28d1f895c6fe | 1912 | assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); |
mbed_official | 340:28d1f895c6fe | 1913 | |
mbed_official | 340:28d1f895c6fe | 1914 | /* Get the CR2 register value */ |
mbed_official | 340:28d1f895c6fe | 1915 | tmpreg = hsmbus->Instance->CR2; |
mbed_official | 340:28d1f895c6fe | 1916 | |
mbed_official | 340:28d1f895c6fe | 1917 | /* clear tmpreg specific bits */ |
mbed_official | 340:28d1f895c6fe | 1918 | tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)); |
mbed_official | 340:28d1f895c6fe | 1919 | |
mbed_official | 340:28d1f895c6fe | 1920 | /* update tmpreg */ |
mbed_official | 340:28d1f895c6fe | 1921 | tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \ |
mbed_official | 340:28d1f895c6fe | 1922 | (uint32_t)Mode | (uint32_t)Request); |
mbed_official | 340:28d1f895c6fe | 1923 | |
mbed_official | 340:28d1f895c6fe | 1924 | /* update CR2 register */ |
mbed_official | 340:28d1f895c6fe | 1925 | hsmbus->Instance->CR2 = tmpreg; |
mbed_official | 340:28d1f895c6fe | 1926 | } |
mbed_official | 340:28d1f895c6fe | 1927 | /** |
mbed_official | 340:28d1f895c6fe | 1928 | * @} |
mbed_official | 340:28d1f895c6fe | 1929 | */ |
mbed_official | 340:28d1f895c6fe | 1930 | |
mbed_official | 340:28d1f895c6fe | 1931 | #endif /* HAL_SMBUS_MODULE_ENABLED */ |
mbed_official | 340:28d1f895c6fe | 1932 | /** |
mbed_official | 340:28d1f895c6fe | 1933 | * @} |
mbed_official | 340:28d1f895c6fe | 1934 | */ |
mbed_official | 340:28d1f895c6fe | 1935 | |
mbed_official | 340:28d1f895c6fe | 1936 | /** |
mbed_official | 340:28d1f895c6fe | 1937 | * @} |
mbed_official | 340:28d1f895c6fe | 1938 | */ |
mbed_official | 340:28d1f895c6fe | 1939 | |
mbed_official | 340:28d1f895c6fe | 1940 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |