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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc_ex.h@340:28d1f895c6fe, 2014-10-09 (annotated)

Committer:: mbed_official
Date:: Thu Oct 09 08:15:07 2014 +0100
Revision:: 340:28d1f895c6fe

Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602

Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/

HAL: nrf51822 - Few fixes for PWM and Serial

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_rcc_ex.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	340:28d1f895c6fe	5	* @version V1.1.0
mbed_official	340:28d1f895c6fe	6	* @date 03-Oct-2014
mbed_official	340:28d1f895c6fe	7	* @brief Header file of RCC HAL Extension module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	340:28d1f895c6fe	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_RCC_EX_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup RCCEx
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	340:28d1f895c6fe	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	340:28d1f895c6fe	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58
mbed_official	340:28d1f895c6fe	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	340:28d1f895c6fe	60	* @{
mbed_official	340:28d1f895c6fe	61	*/
mbed_official	340:28d1f895c6fe	62
mbed_official	340:28d1f895c6fe	63	/**
mbed_official	340:28d1f895c6fe	64	* @brief RCC extended clocks structure definition
mbed_official	340:28d1f895c6fe	65	*/
mbed_official	340:28d1f895c6fe	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
mbed_official	340:28d1f895c6fe	67	typedef struct
mbed_official	340:28d1f895c6fe	68	{
mbed_official	340:28d1f895c6fe	69	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	70	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	71
mbed_official	340:28d1f895c6fe	72	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	73	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	74
mbed_official	340:28d1f895c6fe	75	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	76	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	77
mbed_official	340:28d1f895c6fe	78	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	79	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	80
mbed_official	340:28d1f895c6fe	81	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	82	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx */
mbed_official	340:28d1f895c6fe	83
mbed_official	340:28d1f895c6fe	84	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	85	typedef struct
mbed_official	340:28d1f895c6fe	86	{
mbed_official	340:28d1f895c6fe	87	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	88	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	89
mbed_official	340:28d1f895c6fe	90	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	91	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	92
mbed_official	340:28d1f895c6fe	93	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	94	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	95
mbed_official	340:28d1f895c6fe	96	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	97	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	98
mbed_official	340:28d1f895c6fe	99	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	100	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	101
mbed_official	340:28d1f895c6fe	102	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	103	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	104
mbed_official	340:28d1f895c6fe	105	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	106	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	107
mbed_official	340:28d1f895c6fe	108	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	109	typedef struct
mbed_official	340:28d1f895c6fe	110	{
mbed_official	340:28d1f895c6fe	111	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	112	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	113
mbed_official	340:28d1f895c6fe	114	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	115	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	116
mbed_official	340:28d1f895c6fe	117	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	118	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	119
mbed_official	340:28d1f895c6fe	120	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	121	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	122
mbed_official	340:28d1f895c6fe	123	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	124	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	125
mbed_official	340:28d1f895c6fe	126	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	127	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	128
mbed_official	340:28d1f895c6fe	129	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	130	typedef struct
mbed_official	340:28d1f895c6fe	131	{
mbed_official	340:28d1f895c6fe	132	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	133	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	134
mbed_official	340:28d1f895c6fe	135	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	136	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	137
mbed_official	340:28d1f895c6fe	138	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	139	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	140
mbed_official	340:28d1f895c6fe	141	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	142	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	143
mbed_official	340:28d1f895c6fe	144	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	145	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	146
mbed_official	340:28d1f895c6fe	147	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	148	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	149
mbed_official	340:28d1f895c6fe	150	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	151	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	152
mbed_official	340:28d1f895c6fe	153	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	154	typedef struct
mbed_official	340:28d1f895c6fe	155	{
mbed_official	340:28d1f895c6fe	156	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	157	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	158
mbed_official	340:28d1f895c6fe	159	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	160	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	161
mbed_official	340:28d1f895c6fe	162	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	163	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	164
mbed_official	340:28d1f895c6fe	165	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	166	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	167
mbed_official	340:28d1f895c6fe	168	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	169	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	170
mbed_official	340:28d1f895c6fe	171	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	172	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	173
mbed_official	340:28d1f895c6fe	174	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	175	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	176
mbed_official	340:28d1f895c6fe	177	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	178	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	179
mbed_official	340:28d1f895c6fe	180
mbed_official	340:28d1f895c6fe	181	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	182	typedef struct
mbed_official	340:28d1f895c6fe	183	{
mbed_official	340:28d1f895c6fe	184	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	185	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	186
mbed_official	340:28d1f895c6fe	187	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	188	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	189
mbed_official	340:28d1f895c6fe	190	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	191	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	192
mbed_official	340:28d1f895c6fe	193	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	194	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	195
mbed_official	340:28d1f895c6fe	196	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	340:28d1f895c6fe	197	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
mbed_official	340:28d1f895c6fe	198
mbed_official	340:28d1f895c6fe	199	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	200	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	201
mbed_official	340:28d1f895c6fe	202	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	203	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	204
mbed_official	340:28d1f895c6fe	205	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	206	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	207
mbed_official	340:28d1f895c6fe	208
mbed_official	340:28d1f895c6fe	209	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	210	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	211	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	212	/**
mbed_official	340:28d1f895c6fe	213	* @brief RCC CRS Status structures definition
mbed_official	340:28d1f895c6fe	214	*/
mbed_official	340:28d1f895c6fe	215	typedef enum
mbed_official	340:28d1f895c6fe	216	{
mbed_official	340:28d1f895c6fe	217	RCC_CRS_NONE = 0x00,
mbed_official	340:28d1f895c6fe	218	RCC_CRS_TIMEOUT = 0x01,
mbed_official	340:28d1f895c6fe	219	RCC_CRS_SYNCOK = 0x02,
mbed_official	340:28d1f895c6fe	220	RCC_CRS_SYNCWARM = 0x04,
mbed_official	340:28d1f895c6fe	221	RCC_CRS_SYNCERR = 0x08,
mbed_official	340:28d1f895c6fe	222	RCC_CRS_SYNCMISS = 0x10,
mbed_official	340:28d1f895c6fe	223	RCC_CRS_TRIMOV = 0x20
mbed_official	340:28d1f895c6fe	224	} RCC_CRSStatusTypeDef;
mbed_official	340:28d1f895c6fe	225
mbed_official	340:28d1f895c6fe	226	/**
mbed_official	340:28d1f895c6fe	227	* @brief RCC_CRS Init structure definition
mbed_official	340:28d1f895c6fe	228	*/
mbed_official	340:28d1f895c6fe	229	typedef struct
mbed_official	340:28d1f895c6fe	230	{
mbed_official	340:28d1f895c6fe	231	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
mbed_official	340:28d1f895c6fe	232	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
mbed_official	340:28d1f895c6fe	233
mbed_official	340:28d1f895c6fe	234	uint32_t Source; /*!< Specifies the SYNC signal source.
mbed_official	340:28d1f895c6fe	235	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
mbed_official	340:28d1f895c6fe	236
mbed_official	340:28d1f895c6fe	237	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
mbed_official	340:28d1f895c6fe	238	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
mbed_official	340:28d1f895c6fe	239
mbed_official	340:28d1f895c6fe	240	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
mbed_official	340:28d1f895c6fe	241	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
mbed_official	340:28d1f895c6fe	242	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
mbed_official	340:28d1f895c6fe	243
mbed_official	340:28d1f895c6fe	244	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
mbed_official	340:28d1f895c6fe	245	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
mbed_official	340:28d1f895c6fe	246
mbed_official	340:28d1f895c6fe	247	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
mbed_official	340:28d1f895c6fe	248	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
mbed_official	340:28d1f895c6fe	249
mbed_official	340:28d1f895c6fe	250	}RCC_CRSInitTypeDef;
mbed_official	340:28d1f895c6fe	251
mbed_official	340:28d1f895c6fe	252	/**
mbed_official	340:28d1f895c6fe	253	* @brief RCC_CRS Synchronization structure definition
mbed_official	340:28d1f895c6fe	254	*/
mbed_official	340:28d1f895c6fe	255	typedef struct
mbed_official	340:28d1f895c6fe	256	{
mbed_official	340:28d1f895c6fe	257	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
mbed_official	340:28d1f895c6fe	258	This parameter must be a number between 0 and 0xFFFF*/
mbed_official	340:28d1f895c6fe	259
mbed_official	340:28d1f895c6fe	260	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
mbed_official	340:28d1f895c6fe	261	This parameter must be a number between 0 and 0x3F */
mbed_official	340:28d1f895c6fe	262
mbed_official	340:28d1f895c6fe	263	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
mbed_official	340:28d1f895c6fe	264	value latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	265	This parameter must be a number between 0 and 0xFFFF */
mbed_official	340:28d1f895c6fe	266
mbed_official	340:28d1f895c6fe	267	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
mbed_official	340:28d1f895c6fe	268	frequency error counter latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	269	It shows whether the actual frequency is below or above the target.
mbed_official	340:28d1f895c6fe	270	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
mbed_official	340:28d1f895c6fe	271
mbed_official	340:28d1f895c6fe	272	}RCC_CRSSynchroInfoTypeDef;
mbed_official	340:28d1f895c6fe	273
mbed_official	340:28d1f895c6fe	274	#endif /* STM32F042x6 \|\| */
mbed_official	340:28d1f895c6fe	275	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	276	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	277
mbed_official	340:28d1f895c6fe	278	/**
mbed_official	340:28d1f895c6fe	279	* @}
mbed_official	340:28d1f895c6fe	280	*/
mbed_official	340:28d1f895c6fe	281
mbed_official	340:28d1f895c6fe	282	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	283
mbed_official	340:28d1f895c6fe	284	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	340:28d1f895c6fe	285	* @{
mbed_official	340:28d1f895c6fe	286	*/
mbed_official	340:28d1f895c6fe	287
mbed_official	340:28d1f895c6fe	288	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
mbed_official	340:28d1f895c6fe	289	* @{
mbed_official	340:28d1f895c6fe	290	*/
mbed_official	340:28d1f895c6fe	291	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
mbed_official	340:28d1f895c6fe	292	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	293	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	294	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	295
mbed_official	340:28d1f895c6fe	296	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	297	RCC_PERIPHCLK_RTC))
mbed_official	340:28d1f895c6fe	298	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx */
mbed_official	340:28d1f895c6fe	299
mbed_official	340:28d1f895c6fe	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	301	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	302	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	303	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	304	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	305	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	306
mbed_official	340:28d1f895c6fe	307	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	308	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
mbed_official	340:28d1f895c6fe	309	RCC_PERIPHCLK_USB))
mbed_official	340:28d1f895c6fe	310	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	311
mbed_official	340:28d1f895c6fe	312	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	313	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	314	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	315	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	316	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	317
mbed_official	340:28d1f895c6fe	318	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	319	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
mbed_official	340:28d1f895c6fe	320	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	321
mbed_official	340:28d1f895c6fe	322	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	323	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	324	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	326	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	327	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	328
mbed_official	340:28d1f895c6fe	329	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	330	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	331	RCC_PERIPHCLK_RTC))
mbed_official	340:28d1f895c6fe	332	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	333
mbed_official	340:28d1f895c6fe	334	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	335	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	336	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	337	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	338	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	339	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	340	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	341
mbed_official	340:28d1f895c6fe	342	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	343	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	344	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
mbed_official	340:28d1f895c6fe	345	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	346
mbed_official	340:28d1f895c6fe	347	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	348	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	349	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	350	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	351	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	352	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	353	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
mbed_official	340:28d1f895c6fe	354
mbed_official	340:28d1f895c6fe	355	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	356	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	357	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
mbed_official	340:28d1f895c6fe	358	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	359
mbed_official	340:28d1f895c6fe	360	/**
mbed_official	340:28d1f895c6fe	361	* @}
mbed_official	340:28d1f895c6fe	362	*/
mbed_official	340:28d1f895c6fe	363
mbed_official	340:28d1f895c6fe	364	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
mbed_official	340:28d1f895c6fe	365	* @{
mbed_official	340:28d1f895c6fe	366	*/
mbed_official	340:28d1f895c6fe	367
mbed_official	340:28d1f895c6fe	368	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
mbed_official	340:28d1f895c6fe	369
mbed_official	340:28d1f895c6fe	370	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	340:28d1f895c6fe	371
mbed_official	340:28d1f895c6fe	372	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	373	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	374	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	375	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	376	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	377	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	378	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	340:28d1f895c6fe	379	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	380	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	340:28d1f895c6fe	381
mbed_official	340:28d1f895c6fe	382	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx */
mbed_official	340:28d1f895c6fe	383
mbed_official	340:28d1f895c6fe	384	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	385
mbed_official	340:28d1f895c6fe	386	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	387	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	388	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	389	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	390	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	391	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	392	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	393	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	340:28d1f895c6fe	394
mbed_official	340:28d1f895c6fe	395	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	396
mbed_official	340:28d1f895c6fe	397	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	398	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	399	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	400
mbed_official	340:28d1f895c6fe	401	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
mbed_official	340:28d1f895c6fe	402	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	340:28d1f895c6fe	403
mbed_official	340:28d1f895c6fe	404	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	405	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	406	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	407	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	408	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	409	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	410	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	340:28d1f895c6fe	411	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	412	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
mbed_official	340:28d1f895c6fe	413	((SOURCE) == RCC_MCOSOURCE_HSI48))
mbed_official	340:28d1f895c6fe	414
mbed_official	340:28d1f895c6fe	415	#define RCC_IT_HSI48 ((uint8_t)0x40)
mbed_official	340:28d1f895c6fe	416
mbed_official	340:28d1f895c6fe	417	/* Flags in the CR2 register */
mbed_official	340:28d1f895c6fe	418	#define RCC_CR2_HSI48RDY_BitNumber 16
mbed_official	340:28d1f895c6fe	419
mbed_official	340:28d1f895c6fe	420	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
mbed_official	340:28d1f895c6fe	421
mbed_official	340:28d1f895c6fe	422	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	423	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	424	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	425	/**
mbed_official	340:28d1f895c6fe	426	* @}
mbed_official	340:28d1f895c6fe	427	*/
mbed_official	340:28d1f895c6fe	428
mbed_official	340:28d1f895c6fe	429	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	430
mbed_official	340:28d1f895c6fe	431	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
mbed_official	340:28d1f895c6fe	432	* @{
mbed_official	340:28d1f895c6fe	433	*/
mbed_official	340:28d1f895c6fe	434	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
mbed_official	340:28d1f895c6fe	435	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
mbed_official	340:28d1f895c6fe	436
mbed_official	340:28d1f895c6fe	437	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
mbed_official	340:28d1f895c6fe	438	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	340:28d1f895c6fe	439	/**
mbed_official	340:28d1f895c6fe	440	* @}
mbed_official	340:28d1f895c6fe	441	*/
mbed_official	340:28d1f895c6fe	442
mbed_official	340:28d1f895c6fe	443	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	444
mbed_official	340:28d1f895c6fe	445	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	446	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	447
mbed_official	340:28d1f895c6fe	448	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
mbed_official	340:28d1f895c6fe	449	* @{
mbed_official	340:28d1f895c6fe	450	*/
mbed_official	340:28d1f895c6fe	451	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
mbed_official	340:28d1f895c6fe	452	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
mbed_official	340:28d1f895c6fe	453	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
mbed_official	340:28d1f895c6fe	454	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
mbed_official	340:28d1f895c6fe	455
mbed_official	340:28d1f895c6fe	456	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
mbed_official	340:28d1f895c6fe	457	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	458	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	459	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
mbed_official	340:28d1f895c6fe	460	/**
mbed_official	340:28d1f895c6fe	461	* @}
mbed_official	340:28d1f895c6fe	462	*/
mbed_official	340:28d1f895c6fe	463
mbed_official	340:28d1f895c6fe	464	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	465	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	466
mbed_official	340:28d1f895c6fe	467	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	468
mbed_official	340:28d1f895c6fe	469	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
mbed_official	340:28d1f895c6fe	470	* @{
mbed_official	340:28d1f895c6fe	471	*/
mbed_official	340:28d1f895c6fe	472	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
mbed_official	340:28d1f895c6fe	473	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
mbed_official	340:28d1f895c6fe	474	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
mbed_official	340:28d1f895c6fe	475	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
mbed_official	340:28d1f895c6fe	476
mbed_official	340:28d1f895c6fe	477	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
mbed_official	340:28d1f895c6fe	478	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	479	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	480	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
mbed_official	340:28d1f895c6fe	481	/**
mbed_official	340:28d1f895c6fe	482	* @}
mbed_official	340:28d1f895c6fe	483	*/
mbed_official	340:28d1f895c6fe	484
mbed_official	340:28d1f895c6fe	485	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	486
mbed_official	340:28d1f895c6fe	487
mbed_official	340:28d1f895c6fe	488	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	489	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	490	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	491	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	492
mbed_official	340:28d1f895c6fe	493	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
mbed_official	340:28d1f895c6fe	494	* @{
mbed_official	340:28d1f895c6fe	495	*/
mbed_official	340:28d1f895c6fe	496	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
mbed_official	340:28d1f895c6fe	497	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
mbed_official	340:28d1f895c6fe	498
mbed_official	340:28d1f895c6fe	499	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	500	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	340:28d1f895c6fe	501	/**
mbed_official	340:28d1f895c6fe	502	* @}
mbed_official	340:28d1f895c6fe	503	*/
mbed_official	340:28d1f895c6fe	504
mbed_official	340:28d1f895c6fe	505	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	506	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	507	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	508	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	509
mbed_official	340:28d1f895c6fe	510	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	511	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	512	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	513
mbed_official	340:28d1f895c6fe	514	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
mbed_official	340:28d1f895c6fe	515	* @{
mbed_official	340:28d1f895c6fe	516	*/
mbed_official	340:28d1f895c6fe	517	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	340:28d1f895c6fe	518	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
mbed_official	340:28d1f895c6fe	519
mbed_official	340:28d1f895c6fe	520	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	521	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
mbed_official	340:28d1f895c6fe	522	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	340:28d1f895c6fe	523	/**
mbed_official	340:28d1f895c6fe	524	* @}
mbed_official	340:28d1f895c6fe	525	*/
mbed_official	340:28d1f895c6fe	526
mbed_official	340:28d1f895c6fe	527	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
mbed_official	340:28d1f895c6fe	528	* @{
mbed_official	340:28d1f895c6fe	529	*/
mbed_official	340:28d1f895c6fe	530	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
mbed_official	340:28d1f895c6fe	531
mbed_official	340:28d1f895c6fe	532	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	533	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	534	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
mbed_official	340:28d1f895c6fe	535	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
mbed_official	340:28d1f895c6fe	536
mbed_official	340:28d1f895c6fe	537	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
mbed_official	340:28d1f895c6fe	538
mbed_official	340:28d1f895c6fe	539	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	340:28d1f895c6fe	540	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	340:28d1f895c6fe	541	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
mbed_official	340:28d1f895c6fe	542	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
mbed_official	340:28d1f895c6fe	543	/**
mbed_official	340:28d1f895c6fe	544	* @}
mbed_official	340:28d1f895c6fe	545	*/
mbed_official	340:28d1f895c6fe	546
mbed_official	340:28d1f895c6fe	547	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	340:28d1f895c6fe	548	* @{
mbed_official	340:28d1f895c6fe	549	*/
mbed_official	340:28d1f895c6fe	550	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	551	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	552
mbed_official	340:28d1f895c6fe	553	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
mbed_official	340:28d1f895c6fe	554	/**
mbed_official	340:28d1f895c6fe	555	* @}
mbed_official	340:28d1f895c6fe	556	*/
mbed_official	340:28d1f895c6fe	557
mbed_official	340:28d1f895c6fe	558	#else
mbed_official	340:28d1f895c6fe	559	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
mbed_official	340:28d1f895c6fe	560	* @{
mbed_official	340:28d1f895c6fe	561	*/
mbed_official	340:28d1f895c6fe	562	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
mbed_official	340:28d1f895c6fe	563
mbed_official	340:28d1f895c6fe	564	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	565	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	340:28d1f895c6fe	566	/**
mbed_official	340:28d1f895c6fe	567	* @}
mbed_official	340:28d1f895c6fe	568	*/
mbed_official	340:28d1f895c6fe	569
mbed_official	340:28d1f895c6fe	570	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
mbed_official	340:28d1f895c6fe	571	* @{
mbed_official	340:28d1f895c6fe	572	*/
mbed_official	340:28d1f895c6fe	573	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	574	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	575	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	340:28d1f895c6fe	576
mbed_official	340:28d1f895c6fe	577	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	340:28d1f895c6fe	578	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	340:28d1f895c6fe	579	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
mbed_official	340:28d1f895c6fe	580	/**
mbed_official	340:28d1f895c6fe	581	* @}
mbed_official	340:28d1f895c6fe	582	*/
mbed_official	340:28d1f895c6fe	583
mbed_official	340:28d1f895c6fe	584	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	340:28d1f895c6fe	585	* @{
mbed_official	340:28d1f895c6fe	586	*/
mbed_official	340:28d1f895c6fe	587	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	588
mbed_official	340:28d1f895c6fe	589	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
mbed_official	340:28d1f895c6fe	590	/**
mbed_official	340:28d1f895c6fe	591	* @}
mbed_official	340:28d1f895c6fe	592	*/
mbed_official	340:28d1f895c6fe	593
mbed_official	340:28d1f895c6fe	594	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	595	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	596	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	597
mbed_official	340:28d1f895c6fe	598
mbed_official	340:28d1f895c6fe	599	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
mbed_official	340:28d1f895c6fe	600	* @{
mbed_official	340:28d1f895c6fe	601	*/
mbed_official	340:28d1f895c6fe	602
mbed_official	340:28d1f895c6fe	603	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	604
mbed_official	340:28d1f895c6fe	605	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	606
mbed_official	340:28d1f895c6fe	607	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
mbed_official	340:28d1f895c6fe	608
mbed_official	340:28d1f895c6fe	609	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	610
mbed_official	340:28d1f895c6fe	611	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	612	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| \
mbed_official	340:28d1f895c6fe	613	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	614	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	615
mbed_official	340:28d1f895c6fe	616	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	617	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
mbed_official	340:28d1f895c6fe	618	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
mbed_official	340:28d1f895c6fe	619	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
mbed_official	340:28d1f895c6fe	620	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
mbed_official	340:28d1f895c6fe	621	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
mbed_official	340:28d1f895c6fe	622	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
mbed_official	340:28d1f895c6fe	623	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
mbed_official	340:28d1f895c6fe	624
mbed_official	340:28d1f895c6fe	625	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	626	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	627	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
mbed_official	340:28d1f895c6fe	628	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
mbed_official	340:28d1f895c6fe	629
mbed_official	340:28d1f895c6fe	630	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	631	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	632	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	633
mbed_official	340:28d1f895c6fe	634	/**
mbed_official	340:28d1f895c6fe	635	* @}
mbed_official	340:28d1f895c6fe	636	*/
mbed_official	340:28d1f895c6fe	637
mbed_official	340:28d1f895c6fe	638	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	639	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	640	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	641
mbed_official	340:28d1f895c6fe	642	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
mbed_official	340:28d1f895c6fe	643	* @{
mbed_official	340:28d1f895c6fe	644	*/
mbed_official	340:28d1f895c6fe	645	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
mbed_official	340:28d1f895c6fe	646	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
mbed_official	340:28d1f895c6fe	647	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
mbed_official	340:28d1f895c6fe	648
mbed_official	340:28d1f895c6fe	649	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
mbed_official	340:28d1f895c6fe	650	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	651	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
mbed_official	340:28d1f895c6fe	652	/**
mbed_official	340:28d1f895c6fe	653	* @}
mbed_official	340:28d1f895c6fe	654	*/
mbed_official	340:28d1f895c6fe	655
mbed_official	340:28d1f895c6fe	656	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
mbed_official	340:28d1f895c6fe	657	* @{
mbed_official	340:28d1f895c6fe	658	*/
mbed_official	340:28d1f895c6fe	659	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
mbed_official	340:28d1f895c6fe	660	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
mbed_official	340:28d1f895c6fe	661	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
mbed_official	340:28d1f895c6fe	662	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
mbed_official	340:28d1f895c6fe	663	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
mbed_official	340:28d1f895c6fe	664	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
mbed_official	340:28d1f895c6fe	665	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
mbed_official	340:28d1f895c6fe	666	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
mbed_official	340:28d1f895c6fe	667
mbed_official	340:28d1f895c6fe	668	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	669	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	670	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
mbed_official	340:28d1f895c6fe	671	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
mbed_official	340:28d1f895c6fe	672	/**
mbed_official	340:28d1f895c6fe	673	* @}
mbed_official	340:28d1f895c6fe	674	*/
mbed_official	340:28d1f895c6fe	675
mbed_official	340:28d1f895c6fe	676	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
mbed_official	340:28d1f895c6fe	677	* @{
mbed_official	340:28d1f895c6fe	678	*/
mbed_official	340:28d1f895c6fe	679	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
mbed_official	340:28d1f895c6fe	680	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
mbed_official	340:28d1f895c6fe	681
mbed_official	340:28d1f895c6fe	682	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
mbed_official	340:28d1f895c6fe	683	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
mbed_official	340:28d1f895c6fe	684	/**
mbed_official	340:28d1f895c6fe	685	* @}
mbed_official	340:28d1f895c6fe	686	*/
mbed_official	340:28d1f895c6fe	687
mbed_official	340:28d1f895c6fe	688	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
mbed_official	340:28d1f895c6fe	689	* @{
mbed_official	340:28d1f895c6fe	690	*/
mbed_official	340:28d1f895c6fe	691	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
mbed_official	340:28d1f895c6fe	692	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
mbed_official	340:28d1f895c6fe	693
mbed_official	340:28d1f895c6fe	694	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
mbed_official	340:28d1f895c6fe	695	/**
mbed_official	340:28d1f895c6fe	696	* @}
mbed_official	340:28d1f895c6fe	697	*/
mbed_official	340:28d1f895c6fe	698
mbed_official	340:28d1f895c6fe	699	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
mbed_official	340:28d1f895c6fe	700	* @{
mbed_official	340:28d1f895c6fe	701	*/
mbed_official	340:28d1f895c6fe	702	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
mbed_official	340:28d1f895c6fe	703
mbed_official	340:28d1f895c6fe	704	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
mbed_official	340:28d1f895c6fe	705	/**
mbed_official	340:28d1f895c6fe	706	* @}
mbed_official	340:28d1f895c6fe	707	*/
mbed_official	340:28d1f895c6fe	708
mbed_official	340:28d1f895c6fe	709	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
mbed_official	340:28d1f895c6fe	710	* @{
mbed_official	340:28d1f895c6fe	711	*/
mbed_official	340:28d1f895c6fe	712	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
mbed_official	340:28d1f895c6fe	713	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
mbed_official	340:28d1f895c6fe	714	corresponds to a higher output frequency */
mbed_official	340:28d1f895c6fe	715
mbed_official	340:28d1f895c6fe	716	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
mbed_official	340:28d1f895c6fe	717	/**
mbed_official	340:28d1f895c6fe	718	* @}
mbed_official	340:28d1f895c6fe	719	*/
mbed_official	340:28d1f895c6fe	720
mbed_official	340:28d1f895c6fe	721	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
mbed_official	340:28d1f895c6fe	722	* @{
mbed_official	340:28d1f895c6fe	723	*/
mbed_official	340:28d1f895c6fe	724	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
mbed_official	340:28d1f895c6fe	725	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
mbed_official	340:28d1f895c6fe	726
mbed_official	340:28d1f895c6fe	727	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
mbed_official	340:28d1f895c6fe	728	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
mbed_official	340:28d1f895c6fe	729	/**
mbed_official	340:28d1f895c6fe	730	* @}
mbed_official	340:28d1f895c6fe	731	*/
mbed_official	340:28d1f895c6fe	732
mbed_official	340:28d1f895c6fe	733	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
mbed_official	340:28d1f895c6fe	734	* @{
mbed_official	340:28d1f895c6fe	735	*/
mbed_official	340:28d1f895c6fe	736	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
mbed_official	340:28d1f895c6fe	737	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
mbed_official	340:28d1f895c6fe	738	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
mbed_official	340:28d1f895c6fe	739	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
mbed_official	340:28d1f895c6fe	740	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	741	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	742	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	743
mbed_official	340:28d1f895c6fe	744	/**
mbed_official	340:28d1f895c6fe	745	* @}
mbed_official	340:28d1f895c6fe	746	*/
mbed_official	340:28d1f895c6fe	747
mbed_official	340:28d1f895c6fe	748	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
mbed_official	340:28d1f895c6fe	749	* @{
mbed_official	340:28d1f895c6fe	750	*/
mbed_official	340:28d1f895c6fe	751	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
mbed_official	340:28d1f895c6fe	752	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
mbed_official	340:28d1f895c6fe	753	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
mbed_official	340:28d1f895c6fe	754	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
mbed_official	340:28d1f895c6fe	755	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	756	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	757	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	758
mbed_official	340:28d1f895c6fe	759	/**
mbed_official	340:28d1f895c6fe	760	* @}
mbed_official	340:28d1f895c6fe	761	*/
mbed_official	340:28d1f895c6fe	762
mbed_official	340:28d1f895c6fe	763	/**
mbed_official	340:28d1f895c6fe	764	* @}
mbed_official	340:28d1f895c6fe	765	*/
mbed_official	340:28d1f895c6fe	766
mbed_official	340:28d1f895c6fe	767	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	768	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	769	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	770
mbed_official	340:28d1f895c6fe	771	/* Exported macros ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	772	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official	340:28d1f895c6fe	773	* @{
mbed_official	340:28d1f895c6fe	774	*/
mbed_official	340:28d1f895c6fe	775
mbed_official	340:28d1f895c6fe	776	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
mbed_official	340:28d1f895c6fe	777	* @brief Enables or disables the AHB1 peripheral clock.
mbed_official	340:28d1f895c6fe	778	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	779	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	780	* using it.
mbed_official	340:28d1f895c6fe	781	* @{
mbed_official	340:28d1f895c6fe	782	*/
mbed_official	340:28d1f895c6fe	783	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	784	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	785	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	786	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	787
mbed_official	340:28d1f895c6fe	788	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
mbed_official	340:28d1f895c6fe	789
mbed_official	340:28d1f895c6fe	790	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
mbed_official	340:28d1f895c6fe	791
mbed_official	340:28d1f895c6fe	792	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	793	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	794	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|[ */
mbed_official	340:28d1f895c6fe	795	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	796
mbed_official	340:28d1f895c6fe	797	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	798	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	799
mbed_official	340:28d1f895c6fe	800	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	340:28d1f895c6fe	801
mbed_official	340:28d1f895c6fe	802	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	340:28d1f895c6fe	803
mbed_official	340:28d1f895c6fe	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	805	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	806
mbed_official	340:28d1f895c6fe	807	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	808	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	809	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	810	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	811
mbed_official	340:28d1f895c6fe	812	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
mbed_official	340:28d1f895c6fe	813
mbed_official	340:28d1f895c6fe	814	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
mbed_official	340:28d1f895c6fe	815
mbed_official	340:28d1f895c6fe	816	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	817	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	818	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	819	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	820
mbed_official	340:28d1f895c6fe	821	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	822
mbed_official	340:28d1f895c6fe	823	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	340:28d1f895c6fe	824
mbed_official	340:28d1f895c6fe	825	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	340:28d1f895c6fe	826
mbed_official	340:28d1f895c6fe	827	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	828
mbed_official	340:28d1f895c6fe	829	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	340:28d1f895c6fe	830	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	831	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	832	* using it.
mbed_official	340:28d1f895c6fe	833	*/
mbed_official	340:28d1f895c6fe	834	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	835	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	836	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	837	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	838	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	839
mbed_official	340:28d1f895c6fe	840	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	340:28d1f895c6fe	841	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	340:28d1f895c6fe	842
mbed_official	340:28d1f895c6fe	843	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	340:28d1f895c6fe	844	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	340:28d1f895c6fe	845
mbed_official	340:28d1f895c6fe	846	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	847	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	848	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	849	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	850
mbed_official	340:28d1f895c6fe	851	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	852	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	853	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	854	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	855	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	856
mbed_official	340:28d1f895c6fe	857	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	340:28d1f895c6fe	858
mbed_official	340:28d1f895c6fe	859	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	340:28d1f895c6fe	860
mbed_official	340:28d1f895c6fe	861	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	862	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	863	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	864	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	865	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	866
mbed_official	340:28d1f895c6fe	867	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	868	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	869	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	870	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	871
mbed_official	340:28d1f895c6fe	872	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	340:28d1f895c6fe	873	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	340:28d1f895c6fe	874
mbed_official	340:28d1f895c6fe	875	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	340:28d1f895c6fe	876	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	340:28d1f895c6fe	877
mbed_official	340:28d1f895c6fe	878	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	879	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	880	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	881	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	882
mbed_official	340:28d1f895c6fe	883	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	884	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	885	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	886
mbed_official	340:28d1f895c6fe	887	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	340:28d1f895c6fe	888
mbed_official	340:28d1f895c6fe	889	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	340:28d1f895c6fe	890
mbed_official	340:28d1f895c6fe	891	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	892	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	893	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	894
mbed_official	340:28d1f895c6fe	895	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	896	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	897	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	898	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	899
mbed_official	340:28d1f895c6fe	900	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
mbed_official	340:28d1f895c6fe	901
mbed_official	340:28d1f895c6fe	902	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	340:28d1f895c6fe	903
mbed_official	340:28d1f895c6fe	904	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	905	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	906	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	907	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	908
mbed_official	340:28d1f895c6fe	909	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	910	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	911
mbed_official	340:28d1f895c6fe	912	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	340:28d1f895c6fe	913	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
mbed_official	340:28d1f895c6fe	914	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
mbed_official	340:28d1f895c6fe	915
mbed_official	340:28d1f895c6fe	916	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	340:28d1f895c6fe	917	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	340:28d1f895c6fe	918	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
mbed_official	340:28d1f895c6fe	919
mbed_official	340:28d1f895c6fe	920	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	921	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	922
mbed_official	340:28d1f895c6fe	923	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	924	defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	925
mbed_official	340:28d1f895c6fe	926	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	340:28d1f895c6fe	927
mbed_official	340:28d1f895c6fe	928	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	340:28d1f895c6fe	929
mbed_official	340:28d1f895c6fe	930	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	931	/* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	932
mbed_official	340:28d1f895c6fe	933	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
mbed_official	340:28d1f895c6fe	934	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	935
mbed_official	340:28d1f895c6fe	936	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
mbed_official	340:28d1f895c6fe	937	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
mbed_official	340:28d1f895c6fe	938
mbed_official	340:28d1f895c6fe	939	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	940	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	941
mbed_official	340:28d1f895c6fe	942	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	943	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	944	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	945
mbed_official	340:28d1f895c6fe	946	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
mbed_official	340:28d1f895c6fe	947
mbed_official	340:28d1f895c6fe	948	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
mbed_official	340:28d1f895c6fe	949
mbed_official	340:28d1f895c6fe	950	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	951	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	952	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	953
mbed_official	340:28d1f895c6fe	954	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	955
mbed_official	340:28d1f895c6fe	956	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
mbed_official	340:28d1f895c6fe	957
mbed_official	340:28d1f895c6fe	958	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
mbed_official	340:28d1f895c6fe	959
mbed_official	340:28d1f895c6fe	960	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	961
mbed_official	340:28d1f895c6fe	962	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	340:28d1f895c6fe	963	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	964	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	965	* using it.
mbed_official	340:28d1f895c6fe	966	*/
mbed_official	340:28d1f895c6fe	967	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	968	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	969	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	970	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	971
mbed_official	340:28d1f895c6fe	972	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
mbed_official	340:28d1f895c6fe	973
mbed_official	340:28d1f895c6fe	974	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
mbed_official	340:28d1f895c6fe	975
mbed_official	340:28d1f895c6fe	976	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	977	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	978	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	979	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	980
mbed_official	340:28d1f895c6fe	981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	982
mbed_official	340:28d1f895c6fe	983	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
mbed_official	340:28d1f895c6fe	984	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
mbed_official	340:28d1f895c6fe	985	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
mbed_official	340:28d1f895c6fe	986
mbed_official	340:28d1f895c6fe	987	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	340:28d1f895c6fe	988	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
mbed_official	340:28d1f895c6fe	989	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
mbed_official	340:28d1f895c6fe	990
mbed_official	340:28d1f895c6fe	991	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	992
mbed_official	340:28d1f895c6fe	993	/**
mbed_official	340:28d1f895c6fe	994	* @}
mbed_official	340:28d1f895c6fe	995	*/
mbed_official	340:28d1f895c6fe	996
mbed_official	340:28d1f895c6fe	997
mbed_official	340:28d1f895c6fe	998	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
mbed_official	340:28d1f895c6fe	999	* @brief Forces or releases peripheral reset.
mbed_official	340:28d1f895c6fe	1000	* @{
mbed_official	340:28d1f895c6fe	1001	*/
mbed_official	340:28d1f895c6fe	1002
mbed_official	340:28d1f895c6fe	1003	/** @brief Force or release AHB peripheral reset.
mbed_official	340:28d1f895c6fe	1004	*/
mbed_official	340:28d1f895c6fe	1005	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	1006	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1007	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1008	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1009
mbed_official	340:28d1f895c6fe	1010	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1011
mbed_official	340:28d1f895c6fe	1012	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1013
mbed_official	340:28d1f895c6fe	1014	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1015	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1016	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1017	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1018
mbed_official	340:28d1f895c6fe	1019	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1020	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1021
mbed_official	340:28d1f895c6fe	1022	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1023
mbed_official	340:28d1f895c6fe	1024	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1025
mbed_official	340:28d1f895c6fe	1026	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1027	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1028
mbed_official	340:28d1f895c6fe	1029	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1030	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1031	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1032	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1033
mbed_official	340:28d1f895c6fe	1034	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1035
mbed_official	340:28d1f895c6fe	1036	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1037
mbed_official	340:28d1f895c6fe	1038	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1039	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1040	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1041	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1042
mbed_official	340:28d1f895c6fe	1043	/** @brief Force or release APB1 peripheral reset.
mbed_official	340:28d1f895c6fe	1044	*/
mbed_official	340:28d1f895c6fe	1045	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	1046	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1047	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1048	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1049	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1050
mbed_official	340:28d1f895c6fe	1051	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	340:28d1f895c6fe	1052	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1053
mbed_official	340:28d1f895c6fe	1054	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	340:28d1f895c6fe	1055	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1056
mbed_official	340:28d1f895c6fe	1057	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1058	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1059	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1060	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1061
mbed_official	340:28d1f895c6fe	1062	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	1063	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1064	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1065	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1066	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1067
mbed_official	340:28d1f895c6fe	1068	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1069
mbed_official	340:28d1f895c6fe	1070	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1071
mbed_official	340:28d1f895c6fe	1072	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	1073	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1074	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1075	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1076	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1077
mbed_official	340:28d1f895c6fe	1078	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	1079	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1080	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1081	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1082
mbed_official	340:28d1f895c6fe	1083	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	340:28d1f895c6fe	1084	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1085
mbed_official	340:28d1f895c6fe	1086	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	340:28d1f895c6fe	1087	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1088
mbed_official	340:28d1f895c6fe	1089	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1090	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1091	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1092	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1093
mbed_official	340:28d1f895c6fe	1094	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1095	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1096	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1097
mbed_official	340:28d1f895c6fe	1098	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1099
mbed_official	340:28d1f895c6fe	1100	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1101
mbed_official	340:28d1f895c6fe	1102	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1103	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1104	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1105
mbed_official	340:28d1f895c6fe	1106	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1107	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1108	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1109	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1110
mbed_official	340:28d1f895c6fe	1111	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1112
mbed_official	340:28d1f895c6fe	1113	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1114
mbed_official	340:28d1f895c6fe	1115	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1116	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1117	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1118	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1119
mbed_official	340:28d1f895c6fe	1120	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1121	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1122
mbed_official	340:28d1f895c6fe	1123	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	340:28d1f895c6fe	1124	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	340:28d1f895c6fe	1125	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1126
mbed_official	340:28d1f895c6fe	1127	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	340:28d1f895c6fe	1128	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	340:28d1f895c6fe	1129	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1130
mbed_official	340:28d1f895c6fe	1131	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1132	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1133
mbed_official	340:28d1f895c6fe	1134	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1135	defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	1136
mbed_official	340:28d1f895c6fe	1137	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1138
mbed_official	340:28d1f895c6fe	1139	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1140
mbed_official	340:28d1f895c6fe	1141	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1142	/* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	1143
mbed_official	340:28d1f895c6fe	1144	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
mbed_official	340:28d1f895c6fe	1145	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1146
mbed_official	340:28d1f895c6fe	1147	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1148
mbed_official	340:28d1f895c6fe	1149	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1150
mbed_official	340:28d1f895c6fe	1151	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	1152	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1153
mbed_official	340:28d1f895c6fe	1154	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1155	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1156	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1157
mbed_official	340:28d1f895c6fe	1158	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1159
mbed_official	340:28d1f895c6fe	1160	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1161
mbed_official	340:28d1f895c6fe	1162	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1163	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1164	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1165
mbed_official	340:28d1f895c6fe	1166	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1167
mbed_official	340:28d1f895c6fe	1168	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1169
mbed_official	340:28d1f895c6fe	1170	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1171
mbed_official	340:28d1f895c6fe	1172	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1173
mbed_official	340:28d1f895c6fe	1174
mbed_official	340:28d1f895c6fe	1175	/** @brief Force or release APB2 peripheral reset.
mbed_official	340:28d1f895c6fe	1176	*/
mbed_official	340:28d1f895c6fe	1177	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1178	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1179	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1180	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1181
mbed_official	340:28d1f895c6fe	1182	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1183
mbed_official	340:28d1f895c6fe	1184	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1185
mbed_official	340:28d1f895c6fe	1186	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1187	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1188	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1189	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1190
mbed_official	340:28d1f895c6fe	1191	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1192
mbed_official	340:28d1f895c6fe	1193	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	340:28d1f895c6fe	1194	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
mbed_official	340:28d1f895c6fe	1195	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1196
mbed_official	340:28d1f895c6fe	1197	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	340:28d1f895c6fe	1198	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
mbed_official	340:28d1f895c6fe	1199	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1200
mbed_official	340:28d1f895c6fe	1201	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1202
mbed_official	340:28d1f895c6fe	1203	/**
mbed_official	340:28d1f895c6fe	1204	* @}
mbed_official	340:28d1f895c6fe	1205	*/
mbed_official	340:28d1f895c6fe	1206
mbed_official	340:28d1f895c6fe	1207	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
mbed_official	340:28d1f895c6fe	1208	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
mbed_official	340:28d1f895c6fe	1209	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1210	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	1211	* you have to select another source of the system clock then stop the HSI14.
mbed_official	340:28d1f895c6fe	1212	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
mbed_official	340:28d1f895c6fe	1213	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
mbed_official	340:28d1f895c6fe	1214	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
mbed_official	340:28d1f895c6fe	1215	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
mbed_official	340:28d1f895c6fe	1216	* clock cycles.
mbed_official	340:28d1f895c6fe	1217	* @{
mbed_official	340:28d1f895c6fe	1218	*/
mbed_official	340:28d1f895c6fe	1219	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1220	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1221	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1222
mbed_official	340:28d1f895c6fe	1223	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1224	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1225
mbed_official	340:28d1f895c6fe	1226	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1227	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1228	* @arg RCC_HSI48_ON: HSI48 enabled
mbed_official	340:28d1f895c6fe	1229	* @arg RCC_HSI48_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1230	*/
mbed_official	340:28d1f895c6fe	1231	#define __HAL_RCC_GET_HSI48_STATE() \
mbed_official	340:28d1f895c6fe	1232	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
mbed_official	340:28d1f895c6fe	1233
mbed_official	340:28d1f895c6fe	1234	#else
mbed_official	340:28d1f895c6fe	1235
mbed_official	340:28d1f895c6fe	1236	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1237	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1238	* @arg RCC_HSI_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1239	*/
mbed_official	340:28d1f895c6fe	1240	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
mbed_official	340:28d1f895c6fe	1241
mbed_official	340:28d1f895c6fe	1242	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1243	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1244	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1245
mbed_official	340:28d1f895c6fe	1246	/**
mbed_official	340:28d1f895c6fe	1247	* @}
mbed_official	340:28d1f895c6fe	1248	*/
mbed_official	340:28d1f895c6fe	1249
mbed_official	340:28d1f895c6fe	1250	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
mbed_official	340:28d1f895c6fe	1251	* @{
mbed_official	340:28d1f895c6fe	1252	*/
mbed_official	340:28d1f895c6fe	1253	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1254	defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	1255
mbed_official	340:28d1f895c6fe	1256	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	340:28d1f895c6fe	1257	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	340:28d1f895c6fe	1258	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1259	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	340:28d1f895c6fe	1260	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1261	*/
mbed_official	340:28d1f895c6fe	1262	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	340:28d1f895c6fe	1263	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
mbed_official	340:28d1f895c6fe	1264
mbed_official	340:28d1f895c6fe	1265	/** @brief Macro to get the USB clock source.
mbed_official	340:28d1f895c6fe	1266	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1267	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	340:28d1f895c6fe	1268	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1269	*/
mbed_official	340:28d1f895c6fe	1270	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
mbed_official	340:28d1f895c6fe	1271
mbed_official	340:28d1f895c6fe	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1273	/* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	1274
mbed_official	340:28d1f895c6fe	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1276	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1277	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1278	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1279
mbed_official	340:28d1f895c6fe	1280	/** @brief Macro to configure the CEC clock.
mbed_official	340:28d1f895c6fe	1281	* @param __CECCLKSource__: specifies the CEC clock source.
mbed_official	340:28d1f895c6fe	1282	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1283	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1284	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1285	*/
mbed_official	340:28d1f895c6fe	1286	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
mbed_official	340:28d1f895c6fe	1287	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
mbed_official	340:28d1f895c6fe	1288
mbed_official	340:28d1f895c6fe	1289	/** @brief Macro to get the HDMI CEC clock source.
mbed_official	340:28d1f895c6fe	1290	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1291	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1292	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1293	*/
mbed_official	340:28d1f895c6fe	1294	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
mbed_official	340:28d1f895c6fe	1295
mbed_official	340:28d1f895c6fe	1296	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1297	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1298	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1299	/* STM32F091xC \|\| defined(STM32F098xx) */
mbed_official	340:28d1f895c6fe	1300
mbed_official	340:28d1f895c6fe	1301	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	1302	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1303	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1304	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1305
mbed_official	340:28d1f895c6fe	1306	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1307	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1308	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1309	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1310	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1311	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1312	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1313	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
mbed_official	340:28d1f895c6fe	1314	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1315	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1316	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1317	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1318	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1319	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1320	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
mbed_official	340:28d1f895c6fe	1321	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
mbed_official	340:28d1f895c6fe	1322	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
mbed_official	340:28d1f895c6fe	1323	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
mbed_official	340:28d1f895c6fe	1324	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
mbed_official	340:28d1f895c6fe	1325	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
mbed_official	340:28d1f895c6fe	1326	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
mbed_official	340:28d1f895c6fe	1327	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
mbed_official	340:28d1f895c6fe	1328	*/
mbed_official	340:28d1f895c6fe	1329	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1330	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
mbed_official	340:28d1f895c6fe	1331	#else
mbed_official	340:28d1f895c6fe	1332
mbed_official	340:28d1f895c6fe	1333	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1334	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1335	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1336	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1337	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1338	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1339	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1340	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1341	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1342	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1343	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1344	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1345	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1346	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
mbed_official	340:28d1f895c6fe	1347	*/
mbed_official	340:28d1f895c6fe	1348	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1349	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
mbed_official	340:28d1f895c6fe	1350
mbed_official	340:28d1f895c6fe	1351	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	1352	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1353	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1354	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1355
mbed_official	340:28d1f895c6fe	1356	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1357	/** @brief Macro to configure the USART3 clock (USART3CLK).
mbed_official	340:28d1f895c6fe	1358	* @param __USART3CLKSource__: specifies the USART3 clock source.
mbed_official	340:28d1f895c6fe	1359	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1360	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1361	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1362	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1363	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1364	*/
mbed_official	340:28d1f895c6fe	1365	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
mbed_official	340:28d1f895c6fe	1366	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
mbed_official	340:28d1f895c6fe	1367
mbed_official	340:28d1f895c6fe	1368	/** @brief Macro to get the USART3 clock source.
mbed_official	340:28d1f895c6fe	1369	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1370	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1371	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1372	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1373	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1374	*/
mbed_official	340:28d1f895c6fe	1375	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
mbed_official	340:28d1f895c6fe	1376
mbed_official	340:28d1f895c6fe	1377	#endif /STM32F091xC \|\| STM32F098xx/
mbed_official	340:28d1f895c6fe	1378	/**
mbed_official	340:28d1f895c6fe	1379	* @}
mbed_official	340:28d1f895c6fe	1380	*/
mbed_official	340:28d1f895c6fe	1381
mbed_official	340:28d1f895c6fe	1382	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1383	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1384	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1385
mbed_official	340:28d1f895c6fe	1386	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
mbed_official	340:28d1f895c6fe	1387	* @{
mbed_official	340:28d1f895c6fe	1388	*/
mbed_official	340:28d1f895c6fe	1389	/* Interrupt & Flag management */
mbed_official	340:28d1f895c6fe	1390
mbed_official	340:28d1f895c6fe	1391	/**
mbed_official	340:28d1f895c6fe	1392	* @brief Enables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	1393	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
mbed_official	340:28d1f895c6fe	1394	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1395	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1396	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1397	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1398	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1399	* @retval None
mbed_official	340:28d1f895c6fe	1400	*/
mbed_official	340:28d1f895c6fe	1401	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1402
mbed_official	340:28d1f895c6fe	1403	/**
mbed_official	340:28d1f895c6fe	1404	* @brief Disables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	1405	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
mbed_official	340:28d1f895c6fe	1406	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1407	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1408	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1409	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1410	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1411	* @retval None
mbed_official	340:28d1f895c6fe	1412	*/
mbed_official	340:28d1f895c6fe	1413	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1414
mbed_official	340:28d1f895c6fe	1415	/** @brief Check the CRS's interrupt has occurred or not.
mbed_official	340:28d1f895c6fe	1416	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
mbed_official	340:28d1f895c6fe	1417	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1418	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1419	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1420	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1421	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1422	* @retval The new state of __INTERRUPT__ (SET or RESET).
mbed_official	340:28d1f895c6fe	1423	*/
mbed_official	340:28d1f895c6fe	1424	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
mbed_official	340:28d1f895c6fe	1425
mbed_official	340:28d1f895c6fe	1426	/** @brief Clear the CRS's interrupt pending bits
mbed_official	340:28d1f895c6fe	1427	* bits to clear the selected interrupt pending bits.
mbed_official	340:28d1f895c6fe	1428	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	340:28d1f895c6fe	1429	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1430	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1431	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1432	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1433	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1434	* @arg RCC_CRS_IT_TRIMOVF
mbed_official	340:28d1f895c6fe	1435	* @arg RCC_CRS_IT_SYNCERR
mbed_official	340:28d1f895c6fe	1436	* @arg RCC_CRS_IT_SYNCMISS
mbed_official	340:28d1f895c6fe	1437	*/
mbed_official	340:28d1f895c6fe	1438	/* CRS IT Error Mask */
mbed_official	340:28d1f895c6fe	1439	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
mbed_official	340:28d1f895c6fe	1440
mbed_official	340:28d1f895c6fe	1441	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	1442	(CRS->ICR \|= (__INTERRUPT__)))
mbed_official	340:28d1f895c6fe	1443
mbed_official	340:28d1f895c6fe	1444	/**
mbed_official	340:28d1f895c6fe	1445	* @brief Checks whether the specified CRS flag is set or not.
mbed_official	340:28d1f895c6fe	1446	* @param _FLAG_: specifies the flag to check.
mbed_official	340:28d1f895c6fe	1447	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1448	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	1449	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	1450	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	1451	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	1452	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	1453	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	1454	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	1455	* @retval The new state of _FLAG_ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1456	*/
mbed_official	340:28d1f895c6fe	1457	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
mbed_official	340:28d1f895c6fe	1458
mbed_official	340:28d1f895c6fe	1459	/**
mbed_official	340:28d1f895c6fe	1460	* @brief Clears the CRS specified FLAG.
mbed_official	340:28d1f895c6fe	1461	* @param _FLAG_: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	1462	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1463	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	1464	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	1465	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	1466	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	1467	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	1468	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	1469	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	1470	* @retval None
mbed_official	340:28d1f895c6fe	1471	*/
mbed_official	340:28d1f895c6fe	1472
mbed_official	340:28d1f895c6fe	1473	/* CRS Flag Error Mask */
mbed_official	340:28d1f895c6fe	1474	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
mbed_official	340:28d1f895c6fe	1475
mbed_official	340:28d1f895c6fe	1476	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	1477	(CRS->ICR \|= (__FLAG__)))
mbed_official	340:28d1f895c6fe	1478
mbed_official	340:28d1f895c6fe	1479	/**
mbed_official	340:28d1f895c6fe	1480	* @}
mbed_official	340:28d1f895c6fe	1481	*/
mbed_official	340:28d1f895c6fe	1482
mbed_official	340:28d1f895c6fe	1483	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
mbed_official	340:28d1f895c6fe	1484	* @{
mbed_official	340:28d1f895c6fe	1485	*/
mbed_official	340:28d1f895c6fe	1486	/**
mbed_official	340:28d1f895c6fe	1487	* @brief Enables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	1488	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	1489	* @retval None
mbed_official	340:28d1f895c6fe	1490	*/
mbed_official	340:28d1f895c6fe	1491	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	1492
mbed_official	340:28d1f895c6fe	1493	/**
mbed_official	340:28d1f895c6fe	1494	* @brief Disables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	1495	* @retval None
mbed_official	340:28d1f895c6fe	1496	*/
mbed_official	340:28d1f895c6fe	1497	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	1498
mbed_official	340:28d1f895c6fe	1499	/**
mbed_official	340:28d1f895c6fe	1500	* @brief Enables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	1501	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	1502	* @retval None
mbed_official	340:28d1f895c6fe	1503	*/
mbed_official	340:28d1f895c6fe	1504	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	1505
mbed_official	340:28d1f895c6fe	1506	/**
mbed_official	340:28d1f895c6fe	1507	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	1508	* @retval None
mbed_official	340:28d1f895c6fe	1509	*/
mbed_official	340:28d1f895c6fe	1510	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	1511
mbed_official	340:28d1f895c6fe	1512	/**
mbed_official	340:28d1f895c6fe	1513	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
mbed_official	340:28d1f895c6fe	1514	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
mbed_official	340:28d1f895c6fe	1515	* of the synchronization source after prescaling. It is then decreased by one in order to
mbed_official	340:28d1f895c6fe	1516	* reach the expected synchronization on the zero value. The formula is the following:
mbed_official	340:28d1f895c6fe	1517	* RELOAD = (fTARGET / fSYNC) -1
mbed_official	340:28d1f895c6fe	1518	* @param _FTARGET_ Target frequency (value in Hz)
mbed_official	340:28d1f895c6fe	1519	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
mbed_official	340:28d1f895c6fe	1520	* @retval None
mbed_official	340:28d1f895c6fe	1521	*/
mbed_official	340:28d1f895c6fe	1522	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
mbed_official	340:28d1f895c6fe	1523
mbed_official	340:28d1f895c6fe	1524	/**
mbed_official	340:28d1f895c6fe	1525	* @}
mbed_official	340:28d1f895c6fe	1526	*/
mbed_official	340:28d1f895c6fe	1527
mbed_official	340:28d1f895c6fe	1528	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1529	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1530	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1531
mbed_official	340:28d1f895c6fe	1532	/**
mbed_official	340:28d1f895c6fe	1533	* @}
mbed_official	340:28d1f895c6fe	1534	*/
mbed_official	340:28d1f895c6fe	1535
mbed_official	340:28d1f895c6fe	1536	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1537	/** @addtogroup RCCEx_Exported_Functions
mbed_official	340:28d1f895c6fe	1538	* @{
mbed_official	340:28d1f895c6fe	1539	*/
mbed_official	340:28d1f895c6fe	1540
mbed_official	340:28d1f895c6fe	1541	/** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	1542	* @{
mbed_official	340:28d1f895c6fe	1543	*/
mbed_official	340:28d1f895c6fe	1544
mbed_official	340:28d1f895c6fe	1545	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	340:28d1f895c6fe	1546	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	340:28d1f895c6fe	1547
mbed_official	340:28d1f895c6fe	1548	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1549	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1550	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1551	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
mbed_official	340:28d1f895c6fe	1552	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
mbed_official	340:28d1f895c6fe	1553	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
mbed_official	340:28d1f895c6fe	1554	RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
mbed_official	340:28d1f895c6fe	1555	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1556	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1557	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1558
mbed_official	340:28d1f895c6fe	1559
mbed_official	340:28d1f895c6fe	1560	/**
mbed_official	340:28d1f895c6fe	1561	* @}
mbed_official	340:28d1f895c6fe	1562	*/
mbed_official	340:28d1f895c6fe	1563
mbed_official	340:28d1f895c6fe	1564	/**
mbed_official	340:28d1f895c6fe	1565	* @}
mbed_official	340:28d1f895c6fe	1566	*/
mbed_official	340:28d1f895c6fe	1567
mbed_official	340:28d1f895c6fe	1568	/**
mbed_official	340:28d1f895c6fe	1569	* @}
mbed_official	340:28d1f895c6fe	1570	*/
mbed_official	340:28d1f895c6fe	1571
mbed_official	340:28d1f895c6fe	1572	/**
mbed_official	340:28d1f895c6fe	1573	* @}
mbed_official	340:28d1f895c6fe	1574	*/
mbed_official	340:28d1f895c6fe	1575
mbed_official	340:28d1f895c6fe	1576	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1577	}
mbed_official	340:28d1f895c6fe	1578	#endif
mbed_official	340:28d1f895c6fe	1579
mbed_official	340:28d1f895c6fe	1580	#endif /* __STM32F0xx_HAL_RCC_EX_H */
mbed_official	340:28d1f895c6fe	1581
mbed_official	340:28d1f895c6fe	1582	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	14 Jan 2015
Imports:	4
Forks:	0
Commits:	446
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc_ex.h@340:28d1f895c6fe, 2014-10-09 (annotated)

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