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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc.c@340:28d1f895c6fe, 2014-10-09 (annotated)

Committer:
mbed_official
Date:
Thu Oct 09 08:15:07 2014 +0100
Revision:
340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602



Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/



HAL: nrf51822 - Few fixes for PWM and Serial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal_rcc.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 340:28d1f895c6fe 5 * @version V1.1.0
mbed_official 340:28d1f895c6fe 6 * @date 03-Oct-2014
mbed_official 340:28d1f895c6fe 7 * @brief RCC HAL module driver.
mbed_official 340:28d1f895c6fe 8 * This file provides firmware functions to manage the following
mbed_official 340:28d1f895c6fe 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official 340:28d1f895c6fe 10 * + Initialization/de-initialization function
mbed_official 340:28d1f895c6fe 11 * + Peripheral Control function
mbed_official 340:28d1f895c6fe 12 *
mbed_official 340:28d1f895c6fe 13 @verbatim
mbed_official 340:28d1f895c6fe 14 ==============================================================================
mbed_official 340:28d1f895c6fe 15 ##### RCC specific features #####
mbed_official 340:28d1f895c6fe 16 ==============================================================================
mbed_official 340:28d1f895c6fe 17 [..]
mbed_official 340:28d1f895c6fe 18 After reset the device is running from Internal High Speed oscillator
mbed_official 340:28d1f895c6fe 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
mbed_official 340:28d1f895c6fe 20 and all peripherals are off except internal SRAM, Flash and JTAG.
mbed_official 340:28d1f895c6fe 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 340:28d1f895c6fe 22 all peripherals mapped on these busses are running at HSI speed.
mbed_official 340:28d1f895c6fe 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official 340:28d1f895c6fe 24 (+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official 340:28d1f895c6fe 25 are assigned to be used for debug purpose.
mbed_official 340:28d1f895c6fe 26
mbed_official 340:28d1f895c6fe 27 [..]
mbed_official 340:28d1f895c6fe 28 Once the device started from reset, the user application has to:
mbed_official 340:28d1f895c6fe 29 (+) Configure the clock source to be used to drive the System clock
mbed_official 340:28d1f895c6fe 30 (if the application needs higher frequency/performance)
mbed_official 340:28d1f895c6fe 31 (+) Configure the System clock frequency and Flash settings
mbed_official 340:28d1f895c6fe 32 (+) Configure the AHB and APB busses prescalers
mbed_official 340:28d1f895c6fe 33 (+) Enable the clock for the peripheral(s) to be used
mbed_official 340:28d1f895c6fe 34 (+) Configure the clock source(s) for peripherals which clocks are not
mbed_official 340:28d1f895c6fe 35 derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
mbed_official 340:28d1f895c6fe 36 @endverbatim
mbed_official 340:28d1f895c6fe 37 ******************************************************************************
mbed_official 340:28d1f895c6fe 38 * @attention
mbed_official 340:28d1f895c6fe 39 *
mbed_official 340:28d1f895c6fe 40 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 41 *
mbed_official 340:28d1f895c6fe 42 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 43 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 44 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 45 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 47 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 48 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 50 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 51 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 52 *
mbed_official 340:28d1f895c6fe 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 63 *
mbed_official 340:28d1f895c6fe 64 ******************************************************************************
mbed_official 340:28d1f895c6fe 65 */
mbed_official 340:28d1f895c6fe 66
mbed_official 340:28d1f895c6fe 67 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 68 #include "stm32f0xx_hal.h"
mbed_official 340:28d1f895c6fe 69
mbed_official 340:28d1f895c6fe 70 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 71 * @{
mbed_official 340:28d1f895c6fe 72 */
mbed_official 340:28d1f895c6fe 73
mbed_official 340:28d1f895c6fe 74 /** @defgroup RCC RCC HAL module driver
mbed_official 340:28d1f895c6fe 75 * @brief RCC HAL module driver
mbed_official 340:28d1f895c6fe 76 * @{
mbed_official 340:28d1f895c6fe 77 */
mbed_official 340:28d1f895c6fe 78
mbed_official 340:28d1f895c6fe 79 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 340:28d1f895c6fe 80
mbed_official 340:28d1f895c6fe 81 /* Private typedef -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 82 /* Private define ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 83 /** @defgroup RCC_Private_Define RCC Private Define
mbed_official 340:28d1f895c6fe 84 * @{
mbed_official 340:28d1f895c6fe 85 */
mbed_official 340:28d1f895c6fe 86 #define RCC_CFGR_HPRE_BITNUMBER 4
mbed_official 340:28d1f895c6fe 87 #define RCC_CFGR_PPRE_BITNUMBER 8
mbed_official 340:28d1f895c6fe 88 /**
mbed_official 340:28d1f895c6fe 89 * @}
mbed_official 340:28d1f895c6fe 90 */
mbed_official 340:28d1f895c6fe 91
mbed_official 340:28d1f895c6fe 92 /* Private macro -------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 93 /** @defgroup RCC_Private_Macros RCC Private Macros
mbed_official 340:28d1f895c6fe 94 * @{
mbed_official 340:28d1f895c6fe 95 */
mbed_official 340:28d1f895c6fe 96 #define __MCO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official 340:28d1f895c6fe 97 #define MCO_GPIO_PORT GPIOA
mbed_official 340:28d1f895c6fe 98 #define MCO_PIN GPIO_PIN_8
mbed_official 340:28d1f895c6fe 99 /**
mbed_official 340:28d1f895c6fe 100 * @}
mbed_official 340:28d1f895c6fe 101 */
mbed_official 340:28d1f895c6fe 102
mbed_official 340:28d1f895c6fe 103 /* Private variables ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 104 /** @defgroup RCC_Private_Variables RCC Private Variables
mbed_official 340:28d1f895c6fe 105 * @{
mbed_official 340:28d1f895c6fe 106 */
mbed_official 340:28d1f895c6fe 107 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 340:28d1f895c6fe 108 /**
mbed_official 340:28d1f895c6fe 109 * @}
mbed_official 340:28d1f895c6fe 110 */
mbed_official 340:28d1f895c6fe 111
mbed_official 340:28d1f895c6fe 112 /* Private function prototypes -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 113 /* Exported functions ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 114
mbed_official 340:28d1f895c6fe 115 /** @defgroup RCC_Exported_Functions RCC Exported Functions
mbed_official 340:28d1f895c6fe 116 * @{
mbed_official 340:28d1f895c6fe 117 */
mbed_official 340:28d1f895c6fe 118
mbed_official 340:28d1f895c6fe 119 /** @defgroup RCC_Exported_Functions_Group1 Initialization/de-initialization function
mbed_official 340:28d1f895c6fe 120 * @brief Initialization and Configuration functions
mbed_official 340:28d1f895c6fe 121 *
mbed_official 340:28d1f895c6fe 122 @verbatim
mbed_official 340:28d1f895c6fe 123 ===============================================================================
mbed_official 340:28d1f895c6fe 124 ##### Initialization and de-initialization function #####
mbed_official 340:28d1f895c6fe 125 ===============================================================================
mbed_official 340:28d1f895c6fe 126 [..]
mbed_official 340:28d1f895c6fe 127 This section provide functions allowing to configure the internal/external oscillators
mbed_official 340:28d1f895c6fe 128 (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK,
mbed_official 340:28d1f895c6fe 129 AHB and APB1).
mbed_official 340:28d1f895c6fe 130
mbed_official 340:28d1f895c6fe 131 [..] Internal/external clock and PLL configuration
mbed_official 340:28d1f895c6fe 132 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
mbed_official 340:28d1f895c6fe 133 the PLL as System clock source.
mbed_official 340:28d1f895c6fe 134 The HSI clock can be used also to clock the USART and I2C peripherals.
mbed_official 340:28d1f895c6fe 135
mbed_official 340:28d1f895c6fe 136 (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
mbed_official 340:28d1f895c6fe 137 the ADC peripheral.
mbed_official 340:28d1f895c6fe 138
mbed_official 340:28d1f895c6fe 139 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
mbed_official 340:28d1f895c6fe 140 clock source.
mbed_official 340:28d1f895c6fe 141
mbed_official 340:28d1f895c6fe 142 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
mbed_official 340:28d1f895c6fe 143 through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official 340:28d1f895c6fe 144
mbed_official 340:28d1f895c6fe 145 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 340:28d1f895c6fe 146
mbed_official 340:28d1f895c6fe 147 (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
mbed_official 340:28d1f895c6fe 148 (++) The first output is used to generate the high speed system clock (up to 48 MHz)
mbed_official 340:28d1f895c6fe 149 (++) The second output is used to generate the clock for the USB FS (48 MHz)
mbed_official 340:28d1f895c6fe 150 (++) The third output may be used to generate the clock for the TIM, I2C and USART
mbed_official 340:28d1f895c6fe 151 peripherals (up to 48 MHz)
mbed_official 340:28d1f895c6fe 152
mbed_official 340:28d1f895c6fe 153 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official 340:28d1f895c6fe 154 and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official 340:28d1f895c6fe 155 clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official 340:28d1f895c6fe 156 is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
mbed_official 340:28d1f895c6fe 157 (Non-Maskable Interrupt) exception vector.
mbed_official 340:28d1f895c6fe 158
mbed_official 340:28d1f895c6fe 159 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
mbed_official 340:28d1f895c6fe 160 clock (divided by 2) output on pin (such as PA8 pin).
mbed_official 340:28d1f895c6fe 161
mbed_official 340:28d1f895c6fe 162 [..] System, AHB and APB busses clocks configuration
mbed_official 340:28d1f895c6fe 163 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official 340:28d1f895c6fe 164 HSE and PLL.
mbed_official 340:28d1f895c6fe 165 The AHB clock (HCLK) is derived from System clock through configurable
mbed_official 340:28d1f895c6fe 166 prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official 340:28d1f895c6fe 167 on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
mbed_official 340:28d1f895c6fe 168 from AHB clock through configurable prescalers and used to clock
mbed_official 340:28d1f895c6fe 169 the peripherals mapped on these busses. You can use
mbed_official 340:28d1f895c6fe 170 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official 340:28d1f895c6fe 171
mbed_official 340:28d1f895c6fe 172 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official 340:28d1f895c6fe 173 (++) The FLASH program/erase clock which is always HSI 8MHz clock.
mbed_official 340:28d1f895c6fe 174 (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
mbed_official 340:28d1f895c6fe 175 (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
mbed_official 340:28d1f895c6fe 176 (++) The I2C clock which can be derived as well from HSI 8MHz clock.
mbed_official 340:28d1f895c6fe 177 (++) The ADC clock which is derived from PLL output.
mbed_official 340:28d1f895c6fe 178 (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
mbed_official 340:28d1f895c6fe 179 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
mbed_official 340:28d1f895c6fe 180 frequency must be higher or equal to the RTC clock frequency.
mbed_official 340:28d1f895c6fe 181 (++) IWDG clock which is always the LSI clock.
mbed_official 340:28d1f895c6fe 182
mbed_official 340:28d1f895c6fe 183 (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
mbed_official 340:28d1f895c6fe 184 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
mbed_official 340:28d1f895c6fe 185 +-----------------------------------------------+
mbed_official 340:28d1f895c6fe 186 | Latency | SYSCLK clock frequency (MHz) |
mbed_official 340:28d1f895c6fe 187 |---------------|-------------------------------|
mbed_official 340:28d1f895c6fe 188 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
mbed_official 340:28d1f895c6fe 189 |---------------|-------------------------------|
mbed_official 340:28d1f895c6fe 190 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
mbed_official 340:28d1f895c6fe 191 +-----------------------------------------------+
mbed_official 340:28d1f895c6fe 192
mbed_official 340:28d1f895c6fe 193 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
mbed_official 340:28d1f895c6fe 194 prefetch is disabled.
mbed_official 340:28d1f895c6fe 195
mbed_official 340:28d1f895c6fe 196 @endverbatim
mbed_official 340:28d1f895c6fe 197 * @{
mbed_official 340:28d1f895c6fe 198 */
mbed_official 340:28d1f895c6fe 199
mbed_official 340:28d1f895c6fe 200 /**
mbed_official 340:28d1f895c6fe 201 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 340:28d1f895c6fe 202 * @note The default reset state of the clock configuration is given below:
mbed_official 340:28d1f895c6fe 203 * - HSI ON and used as system clock source
mbed_official 340:28d1f895c6fe 204 * - HSE and PLL OFF
mbed_official 340:28d1f895c6fe 205 * - AHB, APB1 prescaler set to 1.
mbed_official 340:28d1f895c6fe 206 * - CSS, MCO OFF
mbed_official 340:28d1f895c6fe 207 * - All interrupts disabled
mbed_official 340:28d1f895c6fe 208 * @note This function doesn't modify the configuration of the
mbed_official 340:28d1f895c6fe 209 * - Peripheral clocks
mbed_official 340:28d1f895c6fe 210 * - LSI, LSE and RTC clocks
mbed_official 340:28d1f895c6fe 211 * @retval None
mbed_official 340:28d1f895c6fe 212 */
mbed_official 340:28d1f895c6fe 213 void HAL_RCC_DeInit(void)
mbed_official 340:28d1f895c6fe 214 {
mbed_official 340:28d1f895c6fe 215 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
mbed_official 340:28d1f895c6fe 216 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
mbed_official 340:28d1f895c6fe 217
mbed_official 340:28d1f895c6fe 218 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
mbed_official 340:28d1f895c6fe 219 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
mbed_official 340:28d1f895c6fe 220
mbed_official 340:28d1f895c6fe 221 /* Reset HSEON, CSSON, PLLON bits */
mbed_official 340:28d1f895c6fe 222 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
mbed_official 340:28d1f895c6fe 223
mbed_official 340:28d1f895c6fe 224 /* Reset HSEBYP bit */
mbed_official 340:28d1f895c6fe 225 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official 340:28d1f895c6fe 226
mbed_official 340:28d1f895c6fe 227 /* Reset CFGR register */
mbed_official 340:28d1f895c6fe 228 CLEAR_REG(RCC->CFGR);
mbed_official 340:28d1f895c6fe 229
mbed_official 340:28d1f895c6fe 230 /* Reset CFGR2 register */
mbed_official 340:28d1f895c6fe 231 CLEAR_REG(RCC->CFGR2);
mbed_official 340:28d1f895c6fe 232
mbed_official 340:28d1f895c6fe 233 /* Reset CFGR3 register */
mbed_official 340:28d1f895c6fe 234 CLEAR_REG(RCC->CFGR3);
mbed_official 340:28d1f895c6fe 235
mbed_official 340:28d1f895c6fe 236 /* Disable all interrupts */
mbed_official 340:28d1f895c6fe 237 CLEAR_REG(RCC->CIR);
mbed_official 340:28d1f895c6fe 238 }
mbed_official 340:28d1f895c6fe 239
mbed_official 340:28d1f895c6fe 240 /**
mbed_official 340:28d1f895c6fe 241 * @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official 340:28d1f895c6fe 242 * RCC_OscInitTypeDef.
mbed_official 340:28d1f895c6fe 243 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 340:28d1f895c6fe 244 * contains the configuration information for the RCC Oscillators.
mbed_official 340:28d1f895c6fe 245 * @note The PLL is not disabled when used as system clock.
mbed_official 340:28d1f895c6fe 246 * @retval HAL status
mbed_official 340:28d1f895c6fe 247 */
mbed_official 340:28d1f895c6fe 248 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 340:28d1f895c6fe 249 {
mbed_official 340:28d1f895c6fe 250 /* Note : This function is defined into this file for library reference. */
mbed_official 340:28d1f895c6fe 251 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
mbed_official 340:28d1f895c6fe 252 /* handle the possible oscillators present in STM32F0xx devices */
mbed_official 340:28d1f895c6fe 253
mbed_official 340:28d1f895c6fe 254 /* Return error status as not implemented here */
mbed_official 340:28d1f895c6fe 255 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 256 }
mbed_official 340:28d1f895c6fe 257
mbed_official 340:28d1f895c6fe 258 /**
mbed_official 340:28d1f895c6fe 259 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official 340:28d1f895c6fe 260 * parameters in the RCC_ClkInitStruct.
mbed_official 340:28d1f895c6fe 261 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 340:28d1f895c6fe 262 * contains the configuration information for the RCC peripheral.
mbed_official 340:28d1f895c6fe 263 * @param FLatency: FLASH Latency
mbed_official 340:28d1f895c6fe 264 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 265 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
mbed_official 340:28d1f895c6fe 266 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
mbed_official 340:28d1f895c6fe 267 *
mbed_official 340:28d1f895c6fe 268 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 340:28d1f895c6fe 269 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official 340:28d1f895c6fe 270 *
mbed_official 340:28d1f895c6fe 271 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 340:28d1f895c6fe 272 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 340:28d1f895c6fe 273 * of failure of the HSE used directly or indirectly as system clock
mbed_official 340:28d1f895c6fe 274 * (if the Clock Security System CSS is enabled).
mbed_official 340:28d1f895c6fe 275 *
mbed_official 340:28d1f895c6fe 276 * @note A switch from one clock source to another occurs only if the target
mbed_official 340:28d1f895c6fe 277 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 340:28d1f895c6fe 278 * If a clock source which is not yet ready is selected, the switch will
mbed_official 340:28d1f895c6fe 279 * occur when the clock source will be ready.
mbed_official 340:28d1f895c6fe 280 * @retval HAL status
mbed_official 340:28d1f895c6fe 281 */
mbed_official 340:28d1f895c6fe 282 __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official 340:28d1f895c6fe 283 {
mbed_official 340:28d1f895c6fe 284 /* Note : This function is defined into this file for library reference. */
mbed_official 340:28d1f895c6fe 285 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
mbed_official 340:28d1f895c6fe 286 /* handle the possible oscillators present in STM32F0xx devices */
mbed_official 340:28d1f895c6fe 287
mbed_official 340:28d1f895c6fe 288 /* Return error status as not implemented here */
mbed_official 340:28d1f895c6fe 289 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 290 }
mbed_official 340:28d1f895c6fe 291
mbed_official 340:28d1f895c6fe 292 /**
mbed_official 340:28d1f895c6fe 293 * @}
mbed_official 340:28d1f895c6fe 294 */
mbed_official 340:28d1f895c6fe 295
mbed_official 340:28d1f895c6fe 296 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control function
mbed_official 340:28d1f895c6fe 297 * @brief RCC clocks control functions
mbed_official 340:28d1f895c6fe 298 *
mbed_official 340:28d1f895c6fe 299 @verbatim
mbed_official 340:28d1f895c6fe 300 ===============================================================================
mbed_official 340:28d1f895c6fe 301 ##### Peripheral Control function #####
mbed_official 340:28d1f895c6fe 302 ===============================================================================
mbed_official 340:28d1f895c6fe 303 [..]
mbed_official 340:28d1f895c6fe 304 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 340:28d1f895c6fe 305 frequencies.
mbed_official 340:28d1f895c6fe 306
mbed_official 340:28d1f895c6fe 307 @endverbatim
mbed_official 340:28d1f895c6fe 308 * @{
mbed_official 340:28d1f895c6fe 309 */
mbed_official 340:28d1f895c6fe 310
mbed_official 340:28d1f895c6fe 311 /**
mbed_official 340:28d1f895c6fe 312 * @brief Selects the clock source to output on MCO pin(such as PA8).
mbed_official 340:28d1f895c6fe 313 * @note MCO pin (such as PA8) should be configured in alternate function mode.
mbed_official 340:28d1f895c6fe 314 * @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official 340:28d1f895c6fe 315 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 316 * @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
mbed_official 340:28d1f895c6fe 317 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 340:28d1f895c6fe 318 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 319 * @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
mbed_official 340:28d1f895c6fe 320 * @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
mbed_official 340:28d1f895c6fe 321 * @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
mbed_official 340:28d1f895c6fe 322 * @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
mbed_official 340:28d1f895c6fe 323 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: main PLL clock not divided selected as MCO source (not applicable to STM32F05x devices)
mbed_official 340:28d1f895c6fe 324 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
mbed_official 340:28d1f895c6fe 325 * @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
mbed_official 340:28d1f895c6fe 326 * @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official 340:28d1f895c6fe 327 * This parameter can be one of the following values:
mbed_official 340:28d1f895c6fe 328 * @arg RCC_MCO_NODIV: no division applied to MCO clock
mbed_official 340:28d1f895c6fe 329 * @retval None
mbed_official 340:28d1f895c6fe 330 */
mbed_official 340:28d1f895c6fe 331 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official 340:28d1f895c6fe 332 {
mbed_official 340:28d1f895c6fe 333 GPIO_InitTypeDef gpio;
mbed_official 340:28d1f895c6fe 334 /* Check the parameters */
mbed_official 340:28d1f895c6fe 335 assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official 340:28d1f895c6fe 336 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official 340:28d1f895c6fe 337 /* RCC_MCO */
mbed_official 340:28d1f895c6fe 338 assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
mbed_official 340:28d1f895c6fe 339
mbed_official 340:28d1f895c6fe 340 /* MCO Clock Enable */
mbed_official 340:28d1f895c6fe 341 __MCO_CLK_ENABLE();
mbed_official 340:28d1f895c6fe 342
mbed_official 340:28d1f895c6fe 343 /* Configue the MCO pin in alternate function mode */
mbed_official 340:28d1f895c6fe 344 gpio.Pin = MCO_PIN;
mbed_official 340:28d1f895c6fe 345 gpio.Mode = GPIO_MODE_AF_PP;
mbed_official 340:28d1f895c6fe 346 gpio.Speed = GPIO_SPEED_HIGH;
mbed_official 340:28d1f895c6fe 347 gpio.Pull = GPIO_NOPULL;
mbed_official 340:28d1f895c6fe 348 gpio.Alternate = GPIO_AF0_MCO;
mbed_official 340:28d1f895c6fe 349 HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
mbed_official 340:28d1f895c6fe 350
mbed_official 340:28d1f895c6fe 351 /* Configure the MCO clock source */
mbed_official 340:28d1f895c6fe 352 __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
mbed_official 340:28d1f895c6fe 353 }
mbed_official 340:28d1f895c6fe 354
mbed_official 340:28d1f895c6fe 355 /**
mbed_official 340:28d1f895c6fe 356 * @brief Enables the Clock Security System.
mbed_official 340:28d1f895c6fe 357 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 340:28d1f895c6fe 358 * is automatically disabled and an interrupt is generated to inform the
mbed_official 340:28d1f895c6fe 359 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 340:28d1f895c6fe 360 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 340:28d1f895c6fe 361 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 340:28d1f895c6fe 362 * @retval None
mbed_official 340:28d1f895c6fe 363 */
mbed_official 340:28d1f895c6fe 364 void HAL_RCC_EnableCSS(void)
mbed_official 340:28d1f895c6fe 365 {
mbed_official 340:28d1f895c6fe 366 SET_BIT(RCC->CR, RCC_CR_CSSON);
mbed_official 340:28d1f895c6fe 367 }
mbed_official 340:28d1f895c6fe 368
mbed_official 340:28d1f895c6fe 369 /**
mbed_official 340:28d1f895c6fe 370 * @brief Disables the Clock Security System.
mbed_official 340:28d1f895c6fe 371 * @retval None
mbed_official 340:28d1f895c6fe 372 */
mbed_official 340:28d1f895c6fe 373 void HAL_RCC_DisableCSS(void)
mbed_official 340:28d1f895c6fe 374 {
mbed_official 340:28d1f895c6fe 375 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
mbed_official 340:28d1f895c6fe 376 }
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378 /**
mbed_official 340:28d1f895c6fe 379 * @brief Returns the SYSCLK frequency
mbed_official 340:28d1f895c6fe 380 * @note The system frequency computed by this function is not the real
mbed_official 340:28d1f895c6fe 381 * frequency in the chip. It is calculated based on the predefined
mbed_official 340:28d1f895c6fe 382 * constant and the selected clock source:
mbed_official 340:28d1f895c6fe 383 * @note If SYSCLK source is HSI, function returns a value based on HSI_VALUE(*)
mbed_official 340:28d1f895c6fe 384 * @note If SYSCLK source is HSI48, function returns a value based on HSI48_VALUE(*)
mbed_official 340:28d1f895c6fe 385 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
mbed_official 340:28d1f895c6fe 386 * divided by PREDIV factor(**)
mbed_official 340:28d1f895c6fe 387 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
mbed_official 340:28d1f895c6fe 388 * divided by PREDIV factor(**) or depending on STM32F0xx devices either a value based
mbed_official 340:28d1f895c6fe 389 * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
mbed_official 340:28d1f895c6fe 390 * PLL factor .
mbed_official 340:28d1f895c6fe 391 * @note (*) HSI_VALUE & HSI48_VALUE are constants defined in stm32f0xx_hal_conf.h file
mbed_official 340:28d1f895c6fe 392 * (default values 8 MHz and 48MHz).
mbed_official 340:28d1f895c6fe 393 * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
mbed_official 340:28d1f895c6fe 394 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 340:28d1f895c6fe 395 * frequency of the crystal used. Otherwise, this function may
mbed_official 340:28d1f895c6fe 396 * have wrong result.
mbed_official 340:28d1f895c6fe 397 *
mbed_official 340:28d1f895c6fe 398 * @note The result of this function could be not correct when using fractional
mbed_official 340:28d1f895c6fe 399 * value for HSE crystal.
mbed_official 340:28d1f895c6fe 400 *
mbed_official 340:28d1f895c6fe 401 * @note This function can be used by the user application to compute the
mbed_official 340:28d1f895c6fe 402 * baudrate for the communication peripherals or configure other parameters.
mbed_official 340:28d1f895c6fe 403 *
mbed_official 340:28d1f895c6fe 404 * @note Each time SYSCLK changes, this function must be called to update the
mbed_official 340:28d1f895c6fe 405 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 340:28d1f895c6fe 406 *
mbed_official 340:28d1f895c6fe 407 * @retval SYSCLK frequency
mbed_official 340:28d1f895c6fe 408 */
mbed_official 340:28d1f895c6fe 409 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official 340:28d1f895c6fe 410 {
mbed_official 340:28d1f895c6fe 411 /* Note : This function is defined into this file for library reference. */
mbed_official 340:28d1f895c6fe 412 /* Function content is located into file stm32f0xx_hal_rcc_ex.c to */
mbed_official 340:28d1f895c6fe 413 /* handle the possible oscillators present in STM32F0xx devices */
mbed_official 340:28d1f895c6fe 414
mbed_official 340:28d1f895c6fe 415 /* Return error status as not implemented here */
mbed_official 340:28d1f895c6fe 416 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 417 }
mbed_official 340:28d1f895c6fe 418
mbed_official 340:28d1f895c6fe 419 /**
mbed_official 340:28d1f895c6fe 420 * @brief Returns the HCLK frequency
mbed_official 340:28d1f895c6fe 421 * @note Each time HCLK changes, this function must be called to update the
mbed_official 340:28d1f895c6fe 422 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 340:28d1f895c6fe 423 *
mbed_official 340:28d1f895c6fe 424 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 340:28d1f895c6fe 425 * and updated within this function
mbed_official 340:28d1f895c6fe 426 *
mbed_official 340:28d1f895c6fe 427 * @retval HCLK frequency
mbed_official 340:28d1f895c6fe 428 */
mbed_official 340:28d1f895c6fe 429 uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official 340:28d1f895c6fe 430 {
mbed_official 340:28d1f895c6fe 431 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
mbed_official 340:28d1f895c6fe 432 return SystemCoreClock;
mbed_official 340:28d1f895c6fe 433 }
mbed_official 340:28d1f895c6fe 434
mbed_official 340:28d1f895c6fe 435 /**
mbed_official 340:28d1f895c6fe 436 * @brief Returns the PCLK1 frequency
mbed_official 340:28d1f895c6fe 437 * @note Each time PCLK1 changes, this function must be called to update the
mbed_official 340:28d1f895c6fe 438 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 340:28d1f895c6fe 439 * @retval PCLK1 frequency
mbed_official 340:28d1f895c6fe 440 */
mbed_official 340:28d1f895c6fe 441 uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official 340:28d1f895c6fe 442 {
mbed_official 340:28d1f895c6fe 443 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official 340:28d1f895c6fe 444 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE)>> RCC_CFGR_PPRE_BITNUMBER]);
mbed_official 340:28d1f895c6fe 445 }
mbed_official 340:28d1f895c6fe 446
mbed_official 340:28d1f895c6fe 447 /**
mbed_official 340:28d1f895c6fe 448 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 340:28d1f895c6fe 449 * RCC configuration registers.
mbed_official 340:28d1f895c6fe 450 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 340:28d1f895c6fe 451 * will be configured.
mbed_official 340:28d1f895c6fe 452 * @retval None
mbed_official 340:28d1f895c6fe 453 */
mbed_official 340:28d1f895c6fe 454 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 340:28d1f895c6fe 455 {
mbed_official 340:28d1f895c6fe 456 /* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official 340:28d1f895c6fe 457 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
mbed_official 340:28d1f895c6fe 458
mbed_official 340:28d1f895c6fe 459 /* Get the HSE configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 460 if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official 340:28d1f895c6fe 461 {
mbed_official 340:28d1f895c6fe 462 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official 340:28d1f895c6fe 463 }
mbed_official 340:28d1f895c6fe 464 else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official 340:28d1f895c6fe 465 {
mbed_official 340:28d1f895c6fe 466 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official 340:28d1f895c6fe 467 }
mbed_official 340:28d1f895c6fe 468 else
mbed_official 340:28d1f895c6fe 469 {
mbed_official 340:28d1f895c6fe 470 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official 340:28d1f895c6fe 471 }
mbed_official 340:28d1f895c6fe 472
mbed_official 340:28d1f895c6fe 473 /* Get the HSI configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 474 if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
mbed_official 340:28d1f895c6fe 475 {
mbed_official 340:28d1f895c6fe 476 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official 340:28d1f895c6fe 477 }
mbed_official 340:28d1f895c6fe 478 else
mbed_official 340:28d1f895c6fe 479 {
mbed_official 340:28d1f895c6fe 480 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official 340:28d1f895c6fe 481 }
mbed_official 340:28d1f895c6fe 482
mbed_official 340:28d1f895c6fe 483 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
mbed_official 340:28d1f895c6fe 484
mbed_official 340:28d1f895c6fe 485 /* Get the LSE configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 486 if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official 340:28d1f895c6fe 487 {
mbed_official 340:28d1f895c6fe 488 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official 340:28d1f895c6fe 489 }
mbed_official 340:28d1f895c6fe 490 else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official 340:28d1f895c6fe 491 {
mbed_official 340:28d1f895c6fe 492 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official 340:28d1f895c6fe 493 }
mbed_official 340:28d1f895c6fe 494 else
mbed_official 340:28d1f895c6fe 495 {
mbed_official 340:28d1f895c6fe 496 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official 340:28d1f895c6fe 497 }
mbed_official 340:28d1f895c6fe 498
mbed_official 340:28d1f895c6fe 499 /* Get the LSI configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 500 if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official 340:28d1f895c6fe 501 {
mbed_official 340:28d1f895c6fe 502 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official 340:28d1f895c6fe 503 }
mbed_official 340:28d1f895c6fe 504 else
mbed_official 340:28d1f895c6fe 505 {
mbed_official 340:28d1f895c6fe 506 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official 340:28d1f895c6fe 507 }
mbed_official 340:28d1f895c6fe 508
mbed_official 340:28d1f895c6fe 509 /* Get the PLL configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 510 if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official 340:28d1f895c6fe 511 {
mbed_official 340:28d1f895c6fe 512 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official 340:28d1f895c6fe 513 }
mbed_official 340:28d1f895c6fe 514 else
mbed_official 340:28d1f895c6fe 515 {
mbed_official 340:28d1f895c6fe 516 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official 340:28d1f895c6fe 517 }
mbed_official 340:28d1f895c6fe 518 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
mbed_official 340:28d1f895c6fe 519 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
mbed_official 340:28d1f895c6fe 520 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
mbed_official 340:28d1f895c6fe 521
mbed_official 340:28d1f895c6fe 522 /* Get the HSI14 configuration -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 523 if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
mbed_official 340:28d1f895c6fe 524 {
mbed_official 340:28d1f895c6fe 525 RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
mbed_official 340:28d1f895c6fe 526 }
mbed_official 340:28d1f895c6fe 527 else
mbed_official 340:28d1f895c6fe 528 {
mbed_official 340:28d1f895c6fe 529 RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
mbed_official 340:28d1f895c6fe 530 }
mbed_official 340:28d1f895c6fe 531
mbed_official 340:28d1f895c6fe 532 RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_CR2_HSI14TRIM_BitNumber);
mbed_official 340:28d1f895c6fe 533
mbed_official 340:28d1f895c6fe 534 /* Get the HSI48 configuration if any-----------------------------------------*/
mbed_official 340:28d1f895c6fe 535 RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
mbed_official 340:28d1f895c6fe 536 }
mbed_official 340:28d1f895c6fe 537
mbed_official 340:28d1f895c6fe 538 /**
mbed_official 340:28d1f895c6fe 539 * @brief Get the RCC_ClkInitStruct according to the internal
mbed_official 340:28d1f895c6fe 540 * RCC configuration registers.
mbed_official 340:28d1f895c6fe 541 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official 340:28d1f895c6fe 542 * contains the current clock configuration.
mbed_official 340:28d1f895c6fe 543 * @param pFLatency: Pointer on the Flash Latency.
mbed_official 340:28d1f895c6fe 544 * @retval None
mbed_official 340:28d1f895c6fe 545 */
mbed_official 340:28d1f895c6fe 546 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
mbed_official 340:28d1f895c6fe 547 {
mbed_official 340:28d1f895c6fe 548 /* Set all possible values for the Clock type parameter --------------------*/
mbed_official 340:28d1f895c6fe 549 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
mbed_official 340:28d1f895c6fe 550
mbed_official 340:28d1f895c6fe 551 /* Get the SYSCLK configuration --------------------------------------------*/
mbed_official 340:28d1f895c6fe 552 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official 340:28d1f895c6fe 553
mbed_official 340:28d1f895c6fe 554 /* Get the HCLK configuration ----------------------------------------------*/
mbed_official 340:28d1f895c6fe 555 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official 340:28d1f895c6fe 556
mbed_official 340:28d1f895c6fe 557 /* Get the APB1 configuration ----------------------------------------------*/
mbed_official 340:28d1f895c6fe 558 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
mbed_official 340:28d1f895c6fe 559
mbed_official 340:28d1f895c6fe 560 /* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official 340:28d1f895c6fe 561 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official 340:28d1f895c6fe 562 }
mbed_official 340:28d1f895c6fe 563
mbed_official 340:28d1f895c6fe 564 /**
mbed_official 340:28d1f895c6fe 565 * @brief This function handles the RCC CSS interrupt request.
mbed_official 340:28d1f895c6fe 566 * @note This API should be called under the NMI_Handler().
mbed_official 340:28d1f895c6fe 567 * @retval None
mbed_official 340:28d1f895c6fe 568 */
mbed_official 340:28d1f895c6fe 569 void HAL_RCC_NMI_IRQHandler(void)
mbed_official 340:28d1f895c6fe 570 {
mbed_official 340:28d1f895c6fe 571 /* Check RCC CSSF flag */
mbed_official 340:28d1f895c6fe 572 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official 340:28d1f895c6fe 573 {
mbed_official 340:28d1f895c6fe 574 /* RCC Clock Security System interrupt user callback */
mbed_official 340:28d1f895c6fe 575 HAL_RCC_CCSCallback();
mbed_official 340:28d1f895c6fe 576
mbed_official 340:28d1f895c6fe 577 /* Clear RCC CSS pending bit */
mbed_official 340:28d1f895c6fe 578 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official 340:28d1f895c6fe 579 }
mbed_official 340:28d1f895c6fe 580 }
mbed_official 340:28d1f895c6fe 581
mbed_official 340:28d1f895c6fe 582 /**
mbed_official 340:28d1f895c6fe 583 * @brief RCC Clock Security System interrupt callback
mbed_official 340:28d1f895c6fe 584 * @retval none
mbed_official 340:28d1f895c6fe 585 */
mbed_official 340:28d1f895c6fe 586 __weak void HAL_RCC_CCSCallback(void)
mbed_official 340:28d1f895c6fe 587 {
mbed_official 340:28d1f895c6fe 588 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 589 the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 590 */
mbed_official 340:28d1f895c6fe 591 }
mbed_official 340:28d1f895c6fe 592
mbed_official 340:28d1f895c6fe 593 /**
mbed_official 340:28d1f895c6fe 594 * @}
mbed_official 340:28d1f895c6fe 595 */
mbed_official 340:28d1f895c6fe 596
mbed_official 340:28d1f895c6fe 597 /**
mbed_official 340:28d1f895c6fe 598 * @}
mbed_official 340:28d1f895c6fe 599 */
mbed_official 340:28d1f895c6fe 600
mbed_official 340:28d1f895c6fe 601 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 340:28d1f895c6fe 602 /**
mbed_official 340:28d1f895c6fe 603 * @}
mbed_official 340:28d1f895c6fe 604 */
mbed_official 340:28d1f895c6fe 605
mbed_official 340:28d1f895c6fe 606 /**
mbed_official 340:28d1f895c6fe 607 * @}
mbed_official 340:28d1f895c6fe 608 */
mbed_official 340:28d1f895c6fe 609
mbed_official 340:28d1f895c6fe 610 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/