gabriel della-monica
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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_hal_smbus.h@340:28d1f895c6fe, 2014-10-09 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Oct 09 08:15:07 2014 +0100
- Revision:
- 340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602
Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/
HAL: nrf51822 - Few fixes for PWM and Serial
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_smbus.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 340:28d1f895c6fe | 5 | * @version V1.1.0 |
| mbed_official | 340:28d1f895c6fe | 6 | * @date 03-Oct-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief Header file of SMBUS HAL module. |
| mbed_official | 340:28d1f895c6fe | 8 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 9 | * @attention |
| mbed_official | 340:28d1f895c6fe | 10 | * |
| mbed_official | 340:28d1f895c6fe | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 12 | * |
| mbed_official | 340:28d1f895c6fe | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 22 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 23 | * |
| mbed_official | 340:28d1f895c6fe | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 34 | * |
| mbed_official | 340:28d1f895c6fe | 35 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 36 | */ |
| mbed_official | 340:28d1f895c6fe | 37 | |
| mbed_official | 340:28d1f895c6fe | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 39 | #ifndef __STM32F0xx_HAL_SMBUS_H |
| mbed_official | 340:28d1f895c6fe | 40 | #define __STM32F0xx_HAL_SMBUS_H |
| mbed_official | 340:28d1f895c6fe | 41 | |
| mbed_official | 340:28d1f895c6fe | 42 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 43 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 44 | #endif |
| mbed_official | 340:28d1f895c6fe | 45 | |
| mbed_official | 340:28d1f895c6fe | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 47 | #include "stm32f0xx_hal_def.h" |
| mbed_official | 340:28d1f895c6fe | 48 | |
| mbed_official | 340:28d1f895c6fe | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 50 | * @{ |
| mbed_official | 340:28d1f895c6fe | 51 | */ |
| mbed_official | 340:28d1f895c6fe | 52 | |
| mbed_official | 340:28d1f895c6fe | 53 | /** @addtogroup SMBUS |
| mbed_official | 340:28d1f895c6fe | 54 | * @{ |
| mbed_official | 340:28d1f895c6fe | 55 | */ |
| mbed_official | 340:28d1f895c6fe | 56 | |
| mbed_official | 340:28d1f895c6fe | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 58 | /** @defgroup SMBUS_Exported_Types SMBUS Exported Types |
| mbed_official | 340:28d1f895c6fe | 59 | * @{ |
| mbed_official | 340:28d1f895c6fe | 60 | */ |
| mbed_official | 340:28d1f895c6fe | 61 | |
| mbed_official | 340:28d1f895c6fe | 62 | /** |
| mbed_official | 340:28d1f895c6fe | 63 | * @brief SMBUS Configuration Structure definition |
| mbed_official | 340:28d1f895c6fe | 64 | */ |
| mbed_official | 340:28d1f895c6fe | 65 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 66 | { |
| mbed_official | 340:28d1f895c6fe | 67 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
| mbed_official | 340:28d1f895c6fe | 68 | This parameter calculated by referring to SMBUS initialization |
| mbed_official | 340:28d1f895c6fe | 69 | section in Reference manual */ |
| mbed_official | 340:28d1f895c6fe | 70 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
| mbed_official | 340:28d1f895c6fe | 71 | This parameter can be a a value of @ref SMBUS_Analog_Filter */ |
| mbed_official | 340:28d1f895c6fe | 72 | |
| mbed_official | 340:28d1f895c6fe | 73 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| mbed_official | 340:28d1f895c6fe | 74 | This parameter can be a 7-bit or 10-bit address. */ |
| mbed_official | 340:28d1f895c6fe | 75 | |
| mbed_official | 340:28d1f895c6fe | 76 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
| mbed_official | 340:28d1f895c6fe | 77 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
| mbed_official | 340:28d1f895c6fe | 78 | |
| mbed_official | 340:28d1f895c6fe | 79 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| mbed_official | 340:28d1f895c6fe | 80 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
| mbed_official | 340:28d1f895c6fe | 81 | |
| mbed_official | 340:28d1f895c6fe | 82 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| mbed_official | 340:28d1f895c6fe | 83 | This parameter can be a 7-bit address. */ |
| mbed_official | 340:28d1f895c6fe | 84 | |
| mbed_official | 340:28d1f895c6fe | 85 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
| mbed_official | 340:28d1f895c6fe | 86 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
| mbed_official | 340:28d1f895c6fe | 87 | |
| mbed_official | 340:28d1f895c6fe | 88 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| mbed_official | 340:28d1f895c6fe | 89 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
| mbed_official | 340:28d1f895c6fe | 90 | |
| mbed_official | 340:28d1f895c6fe | 91 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| mbed_official | 340:28d1f895c6fe | 92 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
| mbed_official | 340:28d1f895c6fe | 93 | |
| mbed_official | 340:28d1f895c6fe | 94 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
| mbed_official | 340:28d1f895c6fe | 95 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
| mbed_official | 340:28d1f895c6fe | 96 | |
| mbed_official | 340:28d1f895c6fe | 97 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
| mbed_official | 340:28d1f895c6fe | 98 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
| mbed_official | 340:28d1f895c6fe | 99 | |
| mbed_official | 340:28d1f895c6fe | 100 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
| mbed_official | 340:28d1f895c6fe | 101 | (Enable bits and different timeout values) |
| mbed_official | 340:28d1f895c6fe | 102 | This parameter calculated by referring to SMBUS initialization |
| mbed_official | 340:28d1f895c6fe | 103 | section in Reference manual */ |
| mbed_official | 340:28d1f895c6fe | 104 | } SMBUS_InitTypeDef; |
| mbed_official | 340:28d1f895c6fe | 105 | |
| mbed_official | 340:28d1f895c6fe | 106 | /** |
| mbed_official | 340:28d1f895c6fe | 107 | * @brief HAL State structures definition |
| mbed_official | 340:28d1f895c6fe | 108 | */ |
| mbed_official | 340:28d1f895c6fe | 109 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 110 | { |
| mbed_official | 340:28d1f895c6fe | 111 | HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */ |
| mbed_official | 340:28d1f895c6fe | 112 | HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */ |
| mbed_official | 340:28d1f895c6fe | 113 | HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 114 | HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 115 | HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 116 | HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 117 | HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 118 | HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */ |
| mbed_official | 340:28d1f895c6fe | 119 | HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 120 | HAL_SMBUS_STATE_SLAVE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */ |
| mbed_official | 340:28d1f895c6fe | 121 | /* Aliases for inter STM32 series compatibility */ |
| mbed_official | 340:28d1f895c6fe | 122 | HAL_SMBUS_STATE_LISTEN = HAL_SMBUS_STATE_SLAVE_LISTEN |
| mbed_official | 340:28d1f895c6fe | 123 | }HAL_SMBUS_StateTypeDef; |
| mbed_official | 340:28d1f895c6fe | 124 | |
| mbed_official | 340:28d1f895c6fe | 125 | /** |
| mbed_official | 340:28d1f895c6fe | 126 | * @brief HAL SMBUS Error Code structure definition |
| mbed_official | 340:28d1f895c6fe | 127 | */ |
| mbed_official | 340:28d1f895c6fe | 128 | typedef enum |
| mbed_official | 340:28d1f895c6fe | 129 | { |
| mbed_official | 340:28d1f895c6fe | 130 | HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */ |
| mbed_official | 340:28d1f895c6fe | 131 | HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */ |
| mbed_official | 340:28d1f895c6fe | 132 | HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */ |
| mbed_official | 340:28d1f895c6fe | 133 | HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */ |
| mbed_official | 340:28d1f895c6fe | 134 | HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */ |
| mbed_official | 340:28d1f895c6fe | 135 | HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */ |
| mbed_official | 340:28d1f895c6fe | 136 | HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */ |
| mbed_official | 340:28d1f895c6fe | 137 | HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */ |
| mbed_official | 340:28d1f895c6fe | 138 | HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */ |
| mbed_official | 340:28d1f895c6fe | 139 | |
| mbed_official | 340:28d1f895c6fe | 140 | }HAL_SMBUS_ErrorTypeDef; |
| mbed_official | 340:28d1f895c6fe | 141 | |
| mbed_official | 340:28d1f895c6fe | 142 | /** |
| mbed_official | 340:28d1f895c6fe | 143 | * @brief SMBUS handle Structure definition |
| mbed_official | 340:28d1f895c6fe | 144 | */ |
| mbed_official | 340:28d1f895c6fe | 145 | typedef struct |
| mbed_official | 340:28d1f895c6fe | 146 | { |
| mbed_official | 340:28d1f895c6fe | 147 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
| mbed_official | 340:28d1f895c6fe | 148 | |
| mbed_official | 340:28d1f895c6fe | 149 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
| mbed_official | 340:28d1f895c6fe | 150 | |
| mbed_official | 340:28d1f895c6fe | 151 | uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ |
| mbed_official | 340:28d1f895c6fe | 152 | |
| mbed_official | 340:28d1f895c6fe | 153 | uint16_t XferSize; /*!< SMBUS transfer size */ |
| mbed_official | 340:28d1f895c6fe | 154 | |
| mbed_official | 340:28d1f895c6fe | 155 | __IO uint16_t XferCount; /*!< SMBUS transfer counter */ |
| mbed_official | 340:28d1f895c6fe | 156 | |
| mbed_official | 340:28d1f895c6fe | 157 | __IO uint32_t XferOptions; /*!< SMBUS transfer options */ |
| mbed_official | 340:28d1f895c6fe | 158 | |
| mbed_official | 340:28d1f895c6fe | 159 | __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */ |
| mbed_official | 340:28d1f895c6fe | 160 | |
| mbed_official | 340:28d1f895c6fe | 161 | HAL_LockTypeDef Lock; /*!< SMBUS locking object */ |
| mbed_official | 340:28d1f895c6fe | 162 | |
| mbed_official | 340:28d1f895c6fe | 163 | __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ |
| mbed_official | 340:28d1f895c6fe | 164 | |
| mbed_official | 340:28d1f895c6fe | 165 | __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */ |
| mbed_official | 340:28d1f895c6fe | 166 | |
| mbed_official | 340:28d1f895c6fe | 167 | }SMBUS_HandleTypeDef; |
| mbed_official | 340:28d1f895c6fe | 168 | /** |
| mbed_official | 340:28d1f895c6fe | 169 | * @} |
| mbed_official | 340:28d1f895c6fe | 170 | */ |
| mbed_official | 340:28d1f895c6fe | 171 | |
| mbed_official | 340:28d1f895c6fe | 172 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 173 | |
| mbed_official | 340:28d1f895c6fe | 174 | /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants |
| mbed_official | 340:28d1f895c6fe | 175 | * @{ |
| mbed_official | 340:28d1f895c6fe | 176 | */ |
| mbed_official | 340:28d1f895c6fe | 177 | |
| mbed_official | 340:28d1f895c6fe | 178 | /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter |
| mbed_official | 340:28d1f895c6fe | 179 | * @{ |
| mbed_official | 340:28d1f895c6fe | 180 | */ |
| mbed_official | 340:28d1f895c6fe | 181 | #define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 182 | #define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF |
| mbed_official | 340:28d1f895c6fe | 183 | |
| mbed_official | 340:28d1f895c6fe | 184 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 185 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLED)) |
| mbed_official | 340:28d1f895c6fe | 186 | /** |
| mbed_official | 340:28d1f895c6fe | 187 | * @} |
| mbed_official | 340:28d1f895c6fe | 188 | */ |
| mbed_official | 340:28d1f895c6fe | 189 | |
| mbed_official | 340:28d1f895c6fe | 190 | /** @defgroup SMBUS_addressing_mode SMBUS addressing mode |
| mbed_official | 340:28d1f895c6fe | 191 | * @{ |
| mbed_official | 340:28d1f895c6fe | 192 | */ |
| mbed_official | 340:28d1f895c6fe | 193 | #define SMBUS_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) |
| mbed_official | 340:28d1f895c6fe | 194 | #define SMBUS_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) |
| mbed_official | 340:28d1f895c6fe | 195 | |
| mbed_official | 340:28d1f895c6fe | 196 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
| mbed_official | 340:28d1f895c6fe | 197 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
| mbed_official | 340:28d1f895c6fe | 198 | /** |
| mbed_official | 340:28d1f895c6fe | 199 | * @} |
| mbed_official | 340:28d1f895c6fe | 200 | */ |
| mbed_official | 340:28d1f895c6fe | 201 | |
| mbed_official | 340:28d1f895c6fe | 202 | /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode |
| mbed_official | 340:28d1f895c6fe | 203 | * @{ |
| mbed_official | 340:28d1f895c6fe | 204 | */ |
| mbed_official | 340:28d1f895c6fe | 205 | |
| mbed_official | 340:28d1f895c6fe | 206 | #define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 207 | #define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN |
| mbed_official | 340:28d1f895c6fe | 208 | |
| mbed_official | 340:28d1f895c6fe | 209 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 210 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 211 | /** |
| mbed_official | 340:28d1f895c6fe | 212 | * @} |
| mbed_official | 340:28d1f895c6fe | 213 | */ |
| mbed_official | 340:28d1f895c6fe | 214 | |
| mbed_official | 340:28d1f895c6fe | 215 | /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks |
| mbed_official | 340:28d1f895c6fe | 216 | * @{ |
| mbed_official | 340:28d1f895c6fe | 217 | */ |
| mbed_official | 340:28d1f895c6fe | 218 | |
| mbed_official | 340:28d1f895c6fe | 219 | #define SMBUS_OA2_NOMASK ((uint8_t)0x00) |
| mbed_official | 340:28d1f895c6fe | 220 | #define SMBUS_OA2_MASK01 ((uint8_t)0x01) |
| mbed_official | 340:28d1f895c6fe | 221 | #define SMBUS_OA2_MASK02 ((uint8_t)0x02) |
| mbed_official | 340:28d1f895c6fe | 222 | #define SMBUS_OA2_MASK03 ((uint8_t)0x03) |
| mbed_official | 340:28d1f895c6fe | 223 | #define SMBUS_OA2_MASK04 ((uint8_t)0x04) |
| mbed_official | 340:28d1f895c6fe | 224 | #define SMBUS_OA2_MASK05 ((uint8_t)0x05) |
| mbed_official | 340:28d1f895c6fe | 225 | #define SMBUS_OA2_MASK06 ((uint8_t)0x06) |
| mbed_official | 340:28d1f895c6fe | 226 | #define SMBUS_OA2_MASK07 ((uint8_t)0x07) |
| mbed_official | 340:28d1f895c6fe | 227 | |
| mbed_official | 340:28d1f895c6fe | 228 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
| mbed_official | 340:28d1f895c6fe | 229 | ((MASK) == SMBUS_OA2_MASK01) || \ |
| mbed_official | 340:28d1f895c6fe | 230 | ((MASK) == SMBUS_OA2_MASK02) || \ |
| mbed_official | 340:28d1f895c6fe | 231 | ((MASK) == SMBUS_OA2_MASK03) || \ |
| mbed_official | 340:28d1f895c6fe | 232 | ((MASK) == SMBUS_OA2_MASK04) || \ |
| mbed_official | 340:28d1f895c6fe | 233 | ((MASK) == SMBUS_OA2_MASK05) || \ |
| mbed_official | 340:28d1f895c6fe | 234 | ((MASK) == SMBUS_OA2_MASK06) || \ |
| mbed_official | 340:28d1f895c6fe | 235 | ((MASK) == SMBUS_OA2_MASK07)) |
| mbed_official | 340:28d1f895c6fe | 236 | /** |
| mbed_official | 340:28d1f895c6fe | 237 | * @} |
| mbed_official | 340:28d1f895c6fe | 238 | */ |
| mbed_official | 340:28d1f895c6fe | 239 | |
| mbed_official | 340:28d1f895c6fe | 240 | |
| mbed_official | 340:28d1f895c6fe | 241 | /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode |
| mbed_official | 340:28d1f895c6fe | 242 | * @{ |
| mbed_official | 340:28d1f895c6fe | 243 | */ |
| mbed_official | 340:28d1f895c6fe | 244 | #define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 245 | #define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN |
| mbed_official | 340:28d1f895c6fe | 246 | |
| mbed_official | 340:28d1f895c6fe | 247 | #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 248 | ((CALL) == SMBUS_GENERALCALL_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 249 | /** |
| mbed_official | 340:28d1f895c6fe | 250 | * @} |
| mbed_official | 340:28d1f895c6fe | 251 | */ |
| mbed_official | 340:28d1f895c6fe | 252 | |
| mbed_official | 340:28d1f895c6fe | 253 | /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode |
| mbed_official | 340:28d1f895c6fe | 254 | * @{ |
| mbed_official | 340:28d1f895c6fe | 255 | */ |
| mbed_official | 340:28d1f895c6fe | 256 | #define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 257 | #define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH |
| mbed_official | 340:28d1f895c6fe | 258 | |
| mbed_official | 340:28d1f895c6fe | 259 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 260 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 261 | /** |
| mbed_official | 340:28d1f895c6fe | 262 | * @} |
| mbed_official | 340:28d1f895c6fe | 263 | */ |
| mbed_official | 340:28d1f895c6fe | 264 | |
| mbed_official | 340:28d1f895c6fe | 265 | /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode |
| mbed_official | 340:28d1f895c6fe | 266 | * @{ |
| mbed_official | 340:28d1f895c6fe | 267 | */ |
| mbed_official | 340:28d1f895c6fe | 268 | #define SMBUS_PEC_DISABLED ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 269 | #define SMBUS_PEC_ENABLED I2C_CR1_PECEN |
| mbed_official | 340:28d1f895c6fe | 270 | |
| mbed_official | 340:28d1f895c6fe | 271 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \ |
| mbed_official | 340:28d1f895c6fe | 272 | ((PEC) == SMBUS_PEC_ENABLED)) |
| mbed_official | 340:28d1f895c6fe | 273 | /** |
| mbed_official | 340:28d1f895c6fe | 274 | * @} |
| mbed_official | 340:28d1f895c6fe | 275 | */ |
| mbed_official | 340:28d1f895c6fe | 276 | |
| mbed_official | 340:28d1f895c6fe | 277 | /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode |
| mbed_official | 340:28d1f895c6fe | 278 | * @{ |
| mbed_official | 340:28d1f895c6fe | 279 | */ |
| mbed_official | 340:28d1f895c6fe | 280 | #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBHEN) |
| mbed_official | 340:28d1f895c6fe | 281 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (uint32_t)(0x00000000) |
| mbed_official | 340:28d1f895c6fe | 282 | #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBDEN) |
| mbed_official | 340:28d1f895c6fe | 283 | |
| mbed_official | 340:28d1f895c6fe | 284 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
| mbed_official | 340:28d1f895c6fe | 285 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
| mbed_official | 340:28d1f895c6fe | 286 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
| mbed_official | 340:28d1f895c6fe | 287 | /** |
| mbed_official | 340:28d1f895c6fe | 288 | * @} |
| mbed_official | 340:28d1f895c6fe | 289 | */ |
| mbed_official | 340:28d1f895c6fe | 290 | |
| mbed_official | 340:28d1f895c6fe | 291 | /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition |
| mbed_official | 340:28d1f895c6fe | 292 | * @{ |
| mbed_official | 340:28d1f895c6fe | 293 | */ |
| mbed_official | 340:28d1f895c6fe | 294 | |
| mbed_official | 340:28d1f895c6fe | 295 | #define SMBUS_SOFTEND_MODE ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 296 | #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD |
| mbed_official | 340:28d1f895c6fe | 297 | #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND |
| mbed_official | 340:28d1f895c6fe | 298 | #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE |
| mbed_official | 340:28d1f895c6fe | 299 | |
| mbed_official | 340:28d1f895c6fe | 300 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
| mbed_official | 340:28d1f895c6fe | 301 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
| mbed_official | 340:28d1f895c6fe | 302 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
| mbed_official | 340:28d1f895c6fe | 303 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
| mbed_official | 340:28d1f895c6fe | 304 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
| mbed_official | 340:28d1f895c6fe | 305 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
| mbed_official | 340:28d1f895c6fe | 306 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
| mbed_official | 340:28d1f895c6fe | 307 | |
| mbed_official | 340:28d1f895c6fe | 308 | /** |
| mbed_official | 340:28d1f895c6fe | 309 | * @} |
| mbed_official | 340:28d1f895c6fe | 310 | */ |
| mbed_official | 340:28d1f895c6fe | 311 | |
| mbed_official | 340:28d1f895c6fe | 312 | /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition |
| mbed_official | 340:28d1f895c6fe | 313 | * @{ |
| mbed_official | 340:28d1f895c6fe | 314 | */ |
| mbed_official | 340:28d1f895c6fe | 315 | |
| mbed_official | 340:28d1f895c6fe | 316 | #define SMBUS_NO_STARTSTOP ((uint32_t)0x00000000) |
| mbed_official | 340:28d1f895c6fe | 317 | #define SMBUS_GENERATE_STOP I2C_CR2_STOP |
| mbed_official | 340:28d1f895c6fe | 318 | #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) |
| mbed_official | 340:28d1f895c6fe | 319 | #define SMBUS_GENERATE_START_WRITE I2C_CR2_START |
| mbed_official | 340:28d1f895c6fe | 320 | |
| mbed_official | 340:28d1f895c6fe | 321 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
| mbed_official | 340:28d1f895c6fe | 322 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
| mbed_official | 340:28d1f895c6fe | 323 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
| mbed_official | 340:28d1f895c6fe | 324 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
| mbed_official | 340:28d1f895c6fe | 325 | |
| mbed_official | 340:28d1f895c6fe | 326 | /** |
| mbed_official | 340:28d1f895c6fe | 327 | * @} |
| mbed_official | 340:28d1f895c6fe | 328 | */ |
| mbed_official | 340:28d1f895c6fe | 329 | |
| mbed_official | 340:28d1f895c6fe | 330 | /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition |
| mbed_official | 340:28d1f895c6fe | 331 | * @{ |
| mbed_official | 340:28d1f895c6fe | 332 | */ |
| mbed_official | 340:28d1f895c6fe | 333 | |
| mbed_official | 340:28d1f895c6fe | 334 | #define SMBUS_FIRST_FRAME ((uint32_t)(SMBUS_SOFTEND_MODE)) |
| mbed_official | 340:28d1f895c6fe | 335 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
| mbed_official | 340:28d1f895c6fe | 336 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| mbed_official | 340:28d1f895c6fe | 337 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| mbed_official | 340:28d1f895c6fe | 338 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| mbed_official | 340:28d1f895c6fe | 339 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| mbed_official | 340:28d1f895c6fe | 340 | |
| mbed_official | 340:28d1f895c6fe | 341 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ |
| mbed_official | 340:28d1f895c6fe | 342 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
| mbed_official | 340:28d1f895c6fe | 343 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
| mbed_official | 340:28d1f895c6fe | 344 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
| mbed_official | 340:28d1f895c6fe | 345 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
| mbed_official | 340:28d1f895c6fe | 346 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
| mbed_official | 340:28d1f895c6fe | 347 | |
| mbed_official | 340:28d1f895c6fe | 348 | /** |
| mbed_official | 340:28d1f895c6fe | 349 | * @} |
| mbed_official | 340:28d1f895c6fe | 350 | */ |
| mbed_official | 340:28d1f895c6fe | 351 | |
| mbed_official | 340:28d1f895c6fe | 352 | /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition |
| mbed_official | 340:28d1f895c6fe | 353 | * @brief SMBUS Interrupt definition |
| mbed_official | 340:28d1f895c6fe | 354 | * Elements values convention: 0xXXXXXXXX |
| mbed_official | 340:28d1f895c6fe | 355 | * - XXXXXXXX : Interrupt control mask |
| mbed_official | 340:28d1f895c6fe | 356 | * @{ |
| mbed_official | 340:28d1f895c6fe | 357 | */ |
| mbed_official | 340:28d1f895c6fe | 358 | #define SMBUS_IT_ERRI I2C_CR1_ERRIE |
| mbed_official | 340:28d1f895c6fe | 359 | #define SMBUS_IT_TCI I2C_CR1_TCIE |
| mbed_official | 340:28d1f895c6fe | 360 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
| mbed_official | 340:28d1f895c6fe | 361 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
| mbed_official | 340:28d1f895c6fe | 362 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
| mbed_official | 340:28d1f895c6fe | 363 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
| mbed_official | 340:28d1f895c6fe | 364 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
| mbed_official | 340:28d1f895c6fe | 365 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
| mbed_official | 340:28d1f895c6fe | 366 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
| mbed_official | 340:28d1f895c6fe | 367 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
| mbed_official | 340:28d1f895c6fe | 368 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
| mbed_official | 340:28d1f895c6fe | 369 | /** |
| mbed_official | 340:28d1f895c6fe | 370 | * @} |
| mbed_official | 340:28d1f895c6fe | 371 | */ |
| mbed_official | 340:28d1f895c6fe | 372 | |
| mbed_official | 340:28d1f895c6fe | 373 | /** @defgroup SMBUS_Flag_definition SMBUS Flag definition |
| mbed_official | 340:28d1f895c6fe | 374 | * @brief Flag definition |
| mbed_official | 340:28d1f895c6fe | 375 | * Elements values convention: 0xXXXXYYYY |
| mbed_official | 340:28d1f895c6fe | 376 | * - XXXXXXXX : Flag mask |
| mbed_official | 340:28d1f895c6fe | 377 | * @{ |
| mbed_official | 340:28d1f895c6fe | 378 | */ |
| mbed_official | 340:28d1f895c6fe | 379 | |
| mbed_official | 340:28d1f895c6fe | 380 | #define SMBUS_FLAG_TXE I2C_ISR_TXE |
| mbed_official | 340:28d1f895c6fe | 381 | #define SMBUS_FLAG_TXIS I2C_ISR_TXIS |
| mbed_official | 340:28d1f895c6fe | 382 | #define SMBUS_FLAG_RXNE I2C_ISR_RXNE |
| mbed_official | 340:28d1f895c6fe | 383 | #define SMBUS_FLAG_ADDR I2C_ISR_ADDR |
| mbed_official | 340:28d1f895c6fe | 384 | #define SMBUS_FLAG_AF I2C_ISR_NACKF |
| mbed_official | 340:28d1f895c6fe | 385 | #define SMBUS_FLAG_STOPF I2C_ISR_STOPF |
| mbed_official | 340:28d1f895c6fe | 386 | #define SMBUS_FLAG_TC I2C_ISR_TC |
| mbed_official | 340:28d1f895c6fe | 387 | #define SMBUS_FLAG_TCR I2C_ISR_TCR |
| mbed_official | 340:28d1f895c6fe | 388 | #define SMBUS_FLAG_BERR I2C_ISR_BERR |
| mbed_official | 340:28d1f895c6fe | 389 | #define SMBUS_FLAG_ARLO I2C_ISR_ARLO |
| mbed_official | 340:28d1f895c6fe | 390 | #define SMBUS_FLAG_OVR I2C_ISR_OVR |
| mbed_official | 340:28d1f895c6fe | 391 | #define SMBUS_FLAG_PECERR I2C_ISR_PECERR |
| mbed_official | 340:28d1f895c6fe | 392 | #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT |
| mbed_official | 340:28d1f895c6fe | 393 | #define SMBUS_FLAG_ALERT I2C_ISR_ALERT |
| mbed_official | 340:28d1f895c6fe | 394 | #define SMBUS_FLAG_BUSY I2C_ISR_BUSY |
| mbed_official | 340:28d1f895c6fe | 395 | #define SMBUS_FLAG_DIR I2C_ISR_DIR |
| mbed_official | 340:28d1f895c6fe | 396 | /** |
| mbed_official | 340:28d1f895c6fe | 397 | * @} |
| mbed_official | 340:28d1f895c6fe | 398 | */ |
| mbed_official | 340:28d1f895c6fe | 399 | |
| mbed_official | 340:28d1f895c6fe | 400 | /** |
| mbed_official | 340:28d1f895c6fe | 401 | * @} |
| mbed_official | 340:28d1f895c6fe | 402 | */ |
| mbed_official | 340:28d1f895c6fe | 403 | |
| mbed_official | 340:28d1f895c6fe | 404 | /* Exported macros ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 405 | /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros |
| mbed_official | 340:28d1f895c6fe | 406 | * @{ |
| mbed_official | 340:28d1f895c6fe | 407 | */ |
| mbed_official | 340:28d1f895c6fe | 408 | |
| mbed_official | 340:28d1f895c6fe | 409 | /** @brief Reset SMBUS handle state |
| mbed_official | 340:28d1f895c6fe | 410 | * @param __HANDLE__: SMBUS handle. |
| mbed_official | 340:28d1f895c6fe | 411 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 412 | */ |
| mbed_official | 340:28d1f895c6fe | 413 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
| mbed_official | 340:28d1f895c6fe | 414 | |
| mbed_official | 340:28d1f895c6fe | 415 | /** @brief Enable or disable the specified SMBUS interrupts. |
| mbed_official | 340:28d1f895c6fe | 416 | * @param __HANDLE__: specifies the SMBUS Handle. |
| mbed_official | 340:28d1f895c6fe | 417 | * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. |
| mbed_official | 340:28d1f895c6fe | 418 | * @param __INTERRUPT__: specifies the interrupt source to enable or disable. |
| mbed_official | 340:28d1f895c6fe | 419 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 420 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| mbed_official | 340:28d1f895c6fe | 421 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| mbed_official | 340:28d1f895c6fe | 422 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| mbed_official | 340:28d1f895c6fe | 423 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| mbed_official | 340:28d1f895c6fe | 424 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| mbed_official | 340:28d1f895c6fe | 425 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| mbed_official | 340:28d1f895c6fe | 426 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| mbed_official | 340:28d1f895c6fe | 427 | * |
| mbed_official | 340:28d1f895c6fe | 428 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 429 | */ |
| mbed_official | 340:28d1f895c6fe | 430 | |
| mbed_official | 340:28d1f895c6fe | 431 | #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) |
| mbed_official | 340:28d1f895c6fe | 432 | #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) |
| mbed_official | 340:28d1f895c6fe | 433 | |
| mbed_official | 340:28d1f895c6fe | 434 | /** @brief Checks if the specified SMBUS interrupt source is enabled or disabled. |
| mbed_official | 340:28d1f895c6fe | 435 | * @param __HANDLE__: specifies the SMBUS Handle. |
| mbed_official | 340:28d1f895c6fe | 436 | * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. |
| mbed_official | 340:28d1f895c6fe | 437 | * @param __INTERRUPT__: specifies the SMBUS interrupt source to check. |
| mbed_official | 340:28d1f895c6fe | 438 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 439 | * @arg SMBUS_IT_ERRI: Errors interrupt enable |
| mbed_official | 340:28d1f895c6fe | 440 | * @arg SMBUS_IT_TCI: Transfer complete interrupt enable |
| mbed_official | 340:28d1f895c6fe | 441 | * @arg SMBUS_IT_STOPI: STOP detection interrupt enable |
| mbed_official | 340:28d1f895c6fe | 442 | * @arg SMBUS_IT_NACKI: NACK received interrupt enable |
| mbed_official | 340:28d1f895c6fe | 443 | * @arg SMBUS_IT_ADDRI: Address match interrupt enable |
| mbed_official | 340:28d1f895c6fe | 444 | * @arg SMBUS_IT_RXI: RX interrupt enable |
| mbed_official | 340:28d1f895c6fe | 445 | * @arg SMBUS_IT_TXI: TX interrupt enable |
| mbed_official | 340:28d1f895c6fe | 446 | * |
| mbed_official | 340:28d1f895c6fe | 447 | * @retval The new state of __IT__ (TRUE or FALSE). |
| mbed_official | 340:28d1f895c6fe | 448 | */ |
| mbed_official | 340:28d1f895c6fe | 449 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| mbed_official | 340:28d1f895c6fe | 450 | |
| mbed_official | 340:28d1f895c6fe | 451 | /** @brief Checks whether the specified SMBUS flag is set or not. |
| mbed_official | 340:28d1f895c6fe | 452 | * @param __HANDLE__: specifies the SMBUS Handle. |
| mbed_official | 340:28d1f895c6fe | 453 | * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. |
| mbed_official | 340:28d1f895c6fe | 454 | * @param __FLAG__: specifies the flag to check. |
| mbed_official | 340:28d1f895c6fe | 455 | * This parameter can be one of the following values: |
| mbed_official | 340:28d1f895c6fe | 456 | * @arg SMBUS_FLAG_TXE: Transmit data register empty |
| mbed_official | 340:28d1f895c6fe | 457 | * @arg SMBUS_FLAG_TXIS: Transmit interrupt status |
| mbed_official | 340:28d1f895c6fe | 458 | * @arg SMBUS_FLAG_RXNE: Receive data register not empty |
| mbed_official | 340:28d1f895c6fe | 459 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| mbed_official | 340:28d1f895c6fe | 460 | * @arg SMBUS_FLAG_AF: NACK received flag |
| mbed_official | 340:28d1f895c6fe | 461 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| mbed_official | 340:28d1f895c6fe | 462 | * @arg SMBUS_FLAG_TC: Transfer complete (master mode) |
| mbed_official | 340:28d1f895c6fe | 463 | * @arg SMBUS_FLAG_TCR: Transfer complete reload |
| mbed_official | 340:28d1f895c6fe | 464 | * @arg SMBUS_FLAG_BERR: Bus error |
| mbed_official | 340:28d1f895c6fe | 465 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| mbed_official | 340:28d1f895c6fe | 466 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| mbed_official | 340:28d1f895c6fe | 467 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| mbed_official | 340:28d1f895c6fe | 468 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| mbed_official | 340:28d1f895c6fe | 469 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| mbed_official | 340:28d1f895c6fe | 470 | * @arg SMBUS_FLAG_BUSY: Bus busy |
| mbed_official | 340:28d1f895c6fe | 471 | * @arg SMBUS_FLAG_DIR: Transfer direction (slave mode) |
| mbed_official | 340:28d1f895c6fe | 472 | * |
| mbed_official | 340:28d1f895c6fe | 473 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| mbed_official | 340:28d1f895c6fe | 474 | */ |
| mbed_official | 340:28d1f895c6fe | 475 | #define SMBUS_FLAG_MASK ((uint32_t)0x0001FFFF) |
| mbed_official | 340:28d1f895c6fe | 476 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) |
| mbed_official | 340:28d1f895c6fe | 477 | |
| mbed_official | 340:28d1f895c6fe | 478 | /** @brief Clears the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
| mbed_official | 340:28d1f895c6fe | 479 | * @param __HANDLE__: specifies the SMBUS Handle. |
| mbed_official | 340:28d1f895c6fe | 480 | * This parameter can be SMBUS where x: 1 or 2 to select the SMBUS peripheral. |
| mbed_official | 340:28d1f895c6fe | 481 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 340:28d1f895c6fe | 482 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 483 | * @arg SMBUS_FLAG_ADDR: Address matched (slave mode) |
| mbed_official | 340:28d1f895c6fe | 484 | * @arg SMBUS_FLAG_AF: NACK received flag |
| mbed_official | 340:28d1f895c6fe | 485 | * @arg SMBUS_FLAG_STOPF: STOP detection flag |
| mbed_official | 340:28d1f895c6fe | 486 | * @arg SMBUS_FLAG_BERR: Bus error |
| mbed_official | 340:28d1f895c6fe | 487 | * @arg SMBUS_FLAG_ARLO: Arbitration lost |
| mbed_official | 340:28d1f895c6fe | 488 | * @arg SMBUS_FLAG_OVR: Overrun/Underrun |
| mbed_official | 340:28d1f895c6fe | 489 | * @arg SMBUS_FLAG_PECERR: PEC error in reception |
| mbed_official | 340:28d1f895c6fe | 490 | * @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag |
| mbed_official | 340:28d1f895c6fe | 491 | * @arg SMBUS_FLAG_ALERT: SMBus alert |
| mbed_official | 340:28d1f895c6fe | 492 | * |
| mbed_official | 340:28d1f895c6fe | 493 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 494 | */ |
| mbed_official | 340:28d1f895c6fe | 495 | #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 496 | |
| mbed_official | 340:28d1f895c6fe | 497 | |
| mbed_official | 340:28d1f895c6fe | 498 | #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) |
| mbed_official | 340:28d1f895c6fe | 499 | #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) |
| mbed_official | 340:28d1f895c6fe | 500 | |
| mbed_official | 340:28d1f895c6fe | 501 | #define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
| mbed_official | 340:28d1f895c6fe | 502 | #define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
| mbed_official | 340:28d1f895c6fe | 503 | |
| mbed_official | 340:28d1f895c6fe | 504 | #define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
| mbed_official | 340:28d1f895c6fe | 505 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
| mbed_official | 340:28d1f895c6fe | 506 | |
| mbed_official | 340:28d1f895c6fe | 507 | #define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) |
| mbed_official | 340:28d1f895c6fe | 508 | #define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) |
| mbed_official | 340:28d1f895c6fe | 509 | #define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
| mbed_official | 340:28d1f895c6fe | 510 | #define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
| mbed_official | 340:28d1f895c6fe | 511 | #define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
| mbed_official | 340:28d1f895c6fe | 512 | #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) |
| mbed_official | 340:28d1f895c6fe | 513 | |
| mbed_official | 340:28d1f895c6fe | 514 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) |
| mbed_official | 340:28d1f895c6fe | 515 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) |
| mbed_official | 340:28d1f895c6fe | 516 | /** |
| mbed_official | 340:28d1f895c6fe | 517 | * @} |
| mbed_official | 340:28d1f895c6fe | 518 | */ |
| mbed_official | 340:28d1f895c6fe | 519 | |
| mbed_official | 340:28d1f895c6fe | 520 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 521 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
| mbed_official | 340:28d1f895c6fe | 522 | * @{ |
| mbed_official | 340:28d1f895c6fe | 523 | */ |
| mbed_official | 340:28d1f895c6fe | 524 | |
| mbed_official | 340:28d1f895c6fe | 525 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
| mbed_official | 340:28d1f895c6fe | 526 | * @{ |
| mbed_official | 340:28d1f895c6fe | 527 | */ |
| mbed_official | 340:28d1f895c6fe | 528 | |
| mbed_official | 340:28d1f895c6fe | 529 | /* Initialization and de-initialization functions **********************************/ |
| mbed_official | 340:28d1f895c6fe | 530 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 531 | HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 532 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 533 | void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 534 | |
| mbed_official | 340:28d1f895c6fe | 535 | /** |
| mbed_official | 340:28d1f895c6fe | 536 | * @} |
| mbed_official | 340:28d1f895c6fe | 537 | */ |
| mbed_official | 340:28d1f895c6fe | 538 | |
| mbed_official | 340:28d1f895c6fe | 539 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
| mbed_official | 340:28d1f895c6fe | 540 | * @{ |
| mbed_official | 340:28d1f895c6fe | 541 | */ |
| mbed_official | 340:28d1f895c6fe | 542 | |
| mbed_official | 340:28d1f895c6fe | 543 | /* IO operation functions *****************************************************/ |
| mbed_official | 340:28d1f895c6fe | 544 | /******* Blocking mode: Polling */ |
| mbed_official | 340:28d1f895c6fe | 545 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
| mbed_official | 340:28d1f895c6fe | 546 | |
| mbed_official | 340:28d1f895c6fe | 547 | /******* Non-Blocking mode: Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 548 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| mbed_official | 340:28d1f895c6fe | 549 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| mbed_official | 340:28d1f895c6fe | 550 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
| mbed_official | 340:28d1f895c6fe | 551 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| mbed_official | 340:28d1f895c6fe | 552 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
| mbed_official | 340:28d1f895c6fe | 553 | |
| mbed_official | 340:28d1f895c6fe | 554 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 555 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 556 | HAL_StatusTypeDef HAL_SMBUS_Slave_Listen_IT(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 557 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 558 | |
| mbed_official | 340:28d1f895c6fe | 559 | /* Aliases for new API and to insure inter STM32 series compatibility */ |
| mbed_official | 340:28d1f895c6fe | 560 | #define HAL_SMBUS_EnableListen_IT HAL_SMBUS_Slave_Listen_IT |
| mbed_official | 340:28d1f895c6fe | 561 | |
| mbed_official | 340:28d1f895c6fe | 562 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
| mbed_official | 340:28d1f895c6fe | 563 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 564 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 565 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 566 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 567 | void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 568 | void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 569 | void HAL_SMBUS_SlaveAddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
| mbed_official | 340:28d1f895c6fe | 570 | void HAL_SMBUS_SlaveListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 571 | |
| mbed_official | 340:28d1f895c6fe | 572 | /* Aliases for new API and to insure inter STM32 series compatibility */ |
| mbed_official | 340:28d1f895c6fe | 573 | #define HAL_SMBUS_AddrCallback HAL_SMBUS_SlaveAddrCallback |
| mbed_official | 340:28d1f895c6fe | 574 | #define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_SlaveListenCpltCallback |
| mbed_official | 340:28d1f895c6fe | 575 | |
| mbed_official | 340:28d1f895c6fe | 576 | void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 577 | |
| mbed_official | 340:28d1f895c6fe | 578 | /** |
| mbed_official | 340:28d1f895c6fe | 579 | * @} |
| mbed_official | 340:28d1f895c6fe | 580 | */ |
| mbed_official | 340:28d1f895c6fe | 581 | |
| mbed_official | 340:28d1f895c6fe | 582 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
| mbed_official | 340:28d1f895c6fe | 583 | * @{ |
| mbed_official | 340:28d1f895c6fe | 584 | */ |
| mbed_official | 340:28d1f895c6fe | 585 | |
| mbed_official | 340:28d1f895c6fe | 586 | /* Peripheral State and Errors functions **************************************************/ |
| mbed_official | 340:28d1f895c6fe | 587 | HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 588 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
| mbed_official | 340:28d1f895c6fe | 589 | |
| mbed_official | 340:28d1f895c6fe | 590 | /** |
| mbed_official | 340:28d1f895c6fe | 591 | * @} |
| mbed_official | 340:28d1f895c6fe | 592 | */ |
| mbed_official | 340:28d1f895c6fe | 593 | |
| mbed_official | 340:28d1f895c6fe | 594 | /** |
| mbed_official | 340:28d1f895c6fe | 595 | * @} |
| mbed_official | 340:28d1f895c6fe | 596 | */ |
| mbed_official | 340:28d1f895c6fe | 597 | |
| mbed_official | 340:28d1f895c6fe | 598 | /** |
| mbed_official | 340:28d1f895c6fe | 599 | * @} |
| mbed_official | 340:28d1f895c6fe | 600 | */ |
| mbed_official | 340:28d1f895c6fe | 601 | |
| mbed_official | 340:28d1f895c6fe | 602 | /** |
| mbed_official | 340:28d1f895c6fe | 603 | * @} |
| mbed_official | 340:28d1f895c6fe | 604 | */ |
| mbed_official | 340:28d1f895c6fe | 605 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 606 | } |
| mbed_official | 340:28d1f895c6fe | 607 | #endif |
| mbed_official | 340:28d1f895c6fe | 608 | |
| mbed_official | 340:28d1f895c6fe | 609 | |
| mbed_official | 340:28d1f895c6fe | 610 | #endif /* __STM32F0xx_HAL_SMBUS_H */ |
| mbed_official | 340:28d1f895c6fe | 611 | |
| mbed_official | 340:28d1f895c6fe | 612 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 340:28d1f895c6fe | 613 |