Mohamed Moawya / SnakeGame

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Dependencies:   mbed

snake-test/mbed/TARGET_K64F/TOOLCHAIN_ARM_STD/core_sc000.h@0:e4c5e6ec922e, 2020-05-25 (annotated)

Committer:
mohamedmoawya
Date:
Mon May 25 19:06:11 2020 +0000
Revision:
0:e4c5e6ec922e
snake game tteest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mohamedmoawya 0:e4c5e6ec922e 1 /**************************************************************************//**
mohamedmoawya 0:e4c5e6ec922e 2 * @file core_sc000.h
mohamedmoawya 0:e4c5e6ec922e 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
mohamedmoawya 0:e4c5e6ec922e 4 * @version V5.0.5
mohamedmoawya 0:e4c5e6ec922e 5 * @date 28. May 2018
mohamedmoawya 0:e4c5e6ec922e 6 ******************************************************************************/
mohamedmoawya 0:e4c5e6ec922e 7 /*
mohamedmoawya 0:e4c5e6ec922e 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
mohamedmoawya 0:e4c5e6ec922e 9 *
mohamedmoawya 0:e4c5e6ec922e 10 * SPDX-License-Identifier: Apache-2.0
mohamedmoawya 0:e4c5e6ec922e 11 *
mohamedmoawya 0:e4c5e6ec922e 12 * Licensed under the Apache License, Version 2.0 (the License); you may
mohamedmoawya 0:e4c5e6ec922e 13 * not use this file except in compliance with the License.
mohamedmoawya 0:e4c5e6ec922e 14 * You may obtain a copy of the License at
mohamedmoawya 0:e4c5e6ec922e 15 *
mohamedmoawya 0:e4c5e6ec922e 16 * www.apache.org/licenses/LICENSE-2.0
mohamedmoawya 0:e4c5e6ec922e 17 *
mohamedmoawya 0:e4c5e6ec922e 18 * Unless required by applicable law or agreed to in writing, software
mohamedmoawya 0:e4c5e6ec922e 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
mohamedmoawya 0:e4c5e6ec922e 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mohamedmoawya 0:e4c5e6ec922e 21 * See the License for the specific language governing permissions and
mohamedmoawya 0:e4c5e6ec922e 22 * limitations under the License.
mohamedmoawya 0:e4c5e6ec922e 23 */
mohamedmoawya 0:e4c5e6ec922e 24
mohamedmoawya 0:e4c5e6ec922e 25 #if defined ( __ICCARM__ )
mohamedmoawya 0:e4c5e6ec922e 26 #pragma system_include /* treat file as system include file for MISRA check */
mohamedmoawya 0:e4c5e6ec922e 27 #elif defined (__clang__)
mohamedmoawya 0:e4c5e6ec922e 28 #pragma clang system_header /* treat file as system include file */
mohamedmoawya 0:e4c5e6ec922e 29 #endif
mohamedmoawya 0:e4c5e6ec922e 30
mohamedmoawya 0:e4c5e6ec922e 31 #ifndef __CORE_SC000_H_GENERIC
mohamedmoawya 0:e4c5e6ec922e 32 #define __CORE_SC000_H_GENERIC
mohamedmoawya 0:e4c5e6ec922e 33
mohamedmoawya 0:e4c5e6ec922e 34 #include <stdint.h>
mohamedmoawya 0:e4c5e6ec922e 35
mohamedmoawya 0:e4c5e6ec922e 36 #ifdef __cplusplus
mohamedmoawya 0:e4c5e6ec922e 37 extern "C" {
mohamedmoawya 0:e4c5e6ec922e 38 #endif
mohamedmoawya 0:e4c5e6ec922e 39
mohamedmoawya 0:e4c5e6ec922e 40 /**
mohamedmoawya 0:e4c5e6ec922e 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mohamedmoawya 0:e4c5e6ec922e 42 CMSIS violates the following MISRA-C:2004 rules:
mohamedmoawya 0:e4c5e6ec922e 43
mohamedmoawya 0:e4c5e6ec922e 44 \li Required Rule 8.5, object/function definition in header file.<br>
mohamedmoawya 0:e4c5e6ec922e 45 Function definitions in header files are used to allow 'inlining'.
mohamedmoawya 0:e4c5e6ec922e 46
mohamedmoawya 0:e4c5e6ec922e 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mohamedmoawya 0:e4c5e6ec922e 48 Unions are used for effective representation of core registers.
mohamedmoawya 0:e4c5e6ec922e 49
mohamedmoawya 0:e4c5e6ec922e 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
mohamedmoawya 0:e4c5e6ec922e 51 Function-like macros are used to allow more efficient code.
mohamedmoawya 0:e4c5e6ec922e 52 */
mohamedmoawya 0:e4c5e6ec922e 53
mohamedmoawya 0:e4c5e6ec922e 54
mohamedmoawya 0:e4c5e6ec922e 55 /*******************************************************************************
mohamedmoawya 0:e4c5e6ec922e 56 * CMSIS definitions
mohamedmoawya 0:e4c5e6ec922e 57 ******************************************************************************/
mohamedmoawya 0:e4c5e6ec922e 58 /**
mohamedmoawya 0:e4c5e6ec922e 59 \ingroup SC000
mohamedmoawya 0:e4c5e6ec922e 60 @{
mohamedmoawya 0:e4c5e6ec922e 61 */
mohamedmoawya 0:e4c5e6ec922e 62
mohamedmoawya 0:e4c5e6ec922e 63 #include "cmsis_version.h"
mohamedmoawya 0:e4c5e6ec922e 64
mohamedmoawya 0:e4c5e6ec922e 65 /* CMSIS SC000 definitions */
mohamedmoawya 0:e4c5e6ec922e 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
mohamedmoawya 0:e4c5e6ec922e 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
mohamedmoawya 0:e4c5e6ec922e 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
mohamedmoawya 0:e4c5e6ec922e 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
mohamedmoawya 0:e4c5e6ec922e 70
mohamedmoawya 0:e4c5e6ec922e 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
mohamedmoawya 0:e4c5e6ec922e 72
mohamedmoawya 0:e4c5e6ec922e 73 /** __FPU_USED indicates whether an FPU is used or not.
mohamedmoawya 0:e4c5e6ec922e 74 This core does not support an FPU at all
mohamedmoawya 0:e4c5e6ec922e 75 */
mohamedmoawya 0:e4c5e6ec922e 76 #define __FPU_USED 0U
mohamedmoawya 0:e4c5e6ec922e 77
mohamedmoawya 0:e4c5e6ec922e 78 #if defined ( __CC_ARM )
mohamedmoawya 0:e4c5e6ec922e 79 #if defined __TARGET_FPU_VFP
mohamedmoawya 0:e4c5e6ec922e 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 81 #endif
mohamedmoawya 0:e4c5e6ec922e 82
mohamedmoawya 0:e4c5e6ec922e 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
mohamedmoawya 0:e4c5e6ec922e 84 #if defined __ARM_PCS_VFP
mohamedmoawya 0:e4c5e6ec922e 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 86 #endif
mohamedmoawya 0:e4c5e6ec922e 87
mohamedmoawya 0:e4c5e6ec922e 88 #elif defined ( __GNUC__ )
mohamedmoawya 0:e4c5e6ec922e 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mohamedmoawya 0:e4c5e6ec922e 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 91 #endif
mohamedmoawya 0:e4c5e6ec922e 92
mohamedmoawya 0:e4c5e6ec922e 93 #elif defined ( __ICCARM__ )
mohamedmoawya 0:e4c5e6ec922e 94 #if defined __ARMVFP__
mohamedmoawya 0:e4c5e6ec922e 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 96 #endif
mohamedmoawya 0:e4c5e6ec922e 97
mohamedmoawya 0:e4c5e6ec922e 98 #elif defined ( __TI_ARM__ )
mohamedmoawya 0:e4c5e6ec922e 99 #if defined __TI_VFP_SUPPORT__
mohamedmoawya 0:e4c5e6ec922e 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 101 #endif
mohamedmoawya 0:e4c5e6ec922e 102
mohamedmoawya 0:e4c5e6ec922e 103 #elif defined ( __TASKING__ )
mohamedmoawya 0:e4c5e6ec922e 104 #if defined __FPU_VFP__
mohamedmoawya 0:e4c5e6ec922e 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 106 #endif
mohamedmoawya 0:e4c5e6ec922e 107
mohamedmoawya 0:e4c5e6ec922e 108 #elif defined ( __CSMC__ )
mohamedmoawya 0:e4c5e6ec922e 109 #if ( __CSMC__ & 0x400U)
mohamedmoawya 0:e4c5e6ec922e 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mohamedmoawya 0:e4c5e6ec922e 111 #endif
mohamedmoawya 0:e4c5e6ec922e 112
mohamedmoawya 0:e4c5e6ec922e 113 #endif
mohamedmoawya 0:e4c5e6ec922e 114
mohamedmoawya 0:e4c5e6ec922e 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
mohamedmoawya 0:e4c5e6ec922e 116
mohamedmoawya 0:e4c5e6ec922e 117
mohamedmoawya 0:e4c5e6ec922e 118 #ifdef __cplusplus
mohamedmoawya 0:e4c5e6ec922e 119 }
mohamedmoawya 0:e4c5e6ec922e 120 #endif
mohamedmoawya 0:e4c5e6ec922e 121
mohamedmoawya 0:e4c5e6ec922e 122 #endif /* __CORE_SC000_H_GENERIC */
mohamedmoawya 0:e4c5e6ec922e 123
mohamedmoawya 0:e4c5e6ec922e 124 #ifndef __CMSIS_GENERIC
mohamedmoawya 0:e4c5e6ec922e 125
mohamedmoawya 0:e4c5e6ec922e 126 #ifndef __CORE_SC000_H_DEPENDANT
mohamedmoawya 0:e4c5e6ec922e 127 #define __CORE_SC000_H_DEPENDANT
mohamedmoawya 0:e4c5e6ec922e 128
mohamedmoawya 0:e4c5e6ec922e 129 #ifdef __cplusplus
mohamedmoawya 0:e4c5e6ec922e 130 extern "C" {
mohamedmoawya 0:e4c5e6ec922e 131 #endif
mohamedmoawya 0:e4c5e6ec922e 132
mohamedmoawya 0:e4c5e6ec922e 133 /* check device defines and use defaults */
mohamedmoawya 0:e4c5e6ec922e 134 #if defined __CHECK_DEVICE_DEFINES
mohamedmoawya 0:e4c5e6ec922e 135 #ifndef __SC000_REV
mohamedmoawya 0:e4c5e6ec922e 136 #define __SC000_REV 0x0000U
mohamedmoawya 0:e4c5e6ec922e 137 #warning "__SC000_REV not defined in device header file; using default!"
mohamedmoawya 0:e4c5e6ec922e 138 #endif
mohamedmoawya 0:e4c5e6ec922e 139
mohamedmoawya 0:e4c5e6ec922e 140 #ifndef __MPU_PRESENT
mohamedmoawya 0:e4c5e6ec922e 141 #define __MPU_PRESENT 0U
mohamedmoawya 0:e4c5e6ec922e 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
mohamedmoawya 0:e4c5e6ec922e 143 #endif
mohamedmoawya 0:e4c5e6ec922e 144
mohamedmoawya 0:e4c5e6ec922e 145 #ifndef __NVIC_PRIO_BITS
mohamedmoawya 0:e4c5e6ec922e 146 #define __NVIC_PRIO_BITS 2U
mohamedmoawya 0:e4c5e6ec922e 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mohamedmoawya 0:e4c5e6ec922e 148 #endif
mohamedmoawya 0:e4c5e6ec922e 149
mohamedmoawya 0:e4c5e6ec922e 150 #ifndef __Vendor_SysTickConfig
mohamedmoawya 0:e4c5e6ec922e 151 #define __Vendor_SysTickConfig 0U
mohamedmoawya 0:e4c5e6ec922e 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mohamedmoawya 0:e4c5e6ec922e 153 #endif
mohamedmoawya 0:e4c5e6ec922e 154 #endif
mohamedmoawya 0:e4c5e6ec922e 155
mohamedmoawya 0:e4c5e6ec922e 156 /* IO definitions (access restrictions to peripheral registers) */
mohamedmoawya 0:e4c5e6ec922e 157 /**
mohamedmoawya 0:e4c5e6ec922e 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
mohamedmoawya 0:e4c5e6ec922e 159
mohamedmoawya 0:e4c5e6ec922e 160 <strong>IO Type Qualifiers</strong> are used
mohamedmoawya 0:e4c5e6ec922e 161 \li to specify the access to peripheral variables.
mohamedmoawya 0:e4c5e6ec922e 162 \li for automatic generation of peripheral register debug information.
mohamedmoawya 0:e4c5e6ec922e 163 */
mohamedmoawya 0:e4c5e6ec922e 164 #ifdef __cplusplus
mohamedmoawya 0:e4c5e6ec922e 165 #define __I volatile /*!< Defines 'read only' permissions */
mohamedmoawya 0:e4c5e6ec922e 166 #else
mohamedmoawya 0:e4c5e6ec922e 167 #define __I volatile const /*!< Defines 'read only' permissions */
mohamedmoawya 0:e4c5e6ec922e 168 #endif
mohamedmoawya 0:e4c5e6ec922e 169 #define __O volatile /*!< Defines 'write only' permissions */
mohamedmoawya 0:e4c5e6ec922e 170 #define __IO volatile /*!< Defines 'read / write' permissions */
mohamedmoawya 0:e4c5e6ec922e 171
mohamedmoawya 0:e4c5e6ec922e 172 /* following defines should be used for structure members */
mohamedmoawya 0:e4c5e6ec922e 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
mohamedmoawya 0:e4c5e6ec922e 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
mohamedmoawya 0:e4c5e6ec922e 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
mohamedmoawya 0:e4c5e6ec922e 176
mohamedmoawya 0:e4c5e6ec922e 177 /*@} end of group SC000 */
mohamedmoawya 0:e4c5e6ec922e 178
mohamedmoawya 0:e4c5e6ec922e 179
mohamedmoawya 0:e4c5e6ec922e 180
mohamedmoawya 0:e4c5e6ec922e 181 /*******************************************************************************
mohamedmoawya 0:e4c5e6ec922e 182 * Register Abstraction
mohamedmoawya 0:e4c5e6ec922e 183 Core Register contain:
mohamedmoawya 0:e4c5e6ec922e 184 - Core Register
mohamedmoawya 0:e4c5e6ec922e 185 - Core NVIC Register
mohamedmoawya 0:e4c5e6ec922e 186 - Core SCB Register
mohamedmoawya 0:e4c5e6ec922e 187 - Core SysTick Register
mohamedmoawya 0:e4c5e6ec922e 188 - Core MPU Register
mohamedmoawya 0:e4c5e6ec922e 189 ******************************************************************************/
mohamedmoawya 0:e4c5e6ec922e 190 /**
mohamedmoawya 0:e4c5e6ec922e 191 \defgroup CMSIS_core_register Defines and Type Definitions
mohamedmoawya 0:e4c5e6ec922e 192 \brief Type definitions and defines for Cortex-M processor based devices.
mohamedmoawya 0:e4c5e6ec922e 193 */
mohamedmoawya 0:e4c5e6ec922e 194
mohamedmoawya 0:e4c5e6ec922e 195 /**
mohamedmoawya 0:e4c5e6ec922e 196 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 197 \defgroup CMSIS_CORE Status and Control Registers
mohamedmoawya 0:e4c5e6ec922e 198 \brief Core Register type definitions.
mohamedmoawya 0:e4c5e6ec922e 199 @{
mohamedmoawya 0:e4c5e6ec922e 200 */
mohamedmoawya 0:e4c5e6ec922e 201
mohamedmoawya 0:e4c5e6ec922e 202 /**
mohamedmoawya 0:e4c5e6ec922e 203 \brief Union type to access the Application Program Status Register (APSR).
mohamedmoawya 0:e4c5e6ec922e 204 */
mohamedmoawya 0:e4c5e6ec922e 205 typedef union
mohamedmoawya 0:e4c5e6ec922e 206 {
mohamedmoawya 0:e4c5e6ec922e 207 struct
mohamedmoawya 0:e4c5e6ec922e 208 {
mohamedmoawya 0:e4c5e6ec922e 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mohamedmoawya 0:e4c5e6ec922e 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mohamedmoawya 0:e4c5e6ec922e 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mohamedmoawya 0:e4c5e6ec922e 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mohamedmoawya 0:e4c5e6ec922e 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mohamedmoawya 0:e4c5e6ec922e 214 } b; /*!< Structure used for bit access */
mohamedmoawya 0:e4c5e6ec922e 215 uint32_t w; /*!< Type used for word access */
mohamedmoawya 0:e4c5e6ec922e 216 } APSR_Type;
mohamedmoawya 0:e4c5e6ec922e 217
mohamedmoawya 0:e4c5e6ec922e 218 /* APSR Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
mohamedmoawya 0:e4c5e6ec922e 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mohamedmoawya 0:e4c5e6ec922e 221
mohamedmoawya 0:e4c5e6ec922e 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
mohamedmoawya 0:e4c5e6ec922e 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mohamedmoawya 0:e4c5e6ec922e 224
mohamedmoawya 0:e4c5e6ec922e 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
mohamedmoawya 0:e4c5e6ec922e 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mohamedmoawya 0:e4c5e6ec922e 227
mohamedmoawya 0:e4c5e6ec922e 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
mohamedmoawya 0:e4c5e6ec922e 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mohamedmoawya 0:e4c5e6ec922e 230
mohamedmoawya 0:e4c5e6ec922e 231
mohamedmoawya 0:e4c5e6ec922e 232 /**
mohamedmoawya 0:e4c5e6ec922e 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
mohamedmoawya 0:e4c5e6ec922e 234 */
mohamedmoawya 0:e4c5e6ec922e 235 typedef union
mohamedmoawya 0:e4c5e6ec922e 236 {
mohamedmoawya 0:e4c5e6ec922e 237 struct
mohamedmoawya 0:e4c5e6ec922e 238 {
mohamedmoawya 0:e4c5e6ec922e 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mohamedmoawya 0:e4c5e6ec922e 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mohamedmoawya 0:e4c5e6ec922e 241 } b; /*!< Structure used for bit access */
mohamedmoawya 0:e4c5e6ec922e 242 uint32_t w; /*!< Type used for word access */
mohamedmoawya 0:e4c5e6ec922e 243 } IPSR_Type;
mohamedmoawya 0:e4c5e6ec922e 244
mohamedmoawya 0:e4c5e6ec922e 245 /* IPSR Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
mohamedmoawya 0:e4c5e6ec922e 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mohamedmoawya 0:e4c5e6ec922e 248
mohamedmoawya 0:e4c5e6ec922e 249
mohamedmoawya 0:e4c5e6ec922e 250 /**
mohamedmoawya 0:e4c5e6ec922e 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mohamedmoawya 0:e4c5e6ec922e 252 */
mohamedmoawya 0:e4c5e6ec922e 253 typedef union
mohamedmoawya 0:e4c5e6ec922e 254 {
mohamedmoawya 0:e4c5e6ec922e 255 struct
mohamedmoawya 0:e4c5e6ec922e 256 {
mohamedmoawya 0:e4c5e6ec922e 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mohamedmoawya 0:e4c5e6ec922e 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mohamedmoawya 0:e4c5e6ec922e 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mohamedmoawya 0:e4c5e6ec922e 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mohamedmoawya 0:e4c5e6ec922e 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mohamedmoawya 0:e4c5e6ec922e 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mohamedmoawya 0:e4c5e6ec922e 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mohamedmoawya 0:e4c5e6ec922e 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mohamedmoawya 0:e4c5e6ec922e 265 } b; /*!< Structure used for bit access */
mohamedmoawya 0:e4c5e6ec922e 266 uint32_t w; /*!< Type used for word access */
mohamedmoawya 0:e4c5e6ec922e 267 } xPSR_Type;
mohamedmoawya 0:e4c5e6ec922e 268
mohamedmoawya 0:e4c5e6ec922e 269 /* xPSR Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
mohamedmoawya 0:e4c5e6ec922e 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mohamedmoawya 0:e4c5e6ec922e 272
mohamedmoawya 0:e4c5e6ec922e 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
mohamedmoawya 0:e4c5e6ec922e 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mohamedmoawya 0:e4c5e6ec922e 275
mohamedmoawya 0:e4c5e6ec922e 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
mohamedmoawya 0:e4c5e6ec922e 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mohamedmoawya 0:e4c5e6ec922e 278
mohamedmoawya 0:e4c5e6ec922e 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
mohamedmoawya 0:e4c5e6ec922e 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mohamedmoawya 0:e4c5e6ec922e 281
mohamedmoawya 0:e4c5e6ec922e 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
mohamedmoawya 0:e4c5e6ec922e 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mohamedmoawya 0:e4c5e6ec922e 284
mohamedmoawya 0:e4c5e6ec922e 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
mohamedmoawya 0:e4c5e6ec922e 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mohamedmoawya 0:e4c5e6ec922e 287
mohamedmoawya 0:e4c5e6ec922e 288
mohamedmoawya 0:e4c5e6ec922e 289 /**
mohamedmoawya 0:e4c5e6ec922e 290 \brief Union type to access the Control Registers (CONTROL).
mohamedmoawya 0:e4c5e6ec922e 291 */
mohamedmoawya 0:e4c5e6ec922e 292 typedef union
mohamedmoawya 0:e4c5e6ec922e 293 {
mohamedmoawya 0:e4c5e6ec922e 294 struct
mohamedmoawya 0:e4c5e6ec922e 295 {
mohamedmoawya 0:e4c5e6ec922e 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
mohamedmoawya 0:e4c5e6ec922e 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mohamedmoawya 0:e4c5e6ec922e 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mohamedmoawya 0:e4c5e6ec922e 299 } b; /*!< Structure used for bit access */
mohamedmoawya 0:e4c5e6ec922e 300 uint32_t w; /*!< Type used for word access */
mohamedmoawya 0:e4c5e6ec922e 301 } CONTROL_Type;
mohamedmoawya 0:e4c5e6ec922e 302
mohamedmoawya 0:e4c5e6ec922e 303 /* CONTROL Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
mohamedmoawya 0:e4c5e6ec922e 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mohamedmoawya 0:e4c5e6ec922e 306
mohamedmoawya 0:e4c5e6ec922e 307 /*@} end of group CMSIS_CORE */
mohamedmoawya 0:e4c5e6ec922e 308
mohamedmoawya 0:e4c5e6ec922e 309
mohamedmoawya 0:e4c5e6ec922e 310 /**
mohamedmoawya 0:e4c5e6ec922e 311 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mohamedmoawya 0:e4c5e6ec922e 313 \brief Type definitions for the NVIC Registers
mohamedmoawya 0:e4c5e6ec922e 314 @{
mohamedmoawya 0:e4c5e6ec922e 315 */
mohamedmoawya 0:e4c5e6ec922e 316
mohamedmoawya 0:e4c5e6ec922e 317 /**
mohamedmoawya 0:e4c5e6ec922e 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mohamedmoawya 0:e4c5e6ec922e 319 */
mohamedmoawya 0:e4c5e6ec922e 320 typedef struct
mohamedmoawya 0:e4c5e6ec922e 321 {
mohamedmoawya 0:e4c5e6ec922e 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mohamedmoawya 0:e4c5e6ec922e 323 uint32_t RESERVED0[31U];
mohamedmoawya 0:e4c5e6ec922e 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mohamedmoawya 0:e4c5e6ec922e 325 uint32_t RSERVED1[31U];
mohamedmoawya 0:e4c5e6ec922e 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mohamedmoawya 0:e4c5e6ec922e 327 uint32_t RESERVED2[31U];
mohamedmoawya 0:e4c5e6ec922e 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mohamedmoawya 0:e4c5e6ec922e 329 uint32_t RESERVED3[31U];
mohamedmoawya 0:e4c5e6ec922e 330 uint32_t RESERVED4[64U];
mohamedmoawya 0:e4c5e6ec922e 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mohamedmoawya 0:e4c5e6ec922e 332 } NVIC_Type;
mohamedmoawya 0:e4c5e6ec922e 333
mohamedmoawya 0:e4c5e6ec922e 334 /*@} end of group CMSIS_NVIC */
mohamedmoawya 0:e4c5e6ec922e 335
mohamedmoawya 0:e4c5e6ec922e 336
mohamedmoawya 0:e4c5e6ec922e 337 /**
mohamedmoawya 0:e4c5e6ec922e 338 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 339 \defgroup CMSIS_SCB System Control Block (SCB)
mohamedmoawya 0:e4c5e6ec922e 340 \brief Type definitions for the System Control Block Registers
mohamedmoawya 0:e4c5e6ec922e 341 @{
mohamedmoawya 0:e4c5e6ec922e 342 */
mohamedmoawya 0:e4c5e6ec922e 343
mohamedmoawya 0:e4c5e6ec922e 344 /**
mohamedmoawya 0:e4c5e6ec922e 345 \brief Structure type to access the System Control Block (SCB).
mohamedmoawya 0:e4c5e6ec922e 346 */
mohamedmoawya 0:e4c5e6ec922e 347 typedef struct
mohamedmoawya 0:e4c5e6ec922e 348 {
mohamedmoawya 0:e4c5e6ec922e 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mohamedmoawya 0:e4c5e6ec922e 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mohamedmoawya 0:e4c5e6ec922e 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mohamedmoawya 0:e4c5e6ec922e 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mohamedmoawya 0:e4c5e6ec922e 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mohamedmoawya 0:e4c5e6ec922e 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mohamedmoawya 0:e4c5e6ec922e 355 uint32_t RESERVED0[1U];
mohamedmoawya 0:e4c5e6ec922e 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mohamedmoawya 0:e4c5e6ec922e 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mohamedmoawya 0:e4c5e6ec922e 358 uint32_t RESERVED1[154U];
mohamedmoawya 0:e4c5e6ec922e 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
mohamedmoawya 0:e4c5e6ec922e 360 } SCB_Type;
mohamedmoawya 0:e4c5e6ec922e 361
mohamedmoawya 0:e4c5e6ec922e 362 /* SCB CPUID Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
mohamedmoawya 0:e4c5e6ec922e 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mohamedmoawya 0:e4c5e6ec922e 365
mohamedmoawya 0:e4c5e6ec922e 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
mohamedmoawya 0:e4c5e6ec922e 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mohamedmoawya 0:e4c5e6ec922e 368
mohamedmoawya 0:e4c5e6ec922e 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
mohamedmoawya 0:e4c5e6ec922e 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mohamedmoawya 0:e4c5e6ec922e 371
mohamedmoawya 0:e4c5e6ec922e 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
mohamedmoawya 0:e4c5e6ec922e 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mohamedmoawya 0:e4c5e6ec922e 374
mohamedmoawya 0:e4c5e6ec922e 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
mohamedmoawya 0:e4c5e6ec922e 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mohamedmoawya 0:e4c5e6ec922e 377
mohamedmoawya 0:e4c5e6ec922e 378 /* SCB Interrupt Control State Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
mohamedmoawya 0:e4c5e6ec922e 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mohamedmoawya 0:e4c5e6ec922e 381
mohamedmoawya 0:e4c5e6ec922e 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
mohamedmoawya 0:e4c5e6ec922e 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mohamedmoawya 0:e4c5e6ec922e 384
mohamedmoawya 0:e4c5e6ec922e 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
mohamedmoawya 0:e4c5e6ec922e 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mohamedmoawya 0:e4c5e6ec922e 387
mohamedmoawya 0:e4c5e6ec922e 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
mohamedmoawya 0:e4c5e6ec922e 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mohamedmoawya 0:e4c5e6ec922e 390
mohamedmoawya 0:e4c5e6ec922e 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
mohamedmoawya 0:e4c5e6ec922e 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mohamedmoawya 0:e4c5e6ec922e 393
mohamedmoawya 0:e4c5e6ec922e 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
mohamedmoawya 0:e4c5e6ec922e 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mohamedmoawya 0:e4c5e6ec922e 396
mohamedmoawya 0:e4c5e6ec922e 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
mohamedmoawya 0:e4c5e6ec922e 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mohamedmoawya 0:e4c5e6ec922e 399
mohamedmoawya 0:e4c5e6ec922e 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
mohamedmoawya 0:e4c5e6ec922e 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mohamedmoawya 0:e4c5e6ec922e 402
mohamedmoawya 0:e4c5e6ec922e 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
mohamedmoawya 0:e4c5e6ec922e 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mohamedmoawya 0:e4c5e6ec922e 405
mohamedmoawya 0:e4c5e6ec922e 406 /* SCB Interrupt Control State Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
mohamedmoawya 0:e4c5e6ec922e 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mohamedmoawya 0:e4c5e6ec922e 409
mohamedmoawya 0:e4c5e6ec922e 410 /* SCB Application Interrupt and Reset Control Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
mohamedmoawya 0:e4c5e6ec922e 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mohamedmoawya 0:e4c5e6ec922e 413
mohamedmoawya 0:e4c5e6ec922e 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
mohamedmoawya 0:e4c5e6ec922e 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mohamedmoawya 0:e4c5e6ec922e 416
mohamedmoawya 0:e4c5e6ec922e 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
mohamedmoawya 0:e4c5e6ec922e 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mohamedmoawya 0:e4c5e6ec922e 419
mohamedmoawya 0:e4c5e6ec922e 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
mohamedmoawya 0:e4c5e6ec922e 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mohamedmoawya 0:e4c5e6ec922e 422
mohamedmoawya 0:e4c5e6ec922e 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
mohamedmoawya 0:e4c5e6ec922e 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mohamedmoawya 0:e4c5e6ec922e 425
mohamedmoawya 0:e4c5e6ec922e 426 /* SCB System Control Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
mohamedmoawya 0:e4c5e6ec922e 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mohamedmoawya 0:e4c5e6ec922e 429
mohamedmoawya 0:e4c5e6ec922e 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
mohamedmoawya 0:e4c5e6ec922e 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mohamedmoawya 0:e4c5e6ec922e 432
mohamedmoawya 0:e4c5e6ec922e 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
mohamedmoawya 0:e4c5e6ec922e 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mohamedmoawya 0:e4c5e6ec922e 435
mohamedmoawya 0:e4c5e6ec922e 436 /* SCB Configuration Control Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
mohamedmoawya 0:e4c5e6ec922e 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mohamedmoawya 0:e4c5e6ec922e 439
mohamedmoawya 0:e4c5e6ec922e 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
mohamedmoawya 0:e4c5e6ec922e 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mohamedmoawya 0:e4c5e6ec922e 442
mohamedmoawya 0:e4c5e6ec922e 443 /* SCB System Handler Control and State Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
mohamedmoawya 0:e4c5e6ec922e 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mohamedmoawya 0:e4c5e6ec922e 446
mohamedmoawya 0:e4c5e6ec922e 447 /*@} end of group CMSIS_SCB */
mohamedmoawya 0:e4c5e6ec922e 448
mohamedmoawya 0:e4c5e6ec922e 449
mohamedmoawya 0:e4c5e6ec922e 450 /**
mohamedmoawya 0:e4c5e6ec922e 451 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mohamedmoawya 0:e4c5e6ec922e 453 \brief Type definitions for the System Control and ID Register not in the SCB
mohamedmoawya 0:e4c5e6ec922e 454 @{
mohamedmoawya 0:e4c5e6ec922e 455 */
mohamedmoawya 0:e4c5e6ec922e 456
mohamedmoawya 0:e4c5e6ec922e 457 /**
mohamedmoawya 0:e4c5e6ec922e 458 \brief Structure type to access the System Control and ID Register not in the SCB.
mohamedmoawya 0:e4c5e6ec922e 459 */
mohamedmoawya 0:e4c5e6ec922e 460 typedef struct
mohamedmoawya 0:e4c5e6ec922e 461 {
mohamedmoawya 0:e4c5e6ec922e 462 uint32_t RESERVED0[2U];
mohamedmoawya 0:e4c5e6ec922e 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mohamedmoawya 0:e4c5e6ec922e 464 } SCnSCB_Type;
mohamedmoawya 0:e4c5e6ec922e 465
mohamedmoawya 0:e4c5e6ec922e 466 /* Auxiliary Control Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
mohamedmoawya 0:e4c5e6ec922e 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mohamedmoawya 0:e4c5e6ec922e 469
mohamedmoawya 0:e4c5e6ec922e 470 /*@} end of group CMSIS_SCnotSCB */
mohamedmoawya 0:e4c5e6ec922e 471
mohamedmoawya 0:e4c5e6ec922e 472
mohamedmoawya 0:e4c5e6ec922e 473 /**
mohamedmoawya 0:e4c5e6ec922e 474 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mohamedmoawya 0:e4c5e6ec922e 476 \brief Type definitions for the System Timer Registers.
mohamedmoawya 0:e4c5e6ec922e 477 @{
mohamedmoawya 0:e4c5e6ec922e 478 */
mohamedmoawya 0:e4c5e6ec922e 479
mohamedmoawya 0:e4c5e6ec922e 480 /**
mohamedmoawya 0:e4c5e6ec922e 481 \brief Structure type to access the System Timer (SysTick).
mohamedmoawya 0:e4c5e6ec922e 482 */
mohamedmoawya 0:e4c5e6ec922e 483 typedef struct
mohamedmoawya 0:e4c5e6ec922e 484 {
mohamedmoawya 0:e4c5e6ec922e 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mohamedmoawya 0:e4c5e6ec922e 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mohamedmoawya 0:e4c5e6ec922e 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mohamedmoawya 0:e4c5e6ec922e 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mohamedmoawya 0:e4c5e6ec922e 489 } SysTick_Type;
mohamedmoawya 0:e4c5e6ec922e 490
mohamedmoawya 0:e4c5e6ec922e 491 /* SysTick Control / Status Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
mohamedmoawya 0:e4c5e6ec922e 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mohamedmoawya 0:e4c5e6ec922e 494
mohamedmoawya 0:e4c5e6ec922e 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
mohamedmoawya 0:e4c5e6ec922e 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mohamedmoawya 0:e4c5e6ec922e 497
mohamedmoawya 0:e4c5e6ec922e 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
mohamedmoawya 0:e4c5e6ec922e 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mohamedmoawya 0:e4c5e6ec922e 500
mohamedmoawya 0:e4c5e6ec922e 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
mohamedmoawya 0:e4c5e6ec922e 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mohamedmoawya 0:e4c5e6ec922e 503
mohamedmoawya 0:e4c5e6ec922e 504 /* SysTick Reload Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
mohamedmoawya 0:e4c5e6ec922e 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mohamedmoawya 0:e4c5e6ec922e 507
mohamedmoawya 0:e4c5e6ec922e 508 /* SysTick Current Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
mohamedmoawya 0:e4c5e6ec922e 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mohamedmoawya 0:e4c5e6ec922e 511
mohamedmoawya 0:e4c5e6ec922e 512 /* SysTick Calibration Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
mohamedmoawya 0:e4c5e6ec922e 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mohamedmoawya 0:e4c5e6ec922e 515
mohamedmoawya 0:e4c5e6ec922e 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
mohamedmoawya 0:e4c5e6ec922e 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mohamedmoawya 0:e4c5e6ec922e 518
mohamedmoawya 0:e4c5e6ec922e 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
mohamedmoawya 0:e4c5e6ec922e 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mohamedmoawya 0:e4c5e6ec922e 521
mohamedmoawya 0:e4c5e6ec922e 522 /*@} end of group CMSIS_SysTick */
mohamedmoawya 0:e4c5e6ec922e 523
mohamedmoawya 0:e4c5e6ec922e 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mohamedmoawya 0:e4c5e6ec922e 525 /**
mohamedmoawya 0:e4c5e6ec922e 526 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mohamedmoawya 0:e4c5e6ec922e 528 \brief Type definitions for the Memory Protection Unit (MPU)
mohamedmoawya 0:e4c5e6ec922e 529 @{
mohamedmoawya 0:e4c5e6ec922e 530 */
mohamedmoawya 0:e4c5e6ec922e 531
mohamedmoawya 0:e4c5e6ec922e 532 /**
mohamedmoawya 0:e4c5e6ec922e 533 \brief Structure type to access the Memory Protection Unit (MPU).
mohamedmoawya 0:e4c5e6ec922e 534 */
mohamedmoawya 0:e4c5e6ec922e 535 typedef struct
mohamedmoawya 0:e4c5e6ec922e 536 {
mohamedmoawya 0:e4c5e6ec922e 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mohamedmoawya 0:e4c5e6ec922e 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mohamedmoawya 0:e4c5e6ec922e 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mohamedmoawya 0:e4c5e6ec922e 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mohamedmoawya 0:e4c5e6ec922e 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mohamedmoawya 0:e4c5e6ec922e 542 } MPU_Type;
mohamedmoawya 0:e4c5e6ec922e 543
mohamedmoawya 0:e4c5e6ec922e 544 /* MPU Type Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
mohamedmoawya 0:e4c5e6ec922e 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mohamedmoawya 0:e4c5e6ec922e 547
mohamedmoawya 0:e4c5e6ec922e 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
mohamedmoawya 0:e4c5e6ec922e 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mohamedmoawya 0:e4c5e6ec922e 550
mohamedmoawya 0:e4c5e6ec922e 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
mohamedmoawya 0:e4c5e6ec922e 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mohamedmoawya 0:e4c5e6ec922e 553
mohamedmoawya 0:e4c5e6ec922e 554 /* MPU Control Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
mohamedmoawya 0:e4c5e6ec922e 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mohamedmoawya 0:e4c5e6ec922e 557
mohamedmoawya 0:e4c5e6ec922e 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
mohamedmoawya 0:e4c5e6ec922e 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mohamedmoawya 0:e4c5e6ec922e 560
mohamedmoawya 0:e4c5e6ec922e 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
mohamedmoawya 0:e4c5e6ec922e 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mohamedmoawya 0:e4c5e6ec922e 563
mohamedmoawya 0:e4c5e6ec922e 564 /* MPU Region Number Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
mohamedmoawya 0:e4c5e6ec922e 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mohamedmoawya 0:e4c5e6ec922e 567
mohamedmoawya 0:e4c5e6ec922e 568 /* MPU Region Base Address Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
mohamedmoawya 0:e4c5e6ec922e 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mohamedmoawya 0:e4c5e6ec922e 571
mohamedmoawya 0:e4c5e6ec922e 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
mohamedmoawya 0:e4c5e6ec922e 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mohamedmoawya 0:e4c5e6ec922e 574
mohamedmoawya 0:e4c5e6ec922e 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
mohamedmoawya 0:e4c5e6ec922e 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mohamedmoawya 0:e4c5e6ec922e 577
mohamedmoawya 0:e4c5e6ec922e 578 /* MPU Region Attribute and Size Register Definitions */
mohamedmoawya 0:e4c5e6ec922e 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
mohamedmoawya 0:e4c5e6ec922e 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mohamedmoawya 0:e4c5e6ec922e 581
mohamedmoawya 0:e4c5e6ec922e 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
mohamedmoawya 0:e4c5e6ec922e 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mohamedmoawya 0:e4c5e6ec922e 584
mohamedmoawya 0:e4c5e6ec922e 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
mohamedmoawya 0:e4c5e6ec922e 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mohamedmoawya 0:e4c5e6ec922e 587
mohamedmoawya 0:e4c5e6ec922e 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
mohamedmoawya 0:e4c5e6ec922e 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mohamedmoawya 0:e4c5e6ec922e 590
mohamedmoawya 0:e4c5e6ec922e 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
mohamedmoawya 0:e4c5e6ec922e 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mohamedmoawya 0:e4c5e6ec922e 593
mohamedmoawya 0:e4c5e6ec922e 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
mohamedmoawya 0:e4c5e6ec922e 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mohamedmoawya 0:e4c5e6ec922e 596
mohamedmoawya 0:e4c5e6ec922e 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
mohamedmoawya 0:e4c5e6ec922e 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mohamedmoawya 0:e4c5e6ec922e 599
mohamedmoawya 0:e4c5e6ec922e 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
mohamedmoawya 0:e4c5e6ec922e 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mohamedmoawya 0:e4c5e6ec922e 602
mohamedmoawya 0:e4c5e6ec922e 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
mohamedmoawya 0:e4c5e6ec922e 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mohamedmoawya 0:e4c5e6ec922e 605
mohamedmoawya 0:e4c5e6ec922e 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
mohamedmoawya 0:e4c5e6ec922e 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mohamedmoawya 0:e4c5e6ec922e 608
mohamedmoawya 0:e4c5e6ec922e 609 /*@} end of group CMSIS_MPU */
mohamedmoawya 0:e4c5e6ec922e 610 #endif
mohamedmoawya 0:e4c5e6ec922e 611
mohamedmoawya 0:e4c5e6ec922e 612
mohamedmoawya 0:e4c5e6ec922e 613 /**
mohamedmoawya 0:e4c5e6ec922e 614 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mohamedmoawya 0:e4c5e6ec922e 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
mohamedmoawya 0:e4c5e6ec922e 617 Therefore they are not covered by the SC000 header file.
mohamedmoawya 0:e4c5e6ec922e 618 @{
mohamedmoawya 0:e4c5e6ec922e 619 */
mohamedmoawya 0:e4c5e6ec922e 620 /*@} end of group CMSIS_CoreDebug */
mohamedmoawya 0:e4c5e6ec922e 621
mohamedmoawya 0:e4c5e6ec922e 622
mohamedmoawya 0:e4c5e6ec922e 623 /**
mohamedmoawya 0:e4c5e6ec922e 624 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 625 \defgroup CMSIS_core_bitfield Core register bit field macros
mohamedmoawya 0:e4c5e6ec922e 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mohamedmoawya 0:e4c5e6ec922e 627 @{
mohamedmoawya 0:e4c5e6ec922e 628 */
mohamedmoawya 0:e4c5e6ec922e 629
mohamedmoawya 0:e4c5e6ec922e 630 /**
mohamedmoawya 0:e4c5e6ec922e 631 \brief Mask and shift a bit field value for use in a register bit range.
mohamedmoawya 0:e4c5e6ec922e 632 \param[in] field Name of the register bit field.
mohamedmoawya 0:e4c5e6ec922e 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
mohamedmoawya 0:e4c5e6ec922e 634 \return Masked and shifted value.
mohamedmoawya 0:e4c5e6ec922e 635 */
mohamedmoawya 0:e4c5e6ec922e 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
mohamedmoawya 0:e4c5e6ec922e 637
mohamedmoawya 0:e4c5e6ec922e 638 /**
mohamedmoawya 0:e4c5e6ec922e 639 \brief Mask and shift a register value to extract a bit filed value.
mohamedmoawya 0:e4c5e6ec922e 640 \param[in] field Name of the register bit field.
mohamedmoawya 0:e4c5e6ec922e 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
mohamedmoawya 0:e4c5e6ec922e 642 \return Masked and shifted bit field value.
mohamedmoawya 0:e4c5e6ec922e 643 */
mohamedmoawya 0:e4c5e6ec922e 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
mohamedmoawya 0:e4c5e6ec922e 645
mohamedmoawya 0:e4c5e6ec922e 646 /*@} end of group CMSIS_core_bitfield */
mohamedmoawya 0:e4c5e6ec922e 647
mohamedmoawya 0:e4c5e6ec922e 648
mohamedmoawya 0:e4c5e6ec922e 649 /**
mohamedmoawya 0:e4c5e6ec922e 650 \ingroup CMSIS_core_register
mohamedmoawya 0:e4c5e6ec922e 651 \defgroup CMSIS_core_base Core Definitions
mohamedmoawya 0:e4c5e6ec922e 652 \brief Definitions for base addresses, unions, and structures.
mohamedmoawya 0:e4c5e6ec922e 653 @{
mohamedmoawya 0:e4c5e6ec922e 654 */
mohamedmoawya 0:e4c5e6ec922e 655
mohamedmoawya 0:e4c5e6ec922e 656 /* Memory mapping of Core Hardware */
mohamedmoawya 0:e4c5e6ec922e 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mohamedmoawya 0:e4c5e6ec922e 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mohamedmoawya 0:e4c5e6ec922e 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mohamedmoawya 0:e4c5e6ec922e 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mohamedmoawya 0:e4c5e6ec922e 661
mohamedmoawya 0:e4c5e6ec922e 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mohamedmoawya 0:e4c5e6ec922e 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mohamedmoawya 0:e4c5e6ec922e 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mohamedmoawya 0:e4c5e6ec922e 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mohamedmoawya 0:e4c5e6ec922e 666
mohamedmoawya 0:e4c5e6ec922e 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
mohamedmoawya 0:e4c5e6ec922e 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mohamedmoawya 0:e4c5e6ec922e 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mohamedmoawya 0:e4c5e6ec922e 670 #endif
mohamedmoawya 0:e4c5e6ec922e 671
mohamedmoawya 0:e4c5e6ec922e 672 /*@} */
mohamedmoawya 0:e4c5e6ec922e 673
mohamedmoawya 0:e4c5e6ec922e 674
mohamedmoawya 0:e4c5e6ec922e 675
mohamedmoawya 0:e4c5e6ec922e 676 /*******************************************************************************
mohamedmoawya 0:e4c5e6ec922e 677 * Hardware Abstraction Layer
mohamedmoawya 0:e4c5e6ec922e 678 Core Function Interface contains:
mohamedmoawya 0:e4c5e6ec922e 679 - Core NVIC Functions
mohamedmoawya 0:e4c5e6ec922e 680 - Core SysTick Functions
mohamedmoawya 0:e4c5e6ec922e 681 - Core Register Access Functions
mohamedmoawya 0:e4c5e6ec922e 682 ******************************************************************************/
mohamedmoawya 0:e4c5e6ec922e 683 /**
mohamedmoawya 0:e4c5e6ec922e 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mohamedmoawya 0:e4c5e6ec922e 685 */
mohamedmoawya 0:e4c5e6ec922e 686
mohamedmoawya 0:e4c5e6ec922e 687
mohamedmoawya 0:e4c5e6ec922e 688
mohamedmoawya 0:e4c5e6ec922e 689 /* ########################## NVIC functions #################################### */
mohamedmoawya 0:e4c5e6ec922e 690 /**
mohamedmoawya 0:e4c5e6ec922e 691 \ingroup CMSIS_Core_FunctionInterface
mohamedmoawya 0:e4c5e6ec922e 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mohamedmoawya 0:e4c5e6ec922e 693 \brief Functions that manage interrupts and exceptions via the NVIC.
mohamedmoawya 0:e4c5e6ec922e 694 @{
mohamedmoawya 0:e4c5e6ec922e 695 */
mohamedmoawya 0:e4c5e6ec922e 696
mohamedmoawya 0:e4c5e6ec922e 697 #ifdef CMSIS_NVIC_VIRTUAL
mohamedmoawya 0:e4c5e6ec922e 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mohamedmoawya 0:e4c5e6ec922e 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mohamedmoawya 0:e4c5e6ec922e 700 #endif
mohamedmoawya 0:e4c5e6ec922e 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mohamedmoawya 0:e4c5e6ec922e 702 #else
mohamedmoawya 0:e4c5e6ec922e 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
mohamedmoawya 0:e4c5e6ec922e 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
mohamedmoawya 0:e4c5e6ec922e 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
mohamedmoawya 0:e4c5e6ec922e 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
mohamedmoawya 0:e4c5e6ec922e 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
mohamedmoawya 0:e4c5e6ec922e 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mohamedmoawya 0:e4c5e6ec922e 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mohamedmoawya 0:e4c5e6ec922e 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mohamedmoawya 0:e4c5e6ec922e 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
mohamedmoawya 0:e4c5e6ec922e 712 #define NVIC_SetPriority __NVIC_SetPriority
mohamedmoawya 0:e4c5e6ec922e 713 #define NVIC_GetPriority __NVIC_GetPriority
mohamedmoawya 0:e4c5e6ec922e 714 #define NVIC_SystemReset __NVIC_SystemReset
mohamedmoawya 0:e4c5e6ec922e 715 #endif /* CMSIS_NVIC_VIRTUAL */
mohamedmoawya 0:e4c5e6ec922e 716
mohamedmoawya 0:e4c5e6ec922e 717 #ifdef CMSIS_VECTAB_VIRTUAL
mohamedmoawya 0:e4c5e6ec922e 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mohamedmoawya 0:e4c5e6ec922e 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mohamedmoawya 0:e4c5e6ec922e 720 #endif
mohamedmoawya 0:e4c5e6ec922e 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mohamedmoawya 0:e4c5e6ec922e 722 #else
mohamedmoawya 0:e4c5e6ec922e 723 #define NVIC_SetVector __NVIC_SetVector
mohamedmoawya 0:e4c5e6ec922e 724 #define NVIC_GetVector __NVIC_GetVector
mohamedmoawya 0:e4c5e6ec922e 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
mohamedmoawya 0:e4c5e6ec922e 726
mohamedmoawya 0:e4c5e6ec922e 727 #define NVIC_USER_IRQ_OFFSET 16
mohamedmoawya 0:e4c5e6ec922e 728
mohamedmoawya 0:e4c5e6ec922e 729
mohamedmoawya 0:e4c5e6ec922e 730 /* The following EXC_RETURN values are saved the LR on exception entry */
mohamedmoawya 0:e4c5e6ec922e 731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
mohamedmoawya 0:e4c5e6ec922e 732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
mohamedmoawya 0:e4c5e6ec922e 733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
mohamedmoawya 0:e4c5e6ec922e 734
mohamedmoawya 0:e4c5e6ec922e 735
mohamedmoawya 0:e4c5e6ec922e 736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
mohamedmoawya 0:e4c5e6ec922e 737 /* The following MACROS handle generation of the register offset and byte masks */
mohamedmoawya 0:e4c5e6ec922e 738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mohamedmoawya 0:e4c5e6ec922e 739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mohamedmoawya 0:e4c5e6ec922e 740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mohamedmoawya 0:e4c5e6ec922e 741
mohamedmoawya 0:e4c5e6ec922e 742
mohamedmoawya 0:e4c5e6ec922e 743 /**
mohamedmoawya 0:e4c5e6ec922e 744 \brief Enable Interrupt
mohamedmoawya 0:e4c5e6ec922e 745 \details Enables a device specific interrupt in the NVIC interrupt controller.
mohamedmoawya 0:e4c5e6ec922e 746 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 747 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 748 */
mohamedmoawya 0:e4c5e6ec922e 749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 750 {
mohamedmoawya 0:e4c5e6ec922e 751 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 752 {
mohamedmoawya 0:e4c5e6ec922e 753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
mohamedmoawya 0:e4c5e6ec922e 754 }
mohamedmoawya 0:e4c5e6ec922e 755 }
mohamedmoawya 0:e4c5e6ec922e 756
mohamedmoawya 0:e4c5e6ec922e 757
mohamedmoawya 0:e4c5e6ec922e 758 /**
mohamedmoawya 0:e4c5e6ec922e 759 \brief Get Interrupt Enable status
mohamedmoawya 0:e4c5e6ec922e 760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
mohamedmoawya 0:e4c5e6ec922e 761 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 762 \return 0 Interrupt is not enabled.
mohamedmoawya 0:e4c5e6ec922e 763 \return 1 Interrupt is enabled.
mohamedmoawya 0:e4c5e6ec922e 764 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 765 */
mohamedmoawya 0:e4c5e6ec922e 766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 767 {
mohamedmoawya 0:e4c5e6ec922e 768 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 769 {
mohamedmoawya 0:e4c5e6ec922e 770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mohamedmoawya 0:e4c5e6ec922e 771 }
mohamedmoawya 0:e4c5e6ec922e 772 else
mohamedmoawya 0:e4c5e6ec922e 773 {
mohamedmoawya 0:e4c5e6ec922e 774 return(0U);
mohamedmoawya 0:e4c5e6ec922e 775 }
mohamedmoawya 0:e4c5e6ec922e 776 }
mohamedmoawya 0:e4c5e6ec922e 777
mohamedmoawya 0:e4c5e6ec922e 778
mohamedmoawya 0:e4c5e6ec922e 779 /**
mohamedmoawya 0:e4c5e6ec922e 780 \brief Disable Interrupt
mohamedmoawya 0:e4c5e6ec922e 781 \details Disables a device specific interrupt in the NVIC interrupt controller.
mohamedmoawya 0:e4c5e6ec922e 782 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 783 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 784 */
mohamedmoawya 0:e4c5e6ec922e 785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 786 {
mohamedmoawya 0:e4c5e6ec922e 787 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 788 {
mohamedmoawya 0:e4c5e6ec922e 789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
mohamedmoawya 0:e4c5e6ec922e 790 __DSB();
mohamedmoawya 0:e4c5e6ec922e 791 __ISB();
mohamedmoawya 0:e4c5e6ec922e 792 }
mohamedmoawya 0:e4c5e6ec922e 793 }
mohamedmoawya 0:e4c5e6ec922e 794
mohamedmoawya 0:e4c5e6ec922e 795
mohamedmoawya 0:e4c5e6ec922e 796 /**
mohamedmoawya 0:e4c5e6ec922e 797 \brief Get Pending Interrupt
mohamedmoawya 0:e4c5e6ec922e 798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
mohamedmoawya 0:e4c5e6ec922e 799 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 800 \return 0 Interrupt status is not pending.
mohamedmoawya 0:e4c5e6ec922e 801 \return 1 Interrupt status is pending.
mohamedmoawya 0:e4c5e6ec922e 802 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 803 */
mohamedmoawya 0:e4c5e6ec922e 804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 805 {
mohamedmoawya 0:e4c5e6ec922e 806 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 807 {
mohamedmoawya 0:e4c5e6ec922e 808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mohamedmoawya 0:e4c5e6ec922e 809 }
mohamedmoawya 0:e4c5e6ec922e 810 else
mohamedmoawya 0:e4c5e6ec922e 811 {
mohamedmoawya 0:e4c5e6ec922e 812 return(0U);
mohamedmoawya 0:e4c5e6ec922e 813 }
mohamedmoawya 0:e4c5e6ec922e 814 }
mohamedmoawya 0:e4c5e6ec922e 815
mohamedmoawya 0:e4c5e6ec922e 816
mohamedmoawya 0:e4c5e6ec922e 817 /**
mohamedmoawya 0:e4c5e6ec922e 818 \brief Set Pending Interrupt
mohamedmoawya 0:e4c5e6ec922e 819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
mohamedmoawya 0:e4c5e6ec922e 820 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 821 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 822 */
mohamedmoawya 0:e4c5e6ec922e 823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 824 {
mohamedmoawya 0:e4c5e6ec922e 825 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 826 {
mohamedmoawya 0:e4c5e6ec922e 827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
mohamedmoawya 0:e4c5e6ec922e 828 }
mohamedmoawya 0:e4c5e6ec922e 829 }
mohamedmoawya 0:e4c5e6ec922e 830
mohamedmoawya 0:e4c5e6ec922e 831
mohamedmoawya 0:e4c5e6ec922e 832 /**
mohamedmoawya 0:e4c5e6ec922e 833 \brief Clear Pending Interrupt
mohamedmoawya 0:e4c5e6ec922e 834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
mohamedmoawya 0:e4c5e6ec922e 835 \param [in] IRQn Device specific interrupt number.
mohamedmoawya 0:e4c5e6ec922e 836 \note IRQn must not be negative.
mohamedmoawya 0:e4c5e6ec922e 837 */
mohamedmoawya 0:e4c5e6ec922e 838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 839 {
mohamedmoawya 0:e4c5e6ec922e 840 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 841 {
mohamedmoawya 0:e4c5e6ec922e 842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
mohamedmoawya 0:e4c5e6ec922e 843 }
mohamedmoawya 0:e4c5e6ec922e 844 }
mohamedmoawya 0:e4c5e6ec922e 845
mohamedmoawya 0:e4c5e6ec922e 846
mohamedmoawya 0:e4c5e6ec922e 847 /**
mohamedmoawya 0:e4c5e6ec922e 848 \brief Set Interrupt Priority
mohamedmoawya 0:e4c5e6ec922e 849 \details Sets the priority of a device specific interrupt or a processor exception.
mohamedmoawya 0:e4c5e6ec922e 850 The interrupt number can be positive to specify a device specific interrupt,
mohamedmoawya 0:e4c5e6ec922e 851 or negative to specify a processor exception.
mohamedmoawya 0:e4c5e6ec922e 852 \param [in] IRQn Interrupt number.
mohamedmoawya 0:e4c5e6ec922e 853 \param [in] priority Priority to set.
mohamedmoawya 0:e4c5e6ec922e 854 \note The priority cannot be set for every processor exception.
mohamedmoawya 0:e4c5e6ec922e 855 */
mohamedmoawya 0:e4c5e6ec922e 856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mohamedmoawya 0:e4c5e6ec922e 857 {
mohamedmoawya 0:e4c5e6ec922e 858 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 859 {
mohamedmoawya 0:e4c5e6ec922e 860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mohamedmoawya 0:e4c5e6ec922e 861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mohamedmoawya 0:e4c5e6ec922e 862 }
mohamedmoawya 0:e4c5e6ec922e 863 else
mohamedmoawya 0:e4c5e6ec922e 864 {
mohamedmoawya 0:e4c5e6ec922e 865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mohamedmoawya 0:e4c5e6ec922e 866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mohamedmoawya 0:e4c5e6ec922e 867 }
mohamedmoawya 0:e4c5e6ec922e 868 }
mohamedmoawya 0:e4c5e6ec922e 869
mohamedmoawya 0:e4c5e6ec922e 870
mohamedmoawya 0:e4c5e6ec922e 871 /**
mohamedmoawya 0:e4c5e6ec922e 872 \brief Get Interrupt Priority
mohamedmoawya 0:e4c5e6ec922e 873 \details Reads the priority of a device specific interrupt or a processor exception.
mohamedmoawya 0:e4c5e6ec922e 874 The interrupt number can be positive to specify a device specific interrupt,
mohamedmoawya 0:e4c5e6ec922e 875 or negative to specify a processor exception.
mohamedmoawya 0:e4c5e6ec922e 876 \param [in] IRQn Interrupt number.
mohamedmoawya 0:e4c5e6ec922e 877 \return Interrupt Priority.
mohamedmoawya 0:e4c5e6ec922e 878 Value is aligned automatically to the implemented priority bits of the microcontroller.
mohamedmoawya 0:e4c5e6ec922e 879 */
mohamedmoawya 0:e4c5e6ec922e 880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 881 {
mohamedmoawya 0:e4c5e6ec922e 882
mohamedmoawya 0:e4c5e6ec922e 883 if ((int32_t)(IRQn) >= 0)
mohamedmoawya 0:e4c5e6ec922e 884 {
mohamedmoawya 0:e4c5e6ec922e 885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mohamedmoawya 0:e4c5e6ec922e 886 }
mohamedmoawya 0:e4c5e6ec922e 887 else
mohamedmoawya 0:e4c5e6ec922e 888 {
mohamedmoawya 0:e4c5e6ec922e 889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
mohamedmoawya 0:e4c5e6ec922e 890 }
mohamedmoawya 0:e4c5e6ec922e 891 }
mohamedmoawya 0:e4c5e6ec922e 892
mohamedmoawya 0:e4c5e6ec922e 893
mohamedmoawya 0:e4c5e6ec922e 894 /**
mohamedmoawya 0:e4c5e6ec922e 895 \brief Set Interrupt Vector
mohamedmoawya 0:e4c5e6ec922e 896 \details Sets an interrupt vector in SRAM based interrupt vector table.
mohamedmoawya 0:e4c5e6ec922e 897 The interrupt number can be positive to specify a device specific interrupt,
mohamedmoawya 0:e4c5e6ec922e 898 or negative to specify a processor exception.
mohamedmoawya 0:e4c5e6ec922e 899 VTOR must been relocated to SRAM before.
mohamedmoawya 0:e4c5e6ec922e 900 \param [in] IRQn Interrupt number
mohamedmoawya 0:e4c5e6ec922e 901 \param [in] vector Address of interrupt handler function
mohamedmoawya 0:e4c5e6ec922e 902 */
mohamedmoawya 0:e4c5e6ec922e 903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
mohamedmoawya 0:e4c5e6ec922e 904 {
mohamedmoawya 0:e4c5e6ec922e 905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mohamedmoawya 0:e4c5e6ec922e 906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
mohamedmoawya 0:e4c5e6ec922e 907 }
mohamedmoawya 0:e4c5e6ec922e 908
mohamedmoawya 0:e4c5e6ec922e 909
mohamedmoawya 0:e4c5e6ec922e 910 /**
mohamedmoawya 0:e4c5e6ec922e 911 \brief Get Interrupt Vector
mohamedmoawya 0:e4c5e6ec922e 912 \details Reads an interrupt vector from interrupt vector table.
mohamedmoawya 0:e4c5e6ec922e 913 The interrupt number can be positive to specify a device specific interrupt,
mohamedmoawya 0:e4c5e6ec922e 914 or negative to specify a processor exception.
mohamedmoawya 0:e4c5e6ec922e 915 \param [in] IRQn Interrupt number.
mohamedmoawya 0:e4c5e6ec922e 916 \return Address of interrupt handler function
mohamedmoawya 0:e4c5e6ec922e 917 */
mohamedmoawya 0:e4c5e6ec922e 918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
mohamedmoawya 0:e4c5e6ec922e 919 {
mohamedmoawya 0:e4c5e6ec922e 920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
mohamedmoawya 0:e4c5e6ec922e 921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
mohamedmoawya 0:e4c5e6ec922e 922 }
mohamedmoawya 0:e4c5e6ec922e 923
mohamedmoawya 0:e4c5e6ec922e 924
mohamedmoawya 0:e4c5e6ec922e 925 /**
mohamedmoawya 0:e4c5e6ec922e 926 \brief System Reset
mohamedmoawya 0:e4c5e6ec922e 927 \details Initiates a system reset request to reset the MCU.
mohamedmoawya 0:e4c5e6ec922e 928 */
mohamedmoawya 0:e4c5e6ec922e 929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
mohamedmoawya 0:e4c5e6ec922e 930 {
mohamedmoawya 0:e4c5e6ec922e 931 __DSB(); /* Ensure all outstanding memory accesses included
mohamedmoawya 0:e4c5e6ec922e 932 buffered write are completed before reset */
mohamedmoawya 0:e4c5e6ec922e 933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mohamedmoawya 0:e4c5e6ec922e 934 SCB_AIRCR_SYSRESETREQ_Msk);
mohamedmoawya 0:e4c5e6ec922e 935 __DSB(); /* Ensure completion of memory access */
mohamedmoawya 0:e4c5e6ec922e 936
mohamedmoawya 0:e4c5e6ec922e 937 for(;;) /* wait until reset */
mohamedmoawya 0:e4c5e6ec922e 938 {
mohamedmoawya 0:e4c5e6ec922e 939 __NOP();
mohamedmoawya 0:e4c5e6ec922e 940 }
mohamedmoawya 0:e4c5e6ec922e 941 }
mohamedmoawya 0:e4c5e6ec922e 942
mohamedmoawya 0:e4c5e6ec922e 943 /*@} end of CMSIS_Core_NVICFunctions */
mohamedmoawya 0:e4c5e6ec922e 944
mohamedmoawya 0:e4c5e6ec922e 945
mohamedmoawya 0:e4c5e6ec922e 946 /* ########################## FPU functions #################################### */
mohamedmoawya 0:e4c5e6ec922e 947 /**
mohamedmoawya 0:e4c5e6ec922e 948 \ingroup CMSIS_Core_FunctionInterface
mohamedmoawya 0:e4c5e6ec922e 949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
mohamedmoawya 0:e4c5e6ec922e 950 \brief Function that provides FPU type.
mohamedmoawya 0:e4c5e6ec922e 951 @{
mohamedmoawya 0:e4c5e6ec922e 952 */
mohamedmoawya 0:e4c5e6ec922e 953
mohamedmoawya 0:e4c5e6ec922e 954 /**
mohamedmoawya 0:e4c5e6ec922e 955 \brief get FPU type
mohamedmoawya 0:e4c5e6ec922e 956 \details returns the FPU type
mohamedmoawya 0:e4c5e6ec922e 957 \returns
mohamedmoawya 0:e4c5e6ec922e 958 - \b 0: No FPU
mohamedmoawya 0:e4c5e6ec922e 959 - \b 1: Single precision FPU
mohamedmoawya 0:e4c5e6ec922e 960 - \b 2: Double + Single precision FPU
mohamedmoawya 0:e4c5e6ec922e 961 */
mohamedmoawya 0:e4c5e6ec922e 962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
mohamedmoawya 0:e4c5e6ec922e 963 {
mohamedmoawya 0:e4c5e6ec922e 964 return 0U; /* No FPU */
mohamedmoawya 0:e4c5e6ec922e 965 }
mohamedmoawya 0:e4c5e6ec922e 966
mohamedmoawya 0:e4c5e6ec922e 967
mohamedmoawya 0:e4c5e6ec922e 968 /*@} end of CMSIS_Core_FpuFunctions */
mohamedmoawya 0:e4c5e6ec922e 969
mohamedmoawya 0:e4c5e6ec922e 970
mohamedmoawya 0:e4c5e6ec922e 971
mohamedmoawya 0:e4c5e6ec922e 972 /* ################################## SysTick function ############################################ */
mohamedmoawya 0:e4c5e6ec922e 973 /**
mohamedmoawya 0:e4c5e6ec922e 974 \ingroup CMSIS_Core_FunctionInterface
mohamedmoawya 0:e4c5e6ec922e 975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mohamedmoawya 0:e4c5e6ec922e 976 \brief Functions that configure the System.
mohamedmoawya 0:e4c5e6ec922e 977 @{
mohamedmoawya 0:e4c5e6ec922e 978 */
mohamedmoawya 0:e4c5e6ec922e 979
mohamedmoawya 0:e4c5e6ec922e 980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mohamedmoawya 0:e4c5e6ec922e 981
mohamedmoawya 0:e4c5e6ec922e 982 /**
mohamedmoawya 0:e4c5e6ec922e 983 \brief System Tick Configuration
mohamedmoawya 0:e4c5e6ec922e 984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
mohamedmoawya 0:e4c5e6ec922e 985 Counter is in free running mode to generate periodic interrupts.
mohamedmoawya 0:e4c5e6ec922e 986 \param [in] ticks Number of ticks between two interrupts.
mohamedmoawya 0:e4c5e6ec922e 987 \return 0 Function succeeded.
mohamedmoawya 0:e4c5e6ec922e 988 \return 1 Function failed.
mohamedmoawya 0:e4c5e6ec922e 989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mohamedmoawya 0:e4c5e6ec922e 990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mohamedmoawya 0:e4c5e6ec922e 991 must contain a vendor-specific implementation of this function.
mohamedmoawya 0:e4c5e6ec922e 992 */
mohamedmoawya 0:e4c5e6ec922e 993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mohamedmoawya 0:e4c5e6ec922e 994 {
mohamedmoawya 0:e4c5e6ec922e 995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
mohamedmoawya 0:e4c5e6ec922e 996 {
mohamedmoawya 0:e4c5e6ec922e 997 return (1UL); /* Reload value impossible */
mohamedmoawya 0:e4c5e6ec922e 998 }
mohamedmoawya 0:e4c5e6ec922e 999
mohamedmoawya 0:e4c5e6ec922e 1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mohamedmoawya 0:e4c5e6ec922e 1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mohamedmoawya 0:e4c5e6ec922e 1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mohamedmoawya 0:e4c5e6ec922e 1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mohamedmoawya 0:e4c5e6ec922e 1004 SysTick_CTRL_TICKINT_Msk |
mohamedmoawya 0:e4c5e6ec922e 1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mohamedmoawya 0:e4c5e6ec922e 1006 return (0UL); /* Function successful */
mohamedmoawya 0:e4c5e6ec922e 1007 }
mohamedmoawya 0:e4c5e6ec922e 1008
mohamedmoawya 0:e4c5e6ec922e 1009 #endif
mohamedmoawya 0:e4c5e6ec922e 1010
mohamedmoawya 0:e4c5e6ec922e 1011 /*@} end of CMSIS_Core_SysTickFunctions */
mohamedmoawya 0:e4c5e6ec922e 1012
mohamedmoawya 0:e4c5e6ec922e 1013
mohamedmoawya 0:e4c5e6ec922e 1014
mohamedmoawya 0:e4c5e6ec922e 1015
mohamedmoawya 0:e4c5e6ec922e 1016 #ifdef __cplusplus
mohamedmoawya 0:e4c5e6ec922e 1017 }
mohamedmoawya 0:e4c5e6ec922e 1018 #endif
mohamedmoawya 0:e4c5e6ec922e 1019
mohamedmoawya 0:e4c5e6ec922e 1020 #endif /* __CORE_SC000_H_DEPENDANT */
mohamedmoawya 0:e4c5e6ec922e 1021
mohamedmoawya 0:e4c5e6ec922e 1022 #endif /* __CMSIS_GENERIC */