modtronix H / modtronix_inAir

Based on SX1276Lib. Simplified and targeted for Modtronix inAir modules. All pins can now be specified to use interrupts or general purpose I/O pins.

inair.cpp@1:64a9c4a03244, 2015-08-30 (annotated)

Committer:
modtronix
Date:
Sun Aug 30 09:39:25 2015 +1000
Revision:
1:64a9c4a03244
Child:
2:93cf5cb235ee
Initial version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:64a9c4a03244 1 /*
modtronix 1:64a9c4a03244 2 / _____) _ | |
modtronix 1:64a9c4a03244 3 ( (____ _____ ____ _| |_ _____ ____| |__
modtronix 1:64a9c4a03244 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
modtronix 1:64a9c4a03244 5 _____) ) ____| | | || |_| ____( (___| | | |
modtronix 1:64a9c4a03244 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
modtronix 1:64a9c4a03244 7 ( C )2014 Semtech
modtronix 1:64a9c4a03244 8
modtronix 1:64a9c4a03244 9 Description: Actual implementation of a SX1276 radio, inherits Radio
modtronix 1:64a9c4a03244 10
modtronix 1:64a9c4a03244 11 License: Revised BSD License, see LICENSE.TXT file include in the project
modtronix 1:64a9c4a03244 12
modtronix 1:64a9c4a03244 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
modtronix 1:64a9c4a03244 14 */
modtronix 1:64a9c4a03244 15 #include "inair.h"
modtronix 1:64a9c4a03244 16
modtronix 1:64a9c4a03244 17 #define INAIR_ENABLE_FSK 0
modtronix 1:64a9c4a03244 18
modtronix 1:64a9c4a03244 19 const FskBandwidth_t InAir::FskBandwidths[] =
modtronix 1:64a9c4a03244 20 {
modtronix 1:64a9c4a03244 21 { 2600 , 0x17 },
modtronix 1:64a9c4a03244 22 { 3100 , 0x0F },
modtronix 1:64a9c4a03244 23 { 3900 , 0x07 },
modtronix 1:64a9c4a03244 24 { 5200 , 0x16 },
modtronix 1:64a9c4a03244 25 { 6300 , 0x0E },
modtronix 1:64a9c4a03244 26 { 7800 , 0x06 },
modtronix 1:64a9c4a03244 27 { 10400 , 0x15 },
modtronix 1:64a9c4a03244 28 { 12500 , 0x0D },
modtronix 1:64a9c4a03244 29 { 15600 , 0x05 },
modtronix 1:64a9c4a03244 30 { 20800 , 0x14 },
modtronix 1:64a9c4a03244 31 { 25000 , 0x0C },
modtronix 1:64a9c4a03244 32 { 31300 , 0x04 },
modtronix 1:64a9c4a03244 33 { 41700 , 0x13 },
modtronix 1:64a9c4a03244 34 { 50000 , 0x0B },
modtronix 1:64a9c4a03244 35 { 62500 , 0x03 },
modtronix 1:64a9c4a03244 36 { 83333 , 0x12 },
modtronix 1:64a9c4a03244 37 { 100000, 0x0A },
modtronix 1:64a9c4a03244 38 { 125000, 0x02 },
modtronix 1:64a9c4a03244 39 { 166700, 0x11 },
modtronix 1:64a9c4a03244 40 { 200000, 0x09 },
modtronix 1:64a9c4a03244 41 { 250000, 0x01 },
modtronix 1:64a9c4a03244 42 { 300000, 0x00 }, // Invalid Badwidth
modtronix 1:64a9c4a03244 43 };
modtronix 1:64a9c4a03244 44
modtronix 1:64a9c4a03244 45
modtronix 1:64a9c4a03244 46 InAir::InAir( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
modtronix 1:64a9c4a03244 47 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
modtronix 1:64a9c4a03244 48 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
modtronix 1:64a9c4a03244 49 PinName dio0, PinName dio1, PinName dio2, PinName dio3)
modtronix 1:64a9c4a03244 50 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
modtronix 1:64a9c4a03244 51 spi( mosi, miso, sclk ),
modtronix 1:64a9c4a03244 52 nss( nss ),
modtronix 1:64a9c4a03244 53 reset( reset ),
modtronix 1:64a9c4a03244 54 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ),
modtronix 1:64a9c4a03244 55 isRadioActive( false )
modtronix 1:64a9c4a03244 56 {
modtronix 1:64a9c4a03244 57 wait_ms( 10 );
modtronix 1:64a9c4a03244 58 this->rxTx = 0;
modtronix 1:64a9c4a03244 59 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
modtronix 1:64a9c4a03244 60 previousOpMode = RF_OPMODE_STANDBY;
modtronix 1:64a9c4a03244 61
modtronix 1:64a9c4a03244 62 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 63
modtronix 1:64a9c4a03244 64 // From sx1276-inAir Constructor //////////////////////////////////////////
modtronix 1:64a9c4a03244 65 Reset( );
modtronix 1:64a9c4a03244 66
modtronix 1:64a9c4a03244 67 boardConnected = BOARD_UNKNOWN;
modtronix 1:64a9c4a03244 68
modtronix 1:64a9c4a03244 69 RxChainCalibration( );
modtronix 1:64a9c4a03244 70
modtronix 1:64a9c4a03244 71 IoInit( );
modtronix 1:64a9c4a03244 72
modtronix 1:64a9c4a03244 73 SetOpMode( RF_OPMODE_SLEEP );
modtronix 1:64a9c4a03244 74
modtronix 1:64a9c4a03244 75 IoIrqInit();
modtronix 1:64a9c4a03244 76
modtronix 1:64a9c4a03244 77 RadioRegistersInit( );
modtronix 1:64a9c4a03244 78
modtronix 1:64a9c4a03244 79 SetModem( MODEM_LORA );
modtronix 1:64a9c4a03244 80
modtronix 1:64a9c4a03244 81 this->settings.State = IDLE ;
modtronix 1:64a9c4a03244 82 }
modtronix 1:64a9c4a03244 83
modtronix 1:64a9c4a03244 84 InAir::~InAir( )
modtronix 1:64a9c4a03244 85 {
modtronix 1:64a9c4a03244 86 delete this->rxBuffer;
modtronix 1:64a9c4a03244 87 }
modtronix 1:64a9c4a03244 88
modtronix 1:64a9c4a03244 89 void InAir::task(void)
modtronix 1:64a9c4a03244 90 {
modtronix 1:64a9c4a03244 91 #if(INAIR_DIO0_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 92 static bool dio0Was0 = false;
modtronix 1:64a9c4a03244 93 #endif
modtronix 1:64a9c4a03244 94 #if(INAIR_DIO1_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 95 static bool dio1Was0 = false;
modtronix 1:64a9c4a03244 96 #endif
modtronix 1:64a9c4a03244 97 #if(INAIR_DIO2_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 98 static bool dio2Was0 = false;
modtronix 1:64a9c4a03244 99 #endif
modtronix 1:64a9c4a03244 100 #if(INAIR_DIO3_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 101 static bool dio3Was0 = false;
modtronix 1:64a9c4a03244 102 #endif
modtronix 1:64a9c4a03244 103
modtronix 1:64a9c4a03244 104 #if(INAIR_DIO0_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 105 if (dio0.read() == 0) {
modtronix 1:64a9c4a03244 106 dio0Was0 = true;
modtronix 1:64a9c4a03244 107 }
modtronix 1:64a9c4a03244 108 else {
modtronix 1:64a9c4a03244 109 //Only do once on rising edge of 0-to-1 transition
modtronix 1:64a9c4a03244 110 if (dio0Was0 == true) {
modtronix 1:64a9c4a03244 111 dio0Was0 = false;
modtronix 1:64a9c4a03244 112 OnDio0Irq();
modtronix 1:64a9c4a03244 113 }
modtronix 1:64a9c4a03244 114 }
modtronix 1:64a9c4a03244 115 #endif
modtronix 1:64a9c4a03244 116
modtronix 1:64a9c4a03244 117 #if(INAIR_DIO1_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 118 if (dio1.read() == 0) {
modtronix 1:64a9c4a03244 119 dio1Was0 = true;
modtronix 1:64a9c4a03244 120 }
modtronix 1:64a9c4a03244 121 else {
modtronix 1:64a9c4a03244 122 //Only do once on rising edge of 0-to-1 transition
modtronix 1:64a9c4a03244 123 if (dio1Was0 == true) {
modtronix 1:64a9c4a03244 124 dio1Was0 = false;
modtronix 1:64a9c4a03244 125 OnDio1Irq();
modtronix 1:64a9c4a03244 126 }
modtronix 1:64a9c4a03244 127 }
modtronix 1:64a9c4a03244 128 #endif
modtronix 1:64a9c4a03244 129
modtronix 1:64a9c4a03244 130 #if(INAIR_DIO2_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 131 if (dio2.read() == 0) {
modtronix 1:64a9c4a03244 132 dio2Was0 = true;
modtronix 1:64a9c4a03244 133 }
modtronix 1:64a9c4a03244 134 else {
modtronix 1:64a9c4a03244 135 //Only do once on rising edge of 0-to-1 transition
modtronix 1:64a9c4a03244 136 if (dio2Was0 == true) {
modtronix 1:64a9c4a03244 137 dio2Was0 = false;
modtronix 1:64a9c4a03244 138 OnDio2Irq();
modtronix 1:64a9c4a03244 139 }
modtronix 1:64a9c4a03244 140 }
modtronix 1:64a9c4a03244 141 #endif
modtronix 1:64a9c4a03244 142
modtronix 1:64a9c4a03244 143 #if(INAIR_DIO3_IS_INTERRUPT==0)
modtronix 1:64a9c4a03244 144 if (dio3.read() == 0) {
modtronix 1:64a9c4a03244 145 dio3Was0 = true;
modtronix 1:64a9c4a03244 146 }
modtronix 1:64a9c4a03244 147 else {
modtronix 1:64a9c4a03244 148 //Only do once on rising edge of 0-to-1 transition
modtronix 1:64a9c4a03244 149 if (dio3Was0 == true) {
modtronix 1:64a9c4a03244 150 dio3Was0 = false;
modtronix 1:64a9c4a03244 151 OnDio3Irq();
modtronix 1:64a9c4a03244 152 }
modtronix 1:64a9c4a03244 153 }
modtronix 1:64a9c4a03244 154 #endif
modtronix 1:64a9c4a03244 155
modtronix 1:64a9c4a03244 156 }
modtronix 1:64a9c4a03244 157
modtronix 1:64a9c4a03244 158
modtronix 1:64a9c4a03244 159 uint8_t InAir::GetBoardType( void )
modtronix 1:64a9c4a03244 160 {
modtronix 1:64a9c4a03244 161 return boardConnected;
modtronix 1:64a9c4a03244 162 }
modtronix 1:64a9c4a03244 163
modtronix 1:64a9c4a03244 164 void InAir::SetBoardType( uint8_t boardType)
modtronix 1:64a9c4a03244 165 {
modtronix 1:64a9c4a03244 166 boardConnected = boardType;
modtronix 1:64a9c4a03244 167 }
modtronix 1:64a9c4a03244 168
modtronix 1:64a9c4a03244 169 void InAir::RxChainCalibration( void )
modtronix 1:64a9c4a03244 170 {
modtronix 1:64a9c4a03244 171 uint8_t regPaConfigInitVal;
modtronix 1:64a9c4a03244 172 uint32_t initialFreq;
modtronix 1:64a9c4a03244 173
modtronix 1:64a9c4a03244 174 // Save context
modtronix 1:64a9c4a03244 175 regPaConfigInitVal = this->Read( REG_PACONFIG );
modtronix 1:64a9c4a03244 176 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
modtronix 1:64a9c4a03244 177 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
modtronix 1:64a9c4a03244 178 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
modtronix 1:64a9c4a03244 179
modtronix 1:64a9c4a03244 180 // Cut the PA just in case, RFO output, power = -1 dBm
modtronix 1:64a9c4a03244 181 this->Write( REG_PACONFIG, 0x00 );
modtronix 1:64a9c4a03244 182
modtronix 1:64a9c4a03244 183 // Launch Rx chain calibration for LF band
modtronix 1:64a9c4a03244 184 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
modtronix 1:64a9c4a03244 185 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
modtronix 1:64a9c4a03244 186 {
modtronix 1:64a9c4a03244 187 }
modtronix 1:64a9c4a03244 188
modtronix 1:64a9c4a03244 189 // Sets a Frequency in HF band
modtronix 1:64a9c4a03244 190 settings.Channel= 868000000 ;
modtronix 1:64a9c4a03244 191
modtronix 1:64a9c4a03244 192 // Launch Rx chain calibration for HF band
modtronix 1:64a9c4a03244 193 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
modtronix 1:64a9c4a03244 194 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
modtronix 1:64a9c4a03244 195 {
modtronix 1:64a9c4a03244 196 }
modtronix 1:64a9c4a03244 197
modtronix 1:64a9c4a03244 198 // Restore context
modtronix 1:64a9c4a03244 199 this->Write( REG_PACONFIG, regPaConfigInitVal );
modtronix 1:64a9c4a03244 200 SetChannel( initialFreq );
modtronix 1:64a9c4a03244 201 }
modtronix 1:64a9c4a03244 202
modtronix 1:64a9c4a03244 203 RadioState InAir::GetState( void )
modtronix 1:64a9c4a03244 204 {
modtronix 1:64a9c4a03244 205 return this->settings.State;
modtronix 1:64a9c4a03244 206 }
modtronix 1:64a9c4a03244 207
modtronix 1:64a9c4a03244 208 void InAir::SetChannel( uint32_t freq )
modtronix 1:64a9c4a03244 209 {
modtronix 1:64a9c4a03244 210 this->settings.Channel = freq;
modtronix 1:64a9c4a03244 211 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
modtronix 1:64a9c4a03244 212 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
modtronix 1:64a9c4a03244 213 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
modtronix 1:64a9c4a03244 214 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
modtronix 1:64a9c4a03244 215 }
modtronix 1:64a9c4a03244 216
modtronix 1:64a9c4a03244 217 bool InAir::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
modtronix 1:64a9c4a03244 218 {
modtronix 1:64a9c4a03244 219 int16_t rssi = 0;
modtronix 1:64a9c4a03244 220
modtronix 1:64a9c4a03244 221 SetModem( modem );
modtronix 1:64a9c4a03244 222
modtronix 1:64a9c4a03244 223 SetChannel( freq );
modtronix 1:64a9c4a03244 224
modtronix 1:64a9c4a03244 225 SetOpMode( RF_OPMODE_RECEIVER );
modtronix 1:64a9c4a03244 226
modtronix 1:64a9c4a03244 227 wait_ms( 1 );
modtronix 1:64a9c4a03244 228
modtronix 1:64a9c4a03244 229 rssi = GetRssi( modem );
modtronix 1:64a9c4a03244 230
modtronix 1:64a9c4a03244 231 Sleep( );
modtronix 1:64a9c4a03244 232
modtronix 1:64a9c4a03244 233 if( rssi > ( int16_t )rssiThresh )
modtronix 1:64a9c4a03244 234 {
modtronix 1:64a9c4a03244 235 return false;
modtronix 1:64a9c4a03244 236 }
modtronix 1:64a9c4a03244 237 return true;
modtronix 1:64a9c4a03244 238 }
modtronix 1:64a9c4a03244 239
modtronix 1:64a9c4a03244 240 uint32_t InAir::Random( void )
modtronix 1:64a9c4a03244 241 {
modtronix 1:64a9c4a03244 242 uint8_t i;
modtronix 1:64a9c4a03244 243 uint32_t rnd = 0;
modtronix 1:64a9c4a03244 244
modtronix 1:64a9c4a03244 245 /*
modtronix 1:64a9c4a03244 246 * Radio setup for random number generation
modtronix 1:64a9c4a03244 247 */
modtronix 1:64a9c4a03244 248 // Set LoRa modem ON
modtronix 1:64a9c4a03244 249 SetModem( MODEM_LORA );
modtronix 1:64a9c4a03244 250
modtronix 1:64a9c4a03244 251 // Disable LoRa modem interrupts
modtronix 1:64a9c4a03244 252 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 253 RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 254 RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 255 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 256 RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 257 RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 258 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
modtronix 1:64a9c4a03244 259 RFLR_IRQFLAGS_CADDETECTED );
modtronix 1:64a9c4a03244 260
modtronix 1:64a9c4a03244 261 // Set radio in continuous reception
modtronix 1:64a9c4a03244 262 SetOpMode( RF_OPMODE_RECEIVER );
modtronix 1:64a9c4a03244 263
modtronix 1:64a9c4a03244 264 for( i = 0; i < 32; i++ )
modtronix 1:64a9c4a03244 265 {
modtronix 1:64a9c4a03244 266 wait_ms( 1 );
modtronix 1:64a9c4a03244 267 // Unfiltered RSSI value reading. Only takes the LSB value
modtronix 1:64a9c4a03244 268 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
modtronix 1:64a9c4a03244 269 }
modtronix 1:64a9c4a03244 270
modtronix 1:64a9c4a03244 271 Sleep( );
modtronix 1:64a9c4a03244 272
modtronix 1:64a9c4a03244 273 return rnd;
modtronix 1:64a9c4a03244 274 }
modtronix 1:64a9c4a03244 275
modtronix 1:64a9c4a03244 276 /*!
modtronix 1:64a9c4a03244 277 * Returns the known FSK bandwidth registers value
modtronix 1:64a9c4a03244 278 *
modtronix 1:64a9c4a03244 279 * \param [IN] bandwidth Bandwidth value in Hz
modtronix 1:64a9c4a03244 280 * \retval regValue Bandwidth register value.
modtronix 1:64a9c4a03244 281 */
modtronix 1:64a9c4a03244 282 uint8_t InAir::GetFskBandwidthRegValue( uint32_t bandwidth )
modtronix 1:64a9c4a03244 283 {
modtronix 1:64a9c4a03244 284 uint8_t i;
modtronix 1:64a9c4a03244 285
modtronix 1:64a9c4a03244 286 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
modtronix 1:64a9c4a03244 287 {
modtronix 1:64a9c4a03244 288 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
modtronix 1:64a9c4a03244 289 {
modtronix 1:64a9c4a03244 290 return FskBandwidths[i].RegValue;
modtronix 1:64a9c4a03244 291 }
modtronix 1:64a9c4a03244 292 }
modtronix 1:64a9c4a03244 293 // ERROR: Value not found
modtronix 1:64a9c4a03244 294 while( 1 );
modtronix 1:64a9c4a03244 295 }
modtronix 1:64a9c4a03244 296
modtronix 1:64a9c4a03244 297 void InAir::SetRxConfig( ModemType modem, uint32_t bandwidth,
modtronix 1:64a9c4a03244 298 uint32_t datarate, uint8_t coderate,
modtronix 1:64a9c4a03244 299 uint32_t bandwidthAfc, uint16_t preambleLen,
modtronix 1:64a9c4a03244 300 uint16_t symbTimeout, bool fixLen,
modtronix 1:64a9c4a03244 301 uint8_t payloadLen,
modtronix 1:64a9c4a03244 302 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
modtronix 1:64a9c4a03244 303 bool iqInverted, bool rxContinuous )
modtronix 1:64a9c4a03244 304 {
modtronix 1:64a9c4a03244 305 SetModem( modem );
modtronix 1:64a9c4a03244 306
modtronix 1:64a9c4a03244 307 switch( modem )
modtronix 1:64a9c4a03244 308 {
modtronix 1:64a9c4a03244 309 case MODEM_FSK:
modtronix 1:64a9c4a03244 310 {
modtronix 1:64a9c4a03244 311 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 312 this->settings.Fsk.Bandwidth = bandwidth;
modtronix 1:64a9c4a03244 313 this->settings.Fsk.Datarate = datarate;
modtronix 1:64a9c4a03244 314 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
modtronix 1:64a9c4a03244 315 this->settings.Fsk.FixLen = fixLen;
modtronix 1:64a9c4a03244 316 this->settings.Fsk.PayloadLen = payloadLen;
modtronix 1:64a9c4a03244 317 this->settings.Fsk.CrcOn = crcOn;
modtronix 1:64a9c4a03244 318 this->settings.Fsk.IqInverted = iqInverted;
modtronix 1:64a9c4a03244 319 this->settings.Fsk.RxContinuous = rxContinuous;
modtronix 1:64a9c4a03244 320 this->settings.Fsk.PreambleLen = preambleLen;
modtronix 1:64a9c4a03244 321
modtronix 1:64a9c4a03244 322 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
modtronix 1:64a9c4a03244 323 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
modtronix 1:64a9c4a03244 324 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
modtronix 1:64a9c4a03244 325
modtronix 1:64a9c4a03244 326 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
modtronix 1:64a9c4a03244 327 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
modtronix 1:64a9c4a03244 328
modtronix 1:64a9c4a03244 329 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
modtronix 1:64a9c4a03244 330 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
modtronix 1:64a9c4a03244 331
modtronix 1:64a9c4a03244 332 Write( REG_PACKETCONFIG1,
modtronix 1:64a9c4a03244 333 ( Read( REG_PACKETCONFIG1 ) &
modtronix 1:64a9c4a03244 334 RF_PACKETCONFIG1_CRC_MASK &
modtronix 1:64a9c4a03244 335 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
modtronix 1:64a9c4a03244 336 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
modtronix 1:64a9c4a03244 337 ( crcOn << 4 ) );
modtronix 1:64a9c4a03244 338 if( fixLen == 1 )
modtronix 1:64a9c4a03244 339 {
modtronix 1:64a9c4a03244 340 Write( REG_PAYLOADLENGTH, payloadLen );
modtronix 1:64a9c4a03244 341 }
modtronix 1:64a9c4a03244 342 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 343 }
modtronix 1:64a9c4a03244 344 break;
modtronix 1:64a9c4a03244 345 case MODEM_LORA:
modtronix 1:64a9c4a03244 346 {
modtronix 1:64a9c4a03244 347 if( bandwidth > 9 )
modtronix 1:64a9c4a03244 348 {
modtronix 1:64a9c4a03244 349 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
modtronix 1:64a9c4a03244 350 while( 1 );
modtronix 1:64a9c4a03244 351 }
modtronix 1:64a9c4a03244 352 //bandwidth += 7; //Changed bandwidth from 0-2 to 0-10
modtronix 1:64a9c4a03244 353 this->settings.LoRa.Bandwidth = bandwidth;
modtronix 1:64a9c4a03244 354 this->settings.LoRa.Datarate = datarate;
modtronix 1:64a9c4a03244 355 this->settings.LoRa.Coderate = coderate;
modtronix 1:64a9c4a03244 356 this->settings.LoRa.FixLen = fixLen;
modtronix 1:64a9c4a03244 357 this->settings.LoRa.PayloadLen = payloadLen;
modtronix 1:64a9c4a03244 358 this->settings.LoRa.CrcOn = crcOn;
modtronix 1:64a9c4a03244 359 this->settings.LoRa.FreqHopOn = freqHopOn;
modtronix 1:64a9c4a03244 360 this->settings.LoRa.HopPeriod = hopPeriod;
modtronix 1:64a9c4a03244 361 this->settings.LoRa.IqInverted = iqInverted;
modtronix 1:64a9c4a03244 362 this->settings.LoRa.RxContinuous = rxContinuous;
modtronix 1:64a9c4a03244 363
modtronix 1:64a9c4a03244 364 if( datarate > 12 )
modtronix 1:64a9c4a03244 365 {
modtronix 1:64a9c4a03244 366 datarate = 12;
modtronix 1:64a9c4a03244 367 }
modtronix 1:64a9c4a03244 368 else if( datarate < 6 )
modtronix 1:64a9c4a03244 369 {
modtronix 1:64a9c4a03244 370 datarate = 6;
modtronix 1:64a9c4a03244 371 }
modtronix 1:64a9c4a03244 372
modtronix 1:64a9c4a03244 373 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 1:64a9c4a03244 374 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 1:64a9c4a03244 375 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 1:64a9c4a03244 376 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 1:64a9c4a03244 377 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 1:64a9c4a03244 378 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 1:64a9c4a03244 379 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 1:64a9c4a03244 380 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 1:64a9c4a03244 381 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 1:64a9c4a03244 382 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 1:64a9c4a03244 383 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 1:64a9c4a03244 384 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 1:64a9c4a03244 385 )
modtronix 1:64a9c4a03244 386 {
modtronix 1:64a9c4a03244 387 this->settings.LoRa.LowDatarateOptimize = 0x01;
modtronix 1:64a9c4a03244 388 }
modtronix 1:64a9c4a03244 389 else
modtronix 1:64a9c4a03244 390 {
modtronix 1:64a9c4a03244 391 this->settings.LoRa.LowDatarateOptimize = 0x00;
modtronix 1:64a9c4a03244 392 }
modtronix 1:64a9c4a03244 393
modtronix 1:64a9c4a03244 394 Write( REG_LR_MODEMCONFIG1,
modtronix 1:64a9c4a03244 395 ( Read( REG_LR_MODEMCONFIG1 ) &
modtronix 1:64a9c4a03244 396 RFLR_MODEMCONFIG1_BW_MASK &
modtronix 1:64a9c4a03244 397 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
modtronix 1:64a9c4a03244 398 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
modtronix 1:64a9c4a03244 399 ( bandwidth << 4 ) | ( coderate << 1 ) |
modtronix 1:64a9c4a03244 400 fixLen );
modtronix 1:64a9c4a03244 401
modtronix 1:64a9c4a03244 402 Write( REG_LR_MODEMCONFIG2,
modtronix 1:64a9c4a03244 403 ( Read( REG_LR_MODEMCONFIG2 ) &
modtronix 1:64a9c4a03244 404 RFLR_MODEMCONFIG2_SF_MASK &
modtronix 1:64a9c4a03244 405 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
modtronix 1:64a9c4a03244 406 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
modtronix 1:64a9c4a03244 407 ( datarate << 4 ) | ( crcOn << 2 ) |
modtronix 1:64a9c4a03244 408 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
modtronix 1:64a9c4a03244 409
modtronix 1:64a9c4a03244 410 Write( REG_LR_MODEMCONFIG3,
modtronix 1:64a9c4a03244 411 ( Read( REG_LR_MODEMCONFIG3 ) &
modtronix 1:64a9c4a03244 412 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 413 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
modtronix 1:64a9c4a03244 414
modtronix 1:64a9c4a03244 415 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
modtronix 1:64a9c4a03244 416
modtronix 1:64a9c4a03244 417 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
modtronix 1:64a9c4a03244 418 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
modtronix 1:64a9c4a03244 419
modtronix 1:64a9c4a03244 420 if( fixLen == 1 )
modtronix 1:64a9c4a03244 421 {
modtronix 1:64a9c4a03244 422 Write( REG_LR_PAYLOADLENGTH, payloadLen );
modtronix 1:64a9c4a03244 423 }
modtronix 1:64a9c4a03244 424
modtronix 1:64a9c4a03244 425 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 426 {
modtronix 1:64a9c4a03244 427 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
modtronix 1:64a9c4a03244 428 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
modtronix 1:64a9c4a03244 429 }
modtronix 1:64a9c4a03244 430
modtronix 1:64a9c4a03244 431 if( datarate == 6 )
modtronix 1:64a9c4a03244 432 {
modtronix 1:64a9c4a03244 433 Write( REG_LR_DETECTOPTIMIZE,
modtronix 1:64a9c4a03244 434 ( Read( REG_LR_DETECTOPTIMIZE ) &
modtronix 1:64a9c4a03244 435 RFLR_DETECTIONOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 436 RFLR_DETECTIONOPTIMIZE_SF6 );
modtronix 1:64a9c4a03244 437 Write( REG_LR_DETECTIONTHRESHOLD,
modtronix 1:64a9c4a03244 438 RFLR_DETECTIONTHRESH_SF6 );
modtronix 1:64a9c4a03244 439 }
modtronix 1:64a9c4a03244 440 else
modtronix 1:64a9c4a03244 441 {
modtronix 1:64a9c4a03244 442 Write( REG_LR_DETECTOPTIMIZE,
modtronix 1:64a9c4a03244 443 ( Read( REG_LR_DETECTOPTIMIZE ) &
modtronix 1:64a9c4a03244 444 RFLR_DETECTIONOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 445 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
modtronix 1:64a9c4a03244 446 Write( REG_LR_DETECTIONTHRESHOLD,
modtronix 1:64a9c4a03244 447 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
modtronix 1:64a9c4a03244 448 }
modtronix 1:64a9c4a03244 449 }
modtronix 1:64a9c4a03244 450 break;
modtronix 1:64a9c4a03244 451 }
modtronix 1:64a9c4a03244 452 }
modtronix 1:64a9c4a03244 453
modtronix 1:64a9c4a03244 454 void InAir::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
modtronix 1:64a9c4a03244 455 uint32_t bandwidth, uint32_t datarate,
modtronix 1:64a9c4a03244 456 uint8_t coderate, uint16_t preambleLen,
modtronix 1:64a9c4a03244 457 bool fixLen, bool crcOn, bool freqHopOn,
modtronix 1:64a9c4a03244 458 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
modtronix 1:64a9c4a03244 459 {
modtronix 1:64a9c4a03244 460 uint8_t paConfig = 0;
modtronix 1:64a9c4a03244 461 uint8_t paDac = 0;
modtronix 1:64a9c4a03244 462
modtronix 1:64a9c4a03244 463 SetModem( modem );
modtronix 1:64a9c4a03244 464
modtronix 1:64a9c4a03244 465 paConfig = Read( REG_PACONFIG );
modtronix 1:64a9c4a03244 466 paDac = Read( REG_PADAC );
modtronix 1:64a9c4a03244 467
modtronix 1:64a9c4a03244 468 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
modtronix 1:64a9c4a03244 469 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
modtronix 1:64a9c4a03244 470
modtronix 1:64a9c4a03244 471 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
modtronix 1:64a9c4a03244 472 {
modtronix 1:64a9c4a03244 473 if( power > 17 )
modtronix 1:64a9c4a03244 474 {
modtronix 1:64a9c4a03244 475 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
modtronix 1:64a9c4a03244 476 }
modtronix 1:64a9c4a03244 477 else
modtronix 1:64a9c4a03244 478 {
modtronix 1:64a9c4a03244 479 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
modtronix 1:64a9c4a03244 480 }
modtronix 1:64a9c4a03244 481 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
modtronix 1:64a9c4a03244 482 {
modtronix 1:64a9c4a03244 483 if( power < 5 )
modtronix 1:64a9c4a03244 484 {
modtronix 1:64a9c4a03244 485 power = 5;
modtronix 1:64a9c4a03244 486 }
modtronix 1:64a9c4a03244 487 if( power > 20 )
modtronix 1:64a9c4a03244 488 {
modtronix 1:64a9c4a03244 489 power = 20;
modtronix 1:64a9c4a03244 490 }
modtronix 1:64a9c4a03244 491 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
modtronix 1:64a9c4a03244 492 }
modtronix 1:64a9c4a03244 493 else
modtronix 1:64a9c4a03244 494 {
modtronix 1:64a9c4a03244 495 if( power < 2 )
modtronix 1:64a9c4a03244 496 {
modtronix 1:64a9c4a03244 497 power = 2;
modtronix 1:64a9c4a03244 498 }
modtronix 1:64a9c4a03244 499 if( power > 17 )
modtronix 1:64a9c4a03244 500 {
modtronix 1:64a9c4a03244 501 power = 17;
modtronix 1:64a9c4a03244 502 }
modtronix 1:64a9c4a03244 503 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
modtronix 1:64a9c4a03244 504 }
modtronix 1:64a9c4a03244 505 }
modtronix 1:64a9c4a03244 506 else
modtronix 1:64a9c4a03244 507 {
modtronix 1:64a9c4a03244 508 if( power < -1 )
modtronix 1:64a9c4a03244 509 {
modtronix 1:64a9c4a03244 510 power = -1;
modtronix 1:64a9c4a03244 511 }
modtronix 1:64a9c4a03244 512 if( power > 14 )
modtronix 1:64a9c4a03244 513 {
modtronix 1:64a9c4a03244 514 power = 14;
modtronix 1:64a9c4a03244 515 }
modtronix 1:64a9c4a03244 516 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
modtronix 1:64a9c4a03244 517 }
modtronix 1:64a9c4a03244 518 Write( REG_PACONFIG, paConfig );
modtronix 1:64a9c4a03244 519 Write( REG_PADAC, paDac );
modtronix 1:64a9c4a03244 520
modtronix 1:64a9c4a03244 521 switch( modem )
modtronix 1:64a9c4a03244 522 {
modtronix 1:64a9c4a03244 523 case MODEM_FSK:
modtronix 1:64a9c4a03244 524 {
modtronix 1:64a9c4a03244 525 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 526 this->settings.Fsk.Power = power;
modtronix 1:64a9c4a03244 527 this->settings.Fsk.Fdev = fdev;
modtronix 1:64a9c4a03244 528 this->settings.Fsk.Bandwidth = bandwidth;
modtronix 1:64a9c4a03244 529 this->settings.Fsk.Datarate = datarate;
modtronix 1:64a9c4a03244 530 this->settings.Fsk.PreambleLen = preambleLen;
modtronix 1:64a9c4a03244 531 this->settings.Fsk.FixLen = fixLen;
modtronix 1:64a9c4a03244 532 this->settings.Fsk.CrcOn = crcOn;
modtronix 1:64a9c4a03244 533 this->settings.Fsk.IqInverted = iqInverted;
modtronix 1:64a9c4a03244 534 this->settings.Fsk.TxTimeout = timeout;
modtronix 1:64a9c4a03244 535
modtronix 1:64a9c4a03244 536 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
modtronix 1:64a9c4a03244 537 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
modtronix 1:64a9c4a03244 538 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
modtronix 1:64a9c4a03244 539
modtronix 1:64a9c4a03244 540 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
modtronix 1:64a9c4a03244 541 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
modtronix 1:64a9c4a03244 542 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
modtronix 1:64a9c4a03244 543
modtronix 1:64a9c4a03244 544 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
modtronix 1:64a9c4a03244 545 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
modtronix 1:64a9c4a03244 546
modtronix 1:64a9c4a03244 547 Write( REG_PACKETCONFIG1,
modtronix 1:64a9c4a03244 548 ( Read( REG_PACKETCONFIG1 ) &
modtronix 1:64a9c4a03244 549 RF_PACKETCONFIG1_CRC_MASK &
modtronix 1:64a9c4a03244 550 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
modtronix 1:64a9c4a03244 551 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
modtronix 1:64a9c4a03244 552 ( crcOn << 4 ) );
modtronix 1:64a9c4a03244 553 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 554 }
modtronix 1:64a9c4a03244 555 break;
modtronix 1:64a9c4a03244 556 case MODEM_LORA:
modtronix 1:64a9c4a03244 557 {
modtronix 1:64a9c4a03244 558 this->settings.LoRa.Power = power;
modtronix 1:64a9c4a03244 559 if( bandwidth > 9 )
modtronix 1:64a9c4a03244 560 {
modtronix 1:64a9c4a03244 561 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
modtronix 1:64a9c4a03244 562 while( 1 );
modtronix 1:64a9c4a03244 563 }
modtronix 1:64a9c4a03244 564 //bandwidth += 7;
modtronix 1:64a9c4a03244 565 this->settings.LoRa.Bandwidth = bandwidth;
modtronix 1:64a9c4a03244 566 this->settings.LoRa.Datarate = datarate;
modtronix 1:64a9c4a03244 567 this->settings.LoRa.Coderate = coderate;
modtronix 1:64a9c4a03244 568 this->settings.LoRa.PreambleLen = preambleLen;
modtronix 1:64a9c4a03244 569 this->settings.LoRa.FixLen = fixLen;
modtronix 1:64a9c4a03244 570 this->settings.LoRa.CrcOn = crcOn;
modtronix 1:64a9c4a03244 571 this->settings.LoRa.FreqHopOn = freqHopOn;
modtronix 1:64a9c4a03244 572 this->settings.LoRa.HopPeriod = hopPeriod;
modtronix 1:64a9c4a03244 573 this->settings.LoRa.IqInverted = iqInverted;
modtronix 1:64a9c4a03244 574 this->settings.LoRa.TxTimeout = timeout;
modtronix 1:64a9c4a03244 575
modtronix 1:64a9c4a03244 576 if( datarate > 12 )
modtronix 1:64a9c4a03244 577 {
modtronix 1:64a9c4a03244 578 datarate = 12;
modtronix 1:64a9c4a03244 579 }
modtronix 1:64a9c4a03244 580 else if( datarate < 6 )
modtronix 1:64a9c4a03244 581 {
modtronix 1:64a9c4a03244 582 datarate = 6;
modtronix 1:64a9c4a03244 583 }
modtronix 1:64a9c4a03244 584 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 1:64a9c4a03244 585 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 1:64a9c4a03244 586 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 1:64a9c4a03244 587 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 1:64a9c4a03244 588 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 1:64a9c4a03244 589 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 1:64a9c4a03244 590 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 1:64a9c4a03244 591 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 1:64a9c4a03244 592 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 1:64a9c4a03244 593 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 1:64a9c4a03244 594 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 1:64a9c4a03244 595 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 1:64a9c4a03244 596 )
modtronix 1:64a9c4a03244 597 {
modtronix 1:64a9c4a03244 598 this->settings.LoRa.LowDatarateOptimize = 0x01;
modtronix 1:64a9c4a03244 599 }
modtronix 1:64a9c4a03244 600 else
modtronix 1:64a9c4a03244 601 {
modtronix 1:64a9c4a03244 602 this->settings.LoRa.LowDatarateOptimize = 0x00;
modtronix 1:64a9c4a03244 603 }
modtronix 1:64a9c4a03244 604
modtronix 1:64a9c4a03244 605 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 606 {
modtronix 1:64a9c4a03244 607 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
modtronix 1:64a9c4a03244 608 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
modtronix 1:64a9c4a03244 609 }
modtronix 1:64a9c4a03244 610
modtronix 1:64a9c4a03244 611 Write( REG_LR_MODEMCONFIG1,
modtronix 1:64a9c4a03244 612 ( Read( REG_LR_MODEMCONFIG1 ) &
modtronix 1:64a9c4a03244 613 RFLR_MODEMCONFIG1_BW_MASK &
modtronix 1:64a9c4a03244 614 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
modtronix 1:64a9c4a03244 615 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
modtronix 1:64a9c4a03244 616 ( bandwidth << 4 ) | ( coderate << 1 ) |
modtronix 1:64a9c4a03244 617 fixLen );
modtronix 1:64a9c4a03244 618
modtronix 1:64a9c4a03244 619 Write( REG_LR_MODEMCONFIG2,
modtronix 1:64a9c4a03244 620 ( Read( REG_LR_MODEMCONFIG2 ) &
modtronix 1:64a9c4a03244 621 RFLR_MODEMCONFIG2_SF_MASK &
modtronix 1:64a9c4a03244 622 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
modtronix 1:64a9c4a03244 623 ( datarate << 4 ) | ( crcOn << 2 ) );
modtronix 1:64a9c4a03244 624
modtronix 1:64a9c4a03244 625 Write( REG_LR_MODEMCONFIG3,
modtronix 1:64a9c4a03244 626 ( Read( REG_LR_MODEMCONFIG3 ) &
modtronix 1:64a9c4a03244 627 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 628 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
modtronix 1:64a9c4a03244 629
modtronix 1:64a9c4a03244 630 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
modtronix 1:64a9c4a03244 631 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
modtronix 1:64a9c4a03244 632
modtronix 1:64a9c4a03244 633 if( datarate == 6 )
modtronix 1:64a9c4a03244 634 {
modtronix 1:64a9c4a03244 635 Write( REG_LR_DETECTOPTIMIZE,
modtronix 1:64a9c4a03244 636 ( Read( REG_LR_DETECTOPTIMIZE ) &
modtronix 1:64a9c4a03244 637 RFLR_DETECTIONOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 638 RFLR_DETECTIONOPTIMIZE_SF6 );
modtronix 1:64a9c4a03244 639 Write( REG_LR_DETECTIONTHRESHOLD,
modtronix 1:64a9c4a03244 640 RFLR_DETECTIONTHRESH_SF6 );
modtronix 1:64a9c4a03244 641 }
modtronix 1:64a9c4a03244 642 else
modtronix 1:64a9c4a03244 643 {
modtronix 1:64a9c4a03244 644 Write( REG_LR_DETECTOPTIMIZE,
modtronix 1:64a9c4a03244 645 ( Read( REG_LR_DETECTOPTIMIZE ) &
modtronix 1:64a9c4a03244 646 RFLR_DETECTIONOPTIMIZE_MASK ) |
modtronix 1:64a9c4a03244 647 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
modtronix 1:64a9c4a03244 648 Write( REG_LR_DETECTIONTHRESHOLD,
modtronix 1:64a9c4a03244 649 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
modtronix 1:64a9c4a03244 650 }
modtronix 1:64a9c4a03244 651 }
modtronix 1:64a9c4a03244 652 break;
modtronix 1:64a9c4a03244 653 }
modtronix 1:64a9c4a03244 654 }
modtronix 1:64a9c4a03244 655
modtronix 1:64a9c4a03244 656 double InAir::TimeOnAir( ModemType modem, uint8_t pktLen )
modtronix 1:64a9c4a03244 657 {
modtronix 1:64a9c4a03244 658 double airTime = 0.0;
modtronix 1:64a9c4a03244 659
modtronix 1:64a9c4a03244 660 switch( modem )
modtronix 1:64a9c4a03244 661 {
modtronix 1:64a9c4a03244 662 case MODEM_FSK:
modtronix 1:64a9c4a03244 663 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 664 {
modtronix 1:64a9c4a03244 665 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
modtronix 1:64a9c4a03244 666 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
modtronix 1:64a9c4a03244 667 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
modtronix 1:64a9c4a03244 668 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
modtronix 1:64a9c4a03244 669 pktLen +
modtronix 1:64a9c4a03244 670 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
modtronix 1:64a9c4a03244 671 this->settings.Fsk.Datarate ) * 1e6 );
modtronix 1:64a9c4a03244 672 }
modtronix 1:64a9c4a03244 673 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 674 break;
modtronix 1:64a9c4a03244 675 case MODEM_LORA:
modtronix 1:64a9c4a03244 676 {
modtronix 1:64a9c4a03244 677 double bw = 0.0;
modtronix 1:64a9c4a03244 678 switch( this->settings.LoRa.Bandwidth )
modtronix 1:64a9c4a03244 679 {
modtronix 1:64a9c4a03244 680 case 0: // 7.8 kHz
modtronix 1:64a9c4a03244 681 bw = 78e2;
modtronix 1:64a9c4a03244 682 break;
modtronix 1:64a9c4a03244 683 case 1: // 10.4 kHz
modtronix 1:64a9c4a03244 684 bw = 104e2;
modtronix 1:64a9c4a03244 685 break;
modtronix 1:64a9c4a03244 686 case 2: // 15.6 kHz
modtronix 1:64a9c4a03244 687 bw = 156e2;
modtronix 1:64a9c4a03244 688 break;
modtronix 1:64a9c4a03244 689 case 3: // 20.8 kHz
modtronix 1:64a9c4a03244 690 bw = 208e2;
modtronix 1:64a9c4a03244 691 break;
modtronix 1:64a9c4a03244 692 case 4: // 31.2 kHz
modtronix 1:64a9c4a03244 693 bw = 312e2;
modtronix 1:64a9c4a03244 694 break;
modtronix 1:64a9c4a03244 695 case 5: // 41.4 kHz
modtronix 1:64a9c4a03244 696 bw = 414e2;
modtronix 1:64a9c4a03244 697 break;
modtronix 1:64a9c4a03244 698 case 6: // 62.5 kHz
modtronix 1:64a9c4a03244 699 bw = 625e2;
modtronix 1:64a9c4a03244 700 break;
modtronix 1:64a9c4a03244 701 case 7: // 125 kHz
modtronix 1:64a9c4a03244 702 bw = 125e3;
modtronix 1:64a9c4a03244 703 break;
modtronix 1:64a9c4a03244 704 case 8: // 250 kHz
modtronix 1:64a9c4a03244 705 bw = 250e3;
modtronix 1:64a9c4a03244 706 break;
modtronix 1:64a9c4a03244 707 case 9: // 500 kHz
modtronix 1:64a9c4a03244 708 bw = 500e3;
modtronix 1:64a9c4a03244 709 break;
modtronix 1:64a9c4a03244 710 }
modtronix 1:64a9c4a03244 711
modtronix 1:64a9c4a03244 712 // Symbol rate : time for one symbol (secs)
modtronix 1:64a9c4a03244 713 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
modtronix 1:64a9c4a03244 714 double ts = 1 / rs;
modtronix 1:64a9c4a03244 715 // time of preamble
modtronix 1:64a9c4a03244 716 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
modtronix 1:64a9c4a03244 717 // Symbol length of payload and time
modtronix 1:64a9c4a03244 718 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
modtronix 1:64a9c4a03244 719 28 + 16 * this->settings.LoRa.CrcOn -
modtronix 1:64a9c4a03244 720 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
modtronix 1:64a9c4a03244 721 ( double )( 4 * this->settings.LoRa.Datarate -
modtronix 1:64a9c4a03244 722 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
modtronix 1:64a9c4a03244 723 ( this->settings.LoRa.Coderate + 4 );
modtronix 1:64a9c4a03244 724 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
modtronix 1:64a9c4a03244 725 double tPayload = nPayload * ts;
modtronix 1:64a9c4a03244 726 // Time on air
modtronix 1:64a9c4a03244 727 double tOnAir = tPreamble + tPayload;
modtronix 1:64a9c4a03244 728 // return us secs
modtronix 1:64a9c4a03244 729 airTime = floor( tOnAir * 1e6 + 0.999 );
modtronix 1:64a9c4a03244 730 }
modtronix 1:64a9c4a03244 731 break;
modtronix 1:64a9c4a03244 732 }
modtronix 1:64a9c4a03244 733 return airTime;
modtronix 1:64a9c4a03244 734 }
modtronix 1:64a9c4a03244 735
modtronix 1:64a9c4a03244 736 void InAir::Send( uint8_t *buffer, uint8_t size )
modtronix 1:64a9c4a03244 737 {
modtronix 1:64a9c4a03244 738 uint32_t txTimeout = 0;
modtronix 1:64a9c4a03244 739
modtronix 1:64a9c4a03244 740 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 741
modtronix 1:64a9c4a03244 742 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 743 {
modtronix 1:64a9c4a03244 744 case MODEM_FSK:
modtronix 1:64a9c4a03244 745 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 746 {
modtronix 1:64a9c4a03244 747 this->settings.FskPacketHandler.NbBytes = 0;
modtronix 1:64a9c4a03244 748 this->settings.FskPacketHandler.Size = size;
modtronix 1:64a9c4a03244 749
modtronix 1:64a9c4a03244 750 if( this->settings.Fsk.FixLen == false )
modtronix 1:64a9c4a03244 751 {
modtronix 1:64a9c4a03244 752 WriteFifo( ( uint8_t* )&size, 1 );
modtronix 1:64a9c4a03244 753 }
modtronix 1:64a9c4a03244 754 else
modtronix 1:64a9c4a03244 755 {
modtronix 1:64a9c4a03244 756 Write( REG_PAYLOADLENGTH, size );
modtronix 1:64a9c4a03244 757 }
modtronix 1:64a9c4a03244 758
modtronix 1:64a9c4a03244 759 if( ( size > 0 ) && ( size <= 64 ) )
modtronix 1:64a9c4a03244 760 {
modtronix 1:64a9c4a03244 761 this->settings.FskPacketHandler.ChunkSize = size;
modtronix 1:64a9c4a03244 762 }
modtronix 1:64a9c4a03244 763 else
modtronix 1:64a9c4a03244 764 {
modtronix 1:64a9c4a03244 765 this->settings.FskPacketHandler.ChunkSize = 32;
modtronix 1:64a9c4a03244 766 }
modtronix 1:64a9c4a03244 767
modtronix 1:64a9c4a03244 768 // Write payload buffer
modtronix 1:64a9c4a03244 769 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
modtronix 1:64a9c4a03244 770 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
modtronix 1:64a9c4a03244 771 txTimeout = this->settings.Fsk.TxTimeout;
modtronix 1:64a9c4a03244 772 }
modtronix 1:64a9c4a03244 773 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 774 break;
modtronix 1:64a9c4a03244 775 case MODEM_LORA:
modtronix 1:64a9c4a03244 776 {
modtronix 1:64a9c4a03244 777 if( this->settings.LoRa.IqInverted == true )
modtronix 1:64a9c4a03244 778 {
modtronix 1:64a9c4a03244 779 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
modtronix 1:64a9c4a03244 780 }
modtronix 1:64a9c4a03244 781 else
modtronix 1:64a9c4a03244 782 {
modtronix 1:64a9c4a03244 783 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
modtronix 1:64a9c4a03244 784 }
modtronix 1:64a9c4a03244 785
modtronix 1:64a9c4a03244 786 this->settings.LoRaPacketHandler.Size = size;
modtronix 1:64a9c4a03244 787
modtronix 1:64a9c4a03244 788 // Initializes the payload size
modtronix 1:64a9c4a03244 789 Write( REG_LR_PAYLOADLENGTH, size );
modtronix 1:64a9c4a03244 790
modtronix 1:64a9c4a03244 791 // Full buffer used for Tx
modtronix 1:64a9c4a03244 792 Write( REG_LR_FIFOTXBASEADDR, 0 );
modtronix 1:64a9c4a03244 793 Write( REG_LR_FIFOADDRPTR, 0 );
modtronix 1:64a9c4a03244 794
modtronix 1:64a9c4a03244 795 // FIFO operations can not take place in Sleep mode
modtronix 1:64a9c4a03244 796 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
modtronix 1:64a9c4a03244 797 {
modtronix 1:64a9c4a03244 798 Standby( );
modtronix 1:64a9c4a03244 799 wait_ms( 1 );
modtronix 1:64a9c4a03244 800 }
modtronix 1:64a9c4a03244 801 // Write payload buffer
modtronix 1:64a9c4a03244 802 WriteFifo( buffer, size );
modtronix 1:64a9c4a03244 803 txTimeout = this->settings.LoRa.TxTimeout;
modtronix 1:64a9c4a03244 804 }
modtronix 1:64a9c4a03244 805 break;
modtronix 1:64a9c4a03244 806 }
modtronix 1:64a9c4a03244 807
modtronix 1:64a9c4a03244 808 Tx( txTimeout );
modtronix 1:64a9c4a03244 809 }
modtronix 1:64a9c4a03244 810
modtronix 1:64a9c4a03244 811 void InAir::Sleep( void )
modtronix 1:64a9c4a03244 812 {
modtronix 1:64a9c4a03244 813 // Initialize driver timeout timers
modtronix 1:64a9c4a03244 814 txTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 815 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 816 SetOpMode( RF_OPMODE_SLEEP );
modtronix 1:64a9c4a03244 817 }
modtronix 1:64a9c4a03244 818
modtronix 1:64a9c4a03244 819 void InAir::Standby( void )
modtronix 1:64a9c4a03244 820 {
modtronix 1:64a9c4a03244 821 txTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 822 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 823 SetOpMode( RF_OPMODE_STANDBY );
modtronix 1:64a9c4a03244 824 }
modtronix 1:64a9c4a03244 825
modtronix 1:64a9c4a03244 826 void InAir::Rx( uint32_t timeout )
modtronix 1:64a9c4a03244 827 {
modtronix 1:64a9c4a03244 828 bool rxContinuous = false;
modtronix 1:64a9c4a03244 829
modtronix 1:64a9c4a03244 830 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 831 {
modtronix 1:64a9c4a03244 832 case MODEM_FSK:
modtronix 1:64a9c4a03244 833 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 834 {
modtronix 1:64a9c4a03244 835 rxContinuous = this->settings.Fsk.RxContinuous;
modtronix 1:64a9c4a03244 836
modtronix 1:64a9c4a03244 837 // DIO0=PayloadReady
modtronix 1:64a9c4a03244 838 // DIO1=FifoLevel
modtronix 1:64a9c4a03244 839 // DIO2=SyncAddr
modtronix 1:64a9c4a03244 840 // DIO3=FifoEmpty
modtronix 1:64a9c4a03244 841 // DIO4=Preamble
modtronix 1:64a9c4a03244 842 // DIO5=ModeReady
modtronix 1:64a9c4a03244 843 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
modtronix 1:64a9c4a03244 844 RF_DIOMAPPING1_DIO2_MASK ) |
modtronix 1:64a9c4a03244 845 RF_DIOMAPPING1_DIO0_00 |
modtronix 1:64a9c4a03244 846 RF_DIOMAPPING1_DIO2_11 );
modtronix 1:64a9c4a03244 847
modtronix 1:64a9c4a03244 848 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
modtronix 1:64a9c4a03244 849 RF_DIOMAPPING2_MAP_MASK ) |
modtronix 1:64a9c4a03244 850 RF_DIOMAPPING2_DIO4_11 |
modtronix 1:64a9c4a03244 851 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
modtronix 1:64a9c4a03244 852
modtronix 1:64a9c4a03244 853 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
modtronix 1:64a9c4a03244 854
modtronix 1:64a9c4a03244 855 this->settings.FskPacketHandler.PreambleDetected = false;
modtronix 1:64a9c4a03244 856 this->settings.FskPacketHandler.SyncWordDetected = false;
modtronix 1:64a9c4a03244 857 this->settings.FskPacketHandler.NbBytes = 0;
modtronix 1:64a9c4a03244 858 this->settings.FskPacketHandler.Size = 0;
modtronix 1:64a9c4a03244 859 }
modtronix 1:64a9c4a03244 860 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 861 break;
modtronix 1:64a9c4a03244 862 case MODEM_LORA:
modtronix 1:64a9c4a03244 863 {
modtronix 1:64a9c4a03244 864 if( this->settings.LoRa.IqInverted == true )
modtronix 1:64a9c4a03244 865 {
modtronix 1:64a9c4a03244 866 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
modtronix 1:64a9c4a03244 867 }
modtronix 1:64a9c4a03244 868 else
modtronix 1:64a9c4a03244 869 {
modtronix 1:64a9c4a03244 870 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
modtronix 1:64a9c4a03244 871 }
modtronix 1:64a9c4a03244 872
modtronix 1:64a9c4a03244 873 rxContinuous = this->settings.LoRa.RxContinuous;
modtronix 1:64a9c4a03244 874
modtronix 1:64a9c4a03244 875 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 876 {
modtronix 1:64a9c4a03244 877 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 878 //RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 879 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 880 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 881 RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 882 RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 883 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
modtronix 1:64a9c4a03244 884 RFLR_IRQFLAGS_CADDETECTED );
modtronix 1:64a9c4a03244 885
modtronix 1:64a9c4a03244 886 // DIO0=RxDone, DIO2=FhssChangeChannel
modtronix 1:64a9c4a03244 887 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
modtronix 1:64a9c4a03244 888 }
modtronix 1:64a9c4a03244 889 else
modtronix 1:64a9c4a03244 890 {
modtronix 1:64a9c4a03244 891 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 892 //RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 893 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 894 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 895 RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 896 RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 897 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
modtronix 1:64a9c4a03244 898 RFLR_IRQFLAGS_CADDETECTED );
modtronix 1:64a9c4a03244 899
modtronix 1:64a9c4a03244 900 // DIO0=RxDone
modtronix 1:64a9c4a03244 901 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
modtronix 1:64a9c4a03244 902 }
modtronix 1:64a9c4a03244 903
modtronix 1:64a9c4a03244 904 Write( REG_LR_FIFORXBASEADDR, 0 );
modtronix 1:64a9c4a03244 905 Write( REG_LR_FIFOADDRPTR, 0 );
modtronix 1:64a9c4a03244 906 }
modtronix 1:64a9c4a03244 907 break;
modtronix 1:64a9c4a03244 908 }
modtronix 1:64a9c4a03244 909
modtronix 1:64a9c4a03244 910 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
modtronix 1:64a9c4a03244 911
modtronix 1:64a9c4a03244 912 this->settings.State = RX_DONE;
modtronix 1:64a9c4a03244 913 if( timeout != 0 )
modtronix 1:64a9c4a03244 914 {
modtronix 1:64a9c4a03244 915 rxTimeoutTimer.attach_us( this, &InAir::OnTimeoutIrq, timeout );
modtronix 1:64a9c4a03244 916 }
modtronix 1:64a9c4a03244 917
modtronix 1:64a9c4a03244 918 if( this->settings.Modem == MODEM_FSK )
modtronix 1:64a9c4a03244 919 {
modtronix 1:64a9c4a03244 920 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 921 SetOpMode( RF_OPMODE_RECEIVER );
modtronix 1:64a9c4a03244 922
modtronix 1:64a9c4a03244 923 if( rxContinuous == false )
modtronix 1:64a9c4a03244 924 {
modtronix 1:64a9c4a03244 925 rxTimeoutSyncWord.attach_us( this, &InAir::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
modtronix 1:64a9c4a03244 926 ( ( Read( REG_SYNCCONFIG ) &
modtronix 1:64a9c4a03244 927 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
modtronix 1:64a9c4a03244 928 1.0 ) + 1.0 ) /
modtronix 1:64a9c4a03244 929 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
modtronix 1:64a9c4a03244 930 }
modtronix 1:64a9c4a03244 931 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 932 }
modtronix 1:64a9c4a03244 933 else
modtronix 1:64a9c4a03244 934 {
modtronix 1:64a9c4a03244 935 if( rxContinuous == true )
modtronix 1:64a9c4a03244 936 {
modtronix 1:64a9c4a03244 937 SetOpMode( RFLR_OPMODE_RECEIVER );
modtronix 1:64a9c4a03244 938 }
modtronix 1:64a9c4a03244 939 else
modtronix 1:64a9c4a03244 940 {
modtronix 1:64a9c4a03244 941 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
modtronix 1:64a9c4a03244 942 }
modtronix 1:64a9c4a03244 943 }
modtronix 1:64a9c4a03244 944 }
modtronix 1:64a9c4a03244 945
modtronix 1:64a9c4a03244 946 void InAir::Tx( uint32_t timeout )
modtronix 1:64a9c4a03244 947 {
modtronix 1:64a9c4a03244 948 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 949 {
modtronix 1:64a9c4a03244 950 case MODEM_FSK:
modtronix 1:64a9c4a03244 951 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 952 {
modtronix 1:64a9c4a03244 953 // DIO0=PacketSent
modtronix 1:64a9c4a03244 954 // DIO1=FifoLevel
modtronix 1:64a9c4a03244 955 // DIO2=FifoFull
modtronix 1:64a9c4a03244 956 // DIO3=FifoEmpty
modtronix 1:64a9c4a03244 957 // DIO4=LowBat
modtronix 1:64a9c4a03244 958 // DIO5=ModeReady
modtronix 1:64a9c4a03244 959 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
modtronix 1:64a9c4a03244 960 RF_DIOMAPPING1_DIO2_MASK ) );
modtronix 1:64a9c4a03244 961
modtronix 1:64a9c4a03244 962 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
modtronix 1:64a9c4a03244 963 RF_DIOMAPPING2_MAP_MASK ) );
modtronix 1:64a9c4a03244 964 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
modtronix 1:64a9c4a03244 965 }
modtronix 1:64a9c4a03244 966 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 967 break;
modtronix 1:64a9c4a03244 968 case MODEM_LORA:
modtronix 1:64a9c4a03244 969 {
modtronix 1:64a9c4a03244 970
modtronix 1:64a9c4a03244 971 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 972 {
modtronix 1:64a9c4a03244 973 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 974 RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 975 RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 976 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 977 //RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 978 RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 979 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
modtronix 1:64a9c4a03244 980 RFLR_IRQFLAGS_CADDETECTED );
modtronix 1:64a9c4a03244 981
modtronix 1:64a9c4a03244 982 // DIO0=TxDone
modtronix 1:64a9c4a03244 983 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
modtronix 1:64a9c4a03244 984 // DIO2=FhssChangeChannel
modtronix 1:64a9c4a03244 985 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
modtronix 1:64a9c4a03244 986 }
modtronix 1:64a9c4a03244 987 else
modtronix 1:64a9c4a03244 988 {
modtronix 1:64a9c4a03244 989 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 990 RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 991 RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 992 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 993 //RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 994 RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 995 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
modtronix 1:64a9c4a03244 996 RFLR_IRQFLAGS_CADDETECTED );
modtronix 1:64a9c4a03244 997
modtronix 1:64a9c4a03244 998 // DIO0=TxDone
modtronix 1:64a9c4a03244 999 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
modtronix 1:64a9c4a03244 1000 }
modtronix 1:64a9c4a03244 1001 }
modtronix 1:64a9c4a03244 1002 break;
modtronix 1:64a9c4a03244 1003 }
modtronix 1:64a9c4a03244 1004
modtronix 1:64a9c4a03244 1005 this->settings.State = TX_DONE;
modtronix 1:64a9c4a03244 1006 txTimeoutTimer.attach_us( this, &InAir::OnTimeoutIrq, timeout );
modtronix 1:64a9c4a03244 1007 SetOpMode( RF_OPMODE_TRANSMITTER );
modtronix 1:64a9c4a03244 1008 }
modtronix 1:64a9c4a03244 1009
modtronix 1:64a9c4a03244 1010 void InAir::StartCad( void )
modtronix 1:64a9c4a03244 1011 {
modtronix 1:64a9c4a03244 1012 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1013 {
modtronix 1:64a9c4a03244 1014 case MODEM_FSK:
modtronix 1:64a9c4a03244 1015 {
modtronix 1:64a9c4a03244 1016
modtronix 1:64a9c4a03244 1017 }
modtronix 1:64a9c4a03244 1018 break;
modtronix 1:64a9c4a03244 1019 case MODEM_LORA:
modtronix 1:64a9c4a03244 1020 {
modtronix 1:64a9c4a03244 1021 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
modtronix 1:64a9c4a03244 1022 RFLR_IRQFLAGS_RXDONE |
modtronix 1:64a9c4a03244 1023 RFLR_IRQFLAGS_PAYLOADCRCERROR |
modtronix 1:64a9c4a03244 1024 RFLR_IRQFLAGS_VALIDHEADER |
modtronix 1:64a9c4a03244 1025 RFLR_IRQFLAGS_TXDONE |
modtronix 1:64a9c4a03244 1026 //RFLR_IRQFLAGS_CADDONE |
modtronix 1:64a9c4a03244 1027 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
modtronix 1:64a9c4a03244 1028 //RFLR_IRQFLAGS_CADDETECTED
modtronix 1:64a9c4a03244 1029 );
modtronix 1:64a9c4a03244 1030
modtronix 1:64a9c4a03244 1031 // DIO3=CADDone
modtronix 1:64a9c4a03244 1032 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
modtronix 1:64a9c4a03244 1033
modtronix 1:64a9c4a03244 1034 this->settings.State = CAD;
modtronix 1:64a9c4a03244 1035 SetOpMode( RFLR_OPMODE_CAD );
modtronix 1:64a9c4a03244 1036 }
modtronix 1:64a9c4a03244 1037 break;
modtronix 1:64a9c4a03244 1038 default:
modtronix 1:64a9c4a03244 1039 break;
modtronix 1:64a9c4a03244 1040 }
modtronix 1:64a9c4a03244 1041 }
modtronix 1:64a9c4a03244 1042
modtronix 1:64a9c4a03244 1043 int16_t InAir::GetRssi( ModemType modem )
modtronix 1:64a9c4a03244 1044 {
modtronix 1:64a9c4a03244 1045 int16_t rssi = 0;
modtronix 1:64a9c4a03244 1046
modtronix 1:64a9c4a03244 1047 switch( modem )
modtronix 1:64a9c4a03244 1048 {
modtronix 1:64a9c4a03244 1049 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1050 case MODEM_FSK:
modtronix 1:64a9c4a03244 1051 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
modtronix 1:64a9c4a03244 1052 break;
modtronix 1:64a9c4a03244 1053 #endif
modtronix 1:64a9c4a03244 1054 case MODEM_LORA:
modtronix 1:64a9c4a03244 1055 if( this->settings.Channel > RF_MID_BAND_THRESH )
modtronix 1:64a9c4a03244 1056 {
modtronix 1:64a9c4a03244 1057 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
modtronix 1:64a9c4a03244 1058 }
modtronix 1:64a9c4a03244 1059 else
modtronix 1:64a9c4a03244 1060 {
modtronix 1:64a9c4a03244 1061 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
modtronix 1:64a9c4a03244 1062 }
modtronix 1:64a9c4a03244 1063 break;
modtronix 1:64a9c4a03244 1064 default:
modtronix 1:64a9c4a03244 1065 rssi = -1;
modtronix 1:64a9c4a03244 1066 break;
modtronix 1:64a9c4a03244 1067 }
modtronix 1:64a9c4a03244 1068 return rssi;
modtronix 1:64a9c4a03244 1069 }
modtronix 1:64a9c4a03244 1070
modtronix 1:64a9c4a03244 1071 void InAir::SetOpMode( uint8_t opMode )
modtronix 1:64a9c4a03244 1072 {
modtronix 1:64a9c4a03244 1073 if( opMode != previousOpMode )
modtronix 1:64a9c4a03244 1074 {
modtronix 1:64a9c4a03244 1075 previousOpMode = opMode;
modtronix 1:64a9c4a03244 1076 if( opMode == RF_OPMODE_SLEEP )
modtronix 1:64a9c4a03244 1077 {
modtronix 1:64a9c4a03244 1078 //SetAntSwLowPower( true );
modtronix 1:64a9c4a03244 1079 }
modtronix 1:64a9c4a03244 1080 else
modtronix 1:64a9c4a03244 1081 {
modtronix 1:64a9c4a03244 1082 //SetAntSwLowPower( false );
modtronix 1:64a9c4a03244 1083 }
modtronix 1:64a9c4a03244 1084 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
modtronix 1:64a9c4a03244 1085 }
modtronix 1:64a9c4a03244 1086 }
modtronix 1:64a9c4a03244 1087
modtronix 1:64a9c4a03244 1088 void InAir::SetModem( ModemType modem )
modtronix 1:64a9c4a03244 1089 {
modtronix 1:64a9c4a03244 1090 if( this->settings.Modem != modem )
modtronix 1:64a9c4a03244 1091 {
modtronix 1:64a9c4a03244 1092 this->settings.Modem = modem;
modtronix 1:64a9c4a03244 1093 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1094 {
modtronix 1:64a9c4a03244 1095 default:
modtronix 1:64a9c4a03244 1096 case MODEM_FSK:
modtronix 1:64a9c4a03244 1097 SetOpMode( RF_OPMODE_SLEEP );
modtronix 1:64a9c4a03244 1098 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
modtronix 1:64a9c4a03244 1099
modtronix 1:64a9c4a03244 1100 Write( REG_DIOMAPPING1, 0x00 );
modtronix 1:64a9c4a03244 1101 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
modtronix 1:64a9c4a03244 1102 break;
modtronix 1:64a9c4a03244 1103 case MODEM_LORA:
modtronix 1:64a9c4a03244 1104 SetOpMode( RF_OPMODE_SLEEP );
modtronix 1:64a9c4a03244 1105 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
modtronix 1:64a9c4a03244 1106 Write( 0x30, 0x00 ); // IF = 0
modtronix 1:64a9c4a03244 1107 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
modtronix 1:64a9c4a03244 1108 Write( REG_DIOMAPPING1, 0x00 );
modtronix 1:64a9c4a03244 1109 Write( REG_DIOMAPPING2, 0x00 );
modtronix 1:64a9c4a03244 1110 break;
modtronix 1:64a9c4a03244 1111 }
modtronix 1:64a9c4a03244 1112 }
modtronix 1:64a9c4a03244 1113 }
modtronix 1:64a9c4a03244 1114
modtronix 1:64a9c4a03244 1115 void InAir::OnTimeoutIrq( void )
modtronix 1:64a9c4a03244 1116 {
modtronix 1:64a9c4a03244 1117 switch( this->settings.State )
modtronix 1:64a9c4a03244 1118 {
modtronix 1:64a9c4a03244 1119 case RX_DONE:
modtronix 1:64a9c4a03244 1120 if( this->settings.Modem == MODEM_FSK )
modtronix 1:64a9c4a03244 1121 {
modtronix 1:64a9c4a03244 1122 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1123 this->settings.FskPacketHandler.PreambleDetected = false;
modtronix 1:64a9c4a03244 1124 this->settings.FskPacketHandler.SyncWordDetected = false;
modtronix 1:64a9c4a03244 1125 this->settings.FskPacketHandler.NbBytes = 0;
modtronix 1:64a9c4a03244 1126 this->settings.FskPacketHandler.Size = 0;
modtronix 1:64a9c4a03244 1127
modtronix 1:64a9c4a03244 1128 // Clear Irqs
modtronix 1:64a9c4a03244 1129 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
modtronix 1:64a9c4a03244 1130 RF_IRQFLAGS1_PREAMBLEDETECT |
modtronix 1:64a9c4a03244 1131 RF_IRQFLAGS1_SYNCADDRESSMATCH );
modtronix 1:64a9c4a03244 1132 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
modtronix 1:64a9c4a03244 1133
modtronix 1:64a9c4a03244 1134 if( this->settings.Fsk.RxContinuous == true )
modtronix 1:64a9c4a03244 1135 {
modtronix 1:64a9c4a03244 1136 // Continuous mode restart Rx chain
modtronix 1:64a9c4a03244 1137 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
modtronix 1:64a9c4a03244 1138 }
modtronix 1:64a9c4a03244 1139 else
modtronix 1:64a9c4a03244 1140 {
modtronix 1:64a9c4a03244 1141 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1142 rxTimeoutSyncWord.detach( );
modtronix 1:64a9c4a03244 1143 }
modtronix 1:64a9c4a03244 1144 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1145 }
modtronix 1:64a9c4a03244 1146 if( ( rxTimeout != NULL ) )
modtronix 1:64a9c4a03244 1147 {
modtronix 1:64a9c4a03244 1148 rxTimeout( );
modtronix 1:64a9c4a03244 1149 }
modtronix 1:64a9c4a03244 1150 break;
modtronix 1:64a9c4a03244 1151 case TX_DONE:
modtronix 1:64a9c4a03244 1152 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1153 if( ( txTimeout != NULL ) )
modtronix 1:64a9c4a03244 1154 {
modtronix 1:64a9c4a03244 1155 txTimeout( );
modtronix 1:64a9c4a03244 1156 }
modtronix 1:64a9c4a03244 1157 break;
modtronix 1:64a9c4a03244 1158 default:
modtronix 1:64a9c4a03244 1159 break;
modtronix 1:64a9c4a03244 1160 }
modtronix 1:64a9c4a03244 1161 }
modtronix 1:64a9c4a03244 1162
modtronix 1:64a9c4a03244 1163 void InAir::OnDio0Irq( void )
modtronix 1:64a9c4a03244 1164 {
modtronix 1:64a9c4a03244 1165 __IO uint8_t irqFlags = 0;
modtronix 1:64a9c4a03244 1166
modtronix 1:64a9c4a03244 1167 switch( this->settings.State )
modtronix 1:64a9c4a03244 1168 {
modtronix 1:64a9c4a03244 1169 case RX_DONE:
modtronix 1:64a9c4a03244 1170 //TimerStop( &RxTimeoutTimer );
modtronix 1:64a9c4a03244 1171 // RxDone interrupt
modtronix 1:64a9c4a03244 1172 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1173 {
modtronix 1:64a9c4a03244 1174 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1175 case MODEM_FSK:
modtronix 1:64a9c4a03244 1176 if( this->settings.Fsk.CrcOn == true )
modtronix 1:64a9c4a03244 1177 {
modtronix 1:64a9c4a03244 1178 irqFlags = Read( REG_IRQFLAGS2 );
modtronix 1:64a9c4a03244 1179 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
modtronix 1:64a9c4a03244 1180 {
modtronix 1:64a9c4a03244 1181 // Clear Irqs
modtronix 1:64a9c4a03244 1182 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
modtronix 1:64a9c4a03244 1183 RF_IRQFLAGS1_PREAMBLEDETECT |
modtronix 1:64a9c4a03244 1184 RF_IRQFLAGS1_SYNCADDRESSMATCH );
modtronix 1:64a9c4a03244 1185 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
modtronix 1:64a9c4a03244 1186
modtronix 1:64a9c4a03244 1187 if( this->settings.Fsk.RxContinuous == false )
modtronix 1:64a9c4a03244 1188 {
modtronix 1:64a9c4a03244 1189 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1190 rxTimeoutSyncWord.attach_us( this, &InAir::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
modtronix 1:64a9c4a03244 1191 ( ( Read( REG_SYNCCONFIG ) &
modtronix 1:64a9c4a03244 1192 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
modtronix 1:64a9c4a03244 1193 1.0 ) + 1.0 ) /
modtronix 1:64a9c4a03244 1194 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
modtronix 1:64a9c4a03244 1195 }
modtronix 1:64a9c4a03244 1196 else
modtronix 1:64a9c4a03244 1197 {
modtronix 1:64a9c4a03244 1198 // Continuous mode restart Rx chain
modtronix 1:64a9c4a03244 1199 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
modtronix 1:64a9c4a03244 1200 }
modtronix 1:64a9c4a03244 1201 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1202
modtronix 1:64a9c4a03244 1203 if( ( rxError != NULL ) )
modtronix 1:64a9c4a03244 1204 {
modtronix 1:64a9c4a03244 1205 rxError( );
modtronix 1:64a9c4a03244 1206 }
modtronix 1:64a9c4a03244 1207 this->settings.FskPacketHandler.PreambleDetected = false;
modtronix 1:64a9c4a03244 1208 this->settings.FskPacketHandler.SyncWordDetected = false;
modtronix 1:64a9c4a03244 1209 this->settings.FskPacketHandler.NbBytes = 0;
modtronix 1:64a9c4a03244 1210 this->settings.FskPacketHandler.Size = 0;
modtronix 1:64a9c4a03244 1211 break;
modtronix 1:64a9c4a03244 1212 }
modtronix 1:64a9c4a03244 1213 }
modtronix 1:64a9c4a03244 1214
modtronix 1:64a9c4a03244 1215 // Read received packet size
modtronix 1:64a9c4a03244 1216 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
modtronix 1:64a9c4a03244 1217 {
modtronix 1:64a9c4a03244 1218 if( this->settings.Fsk.FixLen == false )
modtronix 1:64a9c4a03244 1219 {
modtronix 1:64a9c4a03244 1220 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
modtronix 1:64a9c4a03244 1221 }
modtronix 1:64a9c4a03244 1222 else
modtronix 1:64a9c4a03244 1223 {
modtronix 1:64a9c4a03244 1224 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
modtronix 1:64a9c4a03244 1225 }
modtronix 1:64a9c4a03244 1226 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1227 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1228 }
modtronix 1:64a9c4a03244 1229 else
modtronix 1:64a9c4a03244 1230 {
modtronix 1:64a9c4a03244 1231 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1232 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1233 }
modtronix 1:64a9c4a03244 1234
modtronix 1:64a9c4a03244 1235 if( this->settings.Fsk.RxContinuous == false )
modtronix 1:64a9c4a03244 1236 {
modtronix 1:64a9c4a03244 1237 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1238 rxTimeoutSyncWord.attach_us( this, &InAir::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
modtronix 1:64a9c4a03244 1239 ( ( Read( REG_SYNCCONFIG ) &
modtronix 1:64a9c4a03244 1240 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
modtronix 1:64a9c4a03244 1241 1.0 ) + 1.0 ) /
modtronix 1:64a9c4a03244 1242 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
modtronix 1:64a9c4a03244 1243 }
modtronix 1:64a9c4a03244 1244 else
modtronix 1:64a9c4a03244 1245 {
modtronix 1:64a9c4a03244 1246 // Continuous mode restart Rx chain
modtronix 1:64a9c4a03244 1247 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
modtronix 1:64a9c4a03244 1248 }
modtronix 1:64a9c4a03244 1249 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1250
modtronix 1:64a9c4a03244 1251 if( (rxDone != NULL ) )
modtronix 1:64a9c4a03244 1252 {
modtronix 1:64a9c4a03244 1253 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
modtronix 1:64a9c4a03244 1254 }
modtronix 1:64a9c4a03244 1255 this->settings.FskPacketHandler.PreambleDetected = false;
modtronix 1:64a9c4a03244 1256 this->settings.FskPacketHandler.SyncWordDetected = false;
modtronix 1:64a9c4a03244 1257 this->settings.FskPacketHandler.NbBytes = 0;
modtronix 1:64a9c4a03244 1258 this->settings.FskPacketHandler.Size = 0;
modtronix 1:64a9c4a03244 1259 break;
modtronix 1:64a9c4a03244 1260 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1261 case MODEM_LORA:
modtronix 1:64a9c4a03244 1262 {
modtronix 1:64a9c4a03244 1263 uint8_t snr = 0;
modtronix 1:64a9c4a03244 1264
modtronix 1:64a9c4a03244 1265 // Clear Irq
modtronix 1:64a9c4a03244 1266 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
modtronix 1:64a9c4a03244 1267
modtronix 1:64a9c4a03244 1268 irqFlags = Read( REG_LR_IRQFLAGS );
modtronix 1:64a9c4a03244 1269 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
modtronix 1:64a9c4a03244 1270 {
modtronix 1:64a9c4a03244 1271 // Clear Irq
modtronix 1:64a9c4a03244 1272 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
modtronix 1:64a9c4a03244 1273
modtronix 1:64a9c4a03244 1274 if( this->settings.LoRa.RxContinuous == false )
modtronix 1:64a9c4a03244 1275 {
modtronix 1:64a9c4a03244 1276 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1277 }
modtronix 1:64a9c4a03244 1278 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1279
modtronix 1:64a9c4a03244 1280 if( ( rxError != NULL ) )
modtronix 1:64a9c4a03244 1281 {
modtronix 1:64a9c4a03244 1282 rxError( );
modtronix 1:64a9c4a03244 1283 }
modtronix 1:64a9c4a03244 1284 break;
modtronix 1:64a9c4a03244 1285 }
modtronix 1:64a9c4a03244 1286
modtronix 1:64a9c4a03244 1287 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
modtronix 1:64a9c4a03244 1288 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
modtronix 1:64a9c4a03244 1289 {
modtronix 1:64a9c4a03244 1290 // Invert and divide by 4
modtronix 1:64a9c4a03244 1291 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
modtronix 1:64a9c4a03244 1292 snr = -snr;
modtronix 1:64a9c4a03244 1293 }
modtronix 1:64a9c4a03244 1294 else
modtronix 1:64a9c4a03244 1295 {
modtronix 1:64a9c4a03244 1296 // Divide by 4
modtronix 1:64a9c4a03244 1297 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
modtronix 1:64a9c4a03244 1298 }
modtronix 1:64a9c4a03244 1299
modtronix 1:64a9c4a03244 1300 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
modtronix 1:64a9c4a03244 1301 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
modtronix 1:64a9c4a03244 1302 {
modtronix 1:64a9c4a03244 1303 if( this->settings.Channel > RF_MID_BAND_THRESH )
modtronix 1:64a9c4a03244 1304 {
modtronix 1:64a9c4a03244 1305 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
modtronix 1:64a9c4a03244 1306 snr;
modtronix 1:64a9c4a03244 1307 }
modtronix 1:64a9c4a03244 1308 else
modtronix 1:64a9c4a03244 1309 {
modtronix 1:64a9c4a03244 1310 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
modtronix 1:64a9c4a03244 1311 snr;
modtronix 1:64a9c4a03244 1312 }
modtronix 1:64a9c4a03244 1313 }
modtronix 1:64a9c4a03244 1314 else
modtronix 1:64a9c4a03244 1315 {
modtronix 1:64a9c4a03244 1316 if( this->settings.Channel > RF_MID_BAND_THRESH )
modtronix 1:64a9c4a03244 1317 {
modtronix 1:64a9c4a03244 1318 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
modtronix 1:64a9c4a03244 1319 }
modtronix 1:64a9c4a03244 1320 else
modtronix 1:64a9c4a03244 1321 {
modtronix 1:64a9c4a03244 1322 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
modtronix 1:64a9c4a03244 1323 }
modtronix 1:64a9c4a03244 1324 }
modtronix 1:64a9c4a03244 1325
modtronix 1:64a9c4a03244 1326 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
modtronix 1:64a9c4a03244 1327 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
modtronix 1:64a9c4a03244 1328
modtronix 1:64a9c4a03244 1329 if( this->settings.LoRa.RxContinuous == false )
modtronix 1:64a9c4a03244 1330 {
modtronix 1:64a9c4a03244 1331 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1332 }
modtronix 1:64a9c4a03244 1333 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1334
modtronix 1:64a9c4a03244 1335 if( ( rxDone != NULL ) )
modtronix 1:64a9c4a03244 1336 {
modtronix 1:64a9c4a03244 1337 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
modtronix 1:64a9c4a03244 1338 }
modtronix 1:64a9c4a03244 1339 }
modtronix 1:64a9c4a03244 1340 break;
modtronix 1:64a9c4a03244 1341 default:
modtronix 1:64a9c4a03244 1342 break;
modtronix 1:64a9c4a03244 1343 }
modtronix 1:64a9c4a03244 1344 break;
modtronix 1:64a9c4a03244 1345 case TX_DONE:
modtronix 1:64a9c4a03244 1346 txTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1347 // TxDone interrupt
modtronix 1:64a9c4a03244 1348 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1349 {
modtronix 1:64a9c4a03244 1350 case MODEM_LORA:
modtronix 1:64a9c4a03244 1351 // Clear Irq
modtronix 1:64a9c4a03244 1352 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
modtronix 1:64a9c4a03244 1353 // Intentional fall through
modtronix 1:64a9c4a03244 1354 case MODEM_FSK:
modtronix 1:64a9c4a03244 1355 default:
modtronix 1:64a9c4a03244 1356 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1357 if( ( txDone != NULL ) )
modtronix 1:64a9c4a03244 1358 {
modtronix 1:64a9c4a03244 1359 txDone( );
modtronix 1:64a9c4a03244 1360 }
modtronix 1:64a9c4a03244 1361 break;
modtronix 1:64a9c4a03244 1362 }
modtronix 1:64a9c4a03244 1363 break;
modtronix 1:64a9c4a03244 1364 default:
modtronix 1:64a9c4a03244 1365 break;
modtronix 1:64a9c4a03244 1366 }
modtronix 1:64a9c4a03244 1367 }
modtronix 1:64a9c4a03244 1368
modtronix 1:64a9c4a03244 1369 void InAir::OnDio1Irq( void )
modtronix 1:64a9c4a03244 1370 {
modtronix 1:64a9c4a03244 1371 switch( this->settings.State )
modtronix 1:64a9c4a03244 1372 {
modtronix 1:64a9c4a03244 1373 case RX_DONE:
modtronix 1:64a9c4a03244 1374 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1375 {
modtronix 1:64a9c4a03244 1376 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1377 case MODEM_FSK:
modtronix 1:64a9c4a03244 1378 // FifoLevel interrupt
modtronix 1:64a9c4a03244 1379 // Read received packet size
modtronix 1:64a9c4a03244 1380 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
modtronix 1:64a9c4a03244 1381 {
modtronix 1:64a9c4a03244 1382 if( this->settings.Fsk.FixLen == false )
modtronix 1:64a9c4a03244 1383 {
modtronix 1:64a9c4a03244 1384 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
modtronix 1:64a9c4a03244 1385 }
modtronix 1:64a9c4a03244 1386 else
modtronix 1:64a9c4a03244 1387 {
modtronix 1:64a9c4a03244 1388 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
modtronix 1:64a9c4a03244 1389 }
modtronix 1:64a9c4a03244 1390 }
modtronix 1:64a9c4a03244 1391
modtronix 1:64a9c4a03244 1392 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
modtronix 1:64a9c4a03244 1393 {
modtronix 1:64a9c4a03244 1394 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
modtronix 1:64a9c4a03244 1395 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
modtronix 1:64a9c4a03244 1396 }
modtronix 1:64a9c4a03244 1397 else
modtronix 1:64a9c4a03244 1398 {
modtronix 1:64a9c4a03244 1399 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1400 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1401 }
modtronix 1:64a9c4a03244 1402 break;
modtronix 1:64a9c4a03244 1403 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1404 case MODEM_LORA:
modtronix 1:64a9c4a03244 1405 // Sync time out
modtronix 1:64a9c4a03244 1406 rxTimeoutTimer.detach( );
modtronix 1:64a9c4a03244 1407 this->settings.State = IDLE;
modtronix 1:64a9c4a03244 1408 if( ( rxTimeout != NULL ) )
modtronix 1:64a9c4a03244 1409 {
modtronix 1:64a9c4a03244 1410 rxTimeout( );
modtronix 1:64a9c4a03244 1411 }
modtronix 1:64a9c4a03244 1412 break;
modtronix 1:64a9c4a03244 1413 default:
modtronix 1:64a9c4a03244 1414 break;
modtronix 1:64a9c4a03244 1415 }
modtronix 1:64a9c4a03244 1416 break;
modtronix 1:64a9c4a03244 1417 case TX_DONE:
modtronix 1:64a9c4a03244 1418 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1419 {
modtronix 1:64a9c4a03244 1420 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1421 case MODEM_FSK:
modtronix 1:64a9c4a03244 1422 // FifoLevel interrupt
modtronix 1:64a9c4a03244 1423 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
modtronix 1:64a9c4a03244 1424 {
modtronix 1:64a9c4a03244 1425 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
modtronix 1:64a9c4a03244 1426 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
modtronix 1:64a9c4a03244 1427 }
modtronix 1:64a9c4a03244 1428 else
modtronix 1:64a9c4a03244 1429 {
modtronix 1:64a9c4a03244 1430 // Write the last chunk of data
modtronix 1:64a9c4a03244 1431 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
modtronix 1:64a9c4a03244 1432 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
modtronix 1:64a9c4a03244 1433 }
modtronix 1:64a9c4a03244 1434 break;
modtronix 1:64a9c4a03244 1435 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1436 case MODEM_LORA:
modtronix 1:64a9c4a03244 1437 break;
modtronix 1:64a9c4a03244 1438 default:
modtronix 1:64a9c4a03244 1439 break;
modtronix 1:64a9c4a03244 1440 }
modtronix 1:64a9c4a03244 1441 break;
modtronix 1:64a9c4a03244 1442 default:
modtronix 1:64a9c4a03244 1443 break;
modtronix 1:64a9c4a03244 1444 }
modtronix 1:64a9c4a03244 1445 }
modtronix 1:64a9c4a03244 1446
modtronix 1:64a9c4a03244 1447 void InAir::OnDio2Irq( void )
modtronix 1:64a9c4a03244 1448 {
modtronix 1:64a9c4a03244 1449 switch( this->settings.State )
modtronix 1:64a9c4a03244 1450 {
modtronix 1:64a9c4a03244 1451 case RX_DONE:
modtronix 1:64a9c4a03244 1452 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1453 {
modtronix 1:64a9c4a03244 1454 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1455 case MODEM_FSK:
modtronix 1:64a9c4a03244 1456 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
modtronix 1:64a9c4a03244 1457 {
modtronix 1:64a9c4a03244 1458 rxTimeoutSyncWord.detach( );
modtronix 1:64a9c4a03244 1459
modtronix 1:64a9c4a03244 1460 this->settings.FskPacketHandler.SyncWordDetected = true;
modtronix 1:64a9c4a03244 1461
modtronix 1:64a9c4a03244 1462 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
modtronix 1:64a9c4a03244 1463
modtronix 1:64a9c4a03244 1464 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
modtronix 1:64a9c4a03244 1465 ( uint16_t )Read( REG_AFCLSB ) ) *
modtronix 1:64a9c4a03244 1466 ( double )FREQ_STEP;
modtronix 1:64a9c4a03244 1467 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
modtronix 1:64a9c4a03244 1468 }
modtronix 1:64a9c4a03244 1469 break;
modtronix 1:64a9c4a03244 1470 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1471 case MODEM_LORA:
modtronix 1:64a9c4a03244 1472 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 1473 {
modtronix 1:64a9c4a03244 1474 // Clear Irq
modtronix 1:64a9c4a03244 1475 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
modtronix 1:64a9c4a03244 1476
modtronix 1:64a9c4a03244 1477 if( ( fhssChangeChannel != NULL ) )
modtronix 1:64a9c4a03244 1478 {
modtronix 1:64a9c4a03244 1479 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
modtronix 1:64a9c4a03244 1480 }
modtronix 1:64a9c4a03244 1481 }
modtronix 1:64a9c4a03244 1482 break;
modtronix 1:64a9c4a03244 1483 default:
modtronix 1:64a9c4a03244 1484 break;
modtronix 1:64a9c4a03244 1485 }
modtronix 1:64a9c4a03244 1486 break;
modtronix 1:64a9c4a03244 1487 case TX_DONE:
modtronix 1:64a9c4a03244 1488 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1489 {
modtronix 1:64a9c4a03244 1490 case MODEM_FSK:
modtronix 1:64a9c4a03244 1491 break;
modtronix 1:64a9c4a03244 1492 case MODEM_LORA:
modtronix 1:64a9c4a03244 1493 if( this->settings.LoRa.FreqHopOn == true )
modtronix 1:64a9c4a03244 1494 {
modtronix 1:64a9c4a03244 1495 // Clear Irq
modtronix 1:64a9c4a03244 1496 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
modtronix 1:64a9c4a03244 1497
modtronix 1:64a9c4a03244 1498 if( ( fhssChangeChannel != NULL ) )
modtronix 1:64a9c4a03244 1499 {
modtronix 1:64a9c4a03244 1500 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
modtronix 1:64a9c4a03244 1501 }
modtronix 1:64a9c4a03244 1502 }
modtronix 1:64a9c4a03244 1503 break;
modtronix 1:64a9c4a03244 1504 default:
modtronix 1:64a9c4a03244 1505 break;
modtronix 1:64a9c4a03244 1506 }
modtronix 1:64a9c4a03244 1507 break;
modtronix 1:64a9c4a03244 1508 default:
modtronix 1:64a9c4a03244 1509 break;
modtronix 1:64a9c4a03244 1510 }
modtronix 1:64a9c4a03244 1511 }
modtronix 1:64a9c4a03244 1512
modtronix 1:64a9c4a03244 1513 void InAir::OnDio3Irq( void )
modtronix 1:64a9c4a03244 1514 {
modtronix 1:64a9c4a03244 1515 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1516 {
modtronix 1:64a9c4a03244 1517 case MODEM_FSK:
modtronix 1:64a9c4a03244 1518 break;
modtronix 1:64a9c4a03244 1519 case MODEM_LORA:
modtronix 1:64a9c4a03244 1520 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
modtronix 1:64a9c4a03244 1521 {
modtronix 1:64a9c4a03244 1522 // Clear Irq
modtronix 1:64a9c4a03244 1523 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
modtronix 1:64a9c4a03244 1524 if( ( cadDone != NULL ) )
modtronix 1:64a9c4a03244 1525 {
modtronix 1:64a9c4a03244 1526 cadDone( true );
modtronix 1:64a9c4a03244 1527 }
modtronix 1:64a9c4a03244 1528 }
modtronix 1:64a9c4a03244 1529 else
modtronix 1:64a9c4a03244 1530 {
modtronix 1:64a9c4a03244 1531 // Clear Irq
modtronix 1:64a9c4a03244 1532 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
modtronix 1:64a9c4a03244 1533 if( ( cadDone != NULL ) )
modtronix 1:64a9c4a03244 1534 {
modtronix 1:64a9c4a03244 1535 cadDone( false );
modtronix 1:64a9c4a03244 1536 }
modtronix 1:64a9c4a03244 1537 }
modtronix 1:64a9c4a03244 1538 break;
modtronix 1:64a9c4a03244 1539 default:
modtronix 1:64a9c4a03244 1540 break;
modtronix 1:64a9c4a03244 1541 }
modtronix 1:64a9c4a03244 1542 }
modtronix 1:64a9c4a03244 1543
modtronix 1:64a9c4a03244 1544 /*
modtronix 1:64a9c4a03244 1545 void InAir::OnDio4Irq( void )
modtronix 1:64a9c4a03244 1546 {
modtronix 1:64a9c4a03244 1547 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1548 {
modtronix 1:64a9c4a03244 1549 #if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1550 case MODEM_FSK:
modtronix 1:64a9c4a03244 1551 {
modtronix 1:64a9c4a03244 1552 if( this->settings.FskPacketHandler.PreambleDetected == false )
modtronix 1:64a9c4a03244 1553 {
modtronix 1:64a9c4a03244 1554 this->settings.FskPacketHandler.PreambleDetected = true;
modtronix 1:64a9c4a03244 1555 }
modtronix 1:64a9c4a03244 1556 }
modtronix 1:64a9c4a03244 1557 break;
modtronix 1:64a9c4a03244 1558 #endif //#if (INAIR_ENABLE_FSK==1)
modtronix 1:64a9c4a03244 1559 case MODEM_LORA:
modtronix 1:64a9c4a03244 1560 break;
modtronix 1:64a9c4a03244 1561 default:
modtronix 1:64a9c4a03244 1562 break;
modtronix 1:64a9c4a03244 1563 }
modtronix 1:64a9c4a03244 1564 }
modtronix 1:64a9c4a03244 1565
modtronix 1:64a9c4a03244 1566 void InAir::OnDio5Irq( void )
modtronix 1:64a9c4a03244 1567 {
modtronix 1:64a9c4a03244 1568 switch( this->settings.Modem )
modtronix 1:64a9c4a03244 1569 {
modtronix 1:64a9c4a03244 1570 case MODEM_FSK:
modtronix 1:64a9c4a03244 1571 break;
modtronix 1:64a9c4a03244 1572 case MODEM_LORA:
modtronix 1:64a9c4a03244 1573 break;
modtronix 1:64a9c4a03244 1574 default:
modtronix 1:64a9c4a03244 1575 break;
modtronix 1:64a9c4a03244 1576 }
modtronix 1:64a9c4a03244 1577 }
modtronix 1:64a9c4a03244 1578 */
modtronix 1:64a9c4a03244 1579
modtronix 1:64a9c4a03244 1580
modtronix 1:64a9c4a03244 1581
modtronix 1:64a9c4a03244 1582
modtronix 1:64a9c4a03244 1583
modtronix 1:64a9c4a03244 1584
modtronix 1:64a9c4a03244 1585
modtronix 1:64a9c4a03244 1586
modtronix 1:64a9c4a03244 1587
modtronix 1:64a9c4a03244 1588
modtronix 1:64a9c4a03244 1589
modtronix 1:64a9c4a03244 1590
modtronix 1:64a9c4a03244 1591
modtronix 1:64a9c4a03244 1592
modtronix 1:64a9c4a03244 1593
modtronix 1:64a9c4a03244 1594
modtronix 1:64a9c4a03244 1595 void InAir::Reset( void )
modtronix 1:64a9c4a03244 1596 {
modtronix 1:64a9c4a03244 1597 reset.output();
modtronix 1:64a9c4a03244 1598 reset = 0;
modtronix 1:64a9c4a03244 1599 wait_ms( 1 );
modtronix 1:64a9c4a03244 1600 reset.input();
modtronix 1:64a9c4a03244 1601 wait_ms( 6 );
modtronix 1:64a9c4a03244 1602 }
modtronix 1:64a9c4a03244 1603
modtronix 1:64a9c4a03244 1604 void InAir::Write( uint8_t addr, uint8_t data )
modtronix 1:64a9c4a03244 1605 {
modtronix 1:64a9c4a03244 1606 Write( addr, &data, 1 );
modtronix 1:64a9c4a03244 1607 }
modtronix 1:64a9c4a03244 1608
modtronix 1:64a9c4a03244 1609 uint8_t InAir::Read( uint8_t addr )
modtronix 1:64a9c4a03244 1610 {
modtronix 1:64a9c4a03244 1611 uint8_t data;
modtronix 1:64a9c4a03244 1612 Read( addr, &data, 1 );
modtronix 1:64a9c4a03244 1613 return data;
modtronix 1:64a9c4a03244 1614 }
modtronix 1:64a9c4a03244 1615
modtronix 1:64a9c4a03244 1616 void InAir::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
modtronix 1:64a9c4a03244 1617 {
modtronix 1:64a9c4a03244 1618 uint8_t i;
modtronix 1:64a9c4a03244 1619
modtronix 1:64a9c4a03244 1620 nss = 0;
modtronix 1:64a9c4a03244 1621 spi.write( addr | 0x80 );
modtronix 1:64a9c4a03244 1622 for( i = 0; i < size; i++ )
modtronix 1:64a9c4a03244 1623 {
modtronix 1:64a9c4a03244 1624 spi.write( buffer[i] );
modtronix 1:64a9c4a03244 1625 }
modtronix 1:64a9c4a03244 1626 nss = 1;
modtronix 1:64a9c4a03244 1627 }
modtronix 1:64a9c4a03244 1628
modtronix 1:64a9c4a03244 1629 void InAir::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
modtronix 1:64a9c4a03244 1630 {
modtronix 1:64a9c4a03244 1631 uint8_t i;
modtronix 1:64a9c4a03244 1632
modtronix 1:64a9c4a03244 1633 nss = 0;
modtronix 1:64a9c4a03244 1634 spi.write( addr & 0x7F );
modtronix 1:64a9c4a03244 1635 for( i = 0; i < size; i++ )
modtronix 1:64a9c4a03244 1636 {
modtronix 1:64a9c4a03244 1637 buffer[i] = spi.write( 0 );
modtronix 1:64a9c4a03244 1638 }
modtronix 1:64a9c4a03244 1639 nss = 1;
modtronix 1:64a9c4a03244 1640 }
modtronix 1:64a9c4a03244 1641
modtronix 1:64a9c4a03244 1642 void InAir::WriteFifo( uint8_t *buffer, uint8_t size )
modtronix 1:64a9c4a03244 1643 {
modtronix 1:64a9c4a03244 1644 Write( 0, buffer, size );
modtronix 1:64a9c4a03244 1645 }
modtronix 1:64a9c4a03244 1646
modtronix 1:64a9c4a03244 1647 void InAir::ReadFifo( uint8_t *buffer, uint8_t size )
modtronix 1:64a9c4a03244 1648 {
modtronix 1:64a9c4a03244 1649 Read( 0, buffer, size );
modtronix 1:64a9c4a03244 1650 }
modtronix 1:64a9c4a03244 1651
modtronix 1:64a9c4a03244 1652
modtronix 1:64a9c4a03244 1653 //-------------------------------------------------------------------------
modtronix 1:64a9c4a03244 1654 // Board relative functions
modtronix 1:64a9c4a03244 1655 //-------------------------------------------------------------------------
modtronix 1:64a9c4a03244 1656
modtronix 1:64a9c4a03244 1657 void InAir::IoInit( void )
modtronix 1:64a9c4a03244 1658 {
modtronix 1:64a9c4a03244 1659 SpiInit( );
modtronix 1:64a9c4a03244 1660 }
modtronix 1:64a9c4a03244 1661
modtronix 1:64a9c4a03244 1662 static const RadioRegisters_t RadioRegsInit[] =
modtronix 1:64a9c4a03244 1663 {
modtronix 1:64a9c4a03244 1664 { MODEM_FSK , REG_LNA , 0x23 },
modtronix 1:64a9c4a03244 1665 { MODEM_FSK , REG_RXCONFIG , 0x1E },
modtronix 1:64a9c4a03244 1666 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
modtronix 1:64a9c4a03244 1667 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
modtronix 1:64a9c4a03244 1668 { MODEM_FSK , REG_OSC , 0x07 },
modtronix 1:64a9c4a03244 1669 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
modtronix 1:64a9c4a03244 1670 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
modtronix 1:64a9c4a03244 1671 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
modtronix 1:64a9c4a03244 1672 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
modtronix 1:64a9c4a03244 1673 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },
modtronix 1:64a9c4a03244 1674 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
modtronix 1:64a9c4a03244 1675 { MODEM_FSK , REG_IMAGECAL , 0x02 },
modtronix 1:64a9c4a03244 1676 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
modtronix 1:64a9c4a03244 1677 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
modtronix 1:64a9c4a03244 1678 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
modtronix 1:64a9c4a03244 1679 };
modtronix 1:64a9c4a03244 1680
modtronix 1:64a9c4a03244 1681 void InAir::RadioRegistersInit( ) {
modtronix 1:64a9c4a03244 1682 uint8_t i = 0;
modtronix 1:64a9c4a03244 1683 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
modtronix 1:64a9c4a03244 1684 {
modtronix 1:64a9c4a03244 1685 SetModem( RadioRegsInit[i].Modem );
modtronix 1:64a9c4a03244 1686 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
modtronix 1:64a9c4a03244 1687 }
modtronix 1:64a9c4a03244 1688 }
modtronix 1:64a9c4a03244 1689
modtronix 1:64a9c4a03244 1690 void InAir::SpiInit( void )
modtronix 1:64a9c4a03244 1691 {
modtronix 1:64a9c4a03244 1692 nss = 1;
modtronix 1:64a9c4a03244 1693 spi.format( 8,0 );
modtronix 1:64a9c4a03244 1694 uint32_t frequencyToSet = 8000000;
modtronix 1:64a9c4a03244 1695 #if( defined ( TARGET_NUCLEO_L152RE ) || defined (TARGET_NUCLEO_F401RE) || defined ( TARGET_LPC11U6X ) || defined (TARGET_K64F) || defined ( TARGET_NZ32ST1L ) || defined(TARGET_NZ32SC151) )
modtronix 1:64a9c4a03244 1696 spi.frequency( frequencyToSet );
modtronix 1:64a9c4a03244 1697 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
modtronix 1:64a9c4a03244 1698 spi.frequency( frequencyToSet * 2 );
modtronix 1:64a9c4a03244 1699 #else
modtronix 1:64a9c4a03244 1700 #warning "Check the board's SPI frequency"
modtronix 1:64a9c4a03244 1701 #endif
modtronix 1:64a9c4a03244 1702 wait(0.1);
modtronix 1:64a9c4a03244 1703 }
modtronix 1:64a9c4a03244 1704
modtronix 1:64a9c4a03244 1705 void InAir::IoIrqInit()
modtronix 1:64a9c4a03244 1706 {
modtronix 1:64a9c4a03244 1707 //TARGET_KL25Z board does not have pulldown resistors, seems like TARGET_K64F does have them
modtronix 1:64a9c4a03244 1708 #if( defined ( TARGET_NUCLEO_L152RE ) || defined (TARGET_NUCLEO_F401RE) || defined ( TARGET_LPC11U6X ) || defined (TARGET_K64F) || defined ( TARGET_NZ32ST1L ) || defined(TARGET_NZ32SC151))
modtronix 1:64a9c4a03244 1709 dio0.mode(PullDown);
modtronix 1:64a9c4a03244 1710 dio1.mode(PullDown);
modtronix 1:64a9c4a03244 1711 dio2.mode(PullDown);
modtronix 1:64a9c4a03244 1712 dio3.mode(PullDown);
modtronix 1:64a9c4a03244 1713 #endif
modtronix 1:64a9c4a03244 1714 #if(INAIR_DIO0_IS_INTERRUPT==1)
modtronix 1:64a9c4a03244 1715 dio0.rise(this, &InAir::OnDio0Irq);
modtronix 1:64a9c4a03244 1716 #endif
modtronix 1:64a9c4a03244 1717 #if(INAIR_DIO1_IS_INTERRUPT==1)
modtronix 1:64a9c4a03244 1718 dio1.rise( this, &InAir::OnDio1Irq);
modtronix 1:64a9c4a03244 1719 #endif
modtronix 1:64a9c4a03244 1720 #if(INAIR_DIO2_IS_INTERRUPT==1)
modtronix 1:64a9c4a03244 1721 dio2.rise( this, &InAir::OnDio2Irq);
modtronix 1:64a9c4a03244 1722 #endif
modtronix 1:64a9c4a03244 1723 #if(INAIR_DIO3_IS_INTERRUPT==1)
modtronix 1:64a9c4a03244 1724 dio3.rise( this, &InAir::OnDio3Irq);
modtronix 1:64a9c4a03244 1725 #endif
modtronix 1:64a9c4a03244 1726 }
modtronix 1:64a9c4a03244 1727
modtronix 1:64a9c4a03244 1728 void InAir::IoDeInit( void )
modtronix 1:64a9c4a03244 1729 {
modtronix 1:64a9c4a03244 1730 //nothing
modtronix 1:64a9c4a03244 1731 }
modtronix 1:64a9c4a03244 1732
modtronix 1:64a9c4a03244 1733 uint8_t InAir::GetPaSelect( uint32_t channel )
modtronix 1:64a9c4a03244 1734 {
modtronix 1:64a9c4a03244 1735 if(boardConnected == BOARD_INAIR9B) {
modtronix 1:64a9c4a03244 1736 return RF_PACONFIG_PASELECT_PABOOST;
modtronix 1:64a9c4a03244 1737 }
modtronix 1:64a9c4a03244 1738 else {
modtronix 1:64a9c4a03244 1739 return RF_PACONFIG_PASELECT_RFO;
modtronix 1:64a9c4a03244 1740 }
modtronix 1:64a9c4a03244 1741 }
modtronix 1:64a9c4a03244 1742
modtronix 1:64a9c4a03244 1743 bool InAir::CheckRfFrequency( uint32_t frequency )
modtronix 1:64a9c4a03244 1744 {
modtronix 1:64a9c4a03244 1745 //TODO: Implement check, currently all frequencies are supported
modtronix 1:64a9c4a03244 1746 return true;
modtronix 1:64a9c4a03244 1747 }