modtronix H / mbed_nz32sc151

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targets/cmsis/core_cm0plus.h@1:71204b8406f2, 2015-07-24 (annotated)

Committer:
modtronix
Date:
Fri Jul 24 21:01:44 2015 +1000
Revision:
1:71204b8406f2
Child:
10:6444e6c798ce
Current mbed v103 (594)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:71204b8406f2 1 /**************************************************************************//**
modtronix 1:71204b8406f2 2 * @file core_cm0plus.h
modtronix 1:71204b8406f2 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
modtronix 1:71204b8406f2 4 * @version V3.20
modtronix 1:71204b8406f2 5 * @date 25. February 2013
modtronix 1:71204b8406f2 6 *
modtronix 1:71204b8406f2 7 * @note
modtronix 1:71204b8406f2 8 *
modtronix 1:71204b8406f2 9 ******************************************************************************/
modtronix 1:71204b8406f2 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
modtronix 1:71204b8406f2 11
modtronix 1:71204b8406f2 12 All rights reserved.
modtronix 1:71204b8406f2 13 Redistribution and use in source and binary forms, with or without
modtronix 1:71204b8406f2 14 modification, are permitted provided that the following conditions are met:
modtronix 1:71204b8406f2 15 - Redistributions of source code must retain the above copyright
modtronix 1:71204b8406f2 16 notice, this list of conditions and the following disclaimer.
modtronix 1:71204b8406f2 17 - Redistributions in binary form must reproduce the above copyright
modtronix 1:71204b8406f2 18 notice, this list of conditions and the following disclaimer in the
modtronix 1:71204b8406f2 19 documentation and/or other materials provided with the distribution.
modtronix 1:71204b8406f2 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 1:71204b8406f2 21 to endorse or promote products derived from this software without
modtronix 1:71204b8406f2 22 specific prior written permission.
modtronix 1:71204b8406f2 23 *
modtronix 1:71204b8406f2 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 1:71204b8406f2 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 1:71204b8406f2 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 1:71204b8406f2 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 1:71204b8406f2 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 1:71204b8406f2 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 1:71204b8406f2 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 1:71204b8406f2 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 1:71204b8406f2 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 1:71204b8406f2 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 1:71204b8406f2 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 1:71204b8406f2 35 ---------------------------------------------------------------------------*/
modtronix 1:71204b8406f2 36
modtronix 1:71204b8406f2 37
modtronix 1:71204b8406f2 38 #if defined ( __ICCARM__ )
modtronix 1:71204b8406f2 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 1:71204b8406f2 40 #endif
modtronix 1:71204b8406f2 41
modtronix 1:71204b8406f2 42 #ifdef __cplusplus
modtronix 1:71204b8406f2 43 extern "C" {
modtronix 1:71204b8406f2 44 #endif
modtronix 1:71204b8406f2 45
modtronix 1:71204b8406f2 46 #ifndef __CORE_CM0PLUS_H_GENERIC
modtronix 1:71204b8406f2 47 #define __CORE_CM0PLUS_H_GENERIC
modtronix 1:71204b8406f2 48
modtronix 1:71204b8406f2 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
modtronix 1:71204b8406f2 50 CMSIS violates the following MISRA-C:2004 rules:
modtronix 1:71204b8406f2 51
modtronix 1:71204b8406f2 52 \li Required Rule 8.5, object/function definition in header file.<br>
modtronix 1:71204b8406f2 53 Function definitions in header files are used to allow 'inlining'.
modtronix 1:71204b8406f2 54
modtronix 1:71204b8406f2 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
modtronix 1:71204b8406f2 56 Unions are used for effective representation of core registers.
modtronix 1:71204b8406f2 57
modtronix 1:71204b8406f2 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
modtronix 1:71204b8406f2 59 Function-like macros are used to allow more efficient code.
modtronix 1:71204b8406f2 60 */
modtronix 1:71204b8406f2 61
modtronix 1:71204b8406f2 62
modtronix 1:71204b8406f2 63 /*******************************************************************************
modtronix 1:71204b8406f2 64 * CMSIS definitions
modtronix 1:71204b8406f2 65 ******************************************************************************/
modtronix 1:71204b8406f2 66 /** \ingroup Cortex-M0+
modtronix 1:71204b8406f2 67 @{
modtronix 1:71204b8406f2 68 */
modtronix 1:71204b8406f2 69
modtronix 1:71204b8406f2 70 /* CMSIS CM0P definitions */
modtronix 1:71204b8406f2 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
modtronix 1:71204b8406f2 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
modtronix 1:71204b8406f2 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
modtronix 1:71204b8406f2 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
modtronix 1:71204b8406f2 75
modtronix 1:71204b8406f2 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
modtronix 1:71204b8406f2 77
modtronix 1:71204b8406f2 78
modtronix 1:71204b8406f2 79 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
modtronix 1:71204b8406f2 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
modtronix 1:71204b8406f2 82 #define __STATIC_INLINE static __inline
modtronix 1:71204b8406f2 83
modtronix 1:71204b8406f2 84 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
modtronix 1:71204b8406f2 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
modtronix 1:71204b8406f2 87 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 88
modtronix 1:71204b8406f2 89 #elif defined ( __GNUC__ )
modtronix 1:71204b8406f2 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
modtronix 1:71204b8406f2 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
modtronix 1:71204b8406f2 92 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 93
modtronix 1:71204b8406f2 94 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
modtronix 1:71204b8406f2 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
modtronix 1:71204b8406f2 97 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 98
modtronix 1:71204b8406f2 99 #endif
modtronix 1:71204b8406f2 100
modtronix 1:71204b8406f2 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
modtronix 1:71204b8406f2 102 */
modtronix 1:71204b8406f2 103 #define __FPU_USED 0
modtronix 1:71204b8406f2 104
modtronix 1:71204b8406f2 105 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 106 #if defined __TARGET_FPU_VFP
modtronix 1:71204b8406f2 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 108 #endif
modtronix 1:71204b8406f2 109
modtronix 1:71204b8406f2 110 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 111 #if defined __ARMVFP__
modtronix 1:71204b8406f2 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 113 #endif
modtronix 1:71204b8406f2 114
modtronix 1:71204b8406f2 115 #elif defined ( __GNUC__ )
modtronix 1:71204b8406f2 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
modtronix 1:71204b8406f2 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 118 #endif
modtronix 1:71204b8406f2 119
modtronix 1:71204b8406f2 120 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 121 #if defined __FPU_VFP__
modtronix 1:71204b8406f2 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 123 #endif
modtronix 1:71204b8406f2 124 #endif
modtronix 1:71204b8406f2 125
modtronix 1:71204b8406f2 126 #include <stdint.h> /* standard types definitions */
modtronix 1:71204b8406f2 127 #include <core_cmInstr.h> /* Core Instruction Access */
modtronix 1:71204b8406f2 128 #include <core_cmFunc.h> /* Core Function Access */
modtronix 1:71204b8406f2 129
modtronix 1:71204b8406f2 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
modtronix 1:71204b8406f2 131
modtronix 1:71204b8406f2 132 #ifndef __CMSIS_GENERIC
modtronix 1:71204b8406f2 133
modtronix 1:71204b8406f2 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
modtronix 1:71204b8406f2 135 #define __CORE_CM0PLUS_H_DEPENDANT
modtronix 1:71204b8406f2 136
modtronix 1:71204b8406f2 137 /* check device defines and use defaults */
modtronix 1:71204b8406f2 138 #if defined __CHECK_DEVICE_DEFINES
modtronix 1:71204b8406f2 139 #ifndef __CM0PLUS_REV
modtronix 1:71204b8406f2 140 #define __CM0PLUS_REV 0x0000
modtronix 1:71204b8406f2 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
modtronix 1:71204b8406f2 142 #endif
modtronix 1:71204b8406f2 143
modtronix 1:71204b8406f2 144 #ifndef __MPU_PRESENT
modtronix 1:71204b8406f2 145 #define __MPU_PRESENT 0
modtronix 1:71204b8406f2 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 147 #endif
modtronix 1:71204b8406f2 148
modtronix 1:71204b8406f2 149 #ifndef __VTOR_PRESENT
modtronix 1:71204b8406f2 150 #define __VTOR_PRESENT 0
modtronix 1:71204b8406f2 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 152 #endif
modtronix 1:71204b8406f2 153
modtronix 1:71204b8406f2 154 #ifndef __NVIC_PRIO_BITS
modtronix 1:71204b8406f2 155 #define __NVIC_PRIO_BITS 2
modtronix 1:71204b8406f2 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
modtronix 1:71204b8406f2 157 #endif
modtronix 1:71204b8406f2 158
modtronix 1:71204b8406f2 159 #ifndef __Vendor_SysTickConfig
modtronix 1:71204b8406f2 160 #define __Vendor_SysTickConfig 0
modtronix 1:71204b8406f2 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
modtronix 1:71204b8406f2 162 #endif
modtronix 1:71204b8406f2 163 #endif
modtronix 1:71204b8406f2 164
modtronix 1:71204b8406f2 165 /* IO definitions (access restrictions to peripheral registers) */
modtronix 1:71204b8406f2 166 /**
modtronix 1:71204b8406f2 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
modtronix 1:71204b8406f2 168
modtronix 1:71204b8406f2 169 <strong>IO Type Qualifiers</strong> are used
modtronix 1:71204b8406f2 170 \li to specify the access to peripheral variables.
modtronix 1:71204b8406f2 171 \li for automatic generation of peripheral register debug information.
modtronix 1:71204b8406f2 172 */
modtronix 1:71204b8406f2 173 #ifdef __cplusplus
modtronix 1:71204b8406f2 174 #define __I volatile /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 175 #else
modtronix 1:71204b8406f2 176 #define __I volatile const /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 177 #endif
modtronix 1:71204b8406f2 178 #define __O volatile /*!< Defines 'write only' permissions */
modtronix 1:71204b8406f2 179 #define __IO volatile /*!< Defines 'read / write' permissions */
modtronix 1:71204b8406f2 180
modtronix 1:71204b8406f2 181 /*@} end of group Cortex-M0+ */
modtronix 1:71204b8406f2 182
modtronix 1:71204b8406f2 183
modtronix 1:71204b8406f2 184
modtronix 1:71204b8406f2 185 /*******************************************************************************
modtronix 1:71204b8406f2 186 * Register Abstraction
modtronix 1:71204b8406f2 187 Core Register contain:
modtronix 1:71204b8406f2 188 - Core Register
modtronix 1:71204b8406f2 189 - Core NVIC Register
modtronix 1:71204b8406f2 190 - Core SCB Register
modtronix 1:71204b8406f2 191 - Core SysTick Register
modtronix 1:71204b8406f2 192 - Core MPU Register
modtronix 1:71204b8406f2 193 ******************************************************************************/
modtronix 1:71204b8406f2 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
modtronix 1:71204b8406f2 195 \brief Type definitions and defines for Cortex-M processor based devices.
modtronix 1:71204b8406f2 196 */
modtronix 1:71204b8406f2 197
modtronix 1:71204b8406f2 198 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 199 \defgroup CMSIS_CORE Status and Control Registers
modtronix 1:71204b8406f2 200 \brief Core Register type definitions.
modtronix 1:71204b8406f2 201 @{
modtronix 1:71204b8406f2 202 */
modtronix 1:71204b8406f2 203
modtronix 1:71204b8406f2 204 /** \brief Union type to access the Application Program Status Register (APSR).
modtronix 1:71204b8406f2 205 */
modtronix 1:71204b8406f2 206 typedef union
modtronix 1:71204b8406f2 207 {
modtronix 1:71204b8406f2 208 struct
modtronix 1:71204b8406f2 209 {
modtronix 1:71204b8406f2 210 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
modtronix 1:71204b8406f2 212 #else
modtronix 1:71204b8406f2 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
modtronix 1:71204b8406f2 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
modtronix 1:71204b8406f2 216 #endif
modtronix 1:71204b8406f2 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 222 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 223 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 224 } APSR_Type;
modtronix 1:71204b8406f2 225
modtronix 1:71204b8406f2 226
modtronix 1:71204b8406f2 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
modtronix 1:71204b8406f2 228 */
modtronix 1:71204b8406f2 229 typedef union
modtronix 1:71204b8406f2 230 {
modtronix 1:71204b8406f2 231 struct
modtronix 1:71204b8406f2 232 {
modtronix 1:71204b8406f2 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
modtronix 1:71204b8406f2 235 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 236 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 237 } IPSR_Type;
modtronix 1:71204b8406f2 238
modtronix 1:71204b8406f2 239
modtronix 1:71204b8406f2 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
modtronix 1:71204b8406f2 241 */
modtronix 1:71204b8406f2 242 typedef union
modtronix 1:71204b8406f2 243 {
modtronix 1:71204b8406f2 244 struct
modtronix 1:71204b8406f2 245 {
modtronix 1:71204b8406f2 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 247 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
modtronix 1:71204b8406f2 249 #else
modtronix 1:71204b8406f2 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
modtronix 1:71204b8406f2 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
modtronix 1:71204b8406f2 253 #endif
modtronix 1:71204b8406f2 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
modtronix 1:71204b8406f2 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
modtronix 1:71204b8406f2 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 261 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 262 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 263 } xPSR_Type;
modtronix 1:71204b8406f2 264
modtronix 1:71204b8406f2 265
modtronix 1:71204b8406f2 266 /** \brief Union type to access the Control Registers (CONTROL).
modtronix 1:71204b8406f2 267 */
modtronix 1:71204b8406f2 268 typedef union
modtronix 1:71204b8406f2 269 {
modtronix 1:71204b8406f2 270 struct
modtronix 1:71204b8406f2 271 {
modtronix 1:71204b8406f2 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
modtronix 1:71204b8406f2 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
modtronix 1:71204b8406f2 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
modtronix 1:71204b8406f2 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
modtronix 1:71204b8406f2 276 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 277 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 278 } CONTROL_Type;
modtronix 1:71204b8406f2 279
modtronix 1:71204b8406f2 280 /*@} end of group CMSIS_CORE */
modtronix 1:71204b8406f2 281
modtronix 1:71204b8406f2 282
modtronix 1:71204b8406f2 283 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
modtronix 1:71204b8406f2 285 \brief Type definitions for the NVIC Registers
modtronix 1:71204b8406f2 286 @{
modtronix 1:71204b8406f2 287 */
modtronix 1:71204b8406f2 288
modtronix 1:71204b8406f2 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
modtronix 1:71204b8406f2 290 */
modtronix 1:71204b8406f2 291 typedef struct
modtronix 1:71204b8406f2 292 {
modtronix 1:71204b8406f2 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
modtronix 1:71204b8406f2 294 uint32_t RESERVED0[31];
modtronix 1:71204b8406f2 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
modtronix 1:71204b8406f2 296 uint32_t RSERVED1[31];
modtronix 1:71204b8406f2 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
modtronix 1:71204b8406f2 298 uint32_t RESERVED2[31];
modtronix 1:71204b8406f2 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
modtronix 1:71204b8406f2 300 uint32_t RESERVED3[31];
modtronix 1:71204b8406f2 301 uint32_t RESERVED4[64];
modtronix 1:71204b8406f2 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
modtronix 1:71204b8406f2 303 } NVIC_Type;
modtronix 1:71204b8406f2 304
modtronix 1:71204b8406f2 305 /*@} end of group CMSIS_NVIC */
modtronix 1:71204b8406f2 306
modtronix 1:71204b8406f2 307
modtronix 1:71204b8406f2 308 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 309 \defgroup CMSIS_SCB System Control Block (SCB)
modtronix 1:71204b8406f2 310 \brief Type definitions for the System Control Block Registers
modtronix 1:71204b8406f2 311 @{
modtronix 1:71204b8406f2 312 */
modtronix 1:71204b8406f2 313
modtronix 1:71204b8406f2 314 /** \brief Structure type to access the System Control Block (SCB).
modtronix 1:71204b8406f2 315 */
modtronix 1:71204b8406f2 316 typedef struct
modtronix 1:71204b8406f2 317 {
modtronix 1:71204b8406f2 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
modtronix 1:71204b8406f2 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
modtronix 1:71204b8406f2 320 #if (__VTOR_PRESENT == 1)
modtronix 1:71204b8406f2 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
modtronix 1:71204b8406f2 322 #else
modtronix 1:71204b8406f2 323 uint32_t RESERVED0;
modtronix 1:71204b8406f2 324 #endif
modtronix 1:71204b8406f2 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
modtronix 1:71204b8406f2 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
modtronix 1:71204b8406f2 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
modtronix 1:71204b8406f2 328 uint32_t RESERVED1;
modtronix 1:71204b8406f2 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
modtronix 1:71204b8406f2 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
modtronix 1:71204b8406f2 331 } SCB_Type;
modtronix 1:71204b8406f2 332
modtronix 1:71204b8406f2 333 /* SCB CPUID Register Definitions */
modtronix 1:71204b8406f2 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
modtronix 1:71204b8406f2 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
modtronix 1:71204b8406f2 336
modtronix 1:71204b8406f2 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
modtronix 1:71204b8406f2 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
modtronix 1:71204b8406f2 339
modtronix 1:71204b8406f2 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
modtronix 1:71204b8406f2 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
modtronix 1:71204b8406f2 342
modtronix 1:71204b8406f2 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
modtronix 1:71204b8406f2 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
modtronix 1:71204b8406f2 345
modtronix 1:71204b8406f2 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
modtronix 1:71204b8406f2 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
modtronix 1:71204b8406f2 348
modtronix 1:71204b8406f2 349 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
modtronix 1:71204b8406f2 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
modtronix 1:71204b8406f2 352
modtronix 1:71204b8406f2 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
modtronix 1:71204b8406f2 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
modtronix 1:71204b8406f2 355
modtronix 1:71204b8406f2 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
modtronix 1:71204b8406f2 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
modtronix 1:71204b8406f2 358
modtronix 1:71204b8406f2 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
modtronix 1:71204b8406f2 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
modtronix 1:71204b8406f2 361
modtronix 1:71204b8406f2 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
modtronix 1:71204b8406f2 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
modtronix 1:71204b8406f2 364
modtronix 1:71204b8406f2 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
modtronix 1:71204b8406f2 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
modtronix 1:71204b8406f2 367
modtronix 1:71204b8406f2 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
modtronix 1:71204b8406f2 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
modtronix 1:71204b8406f2 370
modtronix 1:71204b8406f2 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
modtronix 1:71204b8406f2 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
modtronix 1:71204b8406f2 373
modtronix 1:71204b8406f2 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
modtronix 1:71204b8406f2 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
modtronix 1:71204b8406f2 376
modtronix 1:71204b8406f2 377 #if (__VTOR_PRESENT == 1)
modtronix 1:71204b8406f2 378 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
modtronix 1:71204b8406f2 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 1:71204b8406f2 381 #endif
modtronix 1:71204b8406f2 382
modtronix 1:71204b8406f2 383 /* SCB Application Interrupt and Reset Control Register Definitions */
modtronix 1:71204b8406f2 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
modtronix 1:71204b8406f2 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
modtronix 1:71204b8406f2 386
modtronix 1:71204b8406f2 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
modtronix 1:71204b8406f2 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
modtronix 1:71204b8406f2 389
modtronix 1:71204b8406f2 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
modtronix 1:71204b8406f2 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
modtronix 1:71204b8406f2 392
modtronix 1:71204b8406f2 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
modtronix 1:71204b8406f2 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
modtronix 1:71204b8406f2 395
modtronix 1:71204b8406f2 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
modtronix 1:71204b8406f2 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
modtronix 1:71204b8406f2 398
modtronix 1:71204b8406f2 399 /* SCB System Control Register Definitions */
modtronix 1:71204b8406f2 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
modtronix 1:71204b8406f2 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
modtronix 1:71204b8406f2 402
modtronix 1:71204b8406f2 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
modtronix 1:71204b8406f2 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
modtronix 1:71204b8406f2 405
modtronix 1:71204b8406f2 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
modtronix 1:71204b8406f2 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
modtronix 1:71204b8406f2 408
modtronix 1:71204b8406f2 409 /* SCB Configuration Control Register Definitions */
modtronix 1:71204b8406f2 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
modtronix 1:71204b8406f2 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
modtronix 1:71204b8406f2 412
modtronix 1:71204b8406f2 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
modtronix 1:71204b8406f2 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
modtronix 1:71204b8406f2 415
modtronix 1:71204b8406f2 416 /* SCB System Handler Control and State Register Definitions */
modtronix 1:71204b8406f2 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
modtronix 1:71204b8406f2 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
modtronix 1:71204b8406f2 419
modtronix 1:71204b8406f2 420 /*@} end of group CMSIS_SCB */
modtronix 1:71204b8406f2 421
modtronix 1:71204b8406f2 422
modtronix 1:71204b8406f2 423 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
modtronix 1:71204b8406f2 425 \brief Type definitions for the System Timer Registers.
modtronix 1:71204b8406f2 426 @{
modtronix 1:71204b8406f2 427 */
modtronix 1:71204b8406f2 428
modtronix 1:71204b8406f2 429 /** \brief Structure type to access the System Timer (SysTick).
modtronix 1:71204b8406f2 430 */
modtronix 1:71204b8406f2 431 typedef struct
modtronix 1:71204b8406f2 432 {
modtronix 1:71204b8406f2 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
modtronix 1:71204b8406f2 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
modtronix 1:71204b8406f2 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
modtronix 1:71204b8406f2 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
modtronix 1:71204b8406f2 437 } SysTick_Type;
modtronix 1:71204b8406f2 438
modtronix 1:71204b8406f2 439 /* SysTick Control / Status Register Definitions */
modtronix 1:71204b8406f2 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
modtronix 1:71204b8406f2 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
modtronix 1:71204b8406f2 442
modtronix 1:71204b8406f2 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
modtronix 1:71204b8406f2 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
modtronix 1:71204b8406f2 445
modtronix 1:71204b8406f2 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
modtronix 1:71204b8406f2 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
modtronix 1:71204b8406f2 448
modtronix 1:71204b8406f2 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
modtronix 1:71204b8406f2 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 451
modtronix 1:71204b8406f2 452 /* SysTick Reload Register Definitions */
modtronix 1:71204b8406f2 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
modtronix 1:71204b8406f2 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
modtronix 1:71204b8406f2 455
modtronix 1:71204b8406f2 456 /* SysTick Current Register Definitions */
modtronix 1:71204b8406f2 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
modtronix 1:71204b8406f2 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
modtronix 1:71204b8406f2 459
modtronix 1:71204b8406f2 460 /* SysTick Calibration Register Definitions */
modtronix 1:71204b8406f2 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
modtronix 1:71204b8406f2 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
modtronix 1:71204b8406f2 463
modtronix 1:71204b8406f2 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
modtronix 1:71204b8406f2 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
modtronix 1:71204b8406f2 466
modtronix 1:71204b8406f2 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
modtronix 1:71204b8406f2 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
modtronix 1:71204b8406f2 469
modtronix 1:71204b8406f2 470 /*@} end of group CMSIS_SysTick */
modtronix 1:71204b8406f2 471
modtronix 1:71204b8406f2 472 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 473 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 475 \brief Type definitions for the Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 476 @{
modtronix 1:71204b8406f2 477 */
modtronix 1:71204b8406f2 478
modtronix 1:71204b8406f2 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
modtronix 1:71204b8406f2 480 */
modtronix 1:71204b8406f2 481 typedef struct
modtronix 1:71204b8406f2 482 {
modtronix 1:71204b8406f2 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
modtronix 1:71204b8406f2 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
modtronix 1:71204b8406f2 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
modtronix 1:71204b8406f2 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
modtronix 1:71204b8406f2 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 488 } MPU_Type;
modtronix 1:71204b8406f2 489
modtronix 1:71204b8406f2 490 /* MPU Type Register */
modtronix 1:71204b8406f2 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
modtronix 1:71204b8406f2 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
modtronix 1:71204b8406f2 493
modtronix 1:71204b8406f2 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
modtronix 1:71204b8406f2 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
modtronix 1:71204b8406f2 496
modtronix 1:71204b8406f2 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
modtronix 1:71204b8406f2 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
modtronix 1:71204b8406f2 499
modtronix 1:71204b8406f2 500 /* MPU Control Register */
modtronix 1:71204b8406f2 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
modtronix 1:71204b8406f2 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
modtronix 1:71204b8406f2 503
modtronix 1:71204b8406f2 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
modtronix 1:71204b8406f2 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
modtronix 1:71204b8406f2 506
modtronix 1:71204b8406f2 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
modtronix 1:71204b8406f2 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 509
modtronix 1:71204b8406f2 510 /* MPU Region Number Register */
modtronix 1:71204b8406f2 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
modtronix 1:71204b8406f2 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
modtronix 1:71204b8406f2 513
modtronix 1:71204b8406f2 514 /* MPU Region Base Address Register */
modtronix 1:71204b8406f2 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
modtronix 1:71204b8406f2 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
modtronix 1:71204b8406f2 517
modtronix 1:71204b8406f2 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
modtronix 1:71204b8406f2 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
modtronix 1:71204b8406f2 520
modtronix 1:71204b8406f2 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
modtronix 1:71204b8406f2 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
modtronix 1:71204b8406f2 523
modtronix 1:71204b8406f2 524 /* MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
modtronix 1:71204b8406f2 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
modtronix 1:71204b8406f2 527
modtronix 1:71204b8406f2 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
modtronix 1:71204b8406f2 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
modtronix 1:71204b8406f2 530
modtronix 1:71204b8406f2 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
modtronix 1:71204b8406f2 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
modtronix 1:71204b8406f2 533
modtronix 1:71204b8406f2 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
modtronix 1:71204b8406f2 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
modtronix 1:71204b8406f2 536
modtronix 1:71204b8406f2 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
modtronix 1:71204b8406f2 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
modtronix 1:71204b8406f2 539
modtronix 1:71204b8406f2 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
modtronix 1:71204b8406f2 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
modtronix 1:71204b8406f2 542
modtronix 1:71204b8406f2 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
modtronix 1:71204b8406f2 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
modtronix 1:71204b8406f2 545
modtronix 1:71204b8406f2 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
modtronix 1:71204b8406f2 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
modtronix 1:71204b8406f2 548
modtronix 1:71204b8406f2 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
modtronix 1:71204b8406f2 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
modtronix 1:71204b8406f2 551
modtronix 1:71204b8406f2 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
modtronix 1:71204b8406f2 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
modtronix 1:71204b8406f2 554
modtronix 1:71204b8406f2 555 /*@} end of group CMSIS_MPU */
modtronix 1:71204b8406f2 556 #endif
modtronix 1:71204b8406f2 557
modtronix 1:71204b8406f2 558
modtronix 1:71204b8406f2 559 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
modtronix 1:71204b8406f2 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
modtronix 1:71204b8406f2 562 are only accessible over DAP and not via processor. Therefore
modtronix 1:71204b8406f2 563 they are not covered by the Cortex-M0 header file.
modtronix 1:71204b8406f2 564 @{
modtronix 1:71204b8406f2 565 */
modtronix 1:71204b8406f2 566 /*@} end of group CMSIS_CoreDebug */
modtronix 1:71204b8406f2 567
modtronix 1:71204b8406f2 568
modtronix 1:71204b8406f2 569 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 570 \defgroup CMSIS_core_base Core Definitions
modtronix 1:71204b8406f2 571 \brief Definitions for base addresses, unions, and structures.
modtronix 1:71204b8406f2 572 @{
modtronix 1:71204b8406f2 573 */
modtronix 1:71204b8406f2 574
modtronix 1:71204b8406f2 575 /* Memory mapping of Cortex-M0+ Hardware */
modtronix 1:71204b8406f2 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
modtronix 1:71204b8406f2 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
modtronix 1:71204b8406f2 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
modtronix 1:71204b8406f2 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
modtronix 1:71204b8406f2 580
modtronix 1:71204b8406f2 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
modtronix 1:71204b8406f2 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
modtronix 1:71204b8406f2 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
modtronix 1:71204b8406f2 584
modtronix 1:71204b8406f2 585 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 588 #endif
modtronix 1:71204b8406f2 589
modtronix 1:71204b8406f2 590 /*@} */
modtronix 1:71204b8406f2 591
modtronix 1:71204b8406f2 592
modtronix 1:71204b8406f2 593
modtronix 1:71204b8406f2 594 /*******************************************************************************
modtronix 1:71204b8406f2 595 * Hardware Abstraction Layer
modtronix 1:71204b8406f2 596 Core Function Interface contains:
modtronix 1:71204b8406f2 597 - Core NVIC Functions
modtronix 1:71204b8406f2 598 - Core SysTick Functions
modtronix 1:71204b8406f2 599 - Core Register Access Functions
modtronix 1:71204b8406f2 600 ******************************************************************************/
modtronix 1:71204b8406f2 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
modtronix 1:71204b8406f2 602 */
modtronix 1:71204b8406f2 603
modtronix 1:71204b8406f2 604
modtronix 1:71204b8406f2 605
modtronix 1:71204b8406f2 606 /* ########################## NVIC functions #################################### */
modtronix 1:71204b8406f2 607 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
modtronix 1:71204b8406f2 609 \brief Functions that manage interrupts and exceptions via the NVIC.
modtronix 1:71204b8406f2 610 @{
modtronix 1:71204b8406f2 611 */
modtronix 1:71204b8406f2 612
modtronix 1:71204b8406f2 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
modtronix 1:71204b8406f2 614 /* The following MACROS handle generation of the register offset and byte masks */
modtronix 1:71204b8406f2 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
modtronix 1:71204b8406f2 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
modtronix 1:71204b8406f2 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
modtronix 1:71204b8406f2 618
modtronix 1:71204b8406f2 619
modtronix 1:71204b8406f2 620 /** \brief Enable External Interrupt
modtronix 1:71204b8406f2 621
modtronix 1:71204b8406f2 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 623
modtronix 1:71204b8406f2 624 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 625 */
modtronix 1:71204b8406f2 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 627 {
modtronix 1:71204b8406f2 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 629 }
modtronix 1:71204b8406f2 630
modtronix 1:71204b8406f2 631
modtronix 1:71204b8406f2 632 /** \brief Disable External Interrupt
modtronix 1:71204b8406f2 633
modtronix 1:71204b8406f2 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 635
modtronix 1:71204b8406f2 636 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 637 */
modtronix 1:71204b8406f2 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 639 {
modtronix 1:71204b8406f2 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 641 }
modtronix 1:71204b8406f2 642
modtronix 1:71204b8406f2 643
modtronix 1:71204b8406f2 644 /** \brief Get Pending Interrupt
modtronix 1:71204b8406f2 645
modtronix 1:71204b8406f2 646 The function reads the pending register in the NVIC and returns the pending bit
modtronix 1:71204b8406f2 647 for the specified interrupt.
modtronix 1:71204b8406f2 648
modtronix 1:71204b8406f2 649 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 650
modtronix 1:71204b8406f2 651 \return 0 Interrupt status is not pending.
modtronix 1:71204b8406f2 652 \return 1 Interrupt status is pending.
modtronix 1:71204b8406f2 653 */
modtronix 1:71204b8406f2 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 655 {
modtronix 1:71204b8406f2 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
modtronix 1:71204b8406f2 657 }
modtronix 1:71204b8406f2 658
modtronix 1:71204b8406f2 659
modtronix 1:71204b8406f2 660 /** \brief Set Pending Interrupt
modtronix 1:71204b8406f2 661
modtronix 1:71204b8406f2 662 The function sets the pending bit of an external interrupt.
modtronix 1:71204b8406f2 663
modtronix 1:71204b8406f2 664 \param [in] IRQn Interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 665 */
modtronix 1:71204b8406f2 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 667 {
modtronix 1:71204b8406f2 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 669 }
modtronix 1:71204b8406f2 670
modtronix 1:71204b8406f2 671
modtronix 1:71204b8406f2 672 /** \brief Clear Pending Interrupt
modtronix 1:71204b8406f2 673
modtronix 1:71204b8406f2 674 The function clears the pending bit of an external interrupt.
modtronix 1:71204b8406f2 675
modtronix 1:71204b8406f2 676 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 677 */
modtronix 1:71204b8406f2 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 679 {
modtronix 1:71204b8406f2 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
modtronix 1:71204b8406f2 681 }
modtronix 1:71204b8406f2 682
modtronix 1:71204b8406f2 683
modtronix 1:71204b8406f2 684 /** \brief Set Interrupt Priority
modtronix 1:71204b8406f2 685
modtronix 1:71204b8406f2 686 The function sets the priority of an interrupt.
modtronix 1:71204b8406f2 687
modtronix 1:71204b8406f2 688 \note The priority cannot be set for every core interrupt.
modtronix 1:71204b8406f2 689
modtronix 1:71204b8406f2 690 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 691 \param [in] priority Priority to set.
modtronix 1:71204b8406f2 692 */
modtronix 1:71204b8406f2 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
modtronix 1:71204b8406f2 694 {
modtronix 1:71204b8406f2 695 if(IRQn < 0) {
modtronix 1:71204b8406f2 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 1:71204b8406f2 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 1:71204b8406f2 698 else {
modtronix 1:71204b8406f2 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 1:71204b8406f2 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 1:71204b8406f2 701 }
modtronix 1:71204b8406f2 702
modtronix 1:71204b8406f2 703
modtronix 1:71204b8406f2 704 /** \brief Get Interrupt Priority
modtronix 1:71204b8406f2 705
modtronix 1:71204b8406f2 706 The function reads the priority of an interrupt. The interrupt
modtronix 1:71204b8406f2 707 number can be positive to specify an external (device specific)
modtronix 1:71204b8406f2 708 interrupt, or negative to specify an internal (core) interrupt.
modtronix 1:71204b8406f2 709
modtronix 1:71204b8406f2 710
modtronix 1:71204b8406f2 711 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 712 \return Interrupt Priority. Value is aligned automatically to the implemented
modtronix 1:71204b8406f2 713 priority bits of the microcontroller.
modtronix 1:71204b8406f2 714 */
modtronix 1:71204b8406f2 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
modtronix 1:71204b8406f2 716 {
modtronix 1:71204b8406f2 717
modtronix 1:71204b8406f2 718 if(IRQn < 0) {
modtronix 1:71204b8406f2 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
modtronix 1:71204b8406f2 720 else {
modtronix 1:71204b8406f2 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
modtronix 1:71204b8406f2 722 }
modtronix 1:71204b8406f2 723
modtronix 1:71204b8406f2 724
modtronix 1:71204b8406f2 725 /** \brief System Reset
modtronix 1:71204b8406f2 726
modtronix 1:71204b8406f2 727 The function initiates a system reset request to reset the MCU.
modtronix 1:71204b8406f2 728 */
modtronix 1:71204b8406f2 729 __STATIC_INLINE void NVIC_SystemReset(void)
modtronix 1:71204b8406f2 730 {
modtronix 1:71204b8406f2 731 __DSB(); /* Ensure all outstanding memory accesses included
modtronix 1:71204b8406f2 732 buffered write are completed before reset */
modtronix 1:71204b8406f2 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 1:71204b8406f2 734 SCB_AIRCR_SYSRESETREQ_Msk);
modtronix 1:71204b8406f2 735 __DSB(); /* Ensure completion of memory access */
modtronix 1:71204b8406f2 736 while(1); /* wait until reset */
modtronix 1:71204b8406f2 737 }
modtronix 1:71204b8406f2 738
modtronix 1:71204b8406f2 739 /*@} end of CMSIS_Core_NVICFunctions */
modtronix 1:71204b8406f2 740
modtronix 1:71204b8406f2 741
modtronix 1:71204b8406f2 742
modtronix 1:71204b8406f2 743 /* ################################## SysTick function ############################################ */
modtronix 1:71204b8406f2 744 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
modtronix 1:71204b8406f2 746 \brief Functions that configure the System.
modtronix 1:71204b8406f2 747 @{
modtronix 1:71204b8406f2 748 */
modtronix 1:71204b8406f2 749
modtronix 1:71204b8406f2 750 #if (__Vendor_SysTickConfig == 0)
modtronix 1:71204b8406f2 751
modtronix 1:71204b8406f2 752 /** \brief System Tick Configuration
modtronix 1:71204b8406f2 753
modtronix 1:71204b8406f2 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
modtronix 1:71204b8406f2 755 Counter is in free running mode to generate periodic interrupts.
modtronix 1:71204b8406f2 756
modtronix 1:71204b8406f2 757 \param [in] ticks Number of ticks between two interrupts.
modtronix 1:71204b8406f2 758
modtronix 1:71204b8406f2 759 \return 0 Function succeeded.
modtronix 1:71204b8406f2 760 \return 1 Function failed.
modtronix 1:71204b8406f2 761
modtronix 1:71204b8406f2 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
modtronix 1:71204b8406f2 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
modtronix 1:71204b8406f2 764 must contain a vendor-specific implementation of this function.
modtronix 1:71204b8406f2 765
modtronix 1:71204b8406f2 766 */
modtronix 1:71204b8406f2 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
modtronix 1:71204b8406f2 768 {
modtronix 1:71204b8406f2 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
modtronix 1:71204b8406f2 770
modtronix 1:71204b8406f2 771 SysTick->LOAD = ticks - 1; /* set reload register */
modtronix 1:71204b8406f2 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
modtronix 1:71204b8406f2 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
modtronix 1:71204b8406f2 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
modtronix 1:71204b8406f2 775 SysTick_CTRL_TICKINT_Msk |
modtronix 1:71204b8406f2 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
modtronix 1:71204b8406f2 777 return (0); /* Function successful */
modtronix 1:71204b8406f2 778 }
modtronix 1:71204b8406f2 779
modtronix 1:71204b8406f2 780 #endif
modtronix 1:71204b8406f2 781
modtronix 1:71204b8406f2 782 /*@} end of CMSIS_Core_SysTickFunctions */
modtronix 1:71204b8406f2 783
modtronix 1:71204b8406f2 784
modtronix 1:71204b8406f2 785
modtronix 1:71204b8406f2 786
modtronix 1:71204b8406f2 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
modtronix 1:71204b8406f2 788
modtronix 1:71204b8406f2 789 #endif /* __CMSIS_GENERIC */
modtronix 1:71204b8406f2 790
modtronix 1:71204b8406f2 791 #ifdef __cplusplus
modtronix 1:71204b8406f2 792 }
modtronix 1:71204b8406f2 793 #endif