modtronix H / mbed_nz32sc151

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targets/cmsis/core_cm3.h@10:6444e6c798ce, 2015-08-14 (annotated)

Committer:
modtronix
Date:
Fri Aug 14 18:48:46 2015 +1000
Revision:
10:6444e6c798ce
Parent:
1:71204b8406f2 
Updated to STM32CubeL1 V1.0.3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:71204b8406f2 1 /**************************************************************************//**
modtronix 1:71204b8406f2 2 * @file core_cm3.h
modtronix 1:71204b8406f2 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
modtronix 10:6444e6c798ce 4 * @version V4.00
modtronix 10:6444e6c798ce 5 * @date 22. August 2014
modtronix 1:71204b8406f2 6 *
modtronix 1:71204b8406f2 7 * @note
modtronix 1:71204b8406f2 8 *
modtronix 1:71204b8406f2 9 ******************************************************************************/
modtronix 10:6444e6c798ce 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
modtronix 1:71204b8406f2 11
modtronix 1:71204b8406f2 12 All rights reserved.
modtronix 1:71204b8406f2 13 Redistribution and use in source and binary forms, with or without
modtronix 1:71204b8406f2 14 modification, are permitted provided that the following conditions are met:
modtronix 1:71204b8406f2 15 - Redistributions of source code must retain the above copyright
modtronix 1:71204b8406f2 16 notice, this list of conditions and the following disclaimer.
modtronix 1:71204b8406f2 17 - Redistributions in binary form must reproduce the above copyright
modtronix 1:71204b8406f2 18 notice, this list of conditions and the following disclaimer in the
modtronix 1:71204b8406f2 19 documentation and/or other materials provided with the distribution.
modtronix 1:71204b8406f2 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 1:71204b8406f2 21 to endorse or promote products derived from this software without
modtronix 1:71204b8406f2 22 specific prior written permission.
modtronix 1:71204b8406f2 23 *
modtronix 1:71204b8406f2 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 1:71204b8406f2 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 1:71204b8406f2 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 1:71204b8406f2 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 1:71204b8406f2 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 1:71204b8406f2 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 1:71204b8406f2 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 1:71204b8406f2 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 1:71204b8406f2 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 1:71204b8406f2 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 1:71204b8406f2 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 1:71204b8406f2 35 ---------------------------------------------------------------------------*/
modtronix 1:71204b8406f2 36
modtronix 1:71204b8406f2 37
modtronix 1:71204b8406f2 38 #if defined ( __ICCARM__ )
modtronix 1:71204b8406f2 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 1:71204b8406f2 40 #endif
modtronix 1:71204b8406f2 41
modtronix 10:6444e6c798ce 42 #ifndef __CORE_CM3_H_GENERIC
modtronix 10:6444e6c798ce 43 #define __CORE_CM3_H_GENERIC
modtronix 10:6444e6c798ce 44
modtronix 1:71204b8406f2 45 #ifdef __cplusplus
modtronix 1:71204b8406f2 46 extern "C" {
modtronix 1:71204b8406f2 47 #endif
modtronix 1:71204b8406f2 48
modtronix 1:71204b8406f2 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
modtronix 1:71204b8406f2 50 CMSIS violates the following MISRA-C:2004 rules:
modtronix 1:71204b8406f2 51
modtronix 1:71204b8406f2 52 \li Required Rule 8.5, object/function definition in header file.<br>
modtronix 1:71204b8406f2 53 Function definitions in header files are used to allow 'inlining'.
modtronix 1:71204b8406f2 54
modtronix 1:71204b8406f2 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
modtronix 1:71204b8406f2 56 Unions are used for effective representation of core registers.
modtronix 1:71204b8406f2 57
modtronix 1:71204b8406f2 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
modtronix 1:71204b8406f2 59 Function-like macros are used to allow more efficient code.
modtronix 1:71204b8406f2 60 */
modtronix 1:71204b8406f2 61
modtronix 1:71204b8406f2 62
modtronix 1:71204b8406f2 63 /*******************************************************************************
modtronix 1:71204b8406f2 64 * CMSIS definitions
modtronix 1:71204b8406f2 65 ******************************************************************************/
modtronix 1:71204b8406f2 66 /** \ingroup Cortex_M3
modtronix 1:71204b8406f2 67 @{
modtronix 1:71204b8406f2 68 */
modtronix 1:71204b8406f2 69
modtronix 1:71204b8406f2 70 /* CMSIS CM3 definitions */
modtronix 10:6444e6c798ce 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
modtronix 10:6444e6c798ce 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
modtronix 1:71204b8406f2 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
modtronix 1:71204b8406f2 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
modtronix 1:71204b8406f2 75
modtronix 1:71204b8406f2 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
modtronix 1:71204b8406f2 77
modtronix 1:71204b8406f2 78
modtronix 1:71204b8406f2 79 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
modtronix 1:71204b8406f2 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
modtronix 1:71204b8406f2 82 #define __STATIC_INLINE static __inline
modtronix 1:71204b8406f2 83
modtronix 10:6444e6c798ce 84 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
modtronix 10:6444e6c798ce 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
modtronix 10:6444e6c798ce 87 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 88
modtronix 1:71204b8406f2 89 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
modtronix 1:71204b8406f2 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
modtronix 1:71204b8406f2 92 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 93
modtronix 1:71204b8406f2 94 #elif defined ( __TMS470__ )
modtronix 1:71204b8406f2 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
modtronix 1:71204b8406f2 96 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 97
modtronix 1:71204b8406f2 98 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
modtronix 1:71204b8406f2 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
modtronix 1:71204b8406f2 101 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 102
modtronix 10:6444e6c798ce 103 #elif defined ( __CSMC__ )
modtronix 10:6444e6c798ce 104 #define __packed
modtronix 10:6444e6c798ce 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 107 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 108
modtronix 1:71204b8406f2 109 #endif
modtronix 1:71204b8406f2 110
modtronix 10:6444e6c798ce 111 /** __FPU_USED indicates whether an FPU is used or not.
modtronix 10:6444e6c798ce 112 This core does not support an FPU at all
modtronix 1:71204b8406f2 113 */
modtronix 1:71204b8406f2 114 #define __FPU_USED 0
modtronix 1:71204b8406f2 115
modtronix 1:71204b8406f2 116 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 117 #if defined __TARGET_FPU_VFP
modtronix 1:71204b8406f2 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 119 #endif
modtronix 1:71204b8406f2 120
modtronix 10:6444e6c798ce 121 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
modtronix 10:6444e6c798ce 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 124 #endif
modtronix 10:6444e6c798ce 125
modtronix 1:71204b8406f2 126 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 127 #if defined __ARMVFP__
modtronix 1:71204b8406f2 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 129 #endif
modtronix 1:71204b8406f2 130
modtronix 1:71204b8406f2 131 #elif defined ( __TMS470__ )
modtronix 1:71204b8406f2 132 #if defined __TI__VFP_SUPPORT____
modtronix 1:71204b8406f2 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 134 #endif
modtronix 1:71204b8406f2 135
modtronix 10:6444e6c798ce 136 #elif defined ( __TASKING__ )
modtronix 10:6444e6c798ce 137 #if defined __FPU_VFP__
modtronix 10:6444e6c798ce 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 139 #endif
modtronix 1:71204b8406f2 140
modtronix 10:6444e6c798ce 141 #elif defined ( __CSMC__ ) /* Cosmic */
modtronix 10:6444e6c798ce 142 #if ( __CSMC__ & 0x400) // FPU present for parser
modtronix 1:71204b8406f2 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 144 #endif
modtronix 1:71204b8406f2 145 #endif
modtronix 1:71204b8406f2 146
modtronix 1:71204b8406f2 147 #include <stdint.h> /* standard types definitions */
modtronix 1:71204b8406f2 148 #include <core_cmInstr.h> /* Core Instruction Access */
modtronix 1:71204b8406f2 149 #include <core_cmFunc.h> /* Core Function Access */
modtronix 1:71204b8406f2 150
modtronix 10:6444e6c798ce 151 #ifdef __cplusplus
modtronix 10:6444e6c798ce 152 }
modtronix 10:6444e6c798ce 153 #endif
modtronix 10:6444e6c798ce 154
modtronix 1:71204b8406f2 155 #endif /* __CORE_CM3_H_GENERIC */
modtronix 1:71204b8406f2 156
modtronix 1:71204b8406f2 157 #ifndef __CMSIS_GENERIC
modtronix 1:71204b8406f2 158
modtronix 1:71204b8406f2 159 #ifndef __CORE_CM3_H_DEPENDANT
modtronix 1:71204b8406f2 160 #define __CORE_CM3_H_DEPENDANT
modtronix 1:71204b8406f2 161
modtronix 10:6444e6c798ce 162 #ifdef __cplusplus
modtronix 10:6444e6c798ce 163 extern "C" {
modtronix 10:6444e6c798ce 164 #endif
modtronix 10:6444e6c798ce 165
modtronix 1:71204b8406f2 166 /* check device defines and use defaults */
modtronix 1:71204b8406f2 167 #if defined __CHECK_DEVICE_DEFINES
modtronix 1:71204b8406f2 168 #ifndef __CM3_REV
modtronix 1:71204b8406f2 169 #define __CM3_REV 0x0200
modtronix 1:71204b8406f2 170 #warning "__CM3_REV not defined in device header file; using default!"
modtronix 1:71204b8406f2 171 #endif
modtronix 1:71204b8406f2 172
modtronix 1:71204b8406f2 173 #ifndef __MPU_PRESENT
modtronix 1:71204b8406f2 174 #define __MPU_PRESENT 0
modtronix 1:71204b8406f2 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 176 #endif
modtronix 1:71204b8406f2 177
modtronix 1:71204b8406f2 178 #ifndef __NVIC_PRIO_BITS
modtronix 1:71204b8406f2 179 #define __NVIC_PRIO_BITS 4
modtronix 1:71204b8406f2 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
modtronix 1:71204b8406f2 181 #endif
modtronix 1:71204b8406f2 182
modtronix 1:71204b8406f2 183 #ifndef __Vendor_SysTickConfig
modtronix 1:71204b8406f2 184 #define __Vendor_SysTickConfig 0
modtronix 1:71204b8406f2 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
modtronix 1:71204b8406f2 186 #endif
modtronix 1:71204b8406f2 187 #endif
modtronix 1:71204b8406f2 188
modtronix 1:71204b8406f2 189 /* IO definitions (access restrictions to peripheral registers) */
modtronix 1:71204b8406f2 190 /**
modtronix 1:71204b8406f2 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
modtronix 1:71204b8406f2 192
modtronix 1:71204b8406f2 193 <strong>IO Type Qualifiers</strong> are used
modtronix 1:71204b8406f2 194 \li to specify the access to peripheral variables.
modtronix 1:71204b8406f2 195 \li for automatic generation of peripheral register debug information.
modtronix 1:71204b8406f2 196 */
modtronix 1:71204b8406f2 197 #ifdef __cplusplus
modtronix 1:71204b8406f2 198 #define __I volatile /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 199 #else
modtronix 1:71204b8406f2 200 #define __I volatile const /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 201 #endif
modtronix 1:71204b8406f2 202 #define __O volatile /*!< Defines 'write only' permissions */
modtronix 1:71204b8406f2 203 #define __IO volatile /*!< Defines 'read / write' permissions */
modtronix 1:71204b8406f2 204
modtronix 1:71204b8406f2 205 /*@} end of group Cortex_M3 */
modtronix 1:71204b8406f2 206
modtronix 1:71204b8406f2 207
modtronix 1:71204b8406f2 208
modtronix 1:71204b8406f2 209 /*******************************************************************************
modtronix 1:71204b8406f2 210 * Register Abstraction
modtronix 1:71204b8406f2 211 Core Register contain:
modtronix 1:71204b8406f2 212 - Core Register
modtronix 1:71204b8406f2 213 - Core NVIC Register
modtronix 1:71204b8406f2 214 - Core SCB Register
modtronix 1:71204b8406f2 215 - Core SysTick Register
modtronix 1:71204b8406f2 216 - Core Debug Register
modtronix 1:71204b8406f2 217 - Core MPU Register
modtronix 1:71204b8406f2 218 ******************************************************************************/
modtronix 1:71204b8406f2 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
modtronix 1:71204b8406f2 220 \brief Type definitions and defines for Cortex-M processor based devices.
modtronix 1:71204b8406f2 221 */
modtronix 1:71204b8406f2 222
modtronix 1:71204b8406f2 223 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 224 \defgroup CMSIS_CORE Status and Control Registers
modtronix 1:71204b8406f2 225 \brief Core Register type definitions.
modtronix 1:71204b8406f2 226 @{
modtronix 1:71204b8406f2 227 */
modtronix 1:71204b8406f2 228
modtronix 1:71204b8406f2 229 /** \brief Union type to access the Application Program Status Register (APSR).
modtronix 1:71204b8406f2 230 */
modtronix 1:71204b8406f2 231 typedef union
modtronix 1:71204b8406f2 232 {
modtronix 1:71204b8406f2 233 struct
modtronix 1:71204b8406f2 234 {
modtronix 1:71204b8406f2 235 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 236 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
modtronix 1:71204b8406f2 237 #else
modtronix 1:71204b8406f2 238 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
modtronix 1:71204b8406f2 239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 240 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
modtronix 1:71204b8406f2 241 #endif
modtronix 1:71204b8406f2 242 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 243 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 244 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 245 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 246 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 247 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 248 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 249 } APSR_Type;
modtronix 1:71204b8406f2 250
modtronix 1:71204b8406f2 251
modtronix 1:71204b8406f2 252 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
modtronix 1:71204b8406f2 253 */
modtronix 1:71204b8406f2 254 typedef union
modtronix 1:71204b8406f2 255 {
modtronix 1:71204b8406f2 256 struct
modtronix 1:71204b8406f2 257 {
modtronix 1:71204b8406f2 258 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 259 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
modtronix 1:71204b8406f2 260 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 261 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 262 } IPSR_Type;
modtronix 1:71204b8406f2 263
modtronix 1:71204b8406f2 264
modtronix 1:71204b8406f2 265 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
modtronix 1:71204b8406f2 266 */
modtronix 1:71204b8406f2 267 typedef union
modtronix 1:71204b8406f2 268 {
modtronix 1:71204b8406f2 269 struct
modtronix 1:71204b8406f2 270 {
modtronix 1:71204b8406f2 271 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 272 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 273 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
modtronix 1:71204b8406f2 274 #else
modtronix 1:71204b8406f2 275 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
modtronix 1:71204b8406f2 276 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 277 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
modtronix 1:71204b8406f2 278 #endif
modtronix 1:71204b8406f2 279 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
modtronix 1:71204b8406f2 280 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
modtronix 1:71204b8406f2 281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 286 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 287 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 288 } xPSR_Type;
modtronix 1:71204b8406f2 289
modtronix 1:71204b8406f2 290
modtronix 1:71204b8406f2 291 /** \brief Union type to access the Control Registers (CONTROL).
modtronix 1:71204b8406f2 292 */
modtronix 1:71204b8406f2 293 typedef union
modtronix 1:71204b8406f2 294 {
modtronix 1:71204b8406f2 295 struct
modtronix 1:71204b8406f2 296 {
modtronix 1:71204b8406f2 297 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
modtronix 1:71204b8406f2 298 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
modtronix 1:71204b8406f2 299 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
modtronix 1:71204b8406f2 300 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
modtronix 1:71204b8406f2 301 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 302 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 303 } CONTROL_Type;
modtronix 1:71204b8406f2 304
modtronix 1:71204b8406f2 305 /*@} end of group CMSIS_CORE */
modtronix 1:71204b8406f2 306
modtronix 1:71204b8406f2 307
modtronix 1:71204b8406f2 308 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 309 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
modtronix 1:71204b8406f2 310 \brief Type definitions for the NVIC Registers
modtronix 1:71204b8406f2 311 @{
modtronix 1:71204b8406f2 312 */
modtronix 1:71204b8406f2 313
modtronix 1:71204b8406f2 314 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
modtronix 1:71204b8406f2 315 */
modtronix 1:71204b8406f2 316 typedef struct
modtronix 1:71204b8406f2 317 {
modtronix 1:71204b8406f2 318 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
modtronix 1:71204b8406f2 319 uint32_t RESERVED0[24];
modtronix 1:71204b8406f2 320 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
modtronix 1:71204b8406f2 321 uint32_t RSERVED1[24];
modtronix 1:71204b8406f2 322 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
modtronix 1:71204b8406f2 323 uint32_t RESERVED2[24];
modtronix 1:71204b8406f2 324 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
modtronix 1:71204b8406f2 325 uint32_t RESERVED3[24];
modtronix 1:71204b8406f2 326 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
modtronix 1:71204b8406f2 327 uint32_t RESERVED4[56];
modtronix 1:71204b8406f2 328 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
modtronix 1:71204b8406f2 329 uint32_t RESERVED5[644];
modtronix 1:71204b8406f2 330 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
modtronix 1:71204b8406f2 331 } NVIC_Type;
modtronix 1:71204b8406f2 332
modtronix 1:71204b8406f2 333 /* Software Triggered Interrupt Register Definitions */
modtronix 1:71204b8406f2 334 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
modtronix 1:71204b8406f2 335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
modtronix 1:71204b8406f2 336
modtronix 1:71204b8406f2 337 /*@} end of group CMSIS_NVIC */
modtronix 1:71204b8406f2 338
modtronix 1:71204b8406f2 339
modtronix 1:71204b8406f2 340 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 341 \defgroup CMSIS_SCB System Control Block (SCB)
modtronix 1:71204b8406f2 342 \brief Type definitions for the System Control Block Registers
modtronix 1:71204b8406f2 343 @{
modtronix 1:71204b8406f2 344 */
modtronix 1:71204b8406f2 345
modtronix 1:71204b8406f2 346 /** \brief Structure type to access the System Control Block (SCB).
modtronix 1:71204b8406f2 347 */
modtronix 1:71204b8406f2 348 typedef struct
modtronix 1:71204b8406f2 349 {
modtronix 1:71204b8406f2 350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
modtronix 1:71204b8406f2 351 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
modtronix 1:71204b8406f2 352 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
modtronix 1:71204b8406f2 353 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
modtronix 1:71204b8406f2 354 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
modtronix 1:71204b8406f2 355 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
modtronix 1:71204b8406f2 356 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
modtronix 1:71204b8406f2 357 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
modtronix 1:71204b8406f2 358 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
modtronix 1:71204b8406f2 359 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
modtronix 1:71204b8406f2 360 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
modtronix 1:71204b8406f2 361 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
modtronix 1:71204b8406f2 362 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
modtronix 1:71204b8406f2 363 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
modtronix 1:71204b8406f2 364 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
modtronix 1:71204b8406f2 365 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
modtronix 1:71204b8406f2 366 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
modtronix 1:71204b8406f2 367 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
modtronix 1:71204b8406f2 368 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
modtronix 1:71204b8406f2 369 uint32_t RESERVED0[5];
modtronix 1:71204b8406f2 370 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
modtronix 1:71204b8406f2 371 } SCB_Type;
modtronix 1:71204b8406f2 372
modtronix 1:71204b8406f2 373 /* SCB CPUID Register Definitions */
modtronix 1:71204b8406f2 374 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
modtronix 1:71204b8406f2 375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
modtronix 1:71204b8406f2 376
modtronix 1:71204b8406f2 377 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
modtronix 1:71204b8406f2 378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
modtronix 1:71204b8406f2 379
modtronix 1:71204b8406f2 380 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
modtronix 1:71204b8406f2 381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
modtronix 1:71204b8406f2 382
modtronix 1:71204b8406f2 383 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
modtronix 1:71204b8406f2 384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
modtronix 1:71204b8406f2 385
modtronix 1:71204b8406f2 386 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
modtronix 1:71204b8406f2 387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
modtronix 1:71204b8406f2 388
modtronix 1:71204b8406f2 389 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 390 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
modtronix 1:71204b8406f2 391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
modtronix 1:71204b8406f2 392
modtronix 1:71204b8406f2 393 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
modtronix 1:71204b8406f2 394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
modtronix 1:71204b8406f2 395
modtronix 1:71204b8406f2 396 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
modtronix 1:71204b8406f2 397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
modtronix 1:71204b8406f2 398
modtronix 1:71204b8406f2 399 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
modtronix 1:71204b8406f2 400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
modtronix 1:71204b8406f2 401
modtronix 1:71204b8406f2 402 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
modtronix 1:71204b8406f2 403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
modtronix 1:71204b8406f2 404
modtronix 1:71204b8406f2 405 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
modtronix 1:71204b8406f2 406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
modtronix 1:71204b8406f2 407
modtronix 1:71204b8406f2 408 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
modtronix 1:71204b8406f2 409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
modtronix 1:71204b8406f2 410
modtronix 1:71204b8406f2 411 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
modtronix 1:71204b8406f2 412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
modtronix 1:71204b8406f2 413
modtronix 1:71204b8406f2 414 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
modtronix 1:71204b8406f2 415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
modtronix 1:71204b8406f2 416
modtronix 1:71204b8406f2 417 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
modtronix 1:71204b8406f2 418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
modtronix 1:71204b8406f2 419
modtronix 1:71204b8406f2 420 /* SCB Vector Table Offset Register Definitions */
modtronix 1:71204b8406f2 421 #if (__CM3_REV < 0x0201) /* core r2p1 */
modtronix 1:71204b8406f2 422 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
modtronix 1:71204b8406f2 423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
modtronix 1:71204b8406f2 424
modtronix 1:71204b8406f2 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
modtronix 1:71204b8406f2 426 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 1:71204b8406f2 427 #else
modtronix 1:71204b8406f2 428 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
modtronix 1:71204b8406f2 429 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 1:71204b8406f2 430 #endif
modtronix 1:71204b8406f2 431
modtronix 1:71204b8406f2 432 /* SCB Application Interrupt and Reset Control Register Definitions */
modtronix 1:71204b8406f2 433 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
modtronix 1:71204b8406f2 434 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
modtronix 1:71204b8406f2 435
modtronix 1:71204b8406f2 436 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
modtronix 1:71204b8406f2 437 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
modtronix 1:71204b8406f2 438
modtronix 1:71204b8406f2 439 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
modtronix 1:71204b8406f2 440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
modtronix 1:71204b8406f2 441
modtronix 1:71204b8406f2 442 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
modtronix 1:71204b8406f2 443 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
modtronix 1:71204b8406f2 444
modtronix 1:71204b8406f2 445 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
modtronix 1:71204b8406f2 446 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
modtronix 1:71204b8406f2 447
modtronix 1:71204b8406f2 448 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
modtronix 1:71204b8406f2 449 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
modtronix 1:71204b8406f2 450
modtronix 1:71204b8406f2 451 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
modtronix 1:71204b8406f2 452 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
modtronix 1:71204b8406f2 453
modtronix 1:71204b8406f2 454 /* SCB System Control Register Definitions */
modtronix 1:71204b8406f2 455 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
modtronix 1:71204b8406f2 456 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
modtronix 1:71204b8406f2 457
modtronix 1:71204b8406f2 458 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
modtronix 1:71204b8406f2 459 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
modtronix 1:71204b8406f2 460
modtronix 1:71204b8406f2 461 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
modtronix 1:71204b8406f2 462 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
modtronix 1:71204b8406f2 463
modtronix 1:71204b8406f2 464 /* SCB Configuration Control Register Definitions */
modtronix 1:71204b8406f2 465 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
modtronix 1:71204b8406f2 466 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
modtronix 1:71204b8406f2 467
modtronix 1:71204b8406f2 468 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
modtronix 1:71204b8406f2 469 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
modtronix 1:71204b8406f2 470
modtronix 1:71204b8406f2 471 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
modtronix 1:71204b8406f2 472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
modtronix 1:71204b8406f2 473
modtronix 1:71204b8406f2 474 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
modtronix 1:71204b8406f2 475 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
modtronix 1:71204b8406f2 476
modtronix 1:71204b8406f2 477 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
modtronix 1:71204b8406f2 478 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
modtronix 1:71204b8406f2 479
modtronix 1:71204b8406f2 480 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
modtronix 1:71204b8406f2 481 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
modtronix 1:71204b8406f2 482
modtronix 1:71204b8406f2 483 /* SCB System Handler Control and State Register Definitions */
modtronix 1:71204b8406f2 484 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
modtronix 1:71204b8406f2 485 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
modtronix 1:71204b8406f2 486
modtronix 1:71204b8406f2 487 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
modtronix 1:71204b8406f2 488 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
modtronix 1:71204b8406f2 489
modtronix 1:71204b8406f2 490 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
modtronix 1:71204b8406f2 491 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
modtronix 1:71204b8406f2 492
modtronix 1:71204b8406f2 493 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
modtronix 1:71204b8406f2 494 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
modtronix 1:71204b8406f2 495
modtronix 1:71204b8406f2 496 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
modtronix 1:71204b8406f2 497 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
modtronix 1:71204b8406f2 498
modtronix 1:71204b8406f2 499 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
modtronix 1:71204b8406f2 500 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
modtronix 1:71204b8406f2 501
modtronix 1:71204b8406f2 502 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
modtronix 1:71204b8406f2 503 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
modtronix 1:71204b8406f2 504
modtronix 1:71204b8406f2 505 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
modtronix 1:71204b8406f2 506 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
modtronix 1:71204b8406f2 507
modtronix 1:71204b8406f2 508 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
modtronix 1:71204b8406f2 509 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
modtronix 1:71204b8406f2 510
modtronix 1:71204b8406f2 511 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
modtronix 1:71204b8406f2 512 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
modtronix 1:71204b8406f2 513
modtronix 1:71204b8406f2 514 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
modtronix 1:71204b8406f2 515 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
modtronix 1:71204b8406f2 516
modtronix 1:71204b8406f2 517 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
modtronix 1:71204b8406f2 518 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
modtronix 1:71204b8406f2 519
modtronix 1:71204b8406f2 520 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
modtronix 1:71204b8406f2 521 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
modtronix 1:71204b8406f2 522
modtronix 1:71204b8406f2 523 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
modtronix 1:71204b8406f2 524 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
modtronix 1:71204b8406f2 525
modtronix 1:71204b8406f2 526 /* SCB Configurable Fault Status Registers Definitions */
modtronix 1:71204b8406f2 527 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
modtronix 1:71204b8406f2 528 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
modtronix 1:71204b8406f2 529
modtronix 1:71204b8406f2 530 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
modtronix 1:71204b8406f2 531 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
modtronix 1:71204b8406f2 532
modtronix 1:71204b8406f2 533 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
modtronix 1:71204b8406f2 534 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
modtronix 1:71204b8406f2 535
modtronix 1:71204b8406f2 536 /* SCB Hard Fault Status Registers Definitions */
modtronix 1:71204b8406f2 537 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
modtronix 1:71204b8406f2 538 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
modtronix 1:71204b8406f2 539
modtronix 1:71204b8406f2 540 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
modtronix 1:71204b8406f2 541 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
modtronix 1:71204b8406f2 542
modtronix 1:71204b8406f2 543 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
modtronix 1:71204b8406f2 544 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
modtronix 1:71204b8406f2 545
modtronix 1:71204b8406f2 546 /* SCB Debug Fault Status Register Definitions */
modtronix 1:71204b8406f2 547 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
modtronix 1:71204b8406f2 548 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
modtronix 1:71204b8406f2 549
modtronix 1:71204b8406f2 550 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
modtronix 1:71204b8406f2 551 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
modtronix 1:71204b8406f2 552
modtronix 1:71204b8406f2 553 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
modtronix 1:71204b8406f2 554 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
modtronix 1:71204b8406f2 555
modtronix 1:71204b8406f2 556 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
modtronix 1:71204b8406f2 557 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
modtronix 1:71204b8406f2 558
modtronix 1:71204b8406f2 559 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
modtronix 1:71204b8406f2 560 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
modtronix 1:71204b8406f2 561
modtronix 1:71204b8406f2 562 /*@} end of group CMSIS_SCB */
modtronix 1:71204b8406f2 563
modtronix 1:71204b8406f2 564
modtronix 1:71204b8406f2 565 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 566 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
modtronix 1:71204b8406f2 567 \brief Type definitions for the System Control and ID Register not in the SCB
modtronix 1:71204b8406f2 568 @{
modtronix 1:71204b8406f2 569 */
modtronix 1:71204b8406f2 570
modtronix 1:71204b8406f2 571 /** \brief Structure type to access the System Control and ID Register not in the SCB.
modtronix 1:71204b8406f2 572 */
modtronix 1:71204b8406f2 573 typedef struct
modtronix 1:71204b8406f2 574 {
modtronix 1:71204b8406f2 575 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 576 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
modtronix 1:71204b8406f2 577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
modtronix 1:71204b8406f2 578 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
modtronix 1:71204b8406f2 579 #else
modtronix 1:71204b8406f2 580 uint32_t RESERVED1[1];
modtronix 1:71204b8406f2 581 #endif
modtronix 1:71204b8406f2 582 } SCnSCB_Type;
modtronix 1:71204b8406f2 583
modtronix 1:71204b8406f2 584 /* Interrupt Controller Type Register Definitions */
modtronix 1:71204b8406f2 585 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
modtronix 1:71204b8406f2 586 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
modtronix 1:71204b8406f2 587
modtronix 1:71204b8406f2 588 /* Auxiliary Control Register Definitions */
modtronix 1:71204b8406f2 589
modtronix 1:71204b8406f2 590 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
modtronix 1:71204b8406f2 591 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
modtronix 1:71204b8406f2 592
modtronix 1:71204b8406f2 593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
modtronix 1:71204b8406f2 594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
modtronix 1:71204b8406f2 595
modtronix 1:71204b8406f2 596 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
modtronix 1:71204b8406f2 597 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
modtronix 1:71204b8406f2 598
modtronix 1:71204b8406f2 599 /*@} end of group CMSIS_SCnotSCB */
modtronix 1:71204b8406f2 600
modtronix 1:71204b8406f2 601
modtronix 1:71204b8406f2 602 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 603 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
modtronix 1:71204b8406f2 604 \brief Type definitions for the System Timer Registers.
modtronix 1:71204b8406f2 605 @{
modtronix 1:71204b8406f2 606 */
modtronix 1:71204b8406f2 607
modtronix 1:71204b8406f2 608 /** \brief Structure type to access the System Timer (SysTick).
modtronix 1:71204b8406f2 609 */
modtronix 1:71204b8406f2 610 typedef struct
modtronix 1:71204b8406f2 611 {
modtronix 1:71204b8406f2 612 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
modtronix 1:71204b8406f2 613 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
modtronix 1:71204b8406f2 614 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
modtronix 1:71204b8406f2 615 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
modtronix 1:71204b8406f2 616 } SysTick_Type;
modtronix 1:71204b8406f2 617
modtronix 1:71204b8406f2 618 /* SysTick Control / Status Register Definitions */
modtronix 1:71204b8406f2 619 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
modtronix 1:71204b8406f2 620 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
modtronix 1:71204b8406f2 621
modtronix 1:71204b8406f2 622 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
modtronix 1:71204b8406f2 623 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
modtronix 1:71204b8406f2 624
modtronix 1:71204b8406f2 625 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
modtronix 1:71204b8406f2 626 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
modtronix 1:71204b8406f2 627
modtronix 1:71204b8406f2 628 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
modtronix 1:71204b8406f2 629 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 630
modtronix 1:71204b8406f2 631 /* SysTick Reload Register Definitions */
modtronix 1:71204b8406f2 632 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
modtronix 1:71204b8406f2 633 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
modtronix 1:71204b8406f2 634
modtronix 1:71204b8406f2 635 /* SysTick Current Register Definitions */
modtronix 1:71204b8406f2 636 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
modtronix 1:71204b8406f2 637 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
modtronix 1:71204b8406f2 638
modtronix 1:71204b8406f2 639 /* SysTick Calibration Register Definitions */
modtronix 1:71204b8406f2 640 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
modtronix 1:71204b8406f2 641 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
modtronix 1:71204b8406f2 642
modtronix 1:71204b8406f2 643 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
modtronix 1:71204b8406f2 644 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
modtronix 1:71204b8406f2 645
modtronix 1:71204b8406f2 646 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
modtronix 10:6444e6c798ce 647 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
modtronix 1:71204b8406f2 648
modtronix 1:71204b8406f2 649 /*@} end of group CMSIS_SysTick */
modtronix 1:71204b8406f2 650
modtronix 1:71204b8406f2 651
modtronix 1:71204b8406f2 652 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 653 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
modtronix 1:71204b8406f2 654 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
modtronix 1:71204b8406f2 655 @{
modtronix 1:71204b8406f2 656 */
modtronix 1:71204b8406f2 657
modtronix 1:71204b8406f2 658 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
modtronix 1:71204b8406f2 659 */
modtronix 1:71204b8406f2 660 typedef struct
modtronix 1:71204b8406f2 661 {
modtronix 1:71204b8406f2 662 __O union
modtronix 1:71204b8406f2 663 {
modtronix 1:71204b8406f2 664 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
modtronix 1:71204b8406f2 665 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
modtronix 1:71204b8406f2 666 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
modtronix 1:71204b8406f2 667 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
modtronix 1:71204b8406f2 668 uint32_t RESERVED0[864];
modtronix 1:71204b8406f2 669 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
modtronix 1:71204b8406f2 670 uint32_t RESERVED1[15];
modtronix 1:71204b8406f2 671 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
modtronix 1:71204b8406f2 672 uint32_t RESERVED2[15];
modtronix 1:71204b8406f2 673 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
modtronix 1:71204b8406f2 674 uint32_t RESERVED3[29];
modtronix 1:71204b8406f2 675 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
modtronix 1:71204b8406f2 676 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
modtronix 1:71204b8406f2 677 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
modtronix 1:71204b8406f2 678 uint32_t RESERVED4[43];
modtronix 1:71204b8406f2 679 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
modtronix 1:71204b8406f2 680 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
modtronix 1:71204b8406f2 681 uint32_t RESERVED5[6];
modtronix 1:71204b8406f2 682 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
modtronix 1:71204b8406f2 683 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
modtronix 1:71204b8406f2 684 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
modtronix 1:71204b8406f2 685 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
modtronix 1:71204b8406f2 686 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
modtronix 1:71204b8406f2 687 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
modtronix 1:71204b8406f2 688 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
modtronix 1:71204b8406f2 689 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
modtronix 1:71204b8406f2 690 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
modtronix 1:71204b8406f2 691 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
modtronix 1:71204b8406f2 692 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
modtronix 1:71204b8406f2 693 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
modtronix 1:71204b8406f2 694 } ITM_Type;
modtronix 1:71204b8406f2 695
modtronix 1:71204b8406f2 696 /* ITM Trace Privilege Register Definitions */
modtronix 1:71204b8406f2 697 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
modtronix 1:71204b8406f2 698 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
modtronix 1:71204b8406f2 699
modtronix 1:71204b8406f2 700 /* ITM Trace Control Register Definitions */
modtronix 1:71204b8406f2 701 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
modtronix 1:71204b8406f2 702 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
modtronix 1:71204b8406f2 703
modtronix 1:71204b8406f2 704 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
modtronix 1:71204b8406f2 705 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
modtronix 1:71204b8406f2 706
modtronix 1:71204b8406f2 707 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
modtronix 1:71204b8406f2 708 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
modtronix 1:71204b8406f2 709
modtronix 1:71204b8406f2 710 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
modtronix 1:71204b8406f2 711 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
modtronix 1:71204b8406f2 712
modtronix 1:71204b8406f2 713 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
modtronix 1:71204b8406f2 714 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
modtronix 1:71204b8406f2 715
modtronix 1:71204b8406f2 716 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
modtronix 1:71204b8406f2 717 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
modtronix 1:71204b8406f2 718
modtronix 1:71204b8406f2 719 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
modtronix 1:71204b8406f2 720 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
modtronix 1:71204b8406f2 721
modtronix 1:71204b8406f2 722 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
modtronix 1:71204b8406f2 723 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
modtronix 1:71204b8406f2 724
modtronix 1:71204b8406f2 725 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
modtronix 1:71204b8406f2 726 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
modtronix 1:71204b8406f2 727
modtronix 1:71204b8406f2 728 /* ITM Integration Write Register Definitions */
modtronix 1:71204b8406f2 729 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
modtronix 1:71204b8406f2 730 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
modtronix 1:71204b8406f2 731
modtronix 1:71204b8406f2 732 /* ITM Integration Read Register Definitions */
modtronix 1:71204b8406f2 733 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
modtronix 1:71204b8406f2 734 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
modtronix 1:71204b8406f2 735
modtronix 1:71204b8406f2 736 /* ITM Integration Mode Control Register Definitions */
modtronix 1:71204b8406f2 737 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
modtronix 1:71204b8406f2 738 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
modtronix 1:71204b8406f2 739
modtronix 1:71204b8406f2 740 /* ITM Lock Status Register Definitions */
modtronix 1:71204b8406f2 741 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
modtronix 1:71204b8406f2 742 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
modtronix 1:71204b8406f2 743
modtronix 1:71204b8406f2 744 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
modtronix 1:71204b8406f2 745 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
modtronix 1:71204b8406f2 746
modtronix 1:71204b8406f2 747 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
modtronix 1:71204b8406f2 748 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
modtronix 1:71204b8406f2 749
modtronix 1:71204b8406f2 750 /*@}*/ /* end of group CMSIS_ITM */
modtronix 1:71204b8406f2 751
modtronix 1:71204b8406f2 752
modtronix 1:71204b8406f2 753 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 754 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
modtronix 1:71204b8406f2 755 \brief Type definitions for the Data Watchpoint and Trace (DWT)
modtronix 1:71204b8406f2 756 @{
modtronix 1:71204b8406f2 757 */
modtronix 1:71204b8406f2 758
modtronix 1:71204b8406f2 759 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
modtronix 1:71204b8406f2 760 */
modtronix 1:71204b8406f2 761 typedef struct
modtronix 1:71204b8406f2 762 {
modtronix 1:71204b8406f2 763 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
modtronix 1:71204b8406f2 764 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
modtronix 1:71204b8406f2 765 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
modtronix 1:71204b8406f2 766 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
modtronix 1:71204b8406f2 767 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
modtronix 1:71204b8406f2 768 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
modtronix 1:71204b8406f2 769 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
modtronix 1:71204b8406f2 770 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
modtronix 1:71204b8406f2 771 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
modtronix 1:71204b8406f2 772 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
modtronix 1:71204b8406f2 773 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
modtronix 1:71204b8406f2 774 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 775 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
modtronix 1:71204b8406f2 776 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
modtronix 1:71204b8406f2 777 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
modtronix 1:71204b8406f2 778 uint32_t RESERVED1[1];
modtronix 1:71204b8406f2 779 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
modtronix 1:71204b8406f2 780 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
modtronix 1:71204b8406f2 781 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
modtronix 1:71204b8406f2 782 uint32_t RESERVED2[1];
modtronix 1:71204b8406f2 783 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
modtronix 1:71204b8406f2 784 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
modtronix 1:71204b8406f2 785 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
modtronix 1:71204b8406f2 786 } DWT_Type;
modtronix 1:71204b8406f2 787
modtronix 1:71204b8406f2 788 /* DWT Control Register Definitions */
modtronix 1:71204b8406f2 789 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
modtronix 1:71204b8406f2 790 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
modtronix 1:71204b8406f2 791
modtronix 1:71204b8406f2 792 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
modtronix 1:71204b8406f2 793 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
modtronix 1:71204b8406f2 794
modtronix 1:71204b8406f2 795 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
modtronix 1:71204b8406f2 796 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
modtronix 1:71204b8406f2 797
modtronix 1:71204b8406f2 798 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
modtronix 1:71204b8406f2 799 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
modtronix 1:71204b8406f2 800
modtronix 1:71204b8406f2 801 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
modtronix 1:71204b8406f2 802 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
modtronix 1:71204b8406f2 803
modtronix 1:71204b8406f2 804 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
modtronix 1:71204b8406f2 805 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
modtronix 1:71204b8406f2 806
modtronix 1:71204b8406f2 807 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
modtronix 1:71204b8406f2 808 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
modtronix 1:71204b8406f2 809
modtronix 1:71204b8406f2 810 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
modtronix 1:71204b8406f2 811 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
modtronix 1:71204b8406f2 812
modtronix 1:71204b8406f2 813 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
modtronix 1:71204b8406f2 814 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
modtronix 1:71204b8406f2 815
modtronix 1:71204b8406f2 816 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
modtronix 1:71204b8406f2 817 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
modtronix 1:71204b8406f2 818
modtronix 1:71204b8406f2 819 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
modtronix 1:71204b8406f2 820 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
modtronix 1:71204b8406f2 821
modtronix 1:71204b8406f2 822 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
modtronix 1:71204b8406f2 823 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
modtronix 1:71204b8406f2 824
modtronix 1:71204b8406f2 825 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
modtronix 1:71204b8406f2 826 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
modtronix 1:71204b8406f2 827
modtronix 1:71204b8406f2 828 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
modtronix 1:71204b8406f2 829 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
modtronix 1:71204b8406f2 830
modtronix 1:71204b8406f2 831 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
modtronix 1:71204b8406f2 832 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
modtronix 1:71204b8406f2 833
modtronix 1:71204b8406f2 834 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
modtronix 1:71204b8406f2 835 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
modtronix 1:71204b8406f2 836
modtronix 1:71204b8406f2 837 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
modtronix 1:71204b8406f2 838 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
modtronix 1:71204b8406f2 839
modtronix 1:71204b8406f2 840 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
modtronix 1:71204b8406f2 841 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
modtronix 1:71204b8406f2 842
modtronix 1:71204b8406f2 843 /* DWT CPI Count Register Definitions */
modtronix 1:71204b8406f2 844 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
modtronix 1:71204b8406f2 845 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
modtronix 1:71204b8406f2 846
modtronix 1:71204b8406f2 847 /* DWT Exception Overhead Count Register Definitions */
modtronix 1:71204b8406f2 848 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
modtronix 1:71204b8406f2 849 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
modtronix 1:71204b8406f2 850
modtronix 1:71204b8406f2 851 /* DWT Sleep Count Register Definitions */
modtronix 1:71204b8406f2 852 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
modtronix 1:71204b8406f2 853 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
modtronix 1:71204b8406f2 854
modtronix 1:71204b8406f2 855 /* DWT LSU Count Register Definitions */
modtronix 1:71204b8406f2 856 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
modtronix 1:71204b8406f2 857 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
modtronix 1:71204b8406f2 858
modtronix 1:71204b8406f2 859 /* DWT Folded-instruction Count Register Definitions */
modtronix 1:71204b8406f2 860 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
modtronix 1:71204b8406f2 861 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
modtronix 1:71204b8406f2 862
modtronix 1:71204b8406f2 863 /* DWT Comparator Mask Register Definitions */
modtronix 1:71204b8406f2 864 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
modtronix 1:71204b8406f2 865 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
modtronix 1:71204b8406f2 866
modtronix 1:71204b8406f2 867 /* DWT Comparator Function Register Definitions */
modtronix 1:71204b8406f2 868 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
modtronix 1:71204b8406f2 869 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
modtronix 1:71204b8406f2 870
modtronix 1:71204b8406f2 871 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
modtronix 1:71204b8406f2 872 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
modtronix 1:71204b8406f2 873
modtronix 1:71204b8406f2 874 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
modtronix 1:71204b8406f2 875 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
modtronix 1:71204b8406f2 876
modtronix 1:71204b8406f2 877 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
modtronix 1:71204b8406f2 878 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
modtronix 1:71204b8406f2 879
modtronix 1:71204b8406f2 880 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
modtronix 1:71204b8406f2 881 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
modtronix 1:71204b8406f2 882
modtronix 1:71204b8406f2 883 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
modtronix 1:71204b8406f2 884 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
modtronix 1:71204b8406f2 885
modtronix 1:71204b8406f2 886 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
modtronix 1:71204b8406f2 887 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
modtronix 1:71204b8406f2 888
modtronix 1:71204b8406f2 889 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
modtronix 1:71204b8406f2 890 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
modtronix 1:71204b8406f2 891
modtronix 1:71204b8406f2 892 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
modtronix 1:71204b8406f2 893 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
modtronix 1:71204b8406f2 894
modtronix 1:71204b8406f2 895 /*@}*/ /* end of group CMSIS_DWT */
modtronix 1:71204b8406f2 896
modtronix 1:71204b8406f2 897
modtronix 1:71204b8406f2 898 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 899 \defgroup CMSIS_TPI Trace Port Interface (TPI)
modtronix 1:71204b8406f2 900 \brief Type definitions for the Trace Port Interface (TPI)
modtronix 1:71204b8406f2 901 @{
modtronix 1:71204b8406f2 902 */
modtronix 1:71204b8406f2 903
modtronix 1:71204b8406f2 904 /** \brief Structure type to access the Trace Port Interface Register (TPI).
modtronix 1:71204b8406f2 905 */
modtronix 1:71204b8406f2 906 typedef struct
modtronix 1:71204b8406f2 907 {
modtronix 1:71204b8406f2 908 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
modtronix 1:71204b8406f2 909 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
modtronix 1:71204b8406f2 910 uint32_t RESERVED0[2];
modtronix 1:71204b8406f2 911 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
modtronix 1:71204b8406f2 912 uint32_t RESERVED1[55];
modtronix 1:71204b8406f2 913 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
modtronix 1:71204b8406f2 914 uint32_t RESERVED2[131];
modtronix 1:71204b8406f2 915 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
modtronix 1:71204b8406f2 916 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
modtronix 1:71204b8406f2 917 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
modtronix 1:71204b8406f2 918 uint32_t RESERVED3[759];
modtronix 1:71204b8406f2 919 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
modtronix 1:71204b8406f2 920 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
modtronix 1:71204b8406f2 921 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
modtronix 1:71204b8406f2 922 uint32_t RESERVED4[1];
modtronix 1:71204b8406f2 923 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
modtronix 1:71204b8406f2 924 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
modtronix 1:71204b8406f2 925 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
modtronix 1:71204b8406f2 926 uint32_t RESERVED5[39];
modtronix 1:71204b8406f2 927 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
modtronix 1:71204b8406f2 928 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
modtronix 1:71204b8406f2 929 uint32_t RESERVED7[8];
modtronix 1:71204b8406f2 930 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
modtronix 1:71204b8406f2 931 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
modtronix 1:71204b8406f2 932 } TPI_Type;
modtronix 1:71204b8406f2 933
modtronix 1:71204b8406f2 934 /* TPI Asynchronous Clock Prescaler Register Definitions */
modtronix 1:71204b8406f2 935 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
modtronix 1:71204b8406f2 936 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
modtronix 1:71204b8406f2 937
modtronix 1:71204b8406f2 938 /* TPI Selected Pin Protocol Register Definitions */
modtronix 1:71204b8406f2 939 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
modtronix 1:71204b8406f2 940 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
modtronix 1:71204b8406f2 941
modtronix 1:71204b8406f2 942 /* TPI Formatter and Flush Status Register Definitions */
modtronix 1:71204b8406f2 943 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
modtronix 1:71204b8406f2 944 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
modtronix 1:71204b8406f2 945
modtronix 1:71204b8406f2 946 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
modtronix 1:71204b8406f2 947 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
modtronix 1:71204b8406f2 948
modtronix 1:71204b8406f2 949 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
modtronix 1:71204b8406f2 950 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
modtronix 1:71204b8406f2 951
modtronix 1:71204b8406f2 952 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
modtronix 1:71204b8406f2 953 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
modtronix 1:71204b8406f2 954
modtronix 1:71204b8406f2 955 /* TPI Formatter and Flush Control Register Definitions */
modtronix 1:71204b8406f2 956 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
modtronix 1:71204b8406f2 957 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
modtronix 1:71204b8406f2 958
modtronix 1:71204b8406f2 959 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
modtronix 1:71204b8406f2 960 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
modtronix 1:71204b8406f2 961
modtronix 1:71204b8406f2 962 /* TPI TRIGGER Register Definitions */
modtronix 1:71204b8406f2 963 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
modtronix 1:71204b8406f2 964 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
modtronix 1:71204b8406f2 965
modtronix 1:71204b8406f2 966 /* TPI Integration ETM Data Register Definitions (FIFO0) */
modtronix 1:71204b8406f2 967 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
modtronix 1:71204b8406f2 968 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
modtronix 1:71204b8406f2 969
modtronix 1:71204b8406f2 970 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
modtronix 1:71204b8406f2 971 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
modtronix 1:71204b8406f2 972
modtronix 1:71204b8406f2 973 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
modtronix 1:71204b8406f2 974 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
modtronix 1:71204b8406f2 975
modtronix 1:71204b8406f2 976 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
modtronix 1:71204b8406f2 977 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
modtronix 1:71204b8406f2 978
modtronix 1:71204b8406f2 979 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
modtronix 1:71204b8406f2 980 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
modtronix 1:71204b8406f2 981
modtronix 1:71204b8406f2 982 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
modtronix 1:71204b8406f2 983 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
modtronix 1:71204b8406f2 984
modtronix 1:71204b8406f2 985 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
modtronix 1:71204b8406f2 986 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
modtronix 1:71204b8406f2 987
modtronix 1:71204b8406f2 988 /* TPI ITATBCTR2 Register Definitions */
modtronix 1:71204b8406f2 989 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
modtronix 1:71204b8406f2 990 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
modtronix 1:71204b8406f2 991
modtronix 1:71204b8406f2 992 /* TPI Integration ITM Data Register Definitions (FIFO1) */
modtronix 1:71204b8406f2 993 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
modtronix 1:71204b8406f2 994 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
modtronix 1:71204b8406f2 995
modtronix 1:71204b8406f2 996 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
modtronix 1:71204b8406f2 997 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
modtronix 1:71204b8406f2 998
modtronix 1:71204b8406f2 999 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
modtronix 1:71204b8406f2 1000 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
modtronix 1:71204b8406f2 1001
modtronix 1:71204b8406f2 1002 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
modtronix 1:71204b8406f2 1003 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
modtronix 1:71204b8406f2 1004
modtronix 1:71204b8406f2 1005 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
modtronix 1:71204b8406f2 1006 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
modtronix 1:71204b8406f2 1007
modtronix 1:71204b8406f2 1008 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
modtronix 1:71204b8406f2 1009 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
modtronix 1:71204b8406f2 1010
modtronix 1:71204b8406f2 1011 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
modtronix 1:71204b8406f2 1012 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
modtronix 1:71204b8406f2 1013
modtronix 1:71204b8406f2 1014 /* TPI ITATBCTR0 Register Definitions */
modtronix 1:71204b8406f2 1015 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
modtronix 1:71204b8406f2 1016 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
modtronix 1:71204b8406f2 1017
modtronix 1:71204b8406f2 1018 /* TPI Integration Mode Control Register Definitions */
modtronix 1:71204b8406f2 1019 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
modtronix 1:71204b8406f2 1020 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
modtronix 1:71204b8406f2 1021
modtronix 1:71204b8406f2 1022 /* TPI DEVID Register Definitions */
modtronix 1:71204b8406f2 1023 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
modtronix 1:71204b8406f2 1024 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
modtronix 1:71204b8406f2 1025
modtronix 1:71204b8406f2 1026 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
modtronix 1:71204b8406f2 1027 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
modtronix 1:71204b8406f2 1028
modtronix 1:71204b8406f2 1029 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
modtronix 1:71204b8406f2 1030 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
modtronix 1:71204b8406f2 1031
modtronix 1:71204b8406f2 1032 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
modtronix 1:71204b8406f2 1033 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
modtronix 1:71204b8406f2 1034
modtronix 1:71204b8406f2 1035 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
modtronix 1:71204b8406f2 1036 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
modtronix 1:71204b8406f2 1037
modtronix 1:71204b8406f2 1038 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
modtronix 1:71204b8406f2 1039 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
modtronix 1:71204b8406f2 1040
modtronix 1:71204b8406f2 1041 /* TPI DEVTYPE Register Definitions */
modtronix 1:71204b8406f2 1042 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
modtronix 1:71204b8406f2 1043 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
modtronix 1:71204b8406f2 1044
modtronix 1:71204b8406f2 1045 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
modtronix 1:71204b8406f2 1046 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
modtronix 1:71204b8406f2 1047
modtronix 1:71204b8406f2 1048 /*@}*/ /* end of group CMSIS_TPI */
modtronix 1:71204b8406f2 1049
modtronix 1:71204b8406f2 1050
modtronix 1:71204b8406f2 1051 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 1052 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1053 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 1054 \brief Type definitions for the Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 1055 @{
modtronix 1:71204b8406f2 1056 */
modtronix 1:71204b8406f2 1057
modtronix 1:71204b8406f2 1058 /** \brief Structure type to access the Memory Protection Unit (MPU).
modtronix 1:71204b8406f2 1059 */
modtronix 1:71204b8406f2 1060 typedef struct
modtronix 1:71204b8406f2 1061 {
modtronix 1:71204b8406f2 1062 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
modtronix 1:71204b8406f2 1063 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
modtronix 1:71204b8406f2 1064 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
modtronix 1:71204b8406f2 1065 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
modtronix 1:71204b8406f2 1066 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 1067 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
modtronix 1:71204b8406f2 1068 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1069 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
modtronix 1:71204b8406f2 1070 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1071 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
modtronix 1:71204b8406f2 1072 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1073 } MPU_Type;
modtronix 1:71204b8406f2 1074
modtronix 1:71204b8406f2 1075 /* MPU Type Register */
modtronix 1:71204b8406f2 1076 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
modtronix 1:71204b8406f2 1077 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
modtronix 1:71204b8406f2 1078
modtronix 1:71204b8406f2 1079 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
modtronix 1:71204b8406f2 1080 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
modtronix 1:71204b8406f2 1081
modtronix 1:71204b8406f2 1082 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
modtronix 1:71204b8406f2 1083 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
modtronix 1:71204b8406f2 1084
modtronix 1:71204b8406f2 1085 /* MPU Control Register */
modtronix 1:71204b8406f2 1086 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
modtronix 1:71204b8406f2 1087 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
modtronix 1:71204b8406f2 1088
modtronix 1:71204b8406f2 1089 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
modtronix 1:71204b8406f2 1090 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
modtronix 1:71204b8406f2 1091
modtronix 1:71204b8406f2 1092 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
modtronix 1:71204b8406f2 1093 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 1094
modtronix 1:71204b8406f2 1095 /* MPU Region Number Register */
modtronix 1:71204b8406f2 1096 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
modtronix 1:71204b8406f2 1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
modtronix 1:71204b8406f2 1098
modtronix 1:71204b8406f2 1099 /* MPU Region Base Address Register */
modtronix 1:71204b8406f2 1100 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
modtronix 1:71204b8406f2 1101 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
modtronix 1:71204b8406f2 1102
modtronix 1:71204b8406f2 1103 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
modtronix 1:71204b8406f2 1104 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
modtronix 1:71204b8406f2 1105
modtronix 1:71204b8406f2 1106 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
modtronix 1:71204b8406f2 1107 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
modtronix 1:71204b8406f2 1108
modtronix 1:71204b8406f2 1109 /* MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 1110 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
modtronix 1:71204b8406f2 1111 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
modtronix 1:71204b8406f2 1112
modtronix 1:71204b8406f2 1113 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
modtronix 1:71204b8406f2 1114 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
modtronix 1:71204b8406f2 1115
modtronix 1:71204b8406f2 1116 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
modtronix 1:71204b8406f2 1117 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
modtronix 1:71204b8406f2 1118
modtronix 1:71204b8406f2 1119 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
modtronix 1:71204b8406f2 1120 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
modtronix 1:71204b8406f2 1121
modtronix 1:71204b8406f2 1122 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
modtronix 1:71204b8406f2 1123 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
modtronix 1:71204b8406f2 1124
modtronix 1:71204b8406f2 1125 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
modtronix 1:71204b8406f2 1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
modtronix 1:71204b8406f2 1127
modtronix 1:71204b8406f2 1128 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
modtronix 1:71204b8406f2 1129 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
modtronix 1:71204b8406f2 1130
modtronix 1:71204b8406f2 1131 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
modtronix 1:71204b8406f2 1132 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
modtronix 1:71204b8406f2 1133
modtronix 1:71204b8406f2 1134 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
modtronix 1:71204b8406f2 1135 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
modtronix 1:71204b8406f2 1136
modtronix 1:71204b8406f2 1137 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
modtronix 1:71204b8406f2 1138 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
modtronix 1:71204b8406f2 1139
modtronix 1:71204b8406f2 1140 /*@} end of group CMSIS_MPU */
modtronix 1:71204b8406f2 1141 #endif
modtronix 1:71204b8406f2 1142
modtronix 1:71204b8406f2 1143
modtronix 1:71204b8406f2 1144 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1145 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
modtronix 1:71204b8406f2 1146 \brief Type definitions for the Core Debug Registers
modtronix 1:71204b8406f2 1147 @{
modtronix 1:71204b8406f2 1148 */
modtronix 1:71204b8406f2 1149
modtronix 1:71204b8406f2 1150 /** \brief Structure type to access the Core Debug Register (CoreDebug).
modtronix 1:71204b8406f2 1151 */
modtronix 1:71204b8406f2 1152 typedef struct
modtronix 1:71204b8406f2 1153 {
modtronix 1:71204b8406f2 1154 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
modtronix 1:71204b8406f2 1155 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
modtronix 1:71204b8406f2 1156 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
modtronix 1:71204b8406f2 1157 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
modtronix 1:71204b8406f2 1158 } CoreDebug_Type;
modtronix 1:71204b8406f2 1159
modtronix 1:71204b8406f2 1160 /* Debug Halting Control and Status Register */
modtronix 1:71204b8406f2 1161 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
modtronix 1:71204b8406f2 1162 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
modtronix 1:71204b8406f2 1163
modtronix 1:71204b8406f2 1164 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
modtronix 1:71204b8406f2 1165 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
modtronix 1:71204b8406f2 1166
modtronix 1:71204b8406f2 1167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
modtronix 1:71204b8406f2 1168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
modtronix 1:71204b8406f2 1169
modtronix 1:71204b8406f2 1170 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
modtronix 1:71204b8406f2 1171 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
modtronix 1:71204b8406f2 1172
modtronix 1:71204b8406f2 1173 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
modtronix 1:71204b8406f2 1174 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
modtronix 1:71204b8406f2 1175
modtronix 1:71204b8406f2 1176 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
modtronix 1:71204b8406f2 1177 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
modtronix 1:71204b8406f2 1178
modtronix 1:71204b8406f2 1179 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
modtronix 1:71204b8406f2 1180 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
modtronix 1:71204b8406f2 1181
modtronix 1:71204b8406f2 1182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
modtronix 1:71204b8406f2 1183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
modtronix 1:71204b8406f2 1184
modtronix 1:71204b8406f2 1185 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
modtronix 1:71204b8406f2 1186 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
modtronix 1:71204b8406f2 1187
modtronix 1:71204b8406f2 1188 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
modtronix 1:71204b8406f2 1189 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
modtronix 1:71204b8406f2 1190
modtronix 1:71204b8406f2 1191 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
modtronix 1:71204b8406f2 1192 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
modtronix 1:71204b8406f2 1193
modtronix 1:71204b8406f2 1194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
modtronix 1:71204b8406f2 1195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
modtronix 1:71204b8406f2 1196
modtronix 1:71204b8406f2 1197 /* Debug Core Register Selector Register */
modtronix 1:71204b8406f2 1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
modtronix 1:71204b8406f2 1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
modtronix 1:71204b8406f2 1200
modtronix 1:71204b8406f2 1201 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
modtronix 1:71204b8406f2 1202 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
modtronix 1:71204b8406f2 1203
modtronix 1:71204b8406f2 1204 /* Debug Exception and Monitor Control Register */
modtronix 1:71204b8406f2 1205 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
modtronix 1:71204b8406f2 1206 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
modtronix 1:71204b8406f2 1207
modtronix 1:71204b8406f2 1208 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
modtronix 1:71204b8406f2 1209 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
modtronix 1:71204b8406f2 1210
modtronix 1:71204b8406f2 1211 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
modtronix 1:71204b8406f2 1212 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
modtronix 1:71204b8406f2 1213
modtronix 1:71204b8406f2 1214 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
modtronix 1:71204b8406f2 1215 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
modtronix 1:71204b8406f2 1216
modtronix 1:71204b8406f2 1217 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
modtronix 1:71204b8406f2 1218 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
modtronix 1:71204b8406f2 1219
modtronix 1:71204b8406f2 1220 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
modtronix 1:71204b8406f2 1221 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
modtronix 1:71204b8406f2 1222
modtronix 1:71204b8406f2 1223 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
modtronix 1:71204b8406f2 1224 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
modtronix 1:71204b8406f2 1225
modtronix 1:71204b8406f2 1226 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
modtronix 1:71204b8406f2 1227 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
modtronix 1:71204b8406f2 1228
modtronix 1:71204b8406f2 1229 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
modtronix 1:71204b8406f2 1230 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
modtronix 1:71204b8406f2 1231
modtronix 1:71204b8406f2 1232 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
modtronix 1:71204b8406f2 1233 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
modtronix 1:71204b8406f2 1234
modtronix 1:71204b8406f2 1235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
modtronix 1:71204b8406f2 1236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
modtronix 1:71204b8406f2 1237
modtronix 1:71204b8406f2 1238 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
modtronix 1:71204b8406f2 1239 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
modtronix 1:71204b8406f2 1240
modtronix 1:71204b8406f2 1241 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
modtronix 1:71204b8406f2 1242 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
modtronix 1:71204b8406f2 1243
modtronix 1:71204b8406f2 1244 /*@} end of group CMSIS_CoreDebug */
modtronix 1:71204b8406f2 1245
modtronix 1:71204b8406f2 1246
modtronix 1:71204b8406f2 1247 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1248 \defgroup CMSIS_core_base Core Definitions
modtronix 1:71204b8406f2 1249 \brief Definitions for base addresses, unions, and structures.
modtronix 1:71204b8406f2 1250 @{
modtronix 1:71204b8406f2 1251 */
modtronix 1:71204b8406f2 1252
modtronix 1:71204b8406f2 1253 /* Memory mapping of Cortex-M3 Hardware */
modtronix 1:71204b8406f2 1254 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
modtronix 1:71204b8406f2 1255 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
modtronix 1:71204b8406f2 1256 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
modtronix 1:71204b8406f2 1257 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
modtronix 1:71204b8406f2 1258 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
modtronix 1:71204b8406f2 1259 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
modtronix 1:71204b8406f2 1260 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
modtronix 1:71204b8406f2 1261 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
modtronix 1:71204b8406f2 1262
modtronix 1:71204b8406f2 1263 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
modtronix 1:71204b8406f2 1264 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
modtronix 1:71204b8406f2 1265 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
modtronix 1:71204b8406f2 1266 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
modtronix 1:71204b8406f2 1267 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
modtronix 1:71204b8406f2 1268 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
modtronix 1:71204b8406f2 1269 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
modtronix 1:71204b8406f2 1270 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
modtronix 1:71204b8406f2 1271
modtronix 1:71204b8406f2 1272 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 1273 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 1274 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 1275 #endif
modtronix 1:71204b8406f2 1276
modtronix 1:71204b8406f2 1277 /*@} */
modtronix 1:71204b8406f2 1278
modtronix 1:71204b8406f2 1279
modtronix 1:71204b8406f2 1280
modtronix 1:71204b8406f2 1281 /*******************************************************************************
modtronix 1:71204b8406f2 1282 * Hardware Abstraction Layer
modtronix 1:71204b8406f2 1283 Core Function Interface contains:
modtronix 1:71204b8406f2 1284 - Core NVIC Functions
modtronix 1:71204b8406f2 1285 - Core SysTick Functions
modtronix 1:71204b8406f2 1286 - Core Debug Functions
modtronix 1:71204b8406f2 1287 - Core Register Access Functions
modtronix 1:71204b8406f2 1288 ******************************************************************************/
modtronix 1:71204b8406f2 1289 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
modtronix 1:71204b8406f2 1290 */
modtronix 1:71204b8406f2 1291
modtronix 1:71204b8406f2 1292
modtronix 1:71204b8406f2 1293
modtronix 1:71204b8406f2 1294 /* ########################## NVIC functions #################################### */
modtronix 1:71204b8406f2 1295 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 1296 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
modtronix 1:71204b8406f2 1297 \brief Functions that manage interrupts and exceptions via the NVIC.
modtronix 1:71204b8406f2 1298 @{
modtronix 1:71204b8406f2 1299 */
modtronix 1:71204b8406f2 1300
modtronix 1:71204b8406f2 1301 /** \brief Set Priority Grouping
modtronix 1:71204b8406f2 1302
modtronix 1:71204b8406f2 1303 The function sets the priority grouping field using the required unlock sequence.
modtronix 1:71204b8406f2 1304 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
modtronix 1:71204b8406f2 1305 Only values from 0..7 are used.
modtronix 1:71204b8406f2 1306 In case of a conflict between priority grouping and available
modtronix 1:71204b8406f2 1307 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
modtronix 1:71204b8406f2 1308
modtronix 1:71204b8406f2 1309 \param [in] PriorityGroup Priority grouping field.
modtronix 1:71204b8406f2 1310 */
modtronix 1:71204b8406f2 1311 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
modtronix 1:71204b8406f2 1312 {
modtronix 1:71204b8406f2 1313 uint32_t reg_value;
modtronix 1:71204b8406f2 1314 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1315
modtronix 1:71204b8406f2 1316 reg_value = SCB->AIRCR; /* read old register configuration */
modtronix 1:71204b8406f2 1317 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
modtronix 1:71204b8406f2 1318 reg_value = (reg_value |
modtronix 1:71204b8406f2 1319 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 1:71204b8406f2 1320 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
modtronix 1:71204b8406f2 1321 SCB->AIRCR = reg_value;
modtronix 1:71204b8406f2 1322 }
modtronix 1:71204b8406f2 1323
modtronix 1:71204b8406f2 1324
modtronix 1:71204b8406f2 1325 /** \brief Get Priority Grouping
modtronix 1:71204b8406f2 1326
modtronix 1:71204b8406f2 1327 The function reads the priority grouping field from the NVIC Interrupt Controller.
modtronix 1:71204b8406f2 1328
modtronix 1:71204b8406f2 1329 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
modtronix 1:71204b8406f2 1330 */
modtronix 1:71204b8406f2 1331 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
modtronix 1:71204b8406f2 1332 {
modtronix 1:71204b8406f2 1333 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
modtronix 1:71204b8406f2 1334 }
modtronix 1:71204b8406f2 1335
modtronix 1:71204b8406f2 1336
modtronix 1:71204b8406f2 1337 /** \brief Enable External Interrupt
modtronix 1:71204b8406f2 1338
modtronix 1:71204b8406f2 1339 The function enables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 1340
modtronix 1:71204b8406f2 1341 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1342 */
modtronix 1:71204b8406f2 1343 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1344 {
modtronix 1:71204b8406f2 1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
modtronix 1:71204b8406f2 1346 }
modtronix 1:71204b8406f2 1347
modtronix 1:71204b8406f2 1348
modtronix 1:71204b8406f2 1349 /** \brief Disable External Interrupt
modtronix 1:71204b8406f2 1350
modtronix 1:71204b8406f2 1351 The function disables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 1352
modtronix 1:71204b8406f2 1353 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1354 */
modtronix 1:71204b8406f2 1355 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1356 {
modtronix 1:71204b8406f2 1357 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
modtronix 1:71204b8406f2 1358 }
modtronix 1:71204b8406f2 1359
modtronix 1:71204b8406f2 1360
modtronix 1:71204b8406f2 1361 /** \brief Get Pending Interrupt
modtronix 1:71204b8406f2 1362
modtronix 1:71204b8406f2 1363 The function reads the pending register in the NVIC and returns the pending bit
modtronix 1:71204b8406f2 1364 for the specified interrupt.
modtronix 1:71204b8406f2 1365
modtronix 1:71204b8406f2 1366 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1367
modtronix 1:71204b8406f2 1368 \return 0 Interrupt status is not pending.
modtronix 1:71204b8406f2 1369 \return 1 Interrupt status is pending.
modtronix 1:71204b8406f2 1370 */
modtronix 1:71204b8406f2 1371 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1372 {
modtronix 1:71204b8406f2 1373 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
modtronix 1:71204b8406f2 1374 }
modtronix 1:71204b8406f2 1375
modtronix 1:71204b8406f2 1376
modtronix 1:71204b8406f2 1377 /** \brief Set Pending Interrupt
modtronix 1:71204b8406f2 1378
modtronix 1:71204b8406f2 1379 The function sets the pending bit of an external interrupt.
modtronix 1:71204b8406f2 1380
modtronix 1:71204b8406f2 1381 \param [in] IRQn Interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1382 */
modtronix 1:71204b8406f2 1383 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1384 {
modtronix 1:71204b8406f2 1385 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
modtronix 1:71204b8406f2 1386 }
modtronix 1:71204b8406f2 1387
modtronix 1:71204b8406f2 1388
modtronix 1:71204b8406f2 1389 /** \brief Clear Pending Interrupt
modtronix 1:71204b8406f2 1390
modtronix 1:71204b8406f2 1391 The function clears the pending bit of an external interrupt.
modtronix 1:71204b8406f2 1392
modtronix 1:71204b8406f2 1393 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1394 */
modtronix 1:71204b8406f2 1395 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1396 {
modtronix 1:71204b8406f2 1397 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
modtronix 1:71204b8406f2 1398 }
modtronix 1:71204b8406f2 1399
modtronix 1:71204b8406f2 1400
modtronix 1:71204b8406f2 1401 /** \brief Get Active Interrupt
modtronix 1:71204b8406f2 1402
modtronix 1:71204b8406f2 1403 The function reads the active register in NVIC and returns the active bit.
modtronix 1:71204b8406f2 1404
modtronix 1:71204b8406f2 1405 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1406
modtronix 1:71204b8406f2 1407 \return 0 Interrupt status is not active.
modtronix 1:71204b8406f2 1408 \return 1 Interrupt status is active.
modtronix 1:71204b8406f2 1409 */
modtronix 1:71204b8406f2 1410 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1411 {
modtronix 1:71204b8406f2 1412 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
modtronix 1:71204b8406f2 1413 }
modtronix 1:71204b8406f2 1414
modtronix 1:71204b8406f2 1415
modtronix 1:71204b8406f2 1416 /** \brief Set Interrupt Priority
modtronix 1:71204b8406f2 1417
modtronix 1:71204b8406f2 1418 The function sets the priority of an interrupt.
modtronix 1:71204b8406f2 1419
modtronix 1:71204b8406f2 1420 \note The priority cannot be set for every core interrupt.
modtronix 1:71204b8406f2 1421
modtronix 1:71204b8406f2 1422 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1423 \param [in] priority Priority to set.
modtronix 1:71204b8406f2 1424 */
modtronix 1:71204b8406f2 1425 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
modtronix 1:71204b8406f2 1426 {
modtronix 1:71204b8406f2 1427 if(IRQn < 0) {
modtronix 1:71204b8406f2 1428 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
modtronix 1:71204b8406f2 1429 else {
modtronix 1:71204b8406f2 1430 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
modtronix 1:71204b8406f2 1431 }
modtronix 1:71204b8406f2 1432
modtronix 1:71204b8406f2 1433
modtronix 1:71204b8406f2 1434 /** \brief Get Interrupt Priority
modtronix 1:71204b8406f2 1435
modtronix 1:71204b8406f2 1436 The function reads the priority of an interrupt. The interrupt
modtronix 1:71204b8406f2 1437 number can be positive to specify an external (device specific)
modtronix 1:71204b8406f2 1438 interrupt, or negative to specify an internal (core) interrupt.
modtronix 1:71204b8406f2 1439
modtronix 1:71204b8406f2 1440
modtronix 1:71204b8406f2 1441 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1442 \return Interrupt Priority. Value is aligned automatically to the implemented
modtronix 1:71204b8406f2 1443 priority bits of the microcontroller.
modtronix 1:71204b8406f2 1444 */
modtronix 1:71204b8406f2 1445 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1446 {
modtronix 1:71204b8406f2 1447
modtronix 1:71204b8406f2 1448 if(IRQn < 0) {
modtronix 1:71204b8406f2 1449 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
modtronix 1:71204b8406f2 1450 else {
modtronix 1:71204b8406f2 1451 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
modtronix 1:71204b8406f2 1452 }
modtronix 1:71204b8406f2 1453
modtronix 1:71204b8406f2 1454
modtronix 1:71204b8406f2 1455 /** \brief Encode Priority
modtronix 1:71204b8406f2 1456
modtronix 1:71204b8406f2 1457 The function encodes the priority for an interrupt with the given priority group,
modtronix 1:71204b8406f2 1458 preemptive priority value, and subpriority value.
modtronix 1:71204b8406f2 1459 In case of a conflict between priority grouping and available
modtronix 10:6444e6c798ce 1460 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
modtronix 1:71204b8406f2 1461
modtronix 1:71204b8406f2 1462 \param [in] PriorityGroup Used priority group.
modtronix 1:71204b8406f2 1463 \param [in] PreemptPriority Preemptive priority value (starting from 0).
modtronix 1:71204b8406f2 1464 \param [in] SubPriority Subpriority value (starting from 0).
modtronix 1:71204b8406f2 1465 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
modtronix 1:71204b8406f2 1466 */
modtronix 1:71204b8406f2 1467 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
modtronix 1:71204b8406f2 1468 {
modtronix 1:71204b8406f2 1469 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1470 uint32_t PreemptPriorityBits;
modtronix 1:71204b8406f2 1471 uint32_t SubPriorityBits;
modtronix 1:71204b8406f2 1472
modtronix 1:71204b8406f2 1473 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
modtronix 1:71204b8406f2 1474 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
modtronix 1:71204b8406f2 1475
modtronix 1:71204b8406f2 1476 return (
modtronix 1:71204b8406f2 1477 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
modtronix 1:71204b8406f2 1478 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
modtronix 1:71204b8406f2 1479 );
modtronix 1:71204b8406f2 1480 }
modtronix 1:71204b8406f2 1481
modtronix 1:71204b8406f2 1482
modtronix 1:71204b8406f2 1483 /** \brief Decode Priority
modtronix 1:71204b8406f2 1484
modtronix 1:71204b8406f2 1485 The function decodes an interrupt priority value with a given priority group to
modtronix 1:71204b8406f2 1486 preemptive priority value and subpriority value.
modtronix 1:71204b8406f2 1487 In case of a conflict between priority grouping and available
modtronix 10:6444e6c798ce 1488 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
modtronix 1:71204b8406f2 1489
modtronix 1:71204b8406f2 1490 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
modtronix 1:71204b8406f2 1491 \param [in] PriorityGroup Used priority group.
modtronix 1:71204b8406f2 1492 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
modtronix 1:71204b8406f2 1493 \param [out] pSubPriority Subpriority value (starting from 0).
modtronix 1:71204b8406f2 1494 */
modtronix 1:71204b8406f2 1495 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
modtronix 1:71204b8406f2 1496 {
modtronix 1:71204b8406f2 1497 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1498 uint32_t PreemptPriorityBits;
modtronix 1:71204b8406f2 1499 uint32_t SubPriorityBits;
modtronix 1:71204b8406f2 1500
modtronix 1:71204b8406f2 1501 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
modtronix 1:71204b8406f2 1502 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
modtronix 1:71204b8406f2 1503
modtronix 1:71204b8406f2 1504 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
modtronix 1:71204b8406f2 1505 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
modtronix 1:71204b8406f2 1506 }
modtronix 1:71204b8406f2 1507
modtronix 1:71204b8406f2 1508
modtronix 1:71204b8406f2 1509 /** \brief System Reset
modtronix 1:71204b8406f2 1510
modtronix 1:71204b8406f2 1511 The function initiates a system reset request to reset the MCU.
modtronix 1:71204b8406f2 1512 */
modtronix 1:71204b8406f2 1513 __STATIC_INLINE void NVIC_SystemReset(void)
modtronix 1:71204b8406f2 1514 {
modtronix 1:71204b8406f2 1515 __DSB(); /* Ensure all outstanding memory accesses included
modtronix 1:71204b8406f2 1516 buffered write are completed before reset */
modtronix 1:71204b8406f2 1517 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 1:71204b8406f2 1518 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
modtronix 1:71204b8406f2 1519 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
modtronix 1:71204b8406f2 1520 __DSB(); /* Ensure completion of memory access */
modtronix 1:71204b8406f2 1521 while(1); /* wait until reset */
modtronix 1:71204b8406f2 1522 }
modtronix 1:71204b8406f2 1523
modtronix 1:71204b8406f2 1524 /*@} end of CMSIS_Core_NVICFunctions */
modtronix 1:71204b8406f2 1525
modtronix 1:71204b8406f2 1526
modtronix 1:71204b8406f2 1527
modtronix 1:71204b8406f2 1528 /* ################################## SysTick function ############################################ */
modtronix 1:71204b8406f2 1529 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 1530 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
modtronix 1:71204b8406f2 1531 \brief Functions that configure the System.
modtronix 1:71204b8406f2 1532 @{
modtronix 1:71204b8406f2 1533 */
modtronix 1:71204b8406f2 1534
modtronix 1:71204b8406f2 1535 #if (__Vendor_SysTickConfig == 0)
modtronix 1:71204b8406f2 1536
modtronix 1:71204b8406f2 1537 /** \brief System Tick Configuration
modtronix 1:71204b8406f2 1538
modtronix 1:71204b8406f2 1539 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
modtronix 1:71204b8406f2 1540 Counter is in free running mode to generate periodic interrupts.
modtronix 1:71204b8406f2 1541
modtronix 1:71204b8406f2 1542 \param [in] ticks Number of ticks between two interrupts.
modtronix 1:71204b8406f2 1543
modtronix 1:71204b8406f2 1544 \return 0 Function succeeded.
modtronix 1:71204b8406f2 1545 \return 1 Function failed.
modtronix 1:71204b8406f2 1546
modtronix 1:71204b8406f2 1547 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
modtronix 1:71204b8406f2 1548 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
modtronix 1:71204b8406f2 1549 must contain a vendor-specific implementation of this function.
modtronix 1:71204b8406f2 1550
modtronix 1:71204b8406f2 1551 */
modtronix 1:71204b8406f2 1552 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
modtronix 1:71204b8406f2 1553 {
modtronix 1:71204b8406f2 1554 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
modtronix 1:71204b8406f2 1555
modtronix 1:71204b8406f2 1556 SysTick->LOAD = ticks - 1; /* set reload register */
modtronix 1:71204b8406f2 1557 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
modtronix 1:71204b8406f2 1558 SysTick->VAL = 0; /* Load the SysTick Counter Value */
modtronix 1:71204b8406f2 1559 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
modtronix 1:71204b8406f2 1560 SysTick_CTRL_TICKINT_Msk |
modtronix 1:71204b8406f2 1561 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
modtronix 1:71204b8406f2 1562 return (0); /* Function successful */
modtronix 1:71204b8406f2 1563 }
modtronix 1:71204b8406f2 1564
modtronix 1:71204b8406f2 1565 #endif
modtronix 1:71204b8406f2 1566
modtronix 1:71204b8406f2 1567 /*@} end of CMSIS_Core_SysTickFunctions */
modtronix 1:71204b8406f2 1568
modtronix 1:71204b8406f2 1569
modtronix 1:71204b8406f2 1570
modtronix 1:71204b8406f2 1571 /* ##################################### Debug In/Output function ########################################### */
modtronix 1:71204b8406f2 1572 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 1573 \defgroup CMSIS_core_DebugFunctions ITM Functions
modtronix 1:71204b8406f2 1574 \brief Functions that access the ITM debug interface.
modtronix 1:71204b8406f2 1575 @{
modtronix 1:71204b8406f2 1576 */
modtronix 1:71204b8406f2 1577
modtronix 1:71204b8406f2 1578 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
modtronix 1:71204b8406f2 1579 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
modtronix 1:71204b8406f2 1580
modtronix 1:71204b8406f2 1581
modtronix 1:71204b8406f2 1582 /** \brief ITM Send Character
modtronix 1:71204b8406f2 1583
modtronix 1:71204b8406f2 1584 The function transmits a character via the ITM channel 0, and
modtronix 1:71204b8406f2 1585 \li Just returns when no debugger is connected that has booked the output.
modtronix 1:71204b8406f2 1586 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
modtronix 1:71204b8406f2 1587
modtronix 1:71204b8406f2 1588 \param [in] ch Character to transmit.
modtronix 1:71204b8406f2 1589
modtronix 1:71204b8406f2 1590 \returns Character to transmit.
modtronix 1:71204b8406f2 1591 */
modtronix 1:71204b8406f2 1592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
modtronix 1:71204b8406f2 1593 {
modtronix 1:71204b8406f2 1594 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
modtronix 1:71204b8406f2 1595 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
modtronix 1:71204b8406f2 1596 {
modtronix 1:71204b8406f2 1597 while (ITM->PORT[0].u32 == 0);
modtronix 1:71204b8406f2 1598 ITM->PORT[0].u8 = (uint8_t) ch;
modtronix 1:71204b8406f2 1599 }
modtronix 1:71204b8406f2 1600 return (ch);
modtronix 1:71204b8406f2 1601 }
modtronix 1:71204b8406f2 1602
modtronix 1:71204b8406f2 1603
modtronix 1:71204b8406f2 1604 /** \brief ITM Receive Character
modtronix 1:71204b8406f2 1605
modtronix 1:71204b8406f2 1606 The function inputs a character via the external variable \ref ITM_RxBuffer.
modtronix 1:71204b8406f2 1607
modtronix 1:71204b8406f2 1608 \return Received character.
modtronix 1:71204b8406f2 1609 \return -1 No character pending.
modtronix 1:71204b8406f2 1610 */
modtronix 1:71204b8406f2 1611 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
modtronix 1:71204b8406f2 1612 int32_t ch = -1; /* no character available */
modtronix 1:71204b8406f2 1613
modtronix 1:71204b8406f2 1614 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
modtronix 1:71204b8406f2 1615 ch = ITM_RxBuffer;
modtronix 1:71204b8406f2 1616 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
modtronix 1:71204b8406f2 1617 }
modtronix 1:71204b8406f2 1618
modtronix 1:71204b8406f2 1619 return (ch);
modtronix 1:71204b8406f2 1620 }
modtronix 1:71204b8406f2 1621
modtronix 1:71204b8406f2 1622
modtronix 1:71204b8406f2 1623 /** \brief ITM Check Character
modtronix 1:71204b8406f2 1624
modtronix 1:71204b8406f2 1625 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
modtronix 1:71204b8406f2 1626
modtronix 1:71204b8406f2 1627 \return 0 No character available.
modtronix 1:71204b8406f2 1628 \return 1 Character available.
modtronix 1:71204b8406f2 1629 */
modtronix 1:71204b8406f2 1630 __STATIC_INLINE int32_t ITM_CheckChar (void) {
modtronix 1:71204b8406f2 1631
modtronix 1:71204b8406f2 1632 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
modtronix 1:71204b8406f2 1633 return (0); /* no character available */
modtronix 1:71204b8406f2 1634 } else {
modtronix 1:71204b8406f2 1635 return (1); /* character available */
modtronix 1:71204b8406f2 1636 }
modtronix 1:71204b8406f2 1637 }
modtronix 1:71204b8406f2 1638
modtronix 1:71204b8406f2 1639 /*@} end of CMSIS_core_DebugFunctions */
modtronix 1:71204b8406f2 1640
modtronix 1:71204b8406f2 1641
modtronix 10:6444e6c798ce 1642
modtronix 1:71204b8406f2 1643
modtronix 1:71204b8406f2 1644 #ifdef __cplusplus
modtronix 1:71204b8406f2 1645 }
modtronix 1:71204b8406f2 1646 #endif
modtronix 10:6444e6c798ce 1647
modtronix 10:6444e6c798ce 1648 #endif /* __CORE_CM3_H_DEPENDANT */
modtronix 10:6444e6c798ce 1649
modtronix 10:6444e6c798ce 1650 #endif /* __CMSIS_GENERIC */