modtronix H / mbed_nz32sc151

mbed library for NZ32-SC151

targets/cmsis/core_sc000.h@17:639ed60ce759, 2016-08-19 (annotated)

Committer:
modtronix-com
Date:
Fri Aug 19 15:46:42 2016 +1000
Revision:
17:639ed60ce759
Parent:
10:6444e6c798ce 
Added tag v1.1 for changeset 076cbe3e55be

Who changed what in which revision?

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modtronix 10:6444e6c798ce 1 /**************************************************************************//**
modtronix 10:6444e6c798ce 2 * @file core_sc000.h
modtronix 10:6444e6c798ce 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
modtronix 10:6444e6c798ce 4 * @version V4.00
modtronix 10:6444e6c798ce 5 * @date 22. August 2014
modtronix 10:6444e6c798ce 6 *
modtronix 10:6444e6c798ce 7 * @note
modtronix 10:6444e6c798ce 8 *
modtronix 10:6444e6c798ce 9 ******************************************************************************/
modtronix 10:6444e6c798ce 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
modtronix 10:6444e6c798ce 11
modtronix 10:6444e6c798ce 12 All rights reserved.
modtronix 10:6444e6c798ce 13 Redistribution and use in source and binary forms, with or without
modtronix 10:6444e6c798ce 14 modification, are permitted provided that the following conditions are met:
modtronix 10:6444e6c798ce 15 - Redistributions of source code must retain the above copyright
modtronix 10:6444e6c798ce 16 notice, this list of conditions and the following disclaimer.
modtronix 10:6444e6c798ce 17 - Redistributions in binary form must reproduce the above copyright
modtronix 10:6444e6c798ce 18 notice, this list of conditions and the following disclaimer in the
modtronix 10:6444e6c798ce 19 documentation and/or other materials provided with the distribution.
modtronix 10:6444e6c798ce 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 10:6444e6c798ce 21 to endorse or promote products derived from this software without
modtronix 10:6444e6c798ce 22 specific prior written permission.
modtronix 10:6444e6c798ce 23 *
modtronix 10:6444e6c798ce 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 10:6444e6c798ce 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 10:6444e6c798ce 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 10:6444e6c798ce 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 10:6444e6c798ce 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 10:6444e6c798ce 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 10:6444e6c798ce 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 10:6444e6c798ce 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 10:6444e6c798ce 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 10:6444e6c798ce 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 10:6444e6c798ce 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 10:6444e6c798ce 35 ---------------------------------------------------------------------------*/
modtronix 10:6444e6c798ce 36
modtronix 10:6444e6c798ce 37
modtronix 10:6444e6c798ce 38 #if defined ( __ICCARM__ )
modtronix 10:6444e6c798ce 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 10:6444e6c798ce 40 #endif
modtronix 10:6444e6c798ce 41
modtronix 10:6444e6c798ce 42 #ifndef __CORE_SC000_H_GENERIC
modtronix 10:6444e6c798ce 43 #define __CORE_SC000_H_GENERIC
modtronix 10:6444e6c798ce 44
modtronix 10:6444e6c798ce 45 #ifdef __cplusplus
modtronix 10:6444e6c798ce 46 extern "C" {
modtronix 10:6444e6c798ce 47 #endif
modtronix 10:6444e6c798ce 48
modtronix 10:6444e6c798ce 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
modtronix 10:6444e6c798ce 50 CMSIS violates the following MISRA-C:2004 rules:
modtronix 10:6444e6c798ce 51
modtronix 10:6444e6c798ce 52 \li Required Rule 8.5, object/function definition in header file.<br>
modtronix 10:6444e6c798ce 53 Function definitions in header files are used to allow 'inlining'.
modtronix 10:6444e6c798ce 54
modtronix 10:6444e6c798ce 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
modtronix 10:6444e6c798ce 56 Unions are used for effective representation of core registers.
modtronix 10:6444e6c798ce 57
modtronix 10:6444e6c798ce 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
modtronix 10:6444e6c798ce 59 Function-like macros are used to allow more efficient code.
modtronix 10:6444e6c798ce 60 */
modtronix 10:6444e6c798ce 61
modtronix 10:6444e6c798ce 62
modtronix 10:6444e6c798ce 63 /*******************************************************************************
modtronix 10:6444e6c798ce 64 * CMSIS definitions
modtronix 10:6444e6c798ce 65 ******************************************************************************/
modtronix 10:6444e6c798ce 66 /** \ingroup SC000
modtronix 10:6444e6c798ce 67 @{
modtronix 10:6444e6c798ce 68 */
modtronix 10:6444e6c798ce 69
modtronix 10:6444e6c798ce 70 /* CMSIS SC000 definitions */
modtronix 10:6444e6c798ce 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
modtronix 10:6444e6c798ce 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
modtronix 10:6444e6c798ce 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
modtronix 10:6444e6c798ce 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
modtronix 10:6444e6c798ce 75
modtronix 10:6444e6c798ce 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
modtronix 10:6444e6c798ce 77
modtronix 10:6444e6c798ce 78
modtronix 10:6444e6c798ce 79 #if defined ( __CC_ARM )
modtronix 10:6444e6c798ce 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
modtronix 10:6444e6c798ce 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
modtronix 10:6444e6c798ce 82 #define __STATIC_INLINE static __inline
modtronix 10:6444e6c798ce 83
modtronix 10:6444e6c798ce 84 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
modtronix 10:6444e6c798ce 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
modtronix 10:6444e6c798ce 87 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 88
modtronix 10:6444e6c798ce 89 #elif defined ( __ICCARM__ )
modtronix 10:6444e6c798ce 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
modtronix 10:6444e6c798ce 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
modtronix 10:6444e6c798ce 92 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 93
modtronix 10:6444e6c798ce 94 #elif defined ( __TMS470__ )
modtronix 10:6444e6c798ce 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
modtronix 10:6444e6c798ce 96 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 97
modtronix 10:6444e6c798ce 98 #elif defined ( __TASKING__ )
modtronix 10:6444e6c798ce 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
modtronix 10:6444e6c798ce 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
modtronix 10:6444e6c798ce 101 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 102
modtronix 10:6444e6c798ce 103 #elif defined ( __CSMC__ )
modtronix 10:6444e6c798ce 104 #define __packed
modtronix 10:6444e6c798ce 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 107 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 108
modtronix 10:6444e6c798ce 109 #endif
modtronix 10:6444e6c798ce 110
modtronix 10:6444e6c798ce 111 /** __FPU_USED indicates whether an FPU is used or not.
modtronix 10:6444e6c798ce 112 This core does not support an FPU at all
modtronix 10:6444e6c798ce 113 */
modtronix 10:6444e6c798ce 114 #define __FPU_USED 0
modtronix 10:6444e6c798ce 115
modtronix 10:6444e6c798ce 116 #if defined ( __CC_ARM )
modtronix 10:6444e6c798ce 117 #if defined __TARGET_FPU_VFP
modtronix 10:6444e6c798ce 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 119 #endif
modtronix 10:6444e6c798ce 120
modtronix 10:6444e6c798ce 121 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
modtronix 10:6444e6c798ce 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 124 #endif
modtronix 10:6444e6c798ce 125
modtronix 10:6444e6c798ce 126 #elif defined ( __ICCARM__ )
modtronix 10:6444e6c798ce 127 #if defined __ARMVFP__
modtronix 10:6444e6c798ce 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 129 #endif
modtronix 10:6444e6c798ce 130
modtronix 10:6444e6c798ce 131 #elif defined ( __TMS470__ )
modtronix 10:6444e6c798ce 132 #if defined __TI__VFP_SUPPORT____
modtronix 10:6444e6c798ce 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 134 #endif
modtronix 10:6444e6c798ce 135
modtronix 10:6444e6c798ce 136 #elif defined ( __TASKING__ )
modtronix 10:6444e6c798ce 137 #if defined __FPU_VFP__
modtronix 10:6444e6c798ce 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 139 #endif
modtronix 10:6444e6c798ce 140
modtronix 10:6444e6c798ce 141 #elif defined ( __CSMC__ ) /* Cosmic */
modtronix 10:6444e6c798ce 142 #if ( __CSMC__ & 0x400) // FPU present for parser
modtronix 10:6444e6c798ce 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 144 #endif
modtronix 10:6444e6c798ce 145 #endif
modtronix 10:6444e6c798ce 146
modtronix 10:6444e6c798ce 147 #include <stdint.h> /* standard types definitions */
modtronix 10:6444e6c798ce 148 #include <core_cmInstr.h> /* Core Instruction Access */
modtronix 10:6444e6c798ce 149 #include <core_cmFunc.h> /* Core Function Access */
modtronix 10:6444e6c798ce 150
modtronix 10:6444e6c798ce 151 #ifdef __cplusplus
modtronix 10:6444e6c798ce 152 }
modtronix 10:6444e6c798ce 153 #endif
modtronix 10:6444e6c798ce 154
modtronix 10:6444e6c798ce 155 #endif /* __CORE_SC000_H_GENERIC */
modtronix 10:6444e6c798ce 156
modtronix 10:6444e6c798ce 157 #ifndef __CMSIS_GENERIC
modtronix 10:6444e6c798ce 158
modtronix 10:6444e6c798ce 159 #ifndef __CORE_SC000_H_DEPENDANT
modtronix 10:6444e6c798ce 160 #define __CORE_SC000_H_DEPENDANT
modtronix 10:6444e6c798ce 161
modtronix 10:6444e6c798ce 162 #ifdef __cplusplus
modtronix 10:6444e6c798ce 163 extern "C" {
modtronix 10:6444e6c798ce 164 #endif
modtronix 10:6444e6c798ce 165
modtronix 10:6444e6c798ce 166 /* check device defines and use defaults */
modtronix 10:6444e6c798ce 167 #if defined __CHECK_DEVICE_DEFINES
modtronix 10:6444e6c798ce 168 #ifndef __SC000_REV
modtronix 10:6444e6c798ce 169 #define __SC000_REV 0x0000
modtronix 10:6444e6c798ce 170 #warning "__SC000_REV not defined in device header file; using default!"
modtronix 10:6444e6c798ce 171 #endif
modtronix 10:6444e6c798ce 172
modtronix 10:6444e6c798ce 173 #ifndef __MPU_PRESENT
modtronix 10:6444e6c798ce 174 #define __MPU_PRESENT 0
modtronix 10:6444e6c798ce 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
modtronix 10:6444e6c798ce 176 #endif
modtronix 10:6444e6c798ce 177
modtronix 10:6444e6c798ce 178 #ifndef __NVIC_PRIO_BITS
modtronix 10:6444e6c798ce 179 #define __NVIC_PRIO_BITS 2
modtronix 10:6444e6c798ce 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
modtronix 10:6444e6c798ce 181 #endif
modtronix 10:6444e6c798ce 182
modtronix 10:6444e6c798ce 183 #ifndef __Vendor_SysTickConfig
modtronix 10:6444e6c798ce 184 #define __Vendor_SysTickConfig 0
modtronix 10:6444e6c798ce 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
modtronix 10:6444e6c798ce 186 #endif
modtronix 10:6444e6c798ce 187 #endif
modtronix 10:6444e6c798ce 188
modtronix 10:6444e6c798ce 189 /* IO definitions (access restrictions to peripheral registers) */
modtronix 10:6444e6c798ce 190 /**
modtronix 10:6444e6c798ce 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
modtronix 10:6444e6c798ce 192
modtronix 10:6444e6c798ce 193 <strong>IO Type Qualifiers</strong> are used
modtronix 10:6444e6c798ce 194 \li to specify the access to peripheral variables.
modtronix 10:6444e6c798ce 195 \li for automatic generation of peripheral register debug information.
modtronix 10:6444e6c798ce 196 */
modtronix 10:6444e6c798ce 197 #ifdef __cplusplus
modtronix 10:6444e6c798ce 198 #define __I volatile /*!< Defines 'read only' permissions */
modtronix 10:6444e6c798ce 199 #else
modtronix 10:6444e6c798ce 200 #define __I volatile const /*!< Defines 'read only' permissions */
modtronix 10:6444e6c798ce 201 #endif
modtronix 10:6444e6c798ce 202 #define __O volatile /*!< Defines 'write only' permissions */
modtronix 10:6444e6c798ce 203 #define __IO volatile /*!< Defines 'read / write' permissions */
modtronix 10:6444e6c798ce 204
modtronix 10:6444e6c798ce 205 /*@} end of group SC000 */
modtronix 10:6444e6c798ce 206
modtronix 10:6444e6c798ce 207
modtronix 10:6444e6c798ce 208
modtronix 10:6444e6c798ce 209 /*******************************************************************************
modtronix 10:6444e6c798ce 210 * Register Abstraction
modtronix 10:6444e6c798ce 211 Core Register contain:
modtronix 10:6444e6c798ce 212 - Core Register
modtronix 10:6444e6c798ce 213 - Core NVIC Register
modtronix 10:6444e6c798ce 214 - Core SCB Register
modtronix 10:6444e6c798ce 215 - Core SysTick Register
modtronix 10:6444e6c798ce 216 - Core MPU Register
modtronix 10:6444e6c798ce 217 ******************************************************************************/
modtronix 10:6444e6c798ce 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
modtronix 10:6444e6c798ce 219 \brief Type definitions and defines for Cortex-M processor based devices.
modtronix 10:6444e6c798ce 220 */
modtronix 10:6444e6c798ce 221
modtronix 10:6444e6c798ce 222 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 223 \defgroup CMSIS_CORE Status and Control Registers
modtronix 10:6444e6c798ce 224 \brief Core Register type definitions.
modtronix 10:6444e6c798ce 225 @{
modtronix 10:6444e6c798ce 226 */
modtronix 10:6444e6c798ce 227
modtronix 10:6444e6c798ce 228 /** \brief Union type to access the Application Program Status Register (APSR).
modtronix 10:6444e6c798ce 229 */
modtronix 10:6444e6c798ce 230 typedef union
modtronix 10:6444e6c798ce 231 {
modtronix 10:6444e6c798ce 232 struct
modtronix 10:6444e6c798ce 233 {
modtronix 10:6444e6c798ce 234 #if (__CORTEX_M != 0x04)
modtronix 10:6444e6c798ce 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
modtronix 10:6444e6c798ce 236 #else
modtronix 10:6444e6c798ce 237 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
modtronix 10:6444e6c798ce 238 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 10:6444e6c798ce 239 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
modtronix 10:6444e6c798ce 240 #endif
modtronix 10:6444e6c798ce 241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 10:6444e6c798ce 242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 10:6444e6c798ce 243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 10:6444e6c798ce 244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 10:6444e6c798ce 245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 10:6444e6c798ce 246 } b; /*!< Structure used for bit access */
modtronix 10:6444e6c798ce 247 uint32_t w; /*!< Type used for word access */
modtronix 10:6444e6c798ce 248 } APSR_Type;
modtronix 10:6444e6c798ce 249
modtronix 10:6444e6c798ce 250
modtronix 10:6444e6c798ce 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
modtronix 10:6444e6c798ce 252 */
modtronix 10:6444e6c798ce 253 typedef union
modtronix 10:6444e6c798ce 254 {
modtronix 10:6444e6c798ce 255 struct
modtronix 10:6444e6c798ce 256 {
modtronix 10:6444e6c798ce 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 10:6444e6c798ce 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
modtronix 10:6444e6c798ce 259 } b; /*!< Structure used for bit access */
modtronix 10:6444e6c798ce 260 uint32_t w; /*!< Type used for word access */
modtronix 10:6444e6c798ce 261 } IPSR_Type;
modtronix 10:6444e6c798ce 262
modtronix 10:6444e6c798ce 263
modtronix 10:6444e6c798ce 264 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
modtronix 10:6444e6c798ce 265 */
modtronix 10:6444e6c798ce 266 typedef union
modtronix 10:6444e6c798ce 267 {
modtronix 10:6444e6c798ce 268 struct
modtronix 10:6444e6c798ce 269 {
modtronix 10:6444e6c798ce 270 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 10:6444e6c798ce 271 #if (__CORTEX_M != 0x04)
modtronix 10:6444e6c798ce 272 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
modtronix 10:6444e6c798ce 273 #else
modtronix 10:6444e6c798ce 274 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
modtronix 10:6444e6c798ce 275 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 10:6444e6c798ce 276 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
modtronix 10:6444e6c798ce 277 #endif
modtronix 10:6444e6c798ce 278 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
modtronix 10:6444e6c798ce 279 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
modtronix 10:6444e6c798ce 280 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 10:6444e6c798ce 281 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 10:6444e6c798ce 282 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 10:6444e6c798ce 283 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 10:6444e6c798ce 284 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 10:6444e6c798ce 285 } b; /*!< Structure used for bit access */
modtronix 10:6444e6c798ce 286 uint32_t w; /*!< Type used for word access */
modtronix 10:6444e6c798ce 287 } xPSR_Type;
modtronix 10:6444e6c798ce 288
modtronix 10:6444e6c798ce 289
modtronix 10:6444e6c798ce 290 /** \brief Union type to access the Control Registers (CONTROL).
modtronix 10:6444e6c798ce 291 */
modtronix 10:6444e6c798ce 292 typedef union
modtronix 10:6444e6c798ce 293 {
modtronix 10:6444e6c798ce 294 struct
modtronix 10:6444e6c798ce 295 {
modtronix 10:6444e6c798ce 296 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
modtronix 10:6444e6c798ce 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
modtronix 10:6444e6c798ce 298 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
modtronix 10:6444e6c798ce 299 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
modtronix 10:6444e6c798ce 300 } b; /*!< Structure used for bit access */
modtronix 10:6444e6c798ce 301 uint32_t w; /*!< Type used for word access */
modtronix 10:6444e6c798ce 302 } CONTROL_Type;
modtronix 10:6444e6c798ce 303
modtronix 10:6444e6c798ce 304 /*@} end of group CMSIS_CORE */
modtronix 10:6444e6c798ce 305
modtronix 10:6444e6c798ce 306
modtronix 10:6444e6c798ce 307 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 308 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
modtronix 10:6444e6c798ce 309 \brief Type definitions for the NVIC Registers
modtronix 10:6444e6c798ce 310 @{
modtronix 10:6444e6c798ce 311 */
modtronix 10:6444e6c798ce 312
modtronix 10:6444e6c798ce 313 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
modtronix 10:6444e6c798ce 314 */
modtronix 10:6444e6c798ce 315 typedef struct
modtronix 10:6444e6c798ce 316 {
modtronix 10:6444e6c798ce 317 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
modtronix 10:6444e6c798ce 318 uint32_t RESERVED0[31];
modtronix 10:6444e6c798ce 319 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
modtronix 10:6444e6c798ce 320 uint32_t RSERVED1[31];
modtronix 10:6444e6c798ce 321 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
modtronix 10:6444e6c798ce 322 uint32_t RESERVED2[31];
modtronix 10:6444e6c798ce 323 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
modtronix 10:6444e6c798ce 324 uint32_t RESERVED3[31];
modtronix 10:6444e6c798ce 325 uint32_t RESERVED4[64];
modtronix 10:6444e6c798ce 326 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
modtronix 10:6444e6c798ce 327 } NVIC_Type;
modtronix 10:6444e6c798ce 328
modtronix 10:6444e6c798ce 329 /*@} end of group CMSIS_NVIC */
modtronix 10:6444e6c798ce 330
modtronix 10:6444e6c798ce 331
modtronix 10:6444e6c798ce 332 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 333 \defgroup CMSIS_SCB System Control Block (SCB)
modtronix 10:6444e6c798ce 334 \brief Type definitions for the System Control Block Registers
modtronix 10:6444e6c798ce 335 @{
modtronix 10:6444e6c798ce 336 */
modtronix 10:6444e6c798ce 337
modtronix 10:6444e6c798ce 338 /** \brief Structure type to access the System Control Block (SCB).
modtronix 10:6444e6c798ce 339 */
modtronix 10:6444e6c798ce 340 typedef struct
modtronix 10:6444e6c798ce 341 {
modtronix 10:6444e6c798ce 342 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
modtronix 10:6444e6c798ce 343 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
modtronix 10:6444e6c798ce 344 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
modtronix 10:6444e6c798ce 345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
modtronix 10:6444e6c798ce 346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
modtronix 10:6444e6c798ce 347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
modtronix 10:6444e6c798ce 348 uint32_t RESERVED0[1];
modtronix 10:6444e6c798ce 349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
modtronix 10:6444e6c798ce 350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
modtronix 10:6444e6c798ce 351 uint32_t RESERVED1[154];
modtronix 10:6444e6c798ce 352 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
modtronix 10:6444e6c798ce 353 } SCB_Type;
modtronix 10:6444e6c798ce 354
modtronix 10:6444e6c798ce 355 /* SCB CPUID Register Definitions */
modtronix 10:6444e6c798ce 356 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
modtronix 10:6444e6c798ce 357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
modtronix 10:6444e6c798ce 358
modtronix 10:6444e6c798ce 359 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
modtronix 10:6444e6c798ce 360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
modtronix 10:6444e6c798ce 361
modtronix 10:6444e6c798ce 362 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
modtronix 10:6444e6c798ce 363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
modtronix 10:6444e6c798ce 364
modtronix 10:6444e6c798ce 365 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
modtronix 10:6444e6c798ce 366 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
modtronix 10:6444e6c798ce 367
modtronix 10:6444e6c798ce 368 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
modtronix 10:6444e6c798ce 369 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
modtronix 10:6444e6c798ce 370
modtronix 10:6444e6c798ce 371 /* SCB Interrupt Control State Register Definitions */
modtronix 10:6444e6c798ce 372 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
modtronix 10:6444e6c798ce 373 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
modtronix 10:6444e6c798ce 374
modtronix 10:6444e6c798ce 375 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
modtronix 10:6444e6c798ce 376 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
modtronix 10:6444e6c798ce 377
modtronix 10:6444e6c798ce 378 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
modtronix 10:6444e6c798ce 379 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
modtronix 10:6444e6c798ce 380
modtronix 10:6444e6c798ce 381 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
modtronix 10:6444e6c798ce 382 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
modtronix 10:6444e6c798ce 383
modtronix 10:6444e6c798ce 384 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
modtronix 10:6444e6c798ce 385 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
modtronix 10:6444e6c798ce 386
modtronix 10:6444e6c798ce 387 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
modtronix 10:6444e6c798ce 388 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
modtronix 10:6444e6c798ce 389
modtronix 10:6444e6c798ce 390 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
modtronix 10:6444e6c798ce 391 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
modtronix 10:6444e6c798ce 392
modtronix 10:6444e6c798ce 393 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
modtronix 10:6444e6c798ce 394 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
modtronix 10:6444e6c798ce 395
modtronix 10:6444e6c798ce 396 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
modtronix 10:6444e6c798ce 397 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
modtronix 10:6444e6c798ce 398
modtronix 10:6444e6c798ce 399 /* SCB Interrupt Control State Register Definitions */
modtronix 10:6444e6c798ce 400 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
modtronix 10:6444e6c798ce 401 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 10:6444e6c798ce 402
modtronix 10:6444e6c798ce 403 /* SCB Application Interrupt and Reset Control Register Definitions */
modtronix 10:6444e6c798ce 404 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
modtronix 10:6444e6c798ce 405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
modtronix 10:6444e6c798ce 406
modtronix 10:6444e6c798ce 407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
modtronix 10:6444e6c798ce 408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
modtronix 10:6444e6c798ce 409
modtronix 10:6444e6c798ce 410 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
modtronix 10:6444e6c798ce 411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
modtronix 10:6444e6c798ce 412
modtronix 10:6444e6c798ce 413 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
modtronix 10:6444e6c798ce 414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
modtronix 10:6444e6c798ce 415
modtronix 10:6444e6c798ce 416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
modtronix 10:6444e6c798ce 417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
modtronix 10:6444e6c798ce 418
modtronix 10:6444e6c798ce 419 /* SCB System Control Register Definitions */
modtronix 10:6444e6c798ce 420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
modtronix 10:6444e6c798ce 421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
modtronix 10:6444e6c798ce 422
modtronix 10:6444e6c798ce 423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
modtronix 10:6444e6c798ce 424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
modtronix 10:6444e6c798ce 425
modtronix 10:6444e6c798ce 426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
modtronix 10:6444e6c798ce 427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
modtronix 10:6444e6c798ce 428
modtronix 10:6444e6c798ce 429 /* SCB Configuration Control Register Definitions */
modtronix 10:6444e6c798ce 430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
modtronix 10:6444e6c798ce 431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
modtronix 10:6444e6c798ce 432
modtronix 10:6444e6c798ce 433 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
modtronix 10:6444e6c798ce 434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
modtronix 10:6444e6c798ce 435
modtronix 10:6444e6c798ce 436 /* SCB System Handler Control and State Register Definitions */
modtronix 10:6444e6c798ce 437 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
modtronix 10:6444e6c798ce 438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
modtronix 10:6444e6c798ce 439
modtronix 10:6444e6c798ce 440 /* SCB Security Features Register Definitions */
modtronix 10:6444e6c798ce 441 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
modtronix 10:6444e6c798ce 442 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
modtronix 10:6444e6c798ce 443
modtronix 10:6444e6c798ce 444 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
modtronix 10:6444e6c798ce 445 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
modtronix 10:6444e6c798ce 446
modtronix 10:6444e6c798ce 447 /*@} end of group CMSIS_SCB */
modtronix 10:6444e6c798ce 448
modtronix 10:6444e6c798ce 449
modtronix 10:6444e6c798ce 450 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 451 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
modtronix 10:6444e6c798ce 452 \brief Type definitions for the System Control and ID Register not in the SCB
modtronix 10:6444e6c798ce 453 @{
modtronix 10:6444e6c798ce 454 */
modtronix 10:6444e6c798ce 455
modtronix 10:6444e6c798ce 456 /** \brief Structure type to access the System Control and ID Register not in the SCB.
modtronix 10:6444e6c798ce 457 */
modtronix 10:6444e6c798ce 458 typedef struct
modtronix 10:6444e6c798ce 459 {
modtronix 10:6444e6c798ce 460 uint32_t RESERVED0[2];
modtronix 10:6444e6c798ce 461 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
modtronix 10:6444e6c798ce 462 } SCnSCB_Type;
modtronix 10:6444e6c798ce 463
modtronix 10:6444e6c798ce 464 /* Auxiliary Control Register Definitions */
modtronix 10:6444e6c798ce 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
modtronix 10:6444e6c798ce 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
modtronix 10:6444e6c798ce 467
modtronix 10:6444e6c798ce 468 /*@} end of group CMSIS_SCnotSCB */
modtronix 10:6444e6c798ce 469
modtronix 10:6444e6c798ce 470
modtronix 10:6444e6c798ce 471 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 472 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
modtronix 10:6444e6c798ce 473 \brief Type definitions for the System Timer Registers.
modtronix 10:6444e6c798ce 474 @{
modtronix 10:6444e6c798ce 475 */
modtronix 10:6444e6c798ce 476
modtronix 10:6444e6c798ce 477 /** \brief Structure type to access the System Timer (SysTick).
modtronix 10:6444e6c798ce 478 */
modtronix 10:6444e6c798ce 479 typedef struct
modtronix 10:6444e6c798ce 480 {
modtronix 10:6444e6c798ce 481 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
modtronix 10:6444e6c798ce 482 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
modtronix 10:6444e6c798ce 483 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
modtronix 10:6444e6c798ce 484 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
modtronix 10:6444e6c798ce 485 } SysTick_Type;
modtronix 10:6444e6c798ce 486
modtronix 10:6444e6c798ce 487 /* SysTick Control / Status Register Definitions */
modtronix 10:6444e6c798ce 488 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
modtronix 10:6444e6c798ce 489 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
modtronix 10:6444e6c798ce 490
modtronix 10:6444e6c798ce 491 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
modtronix 10:6444e6c798ce 492 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
modtronix 10:6444e6c798ce 493
modtronix 10:6444e6c798ce 494 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
modtronix 10:6444e6c798ce 495 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
modtronix 10:6444e6c798ce 496
modtronix 10:6444e6c798ce 497 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
modtronix 10:6444e6c798ce 498 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
modtronix 10:6444e6c798ce 499
modtronix 10:6444e6c798ce 500 /* SysTick Reload Register Definitions */
modtronix 10:6444e6c798ce 501 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
modtronix 10:6444e6c798ce 502 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
modtronix 10:6444e6c798ce 503
modtronix 10:6444e6c798ce 504 /* SysTick Current Register Definitions */
modtronix 10:6444e6c798ce 505 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
modtronix 10:6444e6c798ce 506 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
modtronix 10:6444e6c798ce 507
modtronix 10:6444e6c798ce 508 /* SysTick Calibration Register Definitions */
modtronix 10:6444e6c798ce 509 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
modtronix 10:6444e6c798ce 510 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
modtronix 10:6444e6c798ce 511
modtronix 10:6444e6c798ce 512 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
modtronix 10:6444e6c798ce 513 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
modtronix 10:6444e6c798ce 514
modtronix 10:6444e6c798ce 515 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
modtronix 10:6444e6c798ce 516 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
modtronix 10:6444e6c798ce 517
modtronix 10:6444e6c798ce 518 /*@} end of group CMSIS_SysTick */
modtronix 10:6444e6c798ce 519
modtronix 10:6444e6c798ce 520 #if (__MPU_PRESENT == 1)
modtronix 10:6444e6c798ce 521 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 522 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
modtronix 10:6444e6c798ce 523 \brief Type definitions for the Memory Protection Unit (MPU)
modtronix 10:6444e6c798ce 524 @{
modtronix 10:6444e6c798ce 525 */
modtronix 10:6444e6c798ce 526
modtronix 10:6444e6c798ce 527 /** \brief Structure type to access the Memory Protection Unit (MPU).
modtronix 10:6444e6c798ce 528 */
modtronix 10:6444e6c798ce 529 typedef struct
modtronix 10:6444e6c798ce 530 {
modtronix 10:6444e6c798ce 531 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
modtronix 10:6444e6c798ce 532 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
modtronix 10:6444e6c798ce 533 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
modtronix 10:6444e6c798ce 534 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
modtronix 10:6444e6c798ce 535 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
modtronix 10:6444e6c798ce 536 } MPU_Type;
modtronix 10:6444e6c798ce 537
modtronix 10:6444e6c798ce 538 /* MPU Type Register */
modtronix 10:6444e6c798ce 539 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
modtronix 10:6444e6c798ce 540 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
modtronix 10:6444e6c798ce 541
modtronix 10:6444e6c798ce 542 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
modtronix 10:6444e6c798ce 543 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
modtronix 10:6444e6c798ce 544
modtronix 10:6444e6c798ce 545 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
modtronix 10:6444e6c798ce 546 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
modtronix 10:6444e6c798ce 547
modtronix 10:6444e6c798ce 548 /* MPU Control Register */
modtronix 10:6444e6c798ce 549 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
modtronix 10:6444e6c798ce 550 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
modtronix 10:6444e6c798ce 551
modtronix 10:6444e6c798ce 552 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
modtronix 10:6444e6c798ce 553 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
modtronix 10:6444e6c798ce 554
modtronix 10:6444e6c798ce 555 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
modtronix 10:6444e6c798ce 556 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
modtronix 10:6444e6c798ce 557
modtronix 10:6444e6c798ce 558 /* MPU Region Number Register */
modtronix 10:6444e6c798ce 559 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
modtronix 10:6444e6c798ce 560 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
modtronix 10:6444e6c798ce 561
modtronix 10:6444e6c798ce 562 /* MPU Region Base Address Register */
modtronix 10:6444e6c798ce 563 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
modtronix 10:6444e6c798ce 564 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
modtronix 10:6444e6c798ce 565
modtronix 10:6444e6c798ce 566 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
modtronix 10:6444e6c798ce 567 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
modtronix 10:6444e6c798ce 568
modtronix 10:6444e6c798ce 569 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
modtronix 10:6444e6c798ce 570 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
modtronix 10:6444e6c798ce 571
modtronix 10:6444e6c798ce 572 /* MPU Region Attribute and Size Register */
modtronix 10:6444e6c798ce 573 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
modtronix 10:6444e6c798ce 574 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
modtronix 10:6444e6c798ce 575
modtronix 10:6444e6c798ce 576 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
modtronix 10:6444e6c798ce 577 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
modtronix 10:6444e6c798ce 578
modtronix 10:6444e6c798ce 579 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
modtronix 10:6444e6c798ce 580 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
modtronix 10:6444e6c798ce 581
modtronix 10:6444e6c798ce 582 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
modtronix 10:6444e6c798ce 583 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
modtronix 10:6444e6c798ce 584
modtronix 10:6444e6c798ce 585 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
modtronix 10:6444e6c798ce 586 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
modtronix 10:6444e6c798ce 587
modtronix 10:6444e6c798ce 588 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
modtronix 10:6444e6c798ce 589 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
modtronix 10:6444e6c798ce 590
modtronix 10:6444e6c798ce 591 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
modtronix 10:6444e6c798ce 592 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
modtronix 10:6444e6c798ce 593
modtronix 10:6444e6c798ce 594 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
modtronix 10:6444e6c798ce 595 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
modtronix 10:6444e6c798ce 596
modtronix 10:6444e6c798ce 597 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
modtronix 10:6444e6c798ce 598 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
modtronix 10:6444e6c798ce 599
modtronix 10:6444e6c798ce 600 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
modtronix 10:6444e6c798ce 601 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
modtronix 10:6444e6c798ce 602
modtronix 10:6444e6c798ce 603 /*@} end of group CMSIS_MPU */
modtronix 10:6444e6c798ce 604 #endif
modtronix 10:6444e6c798ce 605
modtronix 10:6444e6c798ce 606
modtronix 10:6444e6c798ce 607 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 608 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
modtronix 10:6444e6c798ce 609 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
modtronix 10:6444e6c798ce 610 are only accessible over DAP and not via processor. Therefore
modtronix 10:6444e6c798ce 611 they are not covered by the Cortex-M0 header file.
modtronix 10:6444e6c798ce 612 @{
modtronix 10:6444e6c798ce 613 */
modtronix 10:6444e6c798ce 614 /*@} end of group CMSIS_CoreDebug */
modtronix 10:6444e6c798ce 615
modtronix 10:6444e6c798ce 616
modtronix 10:6444e6c798ce 617 /** \ingroup CMSIS_core_register
modtronix 10:6444e6c798ce 618 \defgroup CMSIS_core_base Core Definitions
modtronix 10:6444e6c798ce 619 \brief Definitions for base addresses, unions, and structures.
modtronix 10:6444e6c798ce 620 @{
modtronix 10:6444e6c798ce 621 */
modtronix 10:6444e6c798ce 622
modtronix 10:6444e6c798ce 623 /* Memory mapping of SC000 Hardware */
modtronix 10:6444e6c798ce 624 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
modtronix 10:6444e6c798ce 625 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
modtronix 10:6444e6c798ce 626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
modtronix 10:6444e6c798ce 627 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
modtronix 10:6444e6c798ce 628
modtronix 10:6444e6c798ce 629 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
modtronix 10:6444e6c798ce 630 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
modtronix 10:6444e6c798ce 631 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
modtronix 10:6444e6c798ce 632 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
modtronix 10:6444e6c798ce 633
modtronix 10:6444e6c798ce 634 #if (__MPU_PRESENT == 1)
modtronix 10:6444e6c798ce 635 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
modtronix 10:6444e6c798ce 636 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
modtronix 10:6444e6c798ce 637 #endif
modtronix 10:6444e6c798ce 638
modtronix 10:6444e6c798ce 639 /*@} */
modtronix 10:6444e6c798ce 640
modtronix 10:6444e6c798ce 641
modtronix 10:6444e6c798ce 642
modtronix 10:6444e6c798ce 643 /*******************************************************************************
modtronix 10:6444e6c798ce 644 * Hardware Abstraction Layer
modtronix 10:6444e6c798ce 645 Core Function Interface contains:
modtronix 10:6444e6c798ce 646 - Core NVIC Functions
modtronix 10:6444e6c798ce 647 - Core SysTick Functions
modtronix 10:6444e6c798ce 648 - Core Register Access Functions
modtronix 10:6444e6c798ce 649 ******************************************************************************/
modtronix 10:6444e6c798ce 650 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
modtronix 10:6444e6c798ce 651 */
modtronix 10:6444e6c798ce 652
modtronix 10:6444e6c798ce 653
modtronix 10:6444e6c798ce 654
modtronix 10:6444e6c798ce 655 /* ########################## NVIC functions #################################### */
modtronix 10:6444e6c798ce 656 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 10:6444e6c798ce 657 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
modtronix 10:6444e6c798ce 658 \brief Functions that manage interrupts and exceptions via the NVIC.
modtronix 10:6444e6c798ce 659 @{
modtronix 10:6444e6c798ce 660 */
modtronix 10:6444e6c798ce 661
modtronix 10:6444e6c798ce 662 /* Interrupt Priorities are WORD accessible only under ARMv6M */
modtronix 10:6444e6c798ce 663 /* The following MACROS handle generation of the register offset and byte masks */
modtronix 10:6444e6c798ce 664 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
modtronix 10:6444e6c798ce 665 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
modtronix 10:6444e6c798ce 666 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
modtronix 10:6444e6c798ce 667
modtronix 10:6444e6c798ce 668
modtronix 10:6444e6c798ce 669 /** \brief Enable External Interrupt
modtronix 10:6444e6c798ce 670
modtronix 10:6444e6c798ce 671 The function enables a device-specific interrupt in the NVIC interrupt controller.
modtronix 10:6444e6c798ce 672
modtronix 10:6444e6c798ce 673 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 10:6444e6c798ce 674 */
modtronix 10:6444e6c798ce 675 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 676 {
modtronix 10:6444e6c798ce 677 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 10:6444e6c798ce 678 }
modtronix 10:6444e6c798ce 679
modtronix 10:6444e6c798ce 680
modtronix 10:6444e6c798ce 681 /** \brief Disable External Interrupt
modtronix 10:6444e6c798ce 682
modtronix 10:6444e6c798ce 683 The function disables a device-specific interrupt in the NVIC interrupt controller.
modtronix 10:6444e6c798ce 684
modtronix 10:6444e6c798ce 685 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 10:6444e6c798ce 686 */
modtronix 10:6444e6c798ce 687 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 688 {
modtronix 10:6444e6c798ce 689 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 10:6444e6c798ce 690 }
modtronix 10:6444e6c798ce 691
modtronix 10:6444e6c798ce 692
modtronix 10:6444e6c798ce 693 /** \brief Get Pending Interrupt
modtronix 10:6444e6c798ce 694
modtronix 10:6444e6c798ce 695 The function reads the pending register in the NVIC and returns the pending bit
modtronix 10:6444e6c798ce 696 for the specified interrupt.
modtronix 10:6444e6c798ce 697
modtronix 10:6444e6c798ce 698 \param [in] IRQn Interrupt number.
modtronix 10:6444e6c798ce 699
modtronix 10:6444e6c798ce 700 \return 0 Interrupt status is not pending.
modtronix 10:6444e6c798ce 701 \return 1 Interrupt status is pending.
modtronix 10:6444e6c798ce 702 */
modtronix 10:6444e6c798ce 703 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 704 {
modtronix 10:6444e6c798ce 705 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
modtronix 10:6444e6c798ce 706 }
modtronix 10:6444e6c798ce 707
modtronix 10:6444e6c798ce 708
modtronix 10:6444e6c798ce 709 /** \brief Set Pending Interrupt
modtronix 10:6444e6c798ce 710
modtronix 10:6444e6c798ce 711 The function sets the pending bit of an external interrupt.
modtronix 10:6444e6c798ce 712
modtronix 10:6444e6c798ce 713 \param [in] IRQn Interrupt number. Value cannot be negative.
modtronix 10:6444e6c798ce 714 */
modtronix 10:6444e6c798ce 715 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 716 {
modtronix 10:6444e6c798ce 717 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 10:6444e6c798ce 718 }
modtronix 10:6444e6c798ce 719
modtronix 10:6444e6c798ce 720
modtronix 10:6444e6c798ce 721 /** \brief Clear Pending Interrupt
modtronix 10:6444e6c798ce 722
modtronix 10:6444e6c798ce 723 The function clears the pending bit of an external interrupt.
modtronix 10:6444e6c798ce 724
modtronix 10:6444e6c798ce 725 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 10:6444e6c798ce 726 */
modtronix 10:6444e6c798ce 727 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 728 {
modtronix 10:6444e6c798ce 729 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
modtronix 10:6444e6c798ce 730 }
modtronix 10:6444e6c798ce 731
modtronix 10:6444e6c798ce 732
modtronix 10:6444e6c798ce 733 /** \brief Set Interrupt Priority
modtronix 10:6444e6c798ce 734
modtronix 10:6444e6c798ce 735 The function sets the priority of an interrupt.
modtronix 10:6444e6c798ce 736
modtronix 10:6444e6c798ce 737 \note The priority cannot be set for every core interrupt.
modtronix 10:6444e6c798ce 738
modtronix 10:6444e6c798ce 739 \param [in] IRQn Interrupt number.
modtronix 10:6444e6c798ce 740 \param [in] priority Priority to set.
modtronix 10:6444e6c798ce 741 */
modtronix 10:6444e6c798ce 742 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
modtronix 10:6444e6c798ce 743 {
modtronix 10:6444e6c798ce 744 if(IRQn < 0) {
modtronix 10:6444e6c798ce 745 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 10:6444e6c798ce 746 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 10:6444e6c798ce 747 else {
modtronix 10:6444e6c798ce 748 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 10:6444e6c798ce 749 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 10:6444e6c798ce 750 }
modtronix 10:6444e6c798ce 751
modtronix 10:6444e6c798ce 752
modtronix 10:6444e6c798ce 753 /** \brief Get Interrupt Priority
modtronix 10:6444e6c798ce 754
modtronix 10:6444e6c798ce 755 The function reads the priority of an interrupt. The interrupt
modtronix 10:6444e6c798ce 756 number can be positive to specify an external (device specific)
modtronix 10:6444e6c798ce 757 interrupt, or negative to specify an internal (core) interrupt.
modtronix 10:6444e6c798ce 758
modtronix 10:6444e6c798ce 759
modtronix 10:6444e6c798ce 760 \param [in] IRQn Interrupt number.
modtronix 10:6444e6c798ce 761 \return Interrupt Priority. Value is aligned automatically to the implemented
modtronix 10:6444e6c798ce 762 priority bits of the microcontroller.
modtronix 10:6444e6c798ce 763 */
modtronix 10:6444e6c798ce 764 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
modtronix 10:6444e6c798ce 765 {
modtronix 10:6444e6c798ce 766
modtronix 10:6444e6c798ce 767 if(IRQn < 0) {
modtronix 10:6444e6c798ce 768 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
modtronix 10:6444e6c798ce 769 else {
modtronix 10:6444e6c798ce 770 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
modtronix 10:6444e6c798ce 771 }
modtronix 10:6444e6c798ce 772
modtronix 10:6444e6c798ce 773
modtronix 10:6444e6c798ce 774 /** \brief System Reset
modtronix 10:6444e6c798ce 775
modtronix 10:6444e6c798ce 776 The function initiates a system reset request to reset the MCU.
modtronix 10:6444e6c798ce 777 */
modtronix 10:6444e6c798ce 778 __STATIC_INLINE void NVIC_SystemReset(void)
modtronix 10:6444e6c798ce 779 {
modtronix 10:6444e6c798ce 780 __DSB(); /* Ensure all outstanding memory accesses included
modtronix 10:6444e6c798ce 781 buffered write are completed before reset */
modtronix 10:6444e6c798ce 782 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 10:6444e6c798ce 783 SCB_AIRCR_SYSRESETREQ_Msk);
modtronix 10:6444e6c798ce 784 __DSB(); /* Ensure completion of memory access */
modtronix 10:6444e6c798ce 785 while(1); /* wait until reset */
modtronix 10:6444e6c798ce 786 }
modtronix 10:6444e6c798ce 787
modtronix 10:6444e6c798ce 788 /*@} end of CMSIS_Core_NVICFunctions */
modtronix 10:6444e6c798ce 789
modtronix 10:6444e6c798ce 790
modtronix 10:6444e6c798ce 791
modtronix 10:6444e6c798ce 792 /* ################################## SysTick function ############################################ */
modtronix 10:6444e6c798ce 793 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 10:6444e6c798ce 794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
modtronix 10:6444e6c798ce 795 \brief Functions that configure the System.
modtronix 10:6444e6c798ce 796 @{
modtronix 10:6444e6c798ce 797 */
modtronix 10:6444e6c798ce 798
modtronix 10:6444e6c798ce 799 #if (__Vendor_SysTickConfig == 0)
modtronix 10:6444e6c798ce 800
modtronix 10:6444e6c798ce 801 /** \brief System Tick Configuration
modtronix 10:6444e6c798ce 802
modtronix 10:6444e6c798ce 803 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
modtronix 10:6444e6c798ce 804 Counter is in free running mode to generate periodic interrupts.
modtronix 10:6444e6c798ce 805
modtronix 10:6444e6c798ce 806 \param [in] ticks Number of ticks between two interrupts.
modtronix 10:6444e6c798ce 807
modtronix 10:6444e6c798ce 808 \return 0 Function succeeded.
modtronix 10:6444e6c798ce 809 \return 1 Function failed.
modtronix 10:6444e6c798ce 810
modtronix 10:6444e6c798ce 811 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
modtronix 10:6444e6c798ce 812 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
modtronix 10:6444e6c798ce 813 must contain a vendor-specific implementation of this function.
modtronix 10:6444e6c798ce 814
modtronix 10:6444e6c798ce 815 */
modtronix 10:6444e6c798ce 816 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
modtronix 10:6444e6c798ce 817 {
modtronix 10:6444e6c798ce 818 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
modtronix 10:6444e6c798ce 819
modtronix 10:6444e6c798ce 820 SysTick->LOAD = ticks - 1; /* set reload register */
modtronix 10:6444e6c798ce 821 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
modtronix 10:6444e6c798ce 822 SysTick->VAL = 0; /* Load the SysTick Counter Value */
modtronix 10:6444e6c798ce 823 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
modtronix 10:6444e6c798ce 824 SysTick_CTRL_TICKINT_Msk |
modtronix 10:6444e6c798ce 825 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
modtronix 10:6444e6c798ce 826 return (0); /* Function successful */
modtronix 10:6444e6c798ce 827 }
modtronix 10:6444e6c798ce 828
modtronix 10:6444e6c798ce 829 #endif
modtronix 10:6444e6c798ce 830
modtronix 10:6444e6c798ce 831 /*@} end of CMSIS_Core_SysTickFunctions */
modtronix 10:6444e6c798ce 832
modtronix 10:6444e6c798ce 833
modtronix 10:6444e6c798ce 834
modtronix 10:6444e6c798ce 835
modtronix 10:6444e6c798ce 836 #ifdef __cplusplus
modtronix 10:6444e6c798ce 837 }
modtronix 10:6444e6c798ce 838 #endif
modtronix 10:6444e6c798ce 839
modtronix 10:6444e6c798ce 840 #endif /* __CORE_SC000_H_DEPENDANT */
modtronix 10:6444e6c798ce 841
modtronix 10:6444e6c798ce 842 #endif /* __CMSIS_GENERIC */