modtronix H / mbed_nz32sc151

mbed library for NZ32-SC151

targets/cmsis/core_cmSimd.h@17:639ed60ce759, 2016-08-19 (annotated)

Committer:
modtronix-com
Date:
Fri Aug 19 15:46:42 2016 +1000
Revision:
17:639ed60ce759
Parent:
10:6444e6c798ce 
Added tag v1.1 for changeset 076cbe3e55be

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:71204b8406f2 1 /**************************************************************************//**
modtronix 1:71204b8406f2 2 * @file core_cmSimd.h
modtronix 1:71204b8406f2 3 * @brief CMSIS Cortex-M SIMD Header File
modtronix 10:6444e6c798ce 4 * @version V4.00
modtronix 10:6444e6c798ce 5 * @date 22. August 2014
modtronix 1:71204b8406f2 6 *
modtronix 1:71204b8406f2 7 * @note
modtronix 1:71204b8406f2 8 *
modtronix 1:71204b8406f2 9 ******************************************************************************/
modtronix 1:71204b8406f2 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
modtronix 1:71204b8406f2 11
modtronix 1:71204b8406f2 12 All rights reserved.
modtronix 1:71204b8406f2 13 Redistribution and use in source and binary forms, with or without
modtronix 1:71204b8406f2 14 modification, are permitted provided that the following conditions are met:
modtronix 1:71204b8406f2 15 - Redistributions of source code must retain the above copyright
modtronix 1:71204b8406f2 16 notice, this list of conditions and the following disclaimer.
modtronix 1:71204b8406f2 17 - Redistributions in binary form must reproduce the above copyright
modtronix 1:71204b8406f2 18 notice, this list of conditions and the following disclaimer in the
modtronix 1:71204b8406f2 19 documentation and/or other materials provided with the distribution.
modtronix 1:71204b8406f2 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 1:71204b8406f2 21 to endorse or promote products derived from this software without
modtronix 1:71204b8406f2 22 specific prior written permission.
modtronix 1:71204b8406f2 23 *
modtronix 1:71204b8406f2 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 1:71204b8406f2 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 1:71204b8406f2 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 1:71204b8406f2 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 1:71204b8406f2 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 1:71204b8406f2 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 1:71204b8406f2 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 1:71204b8406f2 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 1:71204b8406f2 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 1:71204b8406f2 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 1:71204b8406f2 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 1:71204b8406f2 35 ---------------------------------------------------------------------------*/
modtronix 1:71204b8406f2 36
modtronix 1:71204b8406f2 37
modtronix 1:71204b8406f2 38 #if defined ( __ICCARM__ )
modtronix 1:71204b8406f2 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 1:71204b8406f2 40 #endif
modtronix 1:71204b8406f2 41
modtronix 1:71204b8406f2 42 #ifndef __CORE_CMSIMD_H
modtronix 1:71204b8406f2 43 #define __CORE_CMSIMD_H
modtronix 1:71204b8406f2 44
modtronix 1:71204b8406f2 45 #ifdef __cplusplus
modtronix 1:71204b8406f2 46 extern "C" {
modtronix 1:71204b8406f2 47 #endif
modtronix 1:71204b8406f2 48
modtronix 1:71204b8406f2 49
modtronix 1:71204b8406f2 50 /*******************************************************************************
modtronix 1:71204b8406f2 51 * Hardware Abstraction Layer
modtronix 1:71204b8406f2 52 ******************************************************************************/
modtronix 1:71204b8406f2 53
modtronix 1:71204b8406f2 54
modtronix 1:71204b8406f2 55 /* ################### Compiler specific Intrinsics ########################### */
modtronix 1:71204b8406f2 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
modtronix 1:71204b8406f2 57 Access to dedicated SIMD instructions
modtronix 1:71204b8406f2 58 @{
modtronix 1:71204b8406f2 59 */
modtronix 1:71204b8406f2 60
modtronix 1:71204b8406f2 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
modtronix 1:71204b8406f2 62 /* ARM armcc specific functions */
modtronix 1:71204b8406f2 63 #define __SADD8 __sadd8
modtronix 1:71204b8406f2 64 #define __QADD8 __qadd8
modtronix 1:71204b8406f2 65 #define __SHADD8 __shadd8
modtronix 1:71204b8406f2 66 #define __UADD8 __uadd8
modtronix 1:71204b8406f2 67 #define __UQADD8 __uqadd8
modtronix 1:71204b8406f2 68 #define __UHADD8 __uhadd8
modtronix 1:71204b8406f2 69 #define __SSUB8 __ssub8
modtronix 1:71204b8406f2 70 #define __QSUB8 __qsub8
modtronix 1:71204b8406f2 71 #define __SHSUB8 __shsub8
modtronix 1:71204b8406f2 72 #define __USUB8 __usub8
modtronix 1:71204b8406f2 73 #define __UQSUB8 __uqsub8
modtronix 1:71204b8406f2 74 #define __UHSUB8 __uhsub8
modtronix 1:71204b8406f2 75 #define __SADD16 __sadd16
modtronix 1:71204b8406f2 76 #define __QADD16 __qadd16
modtronix 1:71204b8406f2 77 #define __SHADD16 __shadd16
modtronix 1:71204b8406f2 78 #define __UADD16 __uadd16
modtronix 1:71204b8406f2 79 #define __UQADD16 __uqadd16
modtronix 1:71204b8406f2 80 #define __UHADD16 __uhadd16
modtronix 1:71204b8406f2 81 #define __SSUB16 __ssub16
modtronix 1:71204b8406f2 82 #define __QSUB16 __qsub16
modtronix 1:71204b8406f2 83 #define __SHSUB16 __shsub16
modtronix 1:71204b8406f2 84 #define __USUB16 __usub16
modtronix 1:71204b8406f2 85 #define __UQSUB16 __uqsub16
modtronix 1:71204b8406f2 86 #define __UHSUB16 __uhsub16
modtronix 1:71204b8406f2 87 #define __SASX __sasx
modtronix 1:71204b8406f2 88 #define __QASX __qasx
modtronix 1:71204b8406f2 89 #define __SHASX __shasx
modtronix 1:71204b8406f2 90 #define __UASX __uasx
modtronix 1:71204b8406f2 91 #define __UQASX __uqasx
modtronix 1:71204b8406f2 92 #define __UHASX __uhasx
modtronix 1:71204b8406f2 93 #define __SSAX __ssax
modtronix 1:71204b8406f2 94 #define __QSAX __qsax
modtronix 1:71204b8406f2 95 #define __SHSAX __shsax
modtronix 1:71204b8406f2 96 #define __USAX __usax
modtronix 1:71204b8406f2 97 #define __UQSAX __uqsax
modtronix 1:71204b8406f2 98 #define __UHSAX __uhsax
modtronix 1:71204b8406f2 99 #define __USAD8 __usad8
modtronix 1:71204b8406f2 100 #define __USADA8 __usada8
modtronix 1:71204b8406f2 101 #define __SSAT16 __ssat16
modtronix 1:71204b8406f2 102 #define __USAT16 __usat16
modtronix 1:71204b8406f2 103 #define __UXTB16 __uxtb16
modtronix 1:71204b8406f2 104 #define __UXTAB16 __uxtab16
modtronix 1:71204b8406f2 105 #define __SXTB16 __sxtb16
modtronix 1:71204b8406f2 106 #define __SXTAB16 __sxtab16
modtronix 1:71204b8406f2 107 #define __SMUAD __smuad
modtronix 1:71204b8406f2 108 #define __SMUADX __smuadx
modtronix 1:71204b8406f2 109 #define __SMLAD __smlad
modtronix 1:71204b8406f2 110 #define __SMLADX __smladx
modtronix 1:71204b8406f2 111 #define __SMLALD __smlald
modtronix 1:71204b8406f2 112 #define __SMLALDX __smlaldx
modtronix 1:71204b8406f2 113 #define __SMUSD __smusd
modtronix 1:71204b8406f2 114 #define __SMUSDX __smusdx
modtronix 1:71204b8406f2 115 #define __SMLSD __smlsd
modtronix 1:71204b8406f2 116 #define __SMLSDX __smlsdx
modtronix 1:71204b8406f2 117 #define __SMLSLD __smlsld
modtronix 1:71204b8406f2 118 #define __SMLSLDX __smlsldx
modtronix 1:71204b8406f2 119 #define __SEL __sel
modtronix 1:71204b8406f2 120 #define __QADD __qadd
modtronix 1:71204b8406f2 121 #define __QSUB __qsub
modtronix 1:71204b8406f2 122
modtronix 1:71204b8406f2 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
modtronix 1:71204b8406f2 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
modtronix 1:71204b8406f2 125
modtronix 1:71204b8406f2 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
modtronix 1:71204b8406f2 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
modtronix 1:71204b8406f2 128
modtronix 1:71204b8406f2 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
modtronix 1:71204b8406f2 130 ((int64_t)(ARG3) << 32) ) >> 32))
modtronix 1:71204b8406f2 131
modtronix 1:71204b8406f2 132
modtronix 1:71204b8406f2 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
modtronix 1:71204b8406f2 134 /* GNU gcc specific functions */
modtronix 1:71204b8406f2 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 136 {
modtronix 1:71204b8406f2 137 uint32_t result;
modtronix 1:71204b8406f2 138
modtronix 1:71204b8406f2 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 140 return(result);
modtronix 1:71204b8406f2 141 }
modtronix 1:71204b8406f2 142
modtronix 1:71204b8406f2 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 144 {
modtronix 1:71204b8406f2 145 uint32_t result;
modtronix 1:71204b8406f2 146
modtronix 1:71204b8406f2 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 148 return(result);
modtronix 1:71204b8406f2 149 }
modtronix 1:71204b8406f2 150
modtronix 1:71204b8406f2 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 152 {
modtronix 1:71204b8406f2 153 uint32_t result;
modtronix 1:71204b8406f2 154
modtronix 1:71204b8406f2 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 156 return(result);
modtronix 1:71204b8406f2 157 }
modtronix 1:71204b8406f2 158
modtronix 1:71204b8406f2 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 160 {
modtronix 1:71204b8406f2 161 uint32_t result;
modtronix 1:71204b8406f2 162
modtronix 1:71204b8406f2 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 164 return(result);
modtronix 1:71204b8406f2 165 }
modtronix 1:71204b8406f2 166
modtronix 1:71204b8406f2 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 168 {
modtronix 1:71204b8406f2 169 uint32_t result;
modtronix 1:71204b8406f2 170
modtronix 1:71204b8406f2 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 172 return(result);
modtronix 1:71204b8406f2 173 }
modtronix 1:71204b8406f2 174
modtronix 1:71204b8406f2 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 176 {
modtronix 1:71204b8406f2 177 uint32_t result;
modtronix 1:71204b8406f2 178
modtronix 1:71204b8406f2 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 180 return(result);
modtronix 1:71204b8406f2 181 }
modtronix 1:71204b8406f2 182
modtronix 1:71204b8406f2 183
modtronix 1:71204b8406f2 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 185 {
modtronix 1:71204b8406f2 186 uint32_t result;
modtronix 1:71204b8406f2 187
modtronix 1:71204b8406f2 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 189 return(result);
modtronix 1:71204b8406f2 190 }
modtronix 1:71204b8406f2 191
modtronix 1:71204b8406f2 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 193 {
modtronix 1:71204b8406f2 194 uint32_t result;
modtronix 1:71204b8406f2 195
modtronix 1:71204b8406f2 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 197 return(result);
modtronix 1:71204b8406f2 198 }
modtronix 1:71204b8406f2 199
modtronix 1:71204b8406f2 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 201 {
modtronix 1:71204b8406f2 202 uint32_t result;
modtronix 1:71204b8406f2 203
modtronix 1:71204b8406f2 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 205 return(result);
modtronix 1:71204b8406f2 206 }
modtronix 1:71204b8406f2 207
modtronix 1:71204b8406f2 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 209 {
modtronix 1:71204b8406f2 210 uint32_t result;
modtronix 1:71204b8406f2 211
modtronix 1:71204b8406f2 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 213 return(result);
modtronix 1:71204b8406f2 214 }
modtronix 1:71204b8406f2 215
modtronix 1:71204b8406f2 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 217 {
modtronix 1:71204b8406f2 218 uint32_t result;
modtronix 1:71204b8406f2 219
modtronix 1:71204b8406f2 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 221 return(result);
modtronix 1:71204b8406f2 222 }
modtronix 1:71204b8406f2 223
modtronix 1:71204b8406f2 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 225 {
modtronix 1:71204b8406f2 226 uint32_t result;
modtronix 1:71204b8406f2 227
modtronix 1:71204b8406f2 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 229 return(result);
modtronix 1:71204b8406f2 230 }
modtronix 1:71204b8406f2 231
modtronix 1:71204b8406f2 232
modtronix 1:71204b8406f2 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 234 {
modtronix 1:71204b8406f2 235 uint32_t result;
modtronix 1:71204b8406f2 236
modtronix 1:71204b8406f2 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 238 return(result);
modtronix 1:71204b8406f2 239 }
modtronix 1:71204b8406f2 240
modtronix 1:71204b8406f2 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 242 {
modtronix 1:71204b8406f2 243 uint32_t result;
modtronix 1:71204b8406f2 244
modtronix 1:71204b8406f2 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 246 return(result);
modtronix 1:71204b8406f2 247 }
modtronix 1:71204b8406f2 248
modtronix 1:71204b8406f2 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 250 {
modtronix 1:71204b8406f2 251 uint32_t result;
modtronix 1:71204b8406f2 252
modtronix 1:71204b8406f2 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 254 return(result);
modtronix 1:71204b8406f2 255 }
modtronix 1:71204b8406f2 256
modtronix 1:71204b8406f2 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 258 {
modtronix 1:71204b8406f2 259 uint32_t result;
modtronix 1:71204b8406f2 260
modtronix 1:71204b8406f2 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 262 return(result);
modtronix 1:71204b8406f2 263 }
modtronix 1:71204b8406f2 264
modtronix 1:71204b8406f2 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 266 {
modtronix 1:71204b8406f2 267 uint32_t result;
modtronix 1:71204b8406f2 268
modtronix 1:71204b8406f2 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 270 return(result);
modtronix 1:71204b8406f2 271 }
modtronix 1:71204b8406f2 272
modtronix 1:71204b8406f2 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 274 {
modtronix 1:71204b8406f2 275 uint32_t result;
modtronix 1:71204b8406f2 276
modtronix 1:71204b8406f2 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 278 return(result);
modtronix 1:71204b8406f2 279 }
modtronix 1:71204b8406f2 280
modtronix 1:71204b8406f2 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 282 {
modtronix 1:71204b8406f2 283 uint32_t result;
modtronix 1:71204b8406f2 284
modtronix 1:71204b8406f2 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 286 return(result);
modtronix 1:71204b8406f2 287 }
modtronix 1:71204b8406f2 288
modtronix 1:71204b8406f2 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 290 {
modtronix 1:71204b8406f2 291 uint32_t result;
modtronix 1:71204b8406f2 292
modtronix 1:71204b8406f2 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 294 return(result);
modtronix 1:71204b8406f2 295 }
modtronix 1:71204b8406f2 296
modtronix 1:71204b8406f2 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 298 {
modtronix 1:71204b8406f2 299 uint32_t result;
modtronix 1:71204b8406f2 300
modtronix 1:71204b8406f2 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 302 return(result);
modtronix 1:71204b8406f2 303 }
modtronix 1:71204b8406f2 304
modtronix 1:71204b8406f2 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 306 {
modtronix 1:71204b8406f2 307 uint32_t result;
modtronix 1:71204b8406f2 308
modtronix 1:71204b8406f2 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 310 return(result);
modtronix 1:71204b8406f2 311 }
modtronix 1:71204b8406f2 312
modtronix 1:71204b8406f2 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 314 {
modtronix 1:71204b8406f2 315 uint32_t result;
modtronix 1:71204b8406f2 316
modtronix 1:71204b8406f2 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 318 return(result);
modtronix 1:71204b8406f2 319 }
modtronix 1:71204b8406f2 320
modtronix 1:71204b8406f2 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 322 {
modtronix 1:71204b8406f2 323 uint32_t result;
modtronix 1:71204b8406f2 324
modtronix 1:71204b8406f2 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 326 return(result);
modtronix 1:71204b8406f2 327 }
modtronix 1:71204b8406f2 328
modtronix 1:71204b8406f2 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 330 {
modtronix 1:71204b8406f2 331 uint32_t result;
modtronix 1:71204b8406f2 332
modtronix 1:71204b8406f2 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 334 return(result);
modtronix 1:71204b8406f2 335 }
modtronix 1:71204b8406f2 336
modtronix 1:71204b8406f2 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 338 {
modtronix 1:71204b8406f2 339 uint32_t result;
modtronix 1:71204b8406f2 340
modtronix 1:71204b8406f2 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 342 return(result);
modtronix 1:71204b8406f2 343 }
modtronix 1:71204b8406f2 344
modtronix 1:71204b8406f2 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 346 {
modtronix 1:71204b8406f2 347 uint32_t result;
modtronix 1:71204b8406f2 348
modtronix 1:71204b8406f2 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 350 return(result);
modtronix 1:71204b8406f2 351 }
modtronix 1:71204b8406f2 352
modtronix 1:71204b8406f2 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 354 {
modtronix 1:71204b8406f2 355 uint32_t result;
modtronix 1:71204b8406f2 356
modtronix 1:71204b8406f2 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 358 return(result);
modtronix 1:71204b8406f2 359 }
modtronix 1:71204b8406f2 360
modtronix 1:71204b8406f2 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 362 {
modtronix 1:71204b8406f2 363 uint32_t result;
modtronix 1:71204b8406f2 364
modtronix 1:71204b8406f2 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 366 return(result);
modtronix 1:71204b8406f2 367 }
modtronix 1:71204b8406f2 368
modtronix 1:71204b8406f2 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 370 {
modtronix 1:71204b8406f2 371 uint32_t result;
modtronix 1:71204b8406f2 372
modtronix 1:71204b8406f2 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 374 return(result);
modtronix 1:71204b8406f2 375 }
modtronix 1:71204b8406f2 376
modtronix 1:71204b8406f2 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 378 {
modtronix 1:71204b8406f2 379 uint32_t result;
modtronix 1:71204b8406f2 380
modtronix 1:71204b8406f2 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 382 return(result);
modtronix 1:71204b8406f2 383 }
modtronix 1:71204b8406f2 384
modtronix 1:71204b8406f2 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 386 {
modtronix 1:71204b8406f2 387 uint32_t result;
modtronix 1:71204b8406f2 388
modtronix 1:71204b8406f2 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 390 return(result);
modtronix 1:71204b8406f2 391 }
modtronix 1:71204b8406f2 392
modtronix 1:71204b8406f2 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 394 {
modtronix 1:71204b8406f2 395 uint32_t result;
modtronix 1:71204b8406f2 396
modtronix 1:71204b8406f2 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 398 return(result);
modtronix 1:71204b8406f2 399 }
modtronix 1:71204b8406f2 400
modtronix 1:71204b8406f2 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 402 {
modtronix 1:71204b8406f2 403 uint32_t result;
modtronix 1:71204b8406f2 404
modtronix 1:71204b8406f2 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 406 return(result);
modtronix 1:71204b8406f2 407 }
modtronix 1:71204b8406f2 408
modtronix 1:71204b8406f2 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 410 {
modtronix 1:71204b8406f2 411 uint32_t result;
modtronix 1:71204b8406f2 412
modtronix 1:71204b8406f2 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 414 return(result);
modtronix 1:71204b8406f2 415 }
modtronix 1:71204b8406f2 416
modtronix 1:71204b8406f2 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 418 {
modtronix 1:71204b8406f2 419 uint32_t result;
modtronix 1:71204b8406f2 420
modtronix 1:71204b8406f2 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 422 return(result);
modtronix 1:71204b8406f2 423 }
modtronix 1:71204b8406f2 424
modtronix 1:71204b8406f2 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 426 {
modtronix 1:71204b8406f2 427 uint32_t result;
modtronix 1:71204b8406f2 428
modtronix 1:71204b8406f2 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 430 return(result);
modtronix 1:71204b8406f2 431 }
modtronix 1:71204b8406f2 432
modtronix 1:71204b8406f2 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
modtronix 1:71204b8406f2 434 {
modtronix 1:71204b8406f2 435 uint32_t result;
modtronix 1:71204b8406f2 436
modtronix 1:71204b8406f2 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 438 return(result);
modtronix 1:71204b8406f2 439 }
modtronix 1:71204b8406f2 440
modtronix 1:71204b8406f2 441 #define __SSAT16(ARG1,ARG2) \
modtronix 1:71204b8406f2 442 ({ \
modtronix 1:71204b8406f2 443 uint32_t __RES, __ARG1 = (ARG1); \
modtronix 1:71204b8406f2 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
modtronix 1:71204b8406f2 445 __RES; \
modtronix 1:71204b8406f2 446 })
modtronix 1:71204b8406f2 447
modtronix 1:71204b8406f2 448 #define __USAT16(ARG1,ARG2) \
modtronix 1:71204b8406f2 449 ({ \
modtronix 1:71204b8406f2 450 uint32_t __RES, __ARG1 = (ARG1); \
modtronix 1:71204b8406f2 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
modtronix 1:71204b8406f2 452 __RES; \
modtronix 1:71204b8406f2 453 })
modtronix 1:71204b8406f2 454
modtronix 1:71204b8406f2 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
modtronix 1:71204b8406f2 456 {
modtronix 1:71204b8406f2 457 uint32_t result;
modtronix 1:71204b8406f2 458
modtronix 1:71204b8406f2 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
modtronix 1:71204b8406f2 460 return(result);
modtronix 1:71204b8406f2 461 }
modtronix 1:71204b8406f2 462
modtronix 1:71204b8406f2 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 464 {
modtronix 1:71204b8406f2 465 uint32_t result;
modtronix 1:71204b8406f2 466
modtronix 1:71204b8406f2 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 468 return(result);
modtronix 1:71204b8406f2 469 }
modtronix 1:71204b8406f2 470
modtronix 1:71204b8406f2 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
modtronix 1:71204b8406f2 472 {
modtronix 1:71204b8406f2 473 uint32_t result;
modtronix 1:71204b8406f2 474
modtronix 1:71204b8406f2 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
modtronix 1:71204b8406f2 476 return(result);
modtronix 1:71204b8406f2 477 }
modtronix 1:71204b8406f2 478
modtronix 1:71204b8406f2 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 480 {
modtronix 1:71204b8406f2 481 uint32_t result;
modtronix 1:71204b8406f2 482
modtronix 1:71204b8406f2 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 484 return(result);
modtronix 1:71204b8406f2 485 }
modtronix 1:71204b8406f2 486
modtronix 1:71204b8406f2 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 488 {
modtronix 1:71204b8406f2 489 uint32_t result;
modtronix 1:71204b8406f2 490
modtronix 1:71204b8406f2 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 492 return(result);
modtronix 1:71204b8406f2 493 }
modtronix 1:71204b8406f2 494
modtronix 1:71204b8406f2 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 496 {
modtronix 1:71204b8406f2 497 uint32_t result;
modtronix 1:71204b8406f2 498
modtronix 1:71204b8406f2 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 500 return(result);
modtronix 1:71204b8406f2 501 }
modtronix 1:71204b8406f2 502
modtronix 1:71204b8406f2 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
modtronix 1:71204b8406f2 504 {
modtronix 1:71204b8406f2 505 uint32_t result;
modtronix 1:71204b8406f2 506
modtronix 1:71204b8406f2 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 508 return(result);
modtronix 1:71204b8406f2 509 }
modtronix 1:71204b8406f2 510
modtronix 1:71204b8406f2 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
modtronix 1:71204b8406f2 512 {
modtronix 1:71204b8406f2 513 uint32_t result;
modtronix 1:71204b8406f2 514
modtronix 1:71204b8406f2 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 516 return(result);
modtronix 1:71204b8406f2 517 }
modtronix 1:71204b8406f2 518
modtronix 1:71204b8406f2 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
modtronix 1:71204b8406f2 520 {
modtronix 1:71204b8406f2 521 union llreg_u{
modtronix 1:71204b8406f2 522 uint32_t w32[2];
modtronix 1:71204b8406f2 523 uint64_t w64;
modtronix 1:71204b8406f2 524 } llr;
modtronix 1:71204b8406f2 525 llr.w64 = acc;
modtronix 1:71204b8406f2 526
modtronix 1:71204b8406f2 527 #ifndef __ARMEB__ // Little endian
modtronix 1:71204b8406f2 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
modtronix 1:71204b8406f2 529 #else // Big endian
modtronix 1:71204b8406f2 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
modtronix 1:71204b8406f2 531 #endif
modtronix 1:71204b8406f2 532
modtronix 1:71204b8406f2 533 return(llr.w64);
modtronix 1:71204b8406f2 534 }
modtronix 1:71204b8406f2 535
modtronix 1:71204b8406f2 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
modtronix 1:71204b8406f2 537 {
modtronix 1:71204b8406f2 538 union llreg_u{
modtronix 1:71204b8406f2 539 uint32_t w32[2];
modtronix 1:71204b8406f2 540 uint64_t w64;
modtronix 1:71204b8406f2 541 } llr;
modtronix 1:71204b8406f2 542 llr.w64 = acc;
modtronix 1:71204b8406f2 543
modtronix 1:71204b8406f2 544 #ifndef __ARMEB__ // Little endian
modtronix 1:71204b8406f2 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
modtronix 1:71204b8406f2 546 #else // Big endian
modtronix 1:71204b8406f2 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
modtronix 1:71204b8406f2 548 #endif
modtronix 1:71204b8406f2 549
modtronix 1:71204b8406f2 550 return(llr.w64);
modtronix 1:71204b8406f2 551 }
modtronix 1:71204b8406f2 552
modtronix 1:71204b8406f2 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 554 {
modtronix 1:71204b8406f2 555 uint32_t result;
modtronix 1:71204b8406f2 556
modtronix 1:71204b8406f2 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 558 return(result);
modtronix 1:71204b8406f2 559 }
modtronix 1:71204b8406f2 560
modtronix 1:71204b8406f2 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 562 {
modtronix 1:71204b8406f2 563 uint32_t result;
modtronix 1:71204b8406f2 564
modtronix 1:71204b8406f2 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 566 return(result);
modtronix 1:71204b8406f2 567 }
modtronix 1:71204b8406f2 568
modtronix 1:71204b8406f2 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
modtronix 1:71204b8406f2 570 {
modtronix 1:71204b8406f2 571 uint32_t result;
modtronix 1:71204b8406f2 572
modtronix 1:71204b8406f2 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 574 return(result);
modtronix 1:71204b8406f2 575 }
modtronix 1:71204b8406f2 576
modtronix 1:71204b8406f2 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
modtronix 1:71204b8406f2 578 {
modtronix 1:71204b8406f2 579 uint32_t result;
modtronix 1:71204b8406f2 580
modtronix 1:71204b8406f2 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 582 return(result);
modtronix 1:71204b8406f2 583 }
modtronix 1:71204b8406f2 584
modtronix 1:71204b8406f2 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
modtronix 1:71204b8406f2 586 {
modtronix 1:71204b8406f2 587 union llreg_u{
modtronix 1:71204b8406f2 588 uint32_t w32[2];
modtronix 1:71204b8406f2 589 uint64_t w64;
modtronix 1:71204b8406f2 590 } llr;
modtronix 1:71204b8406f2 591 llr.w64 = acc;
modtronix 1:71204b8406f2 592
modtronix 1:71204b8406f2 593 #ifndef __ARMEB__ // Little endian
modtronix 1:71204b8406f2 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
modtronix 1:71204b8406f2 595 #else // Big endian
modtronix 1:71204b8406f2 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
modtronix 1:71204b8406f2 597 #endif
modtronix 1:71204b8406f2 598
modtronix 1:71204b8406f2 599 return(llr.w64);
modtronix 1:71204b8406f2 600 }
modtronix 1:71204b8406f2 601
modtronix 1:71204b8406f2 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
modtronix 1:71204b8406f2 603 {
modtronix 1:71204b8406f2 604 union llreg_u{
modtronix 1:71204b8406f2 605 uint32_t w32[2];
modtronix 1:71204b8406f2 606 uint64_t w64;
modtronix 1:71204b8406f2 607 } llr;
modtronix 1:71204b8406f2 608 llr.w64 = acc;
modtronix 1:71204b8406f2 609
modtronix 1:71204b8406f2 610 #ifndef __ARMEB__ // Little endian
modtronix 1:71204b8406f2 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
modtronix 1:71204b8406f2 612 #else // Big endian
modtronix 1:71204b8406f2 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
modtronix 1:71204b8406f2 614 #endif
modtronix 1:71204b8406f2 615
modtronix 1:71204b8406f2 616 return(llr.w64);
modtronix 1:71204b8406f2 617 }
modtronix 1:71204b8406f2 618
modtronix 1:71204b8406f2 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 620 {
modtronix 1:71204b8406f2 621 uint32_t result;
modtronix 1:71204b8406f2 622
modtronix 1:71204b8406f2 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 624 return(result);
modtronix 1:71204b8406f2 625 }
modtronix 1:71204b8406f2 626
modtronix 1:71204b8406f2 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 628 {
modtronix 1:71204b8406f2 629 uint32_t result;
modtronix 1:71204b8406f2 630
modtronix 1:71204b8406f2 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 632 return(result);
modtronix 1:71204b8406f2 633 }
modtronix 1:71204b8406f2 634
modtronix 1:71204b8406f2 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
modtronix 1:71204b8406f2 636 {
modtronix 1:71204b8406f2 637 uint32_t result;
modtronix 1:71204b8406f2 638
modtronix 1:71204b8406f2 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
modtronix 1:71204b8406f2 640 return(result);
modtronix 1:71204b8406f2 641 }
modtronix 1:71204b8406f2 642
modtronix 1:71204b8406f2 643 #define __PKHBT(ARG1,ARG2,ARG3) \
modtronix 1:71204b8406f2 644 ({ \
modtronix 1:71204b8406f2 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
modtronix 1:71204b8406f2 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
modtronix 1:71204b8406f2 647 __RES; \
modtronix 1:71204b8406f2 648 })
modtronix 1:71204b8406f2 649
modtronix 1:71204b8406f2 650 #define __PKHTB(ARG1,ARG2,ARG3) \
modtronix 1:71204b8406f2 651 ({ \
modtronix 1:71204b8406f2 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
modtronix 1:71204b8406f2 653 if (ARG3 == 0) \
modtronix 1:71204b8406f2 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
modtronix 1:71204b8406f2 655 else \
modtronix 1:71204b8406f2 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
modtronix 1:71204b8406f2 657 __RES; \
modtronix 1:71204b8406f2 658 })
modtronix 1:71204b8406f2 659
modtronix 1:71204b8406f2 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
modtronix 1:71204b8406f2 661 {
modtronix 1:71204b8406f2 662 int32_t result;
modtronix 1:71204b8406f2 663
modtronix 1:71204b8406f2 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
modtronix 1:71204b8406f2 665 return(result);
modtronix 1:71204b8406f2 666 }
modtronix 1:71204b8406f2 667
modtronix 1:71204b8406f2 668
modtronix 1:71204b8406f2 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
modtronix 1:71204b8406f2 670 /* IAR iccarm specific functions */
modtronix 1:71204b8406f2 671 #include <cmsis_iar.h>
modtronix 1:71204b8406f2 672
modtronix 1:71204b8406f2 673
modtronix 1:71204b8406f2 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
modtronix 1:71204b8406f2 675 /* TI CCS specific functions */
modtronix 1:71204b8406f2 676 #include <cmsis_ccs.h>
modtronix 1:71204b8406f2 677
modtronix 1:71204b8406f2 678
modtronix 1:71204b8406f2 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
modtronix 1:71204b8406f2 680 /* TASKING carm specific functions */
modtronix 1:71204b8406f2 681 /* not yet supported */
modtronix 1:71204b8406f2 682
modtronix 1:71204b8406f2 683
modtronix 1:71204b8406f2 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
modtronix 1:71204b8406f2 685 /* Cosmic specific functions */
modtronix 1:71204b8406f2 686 #include <cmsis_csm.h>
modtronix 1:71204b8406f2 687
modtronix 1:71204b8406f2 688 #endif
modtronix 1:71204b8406f2 689
modtronix 1:71204b8406f2 690 /*@} end of group CMSIS_SIMD_intrinsics */
modtronix 1:71204b8406f2 691
modtronix 1:71204b8406f2 692
modtronix 1:71204b8406f2 693 #ifdef __cplusplus
modtronix 1:71204b8406f2 694 }
modtronix 1:71204b8406f2 695 #endif
modtronix 1:71204b8406f2 696
modtronix 1:71204b8406f2 697 #endif /* __CORE_CMSIMD_H */