modtronix H / mbed_nz32sc151

mbed library for NZ32-SC151

targets/cmsis/core_cm7.h@17:639ed60ce759, 2016-08-19 (annotated)

Committer:
modtronix-com
Date:
Fri Aug 19 15:46:42 2016 +1000
Revision:
17:639ed60ce759
Parent:
10:6444e6c798ce 
Added tag v1.1 for changeset 076cbe3e55be

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:71204b8406f2 1 /**************************************************************************//**
modtronix 1:71204b8406f2 2 * @file core_cm7.h
modtronix 1:71204b8406f2 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
modtronix 10:6444e6c798ce 4 * @version V4.00
modtronix 10:6444e6c798ce 5 * @date 01. September 2014
modtronix 1:71204b8406f2 6 *
modtronix 1:71204b8406f2 7 * @note
modtronix 1:71204b8406f2 8 *
modtronix 1:71204b8406f2 9 ******************************************************************************/
modtronix 10:6444e6c798ce 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
modtronix 1:71204b8406f2 11
modtronix 1:71204b8406f2 12 All rights reserved.
modtronix 1:71204b8406f2 13 Redistribution and use in source and binary forms, with or without
modtronix 1:71204b8406f2 14 modification, are permitted provided that the following conditions are met:
modtronix 1:71204b8406f2 15 - Redistributions of source code must retain the above copyright
modtronix 1:71204b8406f2 16 notice, this list of conditions and the following disclaimer.
modtronix 1:71204b8406f2 17 - Redistributions in binary form must reproduce the above copyright
modtronix 1:71204b8406f2 18 notice, this list of conditions and the following disclaimer in the
modtronix 1:71204b8406f2 19 documentation and/or other materials provided with the distribution.
modtronix 1:71204b8406f2 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 1:71204b8406f2 21 to endorse or promote products derived from this software without
modtronix 1:71204b8406f2 22 specific prior written permission.
modtronix 1:71204b8406f2 23 *
modtronix 1:71204b8406f2 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 1:71204b8406f2 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 1:71204b8406f2 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 1:71204b8406f2 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 1:71204b8406f2 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 1:71204b8406f2 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 1:71204b8406f2 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 1:71204b8406f2 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 1:71204b8406f2 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 1:71204b8406f2 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 1:71204b8406f2 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 1:71204b8406f2 35 ---------------------------------------------------------------------------*/
modtronix 1:71204b8406f2 36
modtronix 1:71204b8406f2 37
modtronix 1:71204b8406f2 38 #if defined ( __ICCARM__ )
modtronix 1:71204b8406f2 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 1:71204b8406f2 40 #endif
modtronix 1:71204b8406f2 41
modtronix 1:71204b8406f2 42 #ifndef __CORE_CM7_H_GENERIC
modtronix 1:71204b8406f2 43 #define __CORE_CM7_H_GENERIC
modtronix 1:71204b8406f2 44
modtronix 1:71204b8406f2 45 #ifdef __cplusplus
modtronix 1:71204b8406f2 46 extern "C" {
modtronix 1:71204b8406f2 47 #endif
modtronix 1:71204b8406f2 48
modtronix 1:71204b8406f2 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
modtronix 1:71204b8406f2 50 CMSIS violates the following MISRA-C:2004 rules:
modtronix 1:71204b8406f2 51
modtronix 1:71204b8406f2 52 \li Required Rule 8.5, object/function definition in header file.<br>
modtronix 1:71204b8406f2 53 Function definitions in header files are used to allow 'inlining'.
modtronix 1:71204b8406f2 54
modtronix 1:71204b8406f2 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
modtronix 1:71204b8406f2 56 Unions are used for effective representation of core registers.
modtronix 1:71204b8406f2 57
modtronix 1:71204b8406f2 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
modtronix 1:71204b8406f2 59 Function-like macros are used to allow more efficient code.
modtronix 1:71204b8406f2 60 */
modtronix 1:71204b8406f2 61
modtronix 1:71204b8406f2 62
modtronix 1:71204b8406f2 63 /*******************************************************************************
modtronix 1:71204b8406f2 64 * CMSIS definitions
modtronix 1:71204b8406f2 65 ******************************************************************************/
modtronix 1:71204b8406f2 66 /** \ingroup Cortex_M7
modtronix 1:71204b8406f2 67 @{
modtronix 1:71204b8406f2 68 */
modtronix 1:71204b8406f2 69
modtronix 1:71204b8406f2 70 /* CMSIS CM7 definitions */
modtronix 1:71204b8406f2 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
modtronix 1:71204b8406f2 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
modtronix 1:71204b8406f2 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
modtronix 1:71204b8406f2 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
modtronix 1:71204b8406f2 75
modtronix 1:71204b8406f2 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
modtronix 1:71204b8406f2 77
modtronix 1:71204b8406f2 78
modtronix 1:71204b8406f2 79 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
modtronix 1:71204b8406f2 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
modtronix 1:71204b8406f2 82 #define __STATIC_INLINE static __inline
modtronix 1:71204b8406f2 83
modtronix 1:71204b8406f2 84 #elif defined ( __GNUC__ )
modtronix 1:71204b8406f2 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
modtronix 1:71204b8406f2 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
modtronix 1:71204b8406f2 87 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 88
modtronix 1:71204b8406f2 89 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
modtronix 1:71204b8406f2 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
modtronix 1:71204b8406f2 92 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 93
modtronix 1:71204b8406f2 94 #elif defined ( __TMS470__ )
modtronix 1:71204b8406f2 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
modtronix 1:71204b8406f2 96 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 97
modtronix 1:71204b8406f2 98 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
modtronix 1:71204b8406f2 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
modtronix 1:71204b8406f2 101 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 102
modtronix 1:71204b8406f2 103 #elif defined ( __CSMC__ )
modtronix 1:71204b8406f2 104 #define __packed
modtronix 1:71204b8406f2 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
modtronix 1:71204b8406f2 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
modtronix 1:71204b8406f2 107 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 108
modtronix 1:71204b8406f2 109 #endif
modtronix 1:71204b8406f2 110
modtronix 1:71204b8406f2 111 /** __FPU_USED indicates whether an FPU is used or not.
modtronix 1:71204b8406f2 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
modtronix 1:71204b8406f2 113 */
modtronix 1:71204b8406f2 114 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 115 #if defined __TARGET_FPU_VFP
modtronix 1:71204b8406f2 116 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 117 #define __FPU_USED 1
modtronix 1:71204b8406f2 118 #else
modtronix 1:71204b8406f2 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 120 #define __FPU_USED 0
modtronix 1:71204b8406f2 121 #endif
modtronix 1:71204b8406f2 122 #else
modtronix 1:71204b8406f2 123 #define __FPU_USED 0
modtronix 1:71204b8406f2 124 #endif
modtronix 1:71204b8406f2 125
modtronix 1:71204b8406f2 126 #elif defined ( __GNUC__ )
modtronix 1:71204b8406f2 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
modtronix 1:71204b8406f2 128 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 129 #define __FPU_USED 1
modtronix 1:71204b8406f2 130 #else
modtronix 1:71204b8406f2 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 132 #define __FPU_USED 0
modtronix 1:71204b8406f2 133 #endif
modtronix 1:71204b8406f2 134 #else
modtronix 1:71204b8406f2 135 #define __FPU_USED 0
modtronix 1:71204b8406f2 136 #endif
modtronix 1:71204b8406f2 137
modtronix 1:71204b8406f2 138 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 139 #if defined __ARMVFP__
modtronix 1:71204b8406f2 140 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 141 #define __FPU_USED 1
modtronix 1:71204b8406f2 142 #else
modtronix 1:71204b8406f2 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 144 #define __FPU_USED 0
modtronix 1:71204b8406f2 145 #endif
modtronix 1:71204b8406f2 146 #else
modtronix 1:71204b8406f2 147 #define __FPU_USED 0
modtronix 1:71204b8406f2 148 #endif
modtronix 1:71204b8406f2 149
modtronix 1:71204b8406f2 150 #elif defined ( __TMS470__ )
modtronix 1:71204b8406f2 151 #if defined __TI_VFP_SUPPORT__
modtronix 1:71204b8406f2 152 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 153 #define __FPU_USED 1
modtronix 1:71204b8406f2 154 #else
modtronix 1:71204b8406f2 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 156 #define __FPU_USED 0
modtronix 1:71204b8406f2 157 #endif
modtronix 1:71204b8406f2 158 #else
modtronix 1:71204b8406f2 159 #define __FPU_USED 0
modtronix 1:71204b8406f2 160 #endif
modtronix 1:71204b8406f2 161
modtronix 1:71204b8406f2 162 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 163 #if defined __FPU_VFP__
modtronix 1:71204b8406f2 164 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 165 #define __FPU_USED 1
modtronix 1:71204b8406f2 166 #else
modtronix 1:71204b8406f2 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 168 #define __FPU_USED 0
modtronix 1:71204b8406f2 169 #endif
modtronix 1:71204b8406f2 170 #else
modtronix 1:71204b8406f2 171 #define __FPU_USED 0
modtronix 1:71204b8406f2 172 #endif
modtronix 1:71204b8406f2 173
modtronix 1:71204b8406f2 174 #elif defined ( __CSMC__ ) /* Cosmic */
modtronix 1:71204b8406f2 175 #if ( __CSMC__ & 0x400) // FPU present for parser
modtronix 1:71204b8406f2 176 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 177 #define __FPU_USED 1
modtronix 1:71204b8406f2 178 #else
modtronix 1:71204b8406f2 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 180 #define __FPU_USED 0
modtronix 1:71204b8406f2 181 #endif
modtronix 1:71204b8406f2 182 #else
modtronix 1:71204b8406f2 183 #define __FPU_USED 0
modtronix 1:71204b8406f2 184 #endif
modtronix 1:71204b8406f2 185 #endif
modtronix 1:71204b8406f2 186
modtronix 1:71204b8406f2 187 #include <stdint.h> /* standard types definitions */
modtronix 1:71204b8406f2 188 #include <core_cmInstr.h> /* Core Instruction Access */
modtronix 1:71204b8406f2 189 #include <core_cmFunc.h> /* Core Function Access */
modtronix 1:71204b8406f2 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
modtronix 1:71204b8406f2 191
modtronix 1:71204b8406f2 192 #ifdef __cplusplus
modtronix 1:71204b8406f2 193 }
modtronix 1:71204b8406f2 194 #endif
modtronix 1:71204b8406f2 195
modtronix 1:71204b8406f2 196 #endif /* __CORE_CM7_H_GENERIC */
modtronix 1:71204b8406f2 197
modtronix 1:71204b8406f2 198 #ifndef __CMSIS_GENERIC
modtronix 1:71204b8406f2 199
modtronix 1:71204b8406f2 200 #ifndef __CORE_CM7_H_DEPENDANT
modtronix 1:71204b8406f2 201 #define __CORE_CM7_H_DEPENDANT
modtronix 1:71204b8406f2 202
modtronix 1:71204b8406f2 203 #ifdef __cplusplus
modtronix 1:71204b8406f2 204 extern "C" {
modtronix 1:71204b8406f2 205 #endif
modtronix 1:71204b8406f2 206
modtronix 1:71204b8406f2 207 /* check device defines and use defaults */
modtronix 1:71204b8406f2 208 #if defined __CHECK_DEVICE_DEFINES
modtronix 1:71204b8406f2 209 #ifndef __CM7_REV
modtronix 1:71204b8406f2 210 #define __CM7_REV 0x0000
modtronix 1:71204b8406f2 211 #warning "__CM7_REV not defined in device header file; using default!"
modtronix 1:71204b8406f2 212 #endif
modtronix 1:71204b8406f2 213
modtronix 1:71204b8406f2 214 #ifndef __FPU_PRESENT
modtronix 1:71204b8406f2 215 #define __FPU_PRESENT 0
modtronix 1:71204b8406f2 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 217 #endif
modtronix 1:71204b8406f2 218
modtronix 1:71204b8406f2 219 #ifndef __MPU_PRESENT
modtronix 1:71204b8406f2 220 #define __MPU_PRESENT 0
modtronix 1:71204b8406f2 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 222 #endif
modtronix 1:71204b8406f2 223
modtronix 1:71204b8406f2 224 #ifndef __ICACHE_PRESENT
modtronix 1:71204b8406f2 225 #define __ICACHE_PRESENT 0
modtronix 1:71204b8406f2 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 227 #endif
modtronix 1:71204b8406f2 228
modtronix 1:71204b8406f2 229 #ifndef __DCACHE_PRESENT
modtronix 1:71204b8406f2 230 #define __DCACHE_PRESENT 0
modtronix 1:71204b8406f2 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 232 #endif
modtronix 1:71204b8406f2 233
modtronix 1:71204b8406f2 234 #ifndef __DTCM_PRESENT
modtronix 1:71204b8406f2 235 #define __DTCM_PRESENT 0
modtronix 1:71204b8406f2 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 237 #endif
modtronix 1:71204b8406f2 238
modtronix 1:71204b8406f2 239 #ifndef __NVIC_PRIO_BITS
modtronix 1:71204b8406f2 240 #define __NVIC_PRIO_BITS 3
modtronix 1:71204b8406f2 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
modtronix 1:71204b8406f2 242 #endif
modtronix 1:71204b8406f2 243
modtronix 1:71204b8406f2 244 #ifndef __Vendor_SysTickConfig
modtronix 1:71204b8406f2 245 #define __Vendor_SysTickConfig 0
modtronix 1:71204b8406f2 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
modtronix 1:71204b8406f2 247 #endif
modtronix 1:71204b8406f2 248 #endif
modtronix 1:71204b8406f2 249
modtronix 1:71204b8406f2 250 /* IO definitions (access restrictions to peripheral registers) */
modtronix 1:71204b8406f2 251 /**
modtronix 1:71204b8406f2 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
modtronix 1:71204b8406f2 253
modtronix 1:71204b8406f2 254 <strong>IO Type Qualifiers</strong> are used
modtronix 1:71204b8406f2 255 \li to specify the access to peripheral variables.
modtronix 1:71204b8406f2 256 \li for automatic generation of peripheral register debug information.
modtronix 1:71204b8406f2 257 */
modtronix 1:71204b8406f2 258 #ifdef __cplusplus
modtronix 1:71204b8406f2 259 #define __I volatile /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 260 #else
modtronix 1:71204b8406f2 261 #define __I volatile const /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 262 #endif
modtronix 1:71204b8406f2 263 #define __O volatile /*!< Defines 'write only' permissions */
modtronix 1:71204b8406f2 264 #define __IO volatile /*!< Defines 'read / write' permissions */
modtronix 1:71204b8406f2 265
modtronix 1:71204b8406f2 266 /*@} end of group Cortex_M7 */
modtronix 1:71204b8406f2 267
modtronix 1:71204b8406f2 268
modtronix 1:71204b8406f2 269
modtronix 1:71204b8406f2 270 /*******************************************************************************
modtronix 1:71204b8406f2 271 * Register Abstraction
modtronix 1:71204b8406f2 272 Core Register contain:
modtronix 1:71204b8406f2 273 - Core Register
modtronix 1:71204b8406f2 274 - Core NVIC Register
modtronix 1:71204b8406f2 275 - Core SCB Register
modtronix 1:71204b8406f2 276 - Core SysTick Register
modtronix 1:71204b8406f2 277 - Core Debug Register
modtronix 1:71204b8406f2 278 - Core MPU Register
modtronix 1:71204b8406f2 279 - Core FPU Register
modtronix 1:71204b8406f2 280 ******************************************************************************/
modtronix 1:71204b8406f2 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
modtronix 1:71204b8406f2 282 \brief Type definitions and defines for Cortex-M processor based devices.
modtronix 1:71204b8406f2 283 */
modtronix 1:71204b8406f2 284
modtronix 1:71204b8406f2 285 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 286 \defgroup CMSIS_CORE Status and Control Registers
modtronix 1:71204b8406f2 287 \brief Core Register type definitions.
modtronix 1:71204b8406f2 288 @{
modtronix 1:71204b8406f2 289 */
modtronix 1:71204b8406f2 290
modtronix 1:71204b8406f2 291 /** \brief Union type to access the Application Program Status Register (APSR).
modtronix 1:71204b8406f2 292 */
modtronix 1:71204b8406f2 293 typedef union
modtronix 1:71204b8406f2 294 {
modtronix 1:71204b8406f2 295 struct
modtronix 1:71204b8406f2 296 {
modtronix 10:6444e6c798ce 297 #if (__CORTEX_M != 0x07)
modtronix 10:6444e6c798ce 298 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
modtronix 10:6444e6c798ce 299 #else
modtronix 1:71204b8406f2 300 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
modtronix 1:71204b8406f2 301 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 302 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
modtronix 10:6444e6c798ce 303 #endif
modtronix 1:71204b8406f2 304 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 305 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 306 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 307 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 308 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 309 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 310 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 311 } APSR_Type;
modtronix 1:71204b8406f2 312
modtronix 1:71204b8406f2 313
modtronix 1:71204b8406f2 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
modtronix 1:71204b8406f2 315 */
modtronix 1:71204b8406f2 316 typedef union
modtronix 1:71204b8406f2 317 {
modtronix 1:71204b8406f2 318 struct
modtronix 1:71204b8406f2 319 {
modtronix 1:71204b8406f2 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
modtronix 1:71204b8406f2 322 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 323 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 324 } IPSR_Type;
modtronix 1:71204b8406f2 325
modtronix 1:71204b8406f2 326
modtronix 1:71204b8406f2 327 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
modtronix 1:71204b8406f2 328 */
modtronix 1:71204b8406f2 329 typedef union
modtronix 1:71204b8406f2 330 {
modtronix 1:71204b8406f2 331 struct
modtronix 1:71204b8406f2 332 {
modtronix 1:71204b8406f2 333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 10:6444e6c798ce 334 #if (__CORTEX_M != 0x07)
modtronix 10:6444e6c798ce 335 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
modtronix 10:6444e6c798ce 336 #else
modtronix 1:71204b8406f2 337 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
modtronix 1:71204b8406f2 338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
modtronix 10:6444e6c798ce 340 #endif
modtronix 1:71204b8406f2 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
modtronix 1:71204b8406f2 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
modtronix 1:71204b8406f2 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 348 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 349 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 350 } xPSR_Type;
modtronix 1:71204b8406f2 351
modtronix 1:71204b8406f2 352
modtronix 1:71204b8406f2 353 /** \brief Union type to access the Control Registers (CONTROL).
modtronix 1:71204b8406f2 354 */
modtronix 1:71204b8406f2 355 typedef union
modtronix 1:71204b8406f2 356 {
modtronix 1:71204b8406f2 357 struct
modtronix 1:71204b8406f2 358 {
modtronix 1:71204b8406f2 359 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
modtronix 1:71204b8406f2 360 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
modtronix 1:71204b8406f2 361 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
modtronix 1:71204b8406f2 362 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
modtronix 1:71204b8406f2 363 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 364 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 365 } CONTROL_Type;
modtronix 1:71204b8406f2 366
modtronix 1:71204b8406f2 367 /*@} end of group CMSIS_CORE */
modtronix 1:71204b8406f2 368
modtronix 1:71204b8406f2 369
modtronix 1:71204b8406f2 370 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 371 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
modtronix 1:71204b8406f2 372 \brief Type definitions for the NVIC Registers
modtronix 1:71204b8406f2 373 @{
modtronix 1:71204b8406f2 374 */
modtronix 1:71204b8406f2 375
modtronix 1:71204b8406f2 376 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
modtronix 1:71204b8406f2 377 */
modtronix 1:71204b8406f2 378 typedef struct
modtronix 1:71204b8406f2 379 {
modtronix 1:71204b8406f2 380 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
modtronix 1:71204b8406f2 381 uint32_t RESERVED0[24];
modtronix 1:71204b8406f2 382 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
modtronix 1:71204b8406f2 383 uint32_t RSERVED1[24];
modtronix 1:71204b8406f2 384 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
modtronix 1:71204b8406f2 385 uint32_t RESERVED2[24];
modtronix 1:71204b8406f2 386 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
modtronix 1:71204b8406f2 387 uint32_t RESERVED3[24];
modtronix 1:71204b8406f2 388 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
modtronix 1:71204b8406f2 389 uint32_t RESERVED4[56];
modtronix 1:71204b8406f2 390 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
modtronix 1:71204b8406f2 391 uint32_t RESERVED5[644];
modtronix 1:71204b8406f2 392 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
modtronix 1:71204b8406f2 393 } NVIC_Type;
modtronix 1:71204b8406f2 394
modtronix 1:71204b8406f2 395 /* Software Triggered Interrupt Register Definitions */
modtronix 1:71204b8406f2 396 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
modtronix 10:6444e6c798ce 397 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
modtronix 1:71204b8406f2 398
modtronix 1:71204b8406f2 399 /*@} end of group CMSIS_NVIC */
modtronix 1:71204b8406f2 400
modtronix 1:71204b8406f2 401
modtronix 1:71204b8406f2 402 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 403 \defgroup CMSIS_SCB System Control Block (SCB)
modtronix 1:71204b8406f2 404 \brief Type definitions for the System Control Block Registers
modtronix 1:71204b8406f2 405 @{
modtronix 1:71204b8406f2 406 */
modtronix 1:71204b8406f2 407
modtronix 1:71204b8406f2 408 /** \brief Structure type to access the System Control Block (SCB).
modtronix 1:71204b8406f2 409 */
modtronix 1:71204b8406f2 410 typedef struct
modtronix 1:71204b8406f2 411 {
modtronix 1:71204b8406f2 412 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
modtronix 1:71204b8406f2 413 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
modtronix 1:71204b8406f2 414 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
modtronix 1:71204b8406f2 415 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
modtronix 1:71204b8406f2 416 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
modtronix 1:71204b8406f2 417 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
modtronix 1:71204b8406f2 418 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
modtronix 1:71204b8406f2 419 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
modtronix 1:71204b8406f2 420 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
modtronix 1:71204b8406f2 421 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
modtronix 1:71204b8406f2 422 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
modtronix 1:71204b8406f2 423 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
modtronix 1:71204b8406f2 424 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
modtronix 1:71204b8406f2 425 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
modtronix 1:71204b8406f2 426 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
modtronix 1:71204b8406f2 427 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
modtronix 1:71204b8406f2 428 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
modtronix 1:71204b8406f2 429 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
modtronix 1:71204b8406f2 430 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
modtronix 1:71204b8406f2 431 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 432 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
modtronix 1:71204b8406f2 433 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
modtronix 1:71204b8406f2 434 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
modtronix 1:71204b8406f2 435 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
modtronix 1:71204b8406f2 436 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
modtronix 1:71204b8406f2 437 uint32_t RESERVED3[93];
modtronix 1:71204b8406f2 438 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
modtronix 1:71204b8406f2 439 uint32_t RESERVED4[15];
modtronix 1:71204b8406f2 440 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
modtronix 1:71204b8406f2 441 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
modtronix 1:71204b8406f2 442 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
modtronix 1:71204b8406f2 443 uint32_t RESERVED5[1];
modtronix 1:71204b8406f2 444 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
modtronix 1:71204b8406f2 445 uint32_t RESERVED6[1];
modtronix 1:71204b8406f2 446 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
modtronix 10:6444e6c798ce 447 __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
modtronix 1:71204b8406f2 448 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
modtronix 1:71204b8406f2 449 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
modtronix 1:71204b8406f2 450 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
modtronix 1:71204b8406f2 451 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
modtronix 1:71204b8406f2 452 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
modtronix 1:71204b8406f2 453 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
modtronix 1:71204b8406f2 454 uint32_t RESERVED7[6];
modtronix 1:71204b8406f2 455 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
modtronix 1:71204b8406f2 456 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
modtronix 1:71204b8406f2 457 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
modtronix 1:71204b8406f2 458 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
modtronix 1:71204b8406f2 459 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
modtronix 1:71204b8406f2 460 uint32_t RESERVED8[1];
modtronix 1:71204b8406f2 461 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
modtronix 1:71204b8406f2 462 } SCB_Type;
modtronix 1:71204b8406f2 463
modtronix 1:71204b8406f2 464 /* SCB CPUID Register Definitions */
modtronix 1:71204b8406f2 465 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
modtronix 1:71204b8406f2 466 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
modtronix 1:71204b8406f2 467
modtronix 1:71204b8406f2 468 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
modtronix 1:71204b8406f2 469 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
modtronix 1:71204b8406f2 470
modtronix 1:71204b8406f2 471 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
modtronix 1:71204b8406f2 472 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
modtronix 1:71204b8406f2 473
modtronix 1:71204b8406f2 474 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
modtronix 1:71204b8406f2 475 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
modtronix 1:71204b8406f2 476
modtronix 1:71204b8406f2 477 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
modtronix 10:6444e6c798ce 478 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
modtronix 1:71204b8406f2 479
modtronix 1:71204b8406f2 480 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 481 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
modtronix 1:71204b8406f2 482 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
modtronix 1:71204b8406f2 483
modtronix 1:71204b8406f2 484 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
modtronix 1:71204b8406f2 485 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
modtronix 1:71204b8406f2 486
modtronix 1:71204b8406f2 487 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
modtronix 1:71204b8406f2 488 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
modtronix 1:71204b8406f2 489
modtronix 1:71204b8406f2 490 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
modtronix 1:71204b8406f2 491 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
modtronix 1:71204b8406f2 492
modtronix 1:71204b8406f2 493 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
modtronix 1:71204b8406f2 494 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
modtronix 1:71204b8406f2 495
modtronix 1:71204b8406f2 496 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
modtronix 1:71204b8406f2 497 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
modtronix 1:71204b8406f2 498
modtronix 1:71204b8406f2 499 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
modtronix 1:71204b8406f2 500 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
modtronix 1:71204b8406f2 501
modtronix 1:71204b8406f2 502 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
modtronix 1:71204b8406f2 503 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
modtronix 1:71204b8406f2 504
modtronix 1:71204b8406f2 505 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
modtronix 1:71204b8406f2 506 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
modtronix 1:71204b8406f2 507
modtronix 1:71204b8406f2 508 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
modtronix 10:6444e6c798ce 509 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
modtronix 1:71204b8406f2 510
modtronix 1:71204b8406f2 511 /* SCB Vector Table Offset Register Definitions */
modtronix 1:71204b8406f2 512 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
modtronix 1:71204b8406f2 513 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 1:71204b8406f2 514
modtronix 1:71204b8406f2 515 /* SCB Application Interrupt and Reset Control Register Definitions */
modtronix 1:71204b8406f2 516 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
modtronix 1:71204b8406f2 517 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
modtronix 1:71204b8406f2 518
modtronix 1:71204b8406f2 519 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
modtronix 1:71204b8406f2 520 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
modtronix 1:71204b8406f2 521
modtronix 1:71204b8406f2 522 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
modtronix 1:71204b8406f2 523 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
modtronix 1:71204b8406f2 524
modtronix 1:71204b8406f2 525 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
modtronix 1:71204b8406f2 526 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
modtronix 1:71204b8406f2 527
modtronix 1:71204b8406f2 528 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
modtronix 1:71204b8406f2 529 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
modtronix 1:71204b8406f2 530
modtronix 1:71204b8406f2 531 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
modtronix 1:71204b8406f2 532 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
modtronix 1:71204b8406f2 533
modtronix 1:71204b8406f2 534 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
modtronix 10:6444e6c798ce 535 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
modtronix 1:71204b8406f2 536
modtronix 1:71204b8406f2 537 /* SCB System Control Register Definitions */
modtronix 1:71204b8406f2 538 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
modtronix 1:71204b8406f2 539 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
modtronix 1:71204b8406f2 540
modtronix 1:71204b8406f2 541 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
modtronix 1:71204b8406f2 542 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
modtronix 1:71204b8406f2 543
modtronix 1:71204b8406f2 544 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
modtronix 1:71204b8406f2 545 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
modtronix 1:71204b8406f2 546
modtronix 1:71204b8406f2 547 /* SCB Configuration Control Register Definitions */
modtronix 1:71204b8406f2 548 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
modtronix 1:71204b8406f2 549 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
modtronix 1:71204b8406f2 550
modtronix 1:71204b8406f2 551 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
modtronix 1:71204b8406f2 552 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
modtronix 1:71204b8406f2 553
modtronix 1:71204b8406f2 554 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
modtronix 1:71204b8406f2 555 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
modtronix 1:71204b8406f2 556
modtronix 1:71204b8406f2 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
modtronix 1:71204b8406f2 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
modtronix 1:71204b8406f2 559
modtronix 1:71204b8406f2 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
modtronix 1:71204b8406f2 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
modtronix 1:71204b8406f2 562
modtronix 1:71204b8406f2 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
modtronix 1:71204b8406f2 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
modtronix 1:71204b8406f2 565
modtronix 1:71204b8406f2 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
modtronix 1:71204b8406f2 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
modtronix 1:71204b8406f2 568
modtronix 1:71204b8406f2 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
modtronix 1:71204b8406f2 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
modtronix 1:71204b8406f2 571
modtronix 1:71204b8406f2 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
modtronix 10:6444e6c798ce 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
modtronix 1:71204b8406f2 574
modtronix 1:71204b8406f2 575 /* SCB System Handler Control and State Register Definitions */
modtronix 1:71204b8406f2 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
modtronix 1:71204b8406f2 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
modtronix 1:71204b8406f2 578
modtronix 1:71204b8406f2 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
modtronix 1:71204b8406f2 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
modtronix 1:71204b8406f2 581
modtronix 1:71204b8406f2 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
modtronix 1:71204b8406f2 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
modtronix 1:71204b8406f2 584
modtronix 1:71204b8406f2 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
modtronix 1:71204b8406f2 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
modtronix 1:71204b8406f2 587
modtronix 1:71204b8406f2 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
modtronix 1:71204b8406f2 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
modtronix 1:71204b8406f2 590
modtronix 1:71204b8406f2 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
modtronix 1:71204b8406f2 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
modtronix 1:71204b8406f2 593
modtronix 1:71204b8406f2 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
modtronix 1:71204b8406f2 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
modtronix 1:71204b8406f2 596
modtronix 1:71204b8406f2 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
modtronix 1:71204b8406f2 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
modtronix 1:71204b8406f2 599
modtronix 1:71204b8406f2 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
modtronix 1:71204b8406f2 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
modtronix 1:71204b8406f2 602
modtronix 1:71204b8406f2 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
modtronix 1:71204b8406f2 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
modtronix 1:71204b8406f2 605
modtronix 1:71204b8406f2 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
modtronix 1:71204b8406f2 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
modtronix 1:71204b8406f2 608
modtronix 1:71204b8406f2 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
modtronix 1:71204b8406f2 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
modtronix 1:71204b8406f2 611
modtronix 1:71204b8406f2 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
modtronix 1:71204b8406f2 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
modtronix 1:71204b8406f2 614
modtronix 1:71204b8406f2 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
modtronix 10:6444e6c798ce 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
modtronix 1:71204b8406f2 617
modtronix 1:71204b8406f2 618 /* SCB Configurable Fault Status Registers Definitions */
modtronix 1:71204b8406f2 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
modtronix 1:71204b8406f2 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
modtronix 1:71204b8406f2 621
modtronix 1:71204b8406f2 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
modtronix 1:71204b8406f2 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
modtronix 1:71204b8406f2 624
modtronix 1:71204b8406f2 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
modtronix 10:6444e6c798ce 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
modtronix 1:71204b8406f2 627
modtronix 1:71204b8406f2 628 /* SCB Hard Fault Status Registers Definitions */
modtronix 1:71204b8406f2 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
modtronix 1:71204b8406f2 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
modtronix 1:71204b8406f2 631
modtronix 1:71204b8406f2 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
modtronix 1:71204b8406f2 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
modtronix 1:71204b8406f2 634
modtronix 1:71204b8406f2 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
modtronix 1:71204b8406f2 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
modtronix 1:71204b8406f2 637
modtronix 1:71204b8406f2 638 /* SCB Debug Fault Status Register Definitions */
modtronix 1:71204b8406f2 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
modtronix 1:71204b8406f2 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
modtronix 1:71204b8406f2 641
modtronix 1:71204b8406f2 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
modtronix 1:71204b8406f2 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
modtronix 1:71204b8406f2 644
modtronix 1:71204b8406f2 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
modtronix 1:71204b8406f2 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
modtronix 1:71204b8406f2 647
modtronix 1:71204b8406f2 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
modtronix 1:71204b8406f2 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
modtronix 1:71204b8406f2 650
modtronix 1:71204b8406f2 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
modtronix 10:6444e6c798ce 652 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
modtronix 1:71204b8406f2 653
modtronix 1:71204b8406f2 654 /* Cache Level ID register */
modtronix 1:71204b8406f2 655 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
modtronix 1:71204b8406f2 656 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
modtronix 1:71204b8406f2 657
modtronix 1:71204b8406f2 658 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
modtronix 1:71204b8406f2 659 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
modtronix 1:71204b8406f2 660
modtronix 1:71204b8406f2 661 /* Cache Type register */
modtronix 1:71204b8406f2 662 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
modtronix 1:71204b8406f2 663 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
modtronix 1:71204b8406f2 664
modtronix 1:71204b8406f2 665 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
modtronix 1:71204b8406f2 666 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
modtronix 1:71204b8406f2 667
modtronix 1:71204b8406f2 668 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
modtronix 1:71204b8406f2 669 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
modtronix 1:71204b8406f2 670
modtronix 1:71204b8406f2 671 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
modtronix 1:71204b8406f2 672 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
modtronix 1:71204b8406f2 673
modtronix 1:71204b8406f2 674 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
modtronix 10:6444e6c798ce 675 #define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */
modtronix 1:71204b8406f2 676
modtronix 1:71204b8406f2 677 /* Cache Size ID Register */
modtronix 1:71204b8406f2 678 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
modtronix 1:71204b8406f2 679 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
modtronix 1:71204b8406f2 680
modtronix 1:71204b8406f2 681 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
modtronix 1:71204b8406f2 682 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
modtronix 1:71204b8406f2 683
modtronix 1:71204b8406f2 684 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
modtronix 1:71204b8406f2 685 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
modtronix 1:71204b8406f2 686
modtronix 1:71204b8406f2 687 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
modtronix 1:71204b8406f2 688 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
modtronix 1:71204b8406f2 689
modtronix 1:71204b8406f2 690 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
modtronix 1:71204b8406f2 691 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
modtronix 1:71204b8406f2 692
modtronix 1:71204b8406f2 693 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
modtronix 1:71204b8406f2 694 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
modtronix 1:71204b8406f2 695
modtronix 1:71204b8406f2 696 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
modtronix 10:6444e6c798ce 697 #define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */
modtronix 1:71204b8406f2 698
modtronix 1:71204b8406f2 699 /* Cache Size Selection Register */
modtronix 10:6444e6c798ce 700 #define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */
modtronix 10:6444e6c798ce 701 #define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
modtronix 1:71204b8406f2 702
modtronix 1:71204b8406f2 703 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
modtronix 10:6444e6c798ce 704 #define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */
modtronix 1:71204b8406f2 705
modtronix 1:71204b8406f2 706 /* SCB Software Triggered Interrupt Register */
modtronix 1:71204b8406f2 707 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
modtronix 10:6444e6c798ce 708 #define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */
modtronix 1:71204b8406f2 709
modtronix 1:71204b8406f2 710 /* Instruction Tightly-Coupled Memory Control Register*/
modtronix 1:71204b8406f2 711 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
modtronix 1:71204b8406f2 712 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
modtronix 1:71204b8406f2 713
modtronix 1:71204b8406f2 714 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
modtronix 10:6444e6c798ce 715 #define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
modtronix 1:71204b8406f2 716
modtronix 1:71204b8406f2 717 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
modtronix 10:6444e6c798ce 718 #define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
modtronix 1:71204b8406f2 719
modtronix 1:71204b8406f2 720 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
modtronix 10:6444e6c798ce 721 #define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */
modtronix 1:71204b8406f2 722
modtronix 1:71204b8406f2 723 /* Data Tightly-Coupled Memory Control Registers */
modtronix 1:71204b8406f2 724 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
modtronix 1:71204b8406f2 725 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
modtronix 1:71204b8406f2 726
modtronix 1:71204b8406f2 727 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
modtronix 1:71204b8406f2 728 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
modtronix 1:71204b8406f2 729
modtronix 1:71204b8406f2 730 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
modtronix 1:71204b8406f2 731 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
modtronix 1:71204b8406f2 732
modtronix 1:71204b8406f2 733 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
modtronix 10:6444e6c798ce 734 #define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */
modtronix 1:71204b8406f2 735
modtronix 1:71204b8406f2 736 /* AHBP Control Register */
modtronix 1:71204b8406f2 737 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
modtronix 1:71204b8406f2 738 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
modtronix 1:71204b8406f2 739
modtronix 1:71204b8406f2 740 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
modtronix 10:6444e6c798ce 741 #define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */
modtronix 1:71204b8406f2 742
modtronix 1:71204b8406f2 743 /* L1 Cache Control Register */
modtronix 1:71204b8406f2 744 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
modtronix 1:71204b8406f2 745 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
modtronix 1:71204b8406f2 746
modtronix 1:71204b8406f2 747 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
modtronix 1:71204b8406f2 748 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
modtronix 1:71204b8406f2 749
modtronix 1:71204b8406f2 750 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
modtronix 10:6444e6c798ce 751 #define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */
modtronix 1:71204b8406f2 752
modtronix 1:71204b8406f2 753 /* AHBS control register */
modtronix 1:71204b8406f2 754 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
modtronix 1:71204b8406f2 755 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
modtronix 1:71204b8406f2 756
modtronix 1:71204b8406f2 757 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
modtronix 1:71204b8406f2 758 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
modtronix 1:71204b8406f2 759
modtronix 1:71204b8406f2 760 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
modtronix 10:6444e6c798ce 761 #define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */
modtronix 1:71204b8406f2 762
modtronix 1:71204b8406f2 763 /* Auxiliary Bus Fault Status Register */
modtronix 1:71204b8406f2 764 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
modtronix 1:71204b8406f2 765 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
modtronix 1:71204b8406f2 766
modtronix 1:71204b8406f2 767 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
modtronix 1:71204b8406f2 768 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
modtronix 1:71204b8406f2 769
modtronix 1:71204b8406f2 770 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
modtronix 1:71204b8406f2 771 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
modtronix 1:71204b8406f2 772
modtronix 1:71204b8406f2 773 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
modtronix 1:71204b8406f2 774 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
modtronix 1:71204b8406f2 775
modtronix 1:71204b8406f2 776 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
modtronix 1:71204b8406f2 777 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
modtronix 1:71204b8406f2 778
modtronix 1:71204b8406f2 779 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
modtronix 10:6444e6c798ce 780 #define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */
modtronix 1:71204b8406f2 781
modtronix 1:71204b8406f2 782 /*@} end of group CMSIS_SCB */
modtronix 1:71204b8406f2 783
modtronix 1:71204b8406f2 784
modtronix 1:71204b8406f2 785 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 786 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
modtronix 1:71204b8406f2 787 \brief Type definitions for the System Control and ID Register not in the SCB
modtronix 1:71204b8406f2 788 @{
modtronix 1:71204b8406f2 789 */
modtronix 1:71204b8406f2 790
modtronix 1:71204b8406f2 791 /** \brief Structure type to access the System Control and ID Register not in the SCB.
modtronix 1:71204b8406f2 792 */
modtronix 1:71204b8406f2 793 typedef struct
modtronix 1:71204b8406f2 794 {
modtronix 1:71204b8406f2 795 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 796 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
modtronix 1:71204b8406f2 797 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
modtronix 1:71204b8406f2 798 } SCnSCB_Type;
modtronix 1:71204b8406f2 799
modtronix 1:71204b8406f2 800 /* Interrupt Controller Type Register Definitions */
modtronix 1:71204b8406f2 801 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
modtronix 10:6444e6c798ce 802 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
modtronix 1:71204b8406f2 803
modtronix 1:71204b8406f2 804 /* Auxiliary Control Register Definitions */
modtronix 1:71204b8406f2 805 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
modtronix 1:71204b8406f2 806 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
modtronix 1:71204b8406f2 807
modtronix 1:71204b8406f2 808 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
modtronix 1:71204b8406f2 809 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
modtronix 1:71204b8406f2 810
modtronix 1:71204b8406f2 811 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
modtronix 1:71204b8406f2 812 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
modtronix 1:71204b8406f2 813
modtronix 1:71204b8406f2 814 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
modtronix 1:71204b8406f2 815 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
modtronix 1:71204b8406f2 816
modtronix 1:71204b8406f2 817 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
modtronix 10:6444e6c798ce 818 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
modtronix 1:71204b8406f2 819
modtronix 1:71204b8406f2 820 /*@} end of group CMSIS_SCnotSCB */
modtronix 1:71204b8406f2 821
modtronix 1:71204b8406f2 822
modtronix 1:71204b8406f2 823 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 824 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
modtronix 1:71204b8406f2 825 \brief Type definitions for the System Timer Registers.
modtronix 1:71204b8406f2 826 @{
modtronix 1:71204b8406f2 827 */
modtronix 1:71204b8406f2 828
modtronix 1:71204b8406f2 829 /** \brief Structure type to access the System Timer (SysTick).
modtronix 1:71204b8406f2 830 */
modtronix 1:71204b8406f2 831 typedef struct
modtronix 1:71204b8406f2 832 {
modtronix 1:71204b8406f2 833 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
modtronix 1:71204b8406f2 834 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
modtronix 1:71204b8406f2 835 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
modtronix 1:71204b8406f2 836 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
modtronix 1:71204b8406f2 837 } SysTick_Type;
modtronix 1:71204b8406f2 838
modtronix 1:71204b8406f2 839 /* SysTick Control / Status Register Definitions */
modtronix 1:71204b8406f2 840 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
modtronix 1:71204b8406f2 841 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
modtronix 1:71204b8406f2 842
modtronix 1:71204b8406f2 843 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
modtronix 1:71204b8406f2 844 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
modtronix 1:71204b8406f2 845
modtronix 1:71204b8406f2 846 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
modtronix 1:71204b8406f2 847 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
modtronix 1:71204b8406f2 848
modtronix 1:71204b8406f2 849 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
modtronix 10:6444e6c798ce 850 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 851
modtronix 1:71204b8406f2 852 /* SysTick Reload Register Definitions */
modtronix 1:71204b8406f2 853 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
modtronix 10:6444e6c798ce 854 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
modtronix 1:71204b8406f2 855
modtronix 1:71204b8406f2 856 /* SysTick Current Register Definitions */
modtronix 1:71204b8406f2 857 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
modtronix 10:6444e6c798ce 858 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
modtronix 1:71204b8406f2 859
modtronix 1:71204b8406f2 860 /* SysTick Calibration Register Definitions */
modtronix 1:71204b8406f2 861 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
modtronix 1:71204b8406f2 862 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
modtronix 1:71204b8406f2 863
modtronix 1:71204b8406f2 864 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
modtronix 1:71204b8406f2 865 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
modtronix 1:71204b8406f2 866
modtronix 1:71204b8406f2 867 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
modtronix 10:6444e6c798ce 868 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
modtronix 1:71204b8406f2 869
modtronix 1:71204b8406f2 870 /*@} end of group CMSIS_SysTick */
modtronix 1:71204b8406f2 871
modtronix 1:71204b8406f2 872
modtronix 1:71204b8406f2 873 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 874 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
modtronix 1:71204b8406f2 875 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
modtronix 1:71204b8406f2 876 @{
modtronix 1:71204b8406f2 877 */
modtronix 1:71204b8406f2 878
modtronix 1:71204b8406f2 879 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
modtronix 1:71204b8406f2 880 */
modtronix 1:71204b8406f2 881 typedef struct
modtronix 1:71204b8406f2 882 {
modtronix 1:71204b8406f2 883 __O union
modtronix 1:71204b8406f2 884 {
modtronix 1:71204b8406f2 885 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
modtronix 1:71204b8406f2 886 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
modtronix 1:71204b8406f2 887 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
modtronix 1:71204b8406f2 888 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
modtronix 1:71204b8406f2 889 uint32_t RESERVED0[864];
modtronix 1:71204b8406f2 890 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
modtronix 1:71204b8406f2 891 uint32_t RESERVED1[15];
modtronix 1:71204b8406f2 892 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
modtronix 1:71204b8406f2 893 uint32_t RESERVED2[15];
modtronix 1:71204b8406f2 894 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
modtronix 1:71204b8406f2 895 uint32_t RESERVED3[29];
modtronix 1:71204b8406f2 896 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
modtronix 1:71204b8406f2 897 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
modtronix 1:71204b8406f2 898 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
modtronix 1:71204b8406f2 899 uint32_t RESERVED4[43];
modtronix 1:71204b8406f2 900 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
modtronix 1:71204b8406f2 901 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
modtronix 1:71204b8406f2 902 uint32_t RESERVED5[6];
modtronix 1:71204b8406f2 903 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
modtronix 1:71204b8406f2 904 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
modtronix 1:71204b8406f2 905 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
modtronix 1:71204b8406f2 906 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
modtronix 1:71204b8406f2 907 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
modtronix 1:71204b8406f2 908 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
modtronix 1:71204b8406f2 909 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
modtronix 1:71204b8406f2 910 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
modtronix 1:71204b8406f2 911 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
modtronix 1:71204b8406f2 912 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
modtronix 1:71204b8406f2 913 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
modtronix 1:71204b8406f2 914 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
modtronix 1:71204b8406f2 915 } ITM_Type;
modtronix 1:71204b8406f2 916
modtronix 1:71204b8406f2 917 /* ITM Trace Privilege Register Definitions */
modtronix 1:71204b8406f2 918 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
modtronix 10:6444e6c798ce 919 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
modtronix 1:71204b8406f2 920
modtronix 1:71204b8406f2 921 /* ITM Trace Control Register Definitions */
modtronix 1:71204b8406f2 922 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
modtronix 1:71204b8406f2 923 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
modtronix 1:71204b8406f2 924
modtronix 1:71204b8406f2 925 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
modtronix 1:71204b8406f2 926 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
modtronix 1:71204b8406f2 927
modtronix 1:71204b8406f2 928 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
modtronix 1:71204b8406f2 929 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
modtronix 1:71204b8406f2 930
modtronix 1:71204b8406f2 931 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
modtronix 1:71204b8406f2 932 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
modtronix 1:71204b8406f2 933
modtronix 1:71204b8406f2 934 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
modtronix 1:71204b8406f2 935 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
modtronix 1:71204b8406f2 936
modtronix 1:71204b8406f2 937 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
modtronix 1:71204b8406f2 938 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
modtronix 1:71204b8406f2 939
modtronix 1:71204b8406f2 940 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
modtronix 1:71204b8406f2 941 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
modtronix 1:71204b8406f2 942
modtronix 1:71204b8406f2 943 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
modtronix 1:71204b8406f2 944 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
modtronix 1:71204b8406f2 945
modtronix 1:71204b8406f2 946 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
modtronix 10:6444e6c798ce 947 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
modtronix 1:71204b8406f2 948
modtronix 1:71204b8406f2 949 /* ITM Integration Write Register Definitions */
modtronix 1:71204b8406f2 950 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
modtronix 10:6444e6c798ce 951 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
modtronix 1:71204b8406f2 952
modtronix 1:71204b8406f2 953 /* ITM Integration Read Register Definitions */
modtronix 1:71204b8406f2 954 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
modtronix 10:6444e6c798ce 955 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
modtronix 1:71204b8406f2 956
modtronix 1:71204b8406f2 957 /* ITM Integration Mode Control Register Definitions */
modtronix 1:71204b8406f2 958 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
modtronix 10:6444e6c798ce 959 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
modtronix 1:71204b8406f2 960
modtronix 1:71204b8406f2 961 /* ITM Lock Status Register Definitions */
modtronix 1:71204b8406f2 962 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
modtronix 1:71204b8406f2 963 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
modtronix 1:71204b8406f2 964
modtronix 1:71204b8406f2 965 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
modtronix 1:71204b8406f2 966 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
modtronix 1:71204b8406f2 967
modtronix 1:71204b8406f2 968 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
modtronix 10:6444e6c798ce 969 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
modtronix 1:71204b8406f2 970
modtronix 1:71204b8406f2 971 /*@}*/ /* end of group CMSIS_ITM */
modtronix 1:71204b8406f2 972
modtronix 1:71204b8406f2 973
modtronix 1:71204b8406f2 974 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 975 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
modtronix 1:71204b8406f2 976 \brief Type definitions for the Data Watchpoint and Trace (DWT)
modtronix 1:71204b8406f2 977 @{
modtronix 1:71204b8406f2 978 */
modtronix 1:71204b8406f2 979
modtronix 1:71204b8406f2 980 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
modtronix 1:71204b8406f2 981 */
modtronix 1:71204b8406f2 982 typedef struct
modtronix 1:71204b8406f2 983 {
modtronix 1:71204b8406f2 984 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
modtronix 1:71204b8406f2 985 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
modtronix 1:71204b8406f2 986 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
modtronix 1:71204b8406f2 987 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
modtronix 1:71204b8406f2 988 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
modtronix 1:71204b8406f2 989 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
modtronix 1:71204b8406f2 990 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
modtronix 1:71204b8406f2 991 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
modtronix 1:71204b8406f2 992 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
modtronix 1:71204b8406f2 993 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
modtronix 1:71204b8406f2 994 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
modtronix 1:71204b8406f2 995 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 996 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
modtronix 1:71204b8406f2 997 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
modtronix 1:71204b8406f2 998 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
modtronix 1:71204b8406f2 999 uint32_t RESERVED1[1];
modtronix 1:71204b8406f2 1000 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
modtronix 1:71204b8406f2 1001 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
modtronix 1:71204b8406f2 1002 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
modtronix 1:71204b8406f2 1003 uint32_t RESERVED2[1];
modtronix 1:71204b8406f2 1004 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
modtronix 1:71204b8406f2 1005 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
modtronix 1:71204b8406f2 1006 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
modtronix 1:71204b8406f2 1007 uint32_t RESERVED3[981];
modtronix 1:71204b8406f2 1008 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
modtronix 1:71204b8406f2 1009 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
modtronix 1:71204b8406f2 1010 } DWT_Type;
modtronix 1:71204b8406f2 1011
modtronix 1:71204b8406f2 1012 /* DWT Control Register Definitions */
modtronix 1:71204b8406f2 1013 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
modtronix 1:71204b8406f2 1014 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
modtronix 1:71204b8406f2 1015
modtronix 1:71204b8406f2 1016 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
modtronix 1:71204b8406f2 1017 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
modtronix 1:71204b8406f2 1018
modtronix 1:71204b8406f2 1019 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
modtronix 1:71204b8406f2 1020 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
modtronix 1:71204b8406f2 1021
modtronix 1:71204b8406f2 1022 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
modtronix 1:71204b8406f2 1023 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
modtronix 1:71204b8406f2 1024
modtronix 1:71204b8406f2 1025 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
modtronix 1:71204b8406f2 1026 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
modtronix 1:71204b8406f2 1027
modtronix 1:71204b8406f2 1028 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
modtronix 1:71204b8406f2 1029 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
modtronix 1:71204b8406f2 1030
modtronix 1:71204b8406f2 1031 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
modtronix 1:71204b8406f2 1032 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
modtronix 1:71204b8406f2 1033
modtronix 1:71204b8406f2 1034 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
modtronix 1:71204b8406f2 1035 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
modtronix 1:71204b8406f2 1036
modtronix 1:71204b8406f2 1037 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
modtronix 1:71204b8406f2 1038 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
modtronix 1:71204b8406f2 1039
modtronix 1:71204b8406f2 1040 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
modtronix 1:71204b8406f2 1041 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
modtronix 1:71204b8406f2 1042
modtronix 1:71204b8406f2 1043 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
modtronix 1:71204b8406f2 1044 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
modtronix 1:71204b8406f2 1045
modtronix 1:71204b8406f2 1046 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
modtronix 1:71204b8406f2 1047 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
modtronix 1:71204b8406f2 1048
modtronix 1:71204b8406f2 1049 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
modtronix 1:71204b8406f2 1050 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
modtronix 1:71204b8406f2 1051
modtronix 1:71204b8406f2 1052 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
modtronix 1:71204b8406f2 1053 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
modtronix 1:71204b8406f2 1054
modtronix 1:71204b8406f2 1055 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
modtronix 1:71204b8406f2 1056 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
modtronix 1:71204b8406f2 1057
modtronix 1:71204b8406f2 1058 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
modtronix 1:71204b8406f2 1059 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
modtronix 1:71204b8406f2 1060
modtronix 1:71204b8406f2 1061 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
modtronix 1:71204b8406f2 1062 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
modtronix 1:71204b8406f2 1063
modtronix 1:71204b8406f2 1064 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
modtronix 10:6444e6c798ce 1065 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
modtronix 1:71204b8406f2 1066
modtronix 1:71204b8406f2 1067 /* DWT CPI Count Register Definitions */
modtronix 1:71204b8406f2 1068 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
modtronix 10:6444e6c798ce 1069 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
modtronix 1:71204b8406f2 1070
modtronix 1:71204b8406f2 1071 /* DWT Exception Overhead Count Register Definitions */
modtronix 1:71204b8406f2 1072 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
modtronix 10:6444e6c798ce 1073 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
modtronix 1:71204b8406f2 1074
modtronix 1:71204b8406f2 1075 /* DWT Sleep Count Register Definitions */
modtronix 1:71204b8406f2 1076 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
modtronix 10:6444e6c798ce 1077 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
modtronix 1:71204b8406f2 1078
modtronix 1:71204b8406f2 1079 /* DWT LSU Count Register Definitions */
modtronix 1:71204b8406f2 1080 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
modtronix 10:6444e6c798ce 1081 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
modtronix 1:71204b8406f2 1082
modtronix 1:71204b8406f2 1083 /* DWT Folded-instruction Count Register Definitions */
modtronix 1:71204b8406f2 1084 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
modtronix 10:6444e6c798ce 1085 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
modtronix 1:71204b8406f2 1086
modtronix 1:71204b8406f2 1087 /* DWT Comparator Mask Register Definitions */
modtronix 1:71204b8406f2 1088 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
modtronix 10:6444e6c798ce 1089 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
modtronix 1:71204b8406f2 1090
modtronix 1:71204b8406f2 1091 /* DWT Comparator Function Register Definitions */
modtronix 1:71204b8406f2 1092 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
modtronix 1:71204b8406f2 1093 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
modtronix 1:71204b8406f2 1094
modtronix 1:71204b8406f2 1095 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
modtronix 1:71204b8406f2 1096 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
modtronix 1:71204b8406f2 1097
modtronix 1:71204b8406f2 1098 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
modtronix 1:71204b8406f2 1099 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
modtronix 1:71204b8406f2 1100
modtronix 1:71204b8406f2 1101 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
modtronix 1:71204b8406f2 1102 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
modtronix 1:71204b8406f2 1103
modtronix 1:71204b8406f2 1104 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
modtronix 1:71204b8406f2 1105 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
modtronix 1:71204b8406f2 1106
modtronix 1:71204b8406f2 1107 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
modtronix 1:71204b8406f2 1108 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
modtronix 1:71204b8406f2 1109
modtronix 1:71204b8406f2 1110 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
modtronix 1:71204b8406f2 1111 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
modtronix 1:71204b8406f2 1112
modtronix 1:71204b8406f2 1113 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
modtronix 1:71204b8406f2 1114 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
modtronix 1:71204b8406f2 1115
modtronix 1:71204b8406f2 1116 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
modtronix 10:6444e6c798ce 1117 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
modtronix 1:71204b8406f2 1118
modtronix 1:71204b8406f2 1119 /*@}*/ /* end of group CMSIS_DWT */
modtronix 1:71204b8406f2 1120
modtronix 1:71204b8406f2 1121
modtronix 1:71204b8406f2 1122 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1123 \defgroup CMSIS_TPI Trace Port Interface (TPI)
modtronix 1:71204b8406f2 1124 \brief Type definitions for the Trace Port Interface (TPI)
modtronix 1:71204b8406f2 1125 @{
modtronix 1:71204b8406f2 1126 */
modtronix 1:71204b8406f2 1127
modtronix 1:71204b8406f2 1128 /** \brief Structure type to access the Trace Port Interface Register (TPI).
modtronix 1:71204b8406f2 1129 */
modtronix 1:71204b8406f2 1130 typedef struct
modtronix 1:71204b8406f2 1131 {
modtronix 1:71204b8406f2 1132 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
modtronix 1:71204b8406f2 1133 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
modtronix 1:71204b8406f2 1134 uint32_t RESERVED0[2];
modtronix 1:71204b8406f2 1135 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
modtronix 1:71204b8406f2 1136 uint32_t RESERVED1[55];
modtronix 1:71204b8406f2 1137 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
modtronix 1:71204b8406f2 1138 uint32_t RESERVED2[131];
modtronix 1:71204b8406f2 1139 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
modtronix 1:71204b8406f2 1140 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
modtronix 1:71204b8406f2 1141 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
modtronix 1:71204b8406f2 1142 uint32_t RESERVED3[759];
modtronix 1:71204b8406f2 1143 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
modtronix 1:71204b8406f2 1144 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
modtronix 1:71204b8406f2 1145 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
modtronix 1:71204b8406f2 1146 uint32_t RESERVED4[1];
modtronix 1:71204b8406f2 1147 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
modtronix 1:71204b8406f2 1148 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
modtronix 1:71204b8406f2 1149 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
modtronix 1:71204b8406f2 1150 uint32_t RESERVED5[39];
modtronix 1:71204b8406f2 1151 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
modtronix 1:71204b8406f2 1152 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
modtronix 1:71204b8406f2 1153 uint32_t RESERVED7[8];
modtronix 1:71204b8406f2 1154 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
modtronix 1:71204b8406f2 1155 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
modtronix 1:71204b8406f2 1156 } TPI_Type;
modtronix 1:71204b8406f2 1157
modtronix 1:71204b8406f2 1158 /* TPI Asynchronous Clock Prescaler Register Definitions */
modtronix 1:71204b8406f2 1159 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
modtronix 10:6444e6c798ce 1160 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
modtronix 1:71204b8406f2 1161
modtronix 1:71204b8406f2 1162 /* TPI Selected Pin Protocol Register Definitions */
modtronix 1:71204b8406f2 1163 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
modtronix 10:6444e6c798ce 1164 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
modtronix 1:71204b8406f2 1165
modtronix 1:71204b8406f2 1166 /* TPI Formatter and Flush Status Register Definitions */
modtronix 1:71204b8406f2 1167 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
modtronix 1:71204b8406f2 1168 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
modtronix 1:71204b8406f2 1169
modtronix 1:71204b8406f2 1170 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
modtronix 1:71204b8406f2 1171 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
modtronix 1:71204b8406f2 1172
modtronix 1:71204b8406f2 1173 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
modtronix 1:71204b8406f2 1174 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
modtronix 1:71204b8406f2 1175
modtronix 1:71204b8406f2 1176 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
modtronix 10:6444e6c798ce 1177 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
modtronix 1:71204b8406f2 1178
modtronix 1:71204b8406f2 1179 /* TPI Formatter and Flush Control Register Definitions */
modtronix 1:71204b8406f2 1180 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
modtronix 1:71204b8406f2 1181 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
modtronix 1:71204b8406f2 1182
modtronix 1:71204b8406f2 1183 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
modtronix 1:71204b8406f2 1184 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
modtronix 1:71204b8406f2 1185
modtronix 1:71204b8406f2 1186 /* TPI TRIGGER Register Definitions */
modtronix 1:71204b8406f2 1187 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
modtronix 10:6444e6c798ce 1188 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
modtronix 1:71204b8406f2 1189
modtronix 1:71204b8406f2 1190 /* TPI Integration ETM Data Register Definitions (FIFO0) */
modtronix 1:71204b8406f2 1191 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
modtronix 1:71204b8406f2 1192 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
modtronix 1:71204b8406f2 1193
modtronix 1:71204b8406f2 1194 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
modtronix 1:71204b8406f2 1195 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
modtronix 1:71204b8406f2 1196
modtronix 1:71204b8406f2 1197 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
modtronix 1:71204b8406f2 1198 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
modtronix 1:71204b8406f2 1199
modtronix 1:71204b8406f2 1200 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
modtronix 1:71204b8406f2 1201 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
modtronix 1:71204b8406f2 1202
modtronix 1:71204b8406f2 1203 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
modtronix 1:71204b8406f2 1204 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
modtronix 1:71204b8406f2 1205
modtronix 1:71204b8406f2 1206 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
modtronix 1:71204b8406f2 1207 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
modtronix 1:71204b8406f2 1208
modtronix 1:71204b8406f2 1209 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
modtronix 10:6444e6c798ce 1210 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
modtronix 1:71204b8406f2 1211
modtronix 1:71204b8406f2 1212 /* TPI ITATBCTR2 Register Definitions */
modtronix 1:71204b8406f2 1213 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
modtronix 10:6444e6c798ce 1214 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
modtronix 1:71204b8406f2 1215
modtronix 1:71204b8406f2 1216 /* TPI Integration ITM Data Register Definitions (FIFO1) */
modtronix 1:71204b8406f2 1217 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
modtronix 1:71204b8406f2 1218 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
modtronix 1:71204b8406f2 1219
modtronix 1:71204b8406f2 1220 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
modtronix 1:71204b8406f2 1221 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
modtronix 1:71204b8406f2 1222
modtronix 1:71204b8406f2 1223 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
modtronix 1:71204b8406f2 1224 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
modtronix 1:71204b8406f2 1225
modtronix 1:71204b8406f2 1226 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
modtronix 1:71204b8406f2 1227 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
modtronix 1:71204b8406f2 1228
modtronix 1:71204b8406f2 1229 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
modtronix 1:71204b8406f2 1230 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
modtronix 1:71204b8406f2 1231
modtronix 1:71204b8406f2 1232 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
modtronix 1:71204b8406f2 1233 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
modtronix 1:71204b8406f2 1234
modtronix 1:71204b8406f2 1235 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
modtronix 10:6444e6c798ce 1236 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
modtronix 1:71204b8406f2 1237
modtronix 1:71204b8406f2 1238 /* TPI ITATBCTR0 Register Definitions */
modtronix 1:71204b8406f2 1239 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
modtronix 10:6444e6c798ce 1240 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
modtronix 1:71204b8406f2 1241
modtronix 1:71204b8406f2 1242 /* TPI Integration Mode Control Register Definitions */
modtronix 1:71204b8406f2 1243 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
modtronix 10:6444e6c798ce 1244 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
modtronix 1:71204b8406f2 1245
modtronix 1:71204b8406f2 1246 /* TPI DEVID Register Definitions */
modtronix 1:71204b8406f2 1247 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
modtronix 1:71204b8406f2 1248 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
modtronix 1:71204b8406f2 1249
modtronix 1:71204b8406f2 1250 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
modtronix 1:71204b8406f2 1251 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
modtronix 1:71204b8406f2 1252
modtronix 1:71204b8406f2 1253 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
modtronix 1:71204b8406f2 1254 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
modtronix 1:71204b8406f2 1255
modtronix 1:71204b8406f2 1256 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
modtronix 1:71204b8406f2 1257 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
modtronix 1:71204b8406f2 1258
modtronix 1:71204b8406f2 1259 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
modtronix 1:71204b8406f2 1260 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
modtronix 1:71204b8406f2 1261
modtronix 1:71204b8406f2 1262 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
modtronix 10:6444e6c798ce 1263 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
modtronix 1:71204b8406f2 1264
modtronix 1:71204b8406f2 1265 /* TPI DEVTYPE Register Definitions */
modtronix 10:6444e6c798ce 1266 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
modtronix 10:6444e6c798ce 1267 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
modtronix 10:6444e6c798ce 1268
modtronix 1:71204b8406f2 1269 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
modtronix 1:71204b8406f2 1270 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
modtronix 1:71204b8406f2 1271
modtronix 1:71204b8406f2 1272 /*@}*/ /* end of group CMSIS_TPI */
modtronix 1:71204b8406f2 1273
modtronix 1:71204b8406f2 1274
modtronix 1:71204b8406f2 1275 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 1276 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1277 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 1278 \brief Type definitions for the Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 1279 @{
modtronix 1:71204b8406f2 1280 */
modtronix 1:71204b8406f2 1281
modtronix 1:71204b8406f2 1282 /** \brief Structure type to access the Memory Protection Unit (MPU).
modtronix 1:71204b8406f2 1283 */
modtronix 1:71204b8406f2 1284 typedef struct
modtronix 1:71204b8406f2 1285 {
modtronix 1:71204b8406f2 1286 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
modtronix 1:71204b8406f2 1287 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
modtronix 1:71204b8406f2 1288 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
modtronix 1:71204b8406f2 1289 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
modtronix 1:71204b8406f2 1290 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 1291 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
modtronix 1:71204b8406f2 1292 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1293 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
modtronix 1:71204b8406f2 1294 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1295 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
modtronix 1:71204b8406f2 1296 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
modtronix 1:71204b8406f2 1297 } MPU_Type;
modtronix 1:71204b8406f2 1298
modtronix 1:71204b8406f2 1299 /* MPU Type Register */
modtronix 1:71204b8406f2 1300 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
modtronix 1:71204b8406f2 1301 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
modtronix 1:71204b8406f2 1302
modtronix 1:71204b8406f2 1303 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
modtronix 1:71204b8406f2 1304 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
modtronix 1:71204b8406f2 1305
modtronix 1:71204b8406f2 1306 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
modtronix 10:6444e6c798ce 1307 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
modtronix 1:71204b8406f2 1308
modtronix 1:71204b8406f2 1309 /* MPU Control Register */
modtronix 1:71204b8406f2 1310 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
modtronix 1:71204b8406f2 1311 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
modtronix 1:71204b8406f2 1312
modtronix 1:71204b8406f2 1313 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
modtronix 1:71204b8406f2 1314 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
modtronix 1:71204b8406f2 1315
modtronix 1:71204b8406f2 1316 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
modtronix 10:6444e6c798ce 1317 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 1318
modtronix 1:71204b8406f2 1319 /* MPU Region Number Register */
modtronix 1:71204b8406f2 1320 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
modtronix 10:6444e6c798ce 1321 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
modtronix 1:71204b8406f2 1322
modtronix 1:71204b8406f2 1323 /* MPU Region Base Address Register */
modtronix 1:71204b8406f2 1324 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
modtronix 1:71204b8406f2 1325 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
modtronix 1:71204b8406f2 1326
modtronix 1:71204b8406f2 1327 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
modtronix 1:71204b8406f2 1328 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
modtronix 1:71204b8406f2 1329
modtronix 1:71204b8406f2 1330 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
modtronix 10:6444e6c798ce 1331 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
modtronix 1:71204b8406f2 1332
modtronix 1:71204b8406f2 1333 /* MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 1334 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
modtronix 1:71204b8406f2 1335 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
modtronix 1:71204b8406f2 1336
modtronix 1:71204b8406f2 1337 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
modtronix 1:71204b8406f2 1338 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
modtronix 1:71204b8406f2 1339
modtronix 1:71204b8406f2 1340 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
modtronix 1:71204b8406f2 1341 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
modtronix 1:71204b8406f2 1342
modtronix 1:71204b8406f2 1343 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
modtronix 1:71204b8406f2 1344 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
modtronix 1:71204b8406f2 1345
modtronix 1:71204b8406f2 1346 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
modtronix 1:71204b8406f2 1347 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
modtronix 1:71204b8406f2 1348
modtronix 1:71204b8406f2 1349 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
modtronix 1:71204b8406f2 1350 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
modtronix 1:71204b8406f2 1351
modtronix 1:71204b8406f2 1352 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
modtronix 1:71204b8406f2 1353 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
modtronix 1:71204b8406f2 1354
modtronix 1:71204b8406f2 1355 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
modtronix 1:71204b8406f2 1356 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
modtronix 1:71204b8406f2 1357
modtronix 1:71204b8406f2 1358 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
modtronix 1:71204b8406f2 1359 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
modtronix 1:71204b8406f2 1360
modtronix 1:71204b8406f2 1361 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
modtronix 10:6444e6c798ce 1362 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
modtronix 1:71204b8406f2 1363
modtronix 1:71204b8406f2 1364 /*@} end of group CMSIS_MPU */
modtronix 1:71204b8406f2 1365 #endif
modtronix 1:71204b8406f2 1366
modtronix 1:71204b8406f2 1367
modtronix 1:71204b8406f2 1368 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 1369 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1370 \defgroup CMSIS_FPU Floating Point Unit (FPU)
modtronix 1:71204b8406f2 1371 \brief Type definitions for the Floating Point Unit (FPU)
modtronix 1:71204b8406f2 1372 @{
modtronix 1:71204b8406f2 1373 */
modtronix 1:71204b8406f2 1374
modtronix 1:71204b8406f2 1375 /** \brief Structure type to access the Floating Point Unit (FPU).
modtronix 1:71204b8406f2 1376 */
modtronix 1:71204b8406f2 1377 typedef struct
modtronix 1:71204b8406f2 1378 {
modtronix 1:71204b8406f2 1379 uint32_t RESERVED0[1];
modtronix 1:71204b8406f2 1380 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
modtronix 1:71204b8406f2 1381 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
modtronix 1:71204b8406f2 1382 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
modtronix 1:71204b8406f2 1383 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
modtronix 1:71204b8406f2 1384 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
modtronix 1:71204b8406f2 1385 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
modtronix 1:71204b8406f2 1386 } FPU_Type;
modtronix 1:71204b8406f2 1387
modtronix 1:71204b8406f2 1388 /* Floating-Point Context Control Register */
modtronix 1:71204b8406f2 1389 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
modtronix 1:71204b8406f2 1390 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
modtronix 1:71204b8406f2 1391
modtronix 1:71204b8406f2 1392 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
modtronix 1:71204b8406f2 1393 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
modtronix 1:71204b8406f2 1394
modtronix 1:71204b8406f2 1395 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
modtronix 1:71204b8406f2 1396 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
modtronix 1:71204b8406f2 1397
modtronix 1:71204b8406f2 1398 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
modtronix 1:71204b8406f2 1399 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
modtronix 1:71204b8406f2 1400
modtronix 1:71204b8406f2 1401 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
modtronix 1:71204b8406f2 1402 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
modtronix 1:71204b8406f2 1403
modtronix 1:71204b8406f2 1404 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
modtronix 1:71204b8406f2 1405 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
modtronix 1:71204b8406f2 1406
modtronix 1:71204b8406f2 1407 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
modtronix 1:71204b8406f2 1408 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
modtronix 1:71204b8406f2 1409
modtronix 1:71204b8406f2 1410 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
modtronix 1:71204b8406f2 1411 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
modtronix 1:71204b8406f2 1412
modtronix 1:71204b8406f2 1413 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
modtronix 10:6444e6c798ce 1414 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
modtronix 1:71204b8406f2 1415
modtronix 1:71204b8406f2 1416 /* Floating-Point Context Address Register */
modtronix 1:71204b8406f2 1417 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
modtronix 1:71204b8406f2 1418 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
modtronix 1:71204b8406f2 1419
modtronix 1:71204b8406f2 1420 /* Floating-Point Default Status Control Register */
modtronix 1:71204b8406f2 1421 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
modtronix 1:71204b8406f2 1422 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
modtronix 1:71204b8406f2 1423
modtronix 1:71204b8406f2 1424 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
modtronix 1:71204b8406f2 1425 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
modtronix 1:71204b8406f2 1426
modtronix 1:71204b8406f2 1427 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
modtronix 1:71204b8406f2 1428 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
modtronix 1:71204b8406f2 1429
modtronix 1:71204b8406f2 1430 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
modtronix 1:71204b8406f2 1431 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
modtronix 1:71204b8406f2 1432
modtronix 1:71204b8406f2 1433 /* Media and FP Feature Register 0 */
modtronix 1:71204b8406f2 1434 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
modtronix 1:71204b8406f2 1435 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
modtronix 1:71204b8406f2 1436
modtronix 1:71204b8406f2 1437 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
modtronix 1:71204b8406f2 1438 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
modtronix 1:71204b8406f2 1439
modtronix 1:71204b8406f2 1440 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
modtronix 1:71204b8406f2 1441 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
modtronix 1:71204b8406f2 1442
modtronix 1:71204b8406f2 1443 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
modtronix 1:71204b8406f2 1444 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
modtronix 1:71204b8406f2 1445
modtronix 1:71204b8406f2 1446 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
modtronix 1:71204b8406f2 1447 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
modtronix 1:71204b8406f2 1448
modtronix 1:71204b8406f2 1449 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
modtronix 1:71204b8406f2 1450 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
modtronix 1:71204b8406f2 1451
modtronix 1:71204b8406f2 1452 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
modtronix 1:71204b8406f2 1453 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
modtronix 1:71204b8406f2 1454
modtronix 1:71204b8406f2 1455 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
modtronix 10:6444e6c798ce 1456 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
modtronix 1:71204b8406f2 1457
modtronix 1:71204b8406f2 1458 /* Media and FP Feature Register 1 */
modtronix 1:71204b8406f2 1459 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
modtronix 1:71204b8406f2 1460 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
modtronix 1:71204b8406f2 1461
modtronix 1:71204b8406f2 1462 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
modtronix 1:71204b8406f2 1463 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
modtronix 1:71204b8406f2 1464
modtronix 1:71204b8406f2 1465 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
modtronix 1:71204b8406f2 1466 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
modtronix 1:71204b8406f2 1467
modtronix 1:71204b8406f2 1468 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
modtronix 10:6444e6c798ce 1469 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
modtronix 1:71204b8406f2 1470
modtronix 1:71204b8406f2 1471 /* Media and FP Feature Register 2 */
modtronix 1:71204b8406f2 1472
modtronix 1:71204b8406f2 1473 /*@} end of group CMSIS_FPU */
modtronix 1:71204b8406f2 1474 #endif
modtronix 1:71204b8406f2 1475
modtronix 1:71204b8406f2 1476
modtronix 1:71204b8406f2 1477 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1478 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
modtronix 1:71204b8406f2 1479 \brief Type definitions for the Core Debug Registers
modtronix 1:71204b8406f2 1480 @{
modtronix 1:71204b8406f2 1481 */
modtronix 1:71204b8406f2 1482
modtronix 1:71204b8406f2 1483 /** \brief Structure type to access the Core Debug Register (CoreDebug).
modtronix 1:71204b8406f2 1484 */
modtronix 1:71204b8406f2 1485 typedef struct
modtronix 1:71204b8406f2 1486 {
modtronix 1:71204b8406f2 1487 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
modtronix 1:71204b8406f2 1488 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
modtronix 1:71204b8406f2 1489 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
modtronix 1:71204b8406f2 1490 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
modtronix 1:71204b8406f2 1491 } CoreDebug_Type;
modtronix 1:71204b8406f2 1492
modtronix 1:71204b8406f2 1493 /* Debug Halting Control and Status Register */
modtronix 1:71204b8406f2 1494 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
modtronix 1:71204b8406f2 1495 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
modtronix 1:71204b8406f2 1496
modtronix 1:71204b8406f2 1497 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
modtronix 1:71204b8406f2 1498 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
modtronix 1:71204b8406f2 1499
modtronix 1:71204b8406f2 1500 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
modtronix 1:71204b8406f2 1501 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
modtronix 1:71204b8406f2 1502
modtronix 1:71204b8406f2 1503 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
modtronix 1:71204b8406f2 1504 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
modtronix 1:71204b8406f2 1505
modtronix 1:71204b8406f2 1506 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
modtronix 1:71204b8406f2 1507 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
modtronix 1:71204b8406f2 1508
modtronix 1:71204b8406f2 1509 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
modtronix 1:71204b8406f2 1510 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
modtronix 1:71204b8406f2 1511
modtronix 1:71204b8406f2 1512 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
modtronix 1:71204b8406f2 1513 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
modtronix 1:71204b8406f2 1514
modtronix 1:71204b8406f2 1515 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
modtronix 1:71204b8406f2 1516 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
modtronix 1:71204b8406f2 1517
modtronix 1:71204b8406f2 1518 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
modtronix 1:71204b8406f2 1519 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
modtronix 1:71204b8406f2 1520
modtronix 1:71204b8406f2 1521 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
modtronix 1:71204b8406f2 1522 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
modtronix 1:71204b8406f2 1523
modtronix 1:71204b8406f2 1524 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
modtronix 1:71204b8406f2 1525 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
modtronix 1:71204b8406f2 1526
modtronix 1:71204b8406f2 1527 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
modtronix 10:6444e6c798ce 1528 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
modtronix 1:71204b8406f2 1529
modtronix 1:71204b8406f2 1530 /* Debug Core Register Selector Register */
modtronix 1:71204b8406f2 1531 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
modtronix 1:71204b8406f2 1532 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
modtronix 1:71204b8406f2 1533
modtronix 1:71204b8406f2 1534 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
modtronix 10:6444e6c798ce 1535 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
modtronix 1:71204b8406f2 1536
modtronix 1:71204b8406f2 1537 /* Debug Exception and Monitor Control Register */
modtronix 1:71204b8406f2 1538 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
modtronix 1:71204b8406f2 1539 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
modtronix 1:71204b8406f2 1540
modtronix 1:71204b8406f2 1541 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
modtronix 1:71204b8406f2 1542 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
modtronix 1:71204b8406f2 1543
modtronix 1:71204b8406f2 1544 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
modtronix 1:71204b8406f2 1545 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
modtronix 1:71204b8406f2 1546
modtronix 1:71204b8406f2 1547 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
modtronix 1:71204b8406f2 1548 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
modtronix 1:71204b8406f2 1549
modtronix 1:71204b8406f2 1550 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
modtronix 1:71204b8406f2 1551 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
modtronix 1:71204b8406f2 1552
modtronix 1:71204b8406f2 1553 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
modtronix 1:71204b8406f2 1554 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
modtronix 1:71204b8406f2 1555
modtronix 1:71204b8406f2 1556 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
modtronix 1:71204b8406f2 1557 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
modtronix 1:71204b8406f2 1558
modtronix 1:71204b8406f2 1559 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
modtronix 1:71204b8406f2 1560 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
modtronix 1:71204b8406f2 1561
modtronix 1:71204b8406f2 1562 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
modtronix 1:71204b8406f2 1563 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
modtronix 1:71204b8406f2 1564
modtronix 1:71204b8406f2 1565 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
modtronix 1:71204b8406f2 1566 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
modtronix 1:71204b8406f2 1567
modtronix 1:71204b8406f2 1568 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
modtronix 1:71204b8406f2 1569 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
modtronix 1:71204b8406f2 1570
modtronix 1:71204b8406f2 1571 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
modtronix 1:71204b8406f2 1572 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
modtronix 1:71204b8406f2 1573
modtronix 1:71204b8406f2 1574 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
modtronix 10:6444e6c798ce 1575 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
modtronix 1:71204b8406f2 1576
modtronix 1:71204b8406f2 1577 /*@} end of group CMSIS_CoreDebug */
modtronix 1:71204b8406f2 1578
modtronix 1:71204b8406f2 1579
modtronix 1:71204b8406f2 1580 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 1581 \defgroup CMSIS_core_base Core Definitions
modtronix 1:71204b8406f2 1582 \brief Definitions for base addresses, unions, and structures.
modtronix 1:71204b8406f2 1583 @{
modtronix 1:71204b8406f2 1584 */
modtronix 1:71204b8406f2 1585
modtronix 1:71204b8406f2 1586 /* Memory mapping of Cortex-M4 Hardware */
modtronix 1:71204b8406f2 1587 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
modtronix 1:71204b8406f2 1588 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
modtronix 1:71204b8406f2 1589 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
modtronix 1:71204b8406f2 1590 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
modtronix 1:71204b8406f2 1591 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
modtronix 1:71204b8406f2 1592 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
modtronix 1:71204b8406f2 1593 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
modtronix 1:71204b8406f2 1594 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
modtronix 1:71204b8406f2 1595
modtronix 1:71204b8406f2 1596 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
modtronix 1:71204b8406f2 1597 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
modtronix 1:71204b8406f2 1598 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
modtronix 1:71204b8406f2 1599 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
modtronix 1:71204b8406f2 1600 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
modtronix 1:71204b8406f2 1601 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
modtronix 1:71204b8406f2 1602 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
modtronix 1:71204b8406f2 1603 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
modtronix 1:71204b8406f2 1604
modtronix 1:71204b8406f2 1605 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 1606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 1607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 1608 #endif
modtronix 1:71204b8406f2 1609
modtronix 1:71204b8406f2 1610 #if (__FPU_PRESENT == 1)
modtronix 1:71204b8406f2 1611 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
modtronix 1:71204b8406f2 1612 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
modtronix 1:71204b8406f2 1613 #endif
modtronix 1:71204b8406f2 1614
modtronix 1:71204b8406f2 1615 /*@} */
modtronix 1:71204b8406f2 1616
modtronix 1:71204b8406f2 1617
modtronix 1:71204b8406f2 1618
modtronix 1:71204b8406f2 1619 /*******************************************************************************
modtronix 1:71204b8406f2 1620 * Hardware Abstraction Layer
modtronix 1:71204b8406f2 1621 Core Function Interface contains:
modtronix 1:71204b8406f2 1622 - Core NVIC Functions
modtronix 1:71204b8406f2 1623 - Core SysTick Functions
modtronix 1:71204b8406f2 1624 - Core Debug Functions
modtronix 1:71204b8406f2 1625 - Core Register Access Functions
modtronix 1:71204b8406f2 1626 ******************************************************************************/
modtronix 1:71204b8406f2 1627 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
modtronix 1:71204b8406f2 1628 */
modtronix 1:71204b8406f2 1629
modtronix 1:71204b8406f2 1630
modtronix 1:71204b8406f2 1631
modtronix 1:71204b8406f2 1632 /* ########################## NVIC functions #################################### */
modtronix 1:71204b8406f2 1633 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 1634 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
modtronix 1:71204b8406f2 1635 \brief Functions that manage interrupts and exceptions via the NVIC.
modtronix 1:71204b8406f2 1636 @{
modtronix 1:71204b8406f2 1637 */
modtronix 1:71204b8406f2 1638
modtronix 1:71204b8406f2 1639 /** \brief Set Priority Grouping
modtronix 1:71204b8406f2 1640
modtronix 1:71204b8406f2 1641 The function sets the priority grouping field using the required unlock sequence.
modtronix 1:71204b8406f2 1642 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
modtronix 1:71204b8406f2 1643 Only values from 0..7 are used.
modtronix 1:71204b8406f2 1644 In case of a conflict between priority grouping and available
modtronix 1:71204b8406f2 1645 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
modtronix 1:71204b8406f2 1646
modtronix 1:71204b8406f2 1647 \param [in] PriorityGroup Priority grouping field.
modtronix 1:71204b8406f2 1648 */
modtronix 1:71204b8406f2 1649 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
modtronix 1:71204b8406f2 1650 {
modtronix 1:71204b8406f2 1651 uint32_t reg_value;
modtronix 10:6444e6c798ce 1652 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1653
modtronix 1:71204b8406f2 1654 reg_value = SCB->AIRCR; /* read old register configuration */
modtronix 10:6444e6c798ce 1655 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
modtronix 10:6444e6c798ce 1656 reg_value = (reg_value |
modtronix 10:6444e6c798ce 1657 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 10:6444e6c798ce 1658 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
modtronix 1:71204b8406f2 1659 SCB->AIRCR = reg_value;
modtronix 1:71204b8406f2 1660 }
modtronix 1:71204b8406f2 1661
modtronix 1:71204b8406f2 1662
modtronix 1:71204b8406f2 1663 /** \brief Get Priority Grouping
modtronix 1:71204b8406f2 1664
modtronix 1:71204b8406f2 1665 The function reads the priority grouping field from the NVIC Interrupt Controller.
modtronix 1:71204b8406f2 1666
modtronix 1:71204b8406f2 1667 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
modtronix 1:71204b8406f2 1668 */
modtronix 1:71204b8406f2 1669 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
modtronix 1:71204b8406f2 1670 {
modtronix 10:6444e6c798ce 1671 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
modtronix 1:71204b8406f2 1672 }
modtronix 1:71204b8406f2 1673
modtronix 1:71204b8406f2 1674
modtronix 1:71204b8406f2 1675 /** \brief Enable External Interrupt
modtronix 1:71204b8406f2 1676
modtronix 1:71204b8406f2 1677 The function enables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 1678
modtronix 1:71204b8406f2 1679 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1680 */
modtronix 1:71204b8406f2 1681 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1682 {
modtronix 10:6444e6c798ce 1683 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
modtronix 10:6444e6c798ce 1684 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
modtronix 1:71204b8406f2 1685 }
modtronix 1:71204b8406f2 1686
modtronix 1:71204b8406f2 1687
modtronix 1:71204b8406f2 1688 /** \brief Disable External Interrupt
modtronix 1:71204b8406f2 1689
modtronix 1:71204b8406f2 1690 The function disables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 1691
modtronix 1:71204b8406f2 1692 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1693 */
modtronix 1:71204b8406f2 1694 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1695 {
modtronix 10:6444e6c798ce 1696 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
modtronix 1:71204b8406f2 1697 }
modtronix 1:71204b8406f2 1698
modtronix 1:71204b8406f2 1699
modtronix 1:71204b8406f2 1700 /** \brief Get Pending Interrupt
modtronix 1:71204b8406f2 1701
modtronix 1:71204b8406f2 1702 The function reads the pending register in the NVIC and returns the pending bit
modtronix 1:71204b8406f2 1703 for the specified interrupt.
modtronix 1:71204b8406f2 1704
modtronix 1:71204b8406f2 1705 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1706
modtronix 1:71204b8406f2 1707 \return 0 Interrupt status is not pending.
modtronix 1:71204b8406f2 1708 \return 1 Interrupt status is pending.
modtronix 1:71204b8406f2 1709 */
modtronix 1:71204b8406f2 1710 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1711 {
modtronix 10:6444e6c798ce 1712 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
modtronix 1:71204b8406f2 1713 }
modtronix 1:71204b8406f2 1714
modtronix 1:71204b8406f2 1715
modtronix 1:71204b8406f2 1716 /** \brief Set Pending Interrupt
modtronix 1:71204b8406f2 1717
modtronix 1:71204b8406f2 1718 The function sets the pending bit of an external interrupt.
modtronix 1:71204b8406f2 1719
modtronix 1:71204b8406f2 1720 \param [in] IRQn Interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1721 */
modtronix 1:71204b8406f2 1722 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1723 {
modtronix 10:6444e6c798ce 1724 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
modtronix 1:71204b8406f2 1725 }
modtronix 1:71204b8406f2 1726
modtronix 1:71204b8406f2 1727
modtronix 1:71204b8406f2 1728 /** \brief Clear Pending Interrupt
modtronix 1:71204b8406f2 1729
modtronix 1:71204b8406f2 1730 The function clears the pending bit of an external interrupt.
modtronix 1:71204b8406f2 1731
modtronix 1:71204b8406f2 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 1733 */
modtronix 1:71204b8406f2 1734 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1735 {
modtronix 10:6444e6c798ce 1736 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
modtronix 1:71204b8406f2 1737 }
modtronix 1:71204b8406f2 1738
modtronix 1:71204b8406f2 1739
modtronix 1:71204b8406f2 1740 /** \brief Get Active Interrupt
modtronix 1:71204b8406f2 1741
modtronix 1:71204b8406f2 1742 The function reads the active register in NVIC and returns the active bit.
modtronix 1:71204b8406f2 1743
modtronix 1:71204b8406f2 1744 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1745
modtronix 1:71204b8406f2 1746 \return 0 Interrupt status is not active.
modtronix 1:71204b8406f2 1747 \return 1 Interrupt status is active.
modtronix 1:71204b8406f2 1748 */
modtronix 1:71204b8406f2 1749 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1750 {
modtronix 10:6444e6c798ce 1751 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
modtronix 1:71204b8406f2 1752 }
modtronix 1:71204b8406f2 1753
modtronix 1:71204b8406f2 1754
modtronix 1:71204b8406f2 1755 /** \brief Set Interrupt Priority
modtronix 1:71204b8406f2 1756
modtronix 1:71204b8406f2 1757 The function sets the priority of an interrupt.
modtronix 1:71204b8406f2 1758
modtronix 1:71204b8406f2 1759 \note The priority cannot be set for every core interrupt.
modtronix 1:71204b8406f2 1760
modtronix 1:71204b8406f2 1761 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1762 \param [in] priority Priority to set.
modtronix 1:71204b8406f2 1763 */
modtronix 1:71204b8406f2 1764 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
modtronix 1:71204b8406f2 1765 {
modtronix 10:6444e6c798ce 1766 if(IRQn < 0) {
modtronix 10:6444e6c798ce 1767 SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
modtronix 1:71204b8406f2 1768 else {
modtronix 10:6444e6c798ce 1769 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
modtronix 1:71204b8406f2 1770 }
modtronix 1:71204b8406f2 1771
modtronix 1:71204b8406f2 1772
modtronix 1:71204b8406f2 1773 /** \brief Get Interrupt Priority
modtronix 1:71204b8406f2 1774
modtronix 1:71204b8406f2 1775 The function reads the priority of an interrupt. The interrupt
modtronix 1:71204b8406f2 1776 number can be positive to specify an external (device specific)
modtronix 1:71204b8406f2 1777 interrupt, or negative to specify an internal (core) interrupt.
modtronix 1:71204b8406f2 1778
modtronix 1:71204b8406f2 1779
modtronix 1:71204b8406f2 1780 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 1781 \return Interrupt Priority. Value is aligned automatically to the implemented
modtronix 1:71204b8406f2 1782 priority bits of the microcontroller.
modtronix 1:71204b8406f2 1783 */
modtronix 1:71204b8406f2 1784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
modtronix 1:71204b8406f2 1785 {
modtronix 1:71204b8406f2 1786
modtronix 10:6444e6c798ce 1787 if(IRQn < 0) {
modtronix 10:6444e6c798ce 1788 return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
modtronix 1:71204b8406f2 1789 else {
modtronix 10:6444e6c798ce 1790 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
modtronix 1:71204b8406f2 1791 }
modtronix 1:71204b8406f2 1792
modtronix 1:71204b8406f2 1793
modtronix 1:71204b8406f2 1794 /** \brief Encode Priority
modtronix 1:71204b8406f2 1795
modtronix 1:71204b8406f2 1796 The function encodes the priority for an interrupt with the given priority group,
modtronix 1:71204b8406f2 1797 preemptive priority value, and subpriority value.
modtronix 1:71204b8406f2 1798 In case of a conflict between priority grouping and available
modtronix 1:71204b8406f2 1799 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
modtronix 1:71204b8406f2 1800
modtronix 1:71204b8406f2 1801 \param [in] PriorityGroup Used priority group.
modtronix 1:71204b8406f2 1802 \param [in] PreemptPriority Preemptive priority value (starting from 0).
modtronix 1:71204b8406f2 1803 \param [in] SubPriority Subpriority value (starting from 0).
modtronix 1:71204b8406f2 1804 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
modtronix 1:71204b8406f2 1805 */
modtronix 1:71204b8406f2 1806 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
modtronix 1:71204b8406f2 1807 {
modtronix 10:6444e6c798ce 1808 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1809 uint32_t PreemptPriorityBits;
modtronix 1:71204b8406f2 1810 uint32_t SubPriorityBits;
modtronix 1:71204b8406f2 1811
modtronix 10:6444e6c798ce 1812 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
modtronix 10:6444e6c798ce 1813 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
modtronix 1:71204b8406f2 1814
modtronix 1:71204b8406f2 1815 return (
modtronix 10:6444e6c798ce 1816 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
modtronix 10:6444e6c798ce 1817 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
modtronix 1:71204b8406f2 1818 );
modtronix 1:71204b8406f2 1819 }
modtronix 1:71204b8406f2 1820
modtronix 1:71204b8406f2 1821
modtronix 1:71204b8406f2 1822 /** \brief Decode Priority
modtronix 1:71204b8406f2 1823
modtronix 1:71204b8406f2 1824 The function decodes an interrupt priority value with a given priority group to
modtronix 1:71204b8406f2 1825 preemptive priority value and subpriority value.
modtronix 1:71204b8406f2 1826 In case of a conflict between priority grouping and available
modtronix 1:71204b8406f2 1827 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
modtronix 1:71204b8406f2 1828
modtronix 1:71204b8406f2 1829 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
modtronix 1:71204b8406f2 1830 \param [in] PriorityGroup Used priority group.
modtronix 1:71204b8406f2 1831 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
modtronix 1:71204b8406f2 1832 \param [out] pSubPriority Subpriority value (starting from 0).
modtronix 1:71204b8406f2 1833 */
modtronix 1:71204b8406f2 1834 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
modtronix 1:71204b8406f2 1835 {
modtronix 10:6444e6c798ce 1836 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
modtronix 1:71204b8406f2 1837 uint32_t PreemptPriorityBits;
modtronix 1:71204b8406f2 1838 uint32_t SubPriorityBits;
modtronix 1:71204b8406f2 1839
modtronix 10:6444e6c798ce 1840 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
modtronix 10:6444e6c798ce 1841 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
modtronix 10:6444e6c798ce 1842
modtronix 10:6444e6c798ce 1843 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
modtronix 10:6444e6c798ce 1844 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
modtronix 1:71204b8406f2 1845 }
modtronix 1:71204b8406f2 1846
modtronix 1:71204b8406f2 1847
modtronix 1:71204b8406f2 1848 /** \brief System Reset
modtronix 1:71204b8406f2 1849
modtronix 1:71204b8406f2 1850 The function initiates a system reset request to reset the MCU.
modtronix 1:71204b8406f2 1851 */
modtronix 1:71204b8406f2 1852 __STATIC_INLINE void NVIC_SystemReset(void)
modtronix 1:71204b8406f2 1853 {
modtronix 10:6444e6c798ce 1854 __DSB(); /* Ensure all outstanding memory accesses included
modtronix 10:6444e6c798ce 1855 buffered write are completed before reset */
modtronix 10:6444e6c798ce 1856 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 10:6444e6c798ce 1857 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
modtronix 10:6444e6c798ce 1858 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
modtronix 10:6444e6c798ce 1859 __DSB(); /* Ensure completion of memory access */
modtronix 10:6444e6c798ce 1860 while(1); /* wait until reset */
modtronix 1:71204b8406f2 1861 }
modtronix 1:71204b8406f2 1862
modtronix 1:71204b8406f2 1863 /*@} end of CMSIS_Core_NVICFunctions */
modtronix 1:71204b8406f2 1864
modtronix 1:71204b8406f2 1865
modtronix 1:71204b8406f2 1866 /* ########################## Cache functions #################################### */
modtronix 1:71204b8406f2 1867 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 1868 \defgroup CMSIS_Core_CacheFunctions Cache Functions
modtronix 1:71204b8406f2 1869 \brief Functions that configure Instruction and Data cache.
modtronix 1:71204b8406f2 1870 @{
modtronix 1:71204b8406f2 1871 */
modtronix 1:71204b8406f2 1872
modtronix 1:71204b8406f2 1873 /* Cache Size ID Register Macros */
modtronix 1:71204b8406f2 1874 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
modtronix 1:71204b8406f2 1875 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
modtronix 10:6444e6c798ce 1876 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )
modtronix 1:71204b8406f2 1877
modtronix 1:71204b8406f2 1878
modtronix 1:71204b8406f2 1879 /** \brief Enable I-Cache
modtronix 1:71204b8406f2 1880
modtronix 1:71204b8406f2 1881 The function turns on I-Cache
modtronix 1:71204b8406f2 1882 */
modtronix 10:6444e6c798ce 1883 __STATIC_INLINE void SCB_EnableICache(void)
modtronix 1:71204b8406f2 1884 {
modtronix 1:71204b8406f2 1885 #if (__ICACHE_PRESENT == 1)
modtronix 1:71204b8406f2 1886 __DSB();
modtronix 1:71204b8406f2 1887 __ISB();
modtronix 10:6444e6c798ce 1888 SCB->ICIALLU = 0; // invalidate I-Cache
modtronix 10:6444e6c798ce 1889 SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
modtronix 1:71204b8406f2 1890 __DSB();
modtronix 1:71204b8406f2 1891 __ISB();
modtronix 1:71204b8406f2 1892 #endif
modtronix 1:71204b8406f2 1893 }
modtronix 1:71204b8406f2 1894
modtronix 1:71204b8406f2 1895
modtronix 1:71204b8406f2 1896 /** \brief Disable I-Cache
modtronix 1:71204b8406f2 1897
modtronix 1:71204b8406f2 1898 The function turns off I-Cache
modtronix 1:71204b8406f2 1899 */
modtronix 10:6444e6c798ce 1900 __STATIC_INLINE void SCB_DisableICache(void)
modtronix 1:71204b8406f2 1901 {
modtronix 1:71204b8406f2 1902 #if (__ICACHE_PRESENT == 1)
modtronix 1:71204b8406f2 1903 __DSB();
modtronix 1:71204b8406f2 1904 __ISB();
modtronix 10:6444e6c798ce 1905 SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
modtronix 10:6444e6c798ce 1906 SCB->ICIALLU = 0; // invalidate I-Cache
modtronix 1:71204b8406f2 1907 __DSB();
modtronix 1:71204b8406f2 1908 __ISB();
modtronix 1:71204b8406f2 1909 #endif
modtronix 1:71204b8406f2 1910 }
modtronix 1:71204b8406f2 1911
modtronix 1:71204b8406f2 1912
modtronix 1:71204b8406f2 1913 /** \brief Invalidate I-Cache
modtronix 1:71204b8406f2 1914
modtronix 1:71204b8406f2 1915 The function invalidates I-Cache
modtronix 1:71204b8406f2 1916 */
modtronix 10:6444e6c798ce 1917 __STATIC_INLINE void SCB_InvalidateICache(void)
modtronix 1:71204b8406f2 1918 {
modtronix 1:71204b8406f2 1919 #if (__ICACHE_PRESENT == 1)
modtronix 1:71204b8406f2 1920 __DSB();
modtronix 1:71204b8406f2 1921 __ISB();
modtronix 10:6444e6c798ce 1922 SCB->ICIALLU = 0;
modtronix 1:71204b8406f2 1923 __DSB();
modtronix 1:71204b8406f2 1924 __ISB();
modtronix 1:71204b8406f2 1925 #endif
modtronix 1:71204b8406f2 1926 }
modtronix 1:71204b8406f2 1927
modtronix 1:71204b8406f2 1928
modtronix 1:71204b8406f2 1929 /** \brief Enable D-Cache
modtronix 1:71204b8406f2 1930
modtronix 1:71204b8406f2 1931 The function turns on D-Cache
modtronix 1:71204b8406f2 1932 */
modtronix 10:6444e6c798ce 1933 __STATIC_INLINE void SCB_EnableDCache(void)
modtronix 1:71204b8406f2 1934 {
modtronix 1:71204b8406f2 1935 #if (__DCACHE_PRESENT == 1)
modtronix 1:71204b8406f2 1936 uint32_t ccsidr, sshift, wshift, sw;
modtronix 1:71204b8406f2 1937 uint32_t sets, ways;
modtronix 1:71204b8406f2 1938
modtronix 1:71204b8406f2 1939 ccsidr = SCB->CCSIDR;
modtronix 10:6444e6c798ce 1940 sets = CCSIDR_SETS(ccsidr);
modtronix 10:6444e6c798ce 1941 sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
modtronix 10:6444e6c798ce 1942 ways = CCSIDR_WAYS(ccsidr);
modtronix 10:6444e6c798ce 1943 wshift = __CLZ(ways) & 0x1f;
modtronix 1:71204b8406f2 1944
modtronix 1:71204b8406f2 1945 __DSB();
modtronix 1:71204b8406f2 1946
modtronix 10:6444e6c798ce 1947 do { // invalidate D-Cache
modtronix 10:6444e6c798ce 1948 int32_t tmpways = ways;
modtronix 1:71204b8406f2 1949 do {
modtronix 1:71204b8406f2 1950 sw = ((tmpways << wshift) | (sets << sshift));
modtronix 1:71204b8406f2 1951 SCB->DCISW = sw;
modtronix 1:71204b8406f2 1952 } while(tmpways--);
modtronix 1:71204b8406f2 1953 } while(sets--);
modtronix 1:71204b8406f2 1954 __DSB();
modtronix 1:71204b8406f2 1955
modtronix 10:6444e6c798ce 1956 SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
modtronix 1:71204b8406f2 1957
modtronix 1:71204b8406f2 1958 __DSB();
modtronix 1:71204b8406f2 1959 __ISB();
modtronix 1:71204b8406f2 1960 #endif
modtronix 1:71204b8406f2 1961 }
modtronix 1:71204b8406f2 1962
modtronix 1:71204b8406f2 1963
modtronix 1:71204b8406f2 1964 /** \brief Disable D-Cache
modtronix 1:71204b8406f2 1965
modtronix 1:71204b8406f2 1966 The function turns off D-Cache
modtronix 1:71204b8406f2 1967 */
modtronix 10:6444e6c798ce 1968 __STATIC_INLINE void SCB_DisableDCache(void)
modtronix 1:71204b8406f2 1969 {
modtronix 1:71204b8406f2 1970 #if (__DCACHE_PRESENT == 1)
modtronix 1:71204b8406f2 1971 uint32_t ccsidr, sshift, wshift, sw;
modtronix 1:71204b8406f2 1972 uint32_t sets, ways;
modtronix 1:71204b8406f2 1973
modtronix 1:71204b8406f2 1974 ccsidr = SCB->CCSIDR;
modtronix 10:6444e6c798ce 1975 sets = CCSIDR_SETS(ccsidr);
modtronix 10:6444e6c798ce 1976 sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
modtronix 10:6444e6c798ce 1977 ways = CCSIDR_WAYS(ccsidr);
modtronix 10:6444e6c798ce 1978 wshift = __CLZ(ways) & 0x1f;
modtronix 1:71204b8406f2 1979
modtronix 1:71204b8406f2 1980 __DSB();
modtronix 1:71204b8406f2 1981
modtronix 10:6444e6c798ce 1982 SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
modtronix 1:71204b8406f2 1983
modtronix 1:71204b8406f2 1984 do { // clean & invalidate D-Cache
modtronix 10:6444e6c798ce 1985 int32_t tmpways = ways;
modtronix 1:71204b8406f2 1986 do {
modtronix 1:71204b8406f2 1987 sw = ((tmpways << wshift) | (sets << sshift));
modtronix 1:71204b8406f2 1988 SCB->DCCISW = sw;
modtronix 1:71204b8406f2 1989 } while(tmpways--);
modtronix 1:71204b8406f2 1990 } while(sets--);
modtronix 1:71204b8406f2 1991
modtronix 1:71204b8406f2 1992
modtronix 1:71204b8406f2 1993 __DSB();
modtronix 1:71204b8406f2 1994 __ISB();
modtronix 10:6444e6c798ce 1995 #endif
modtronix 1:71204b8406f2 1996 }
modtronix 1:71204b8406f2 1997
modtronix 1:71204b8406f2 1998
modtronix 1:71204b8406f2 1999 /** \brief Invalidate D-Cache
modtronix 1:71204b8406f2 2000
modtronix 1:71204b8406f2 2001 The function invalidates D-Cache
modtronix 1:71204b8406f2 2002 */
modtronix 10:6444e6c798ce 2003 __STATIC_INLINE void SCB_InvalidateDCache(void)
modtronix 1:71204b8406f2 2004 {
modtronix 1:71204b8406f2 2005 #if (__DCACHE_PRESENT == 1)
modtronix 1:71204b8406f2 2006 uint32_t ccsidr, sshift, wshift, sw;
modtronix 1:71204b8406f2 2007 uint32_t sets, ways;
modtronix 1:71204b8406f2 2008
modtronix 1:71204b8406f2 2009 ccsidr = SCB->CCSIDR;
modtronix 10:6444e6c798ce 2010 sets = CCSIDR_SETS(ccsidr);
modtronix 10:6444e6c798ce 2011 sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
modtronix 10:6444e6c798ce 2012 ways = CCSIDR_WAYS(ccsidr);
modtronix 10:6444e6c798ce 2013 wshift = __CLZ(ways) & 0x1f;
modtronix 1:71204b8406f2 2014
modtronix 1:71204b8406f2 2015 __DSB();
modtronix 1:71204b8406f2 2016
modtronix 1:71204b8406f2 2017 do { // invalidate D-Cache
modtronix 10:6444e6c798ce 2018 int32_t tmpways = ways;
modtronix 1:71204b8406f2 2019 do {
modtronix 1:71204b8406f2 2020 sw = ((tmpways << wshift) | (sets << sshift));
modtronix 1:71204b8406f2 2021 SCB->DCISW = sw;
modtronix 1:71204b8406f2 2022 } while(tmpways--);
modtronix 1:71204b8406f2 2023 } while(sets--);
modtronix 1:71204b8406f2 2024
modtronix 1:71204b8406f2 2025 __DSB();
modtronix 1:71204b8406f2 2026 __ISB();
modtronix 10:6444e6c798ce 2027 #endif
modtronix 1:71204b8406f2 2028 }
modtronix 1:71204b8406f2 2029
modtronix 1:71204b8406f2 2030
modtronix 1:71204b8406f2 2031 /** \brief Clean D-Cache
modtronix 1:71204b8406f2 2032
modtronix 1:71204b8406f2 2033 The function cleans D-Cache
modtronix 1:71204b8406f2 2034 */
modtronix 10:6444e6c798ce 2035 __STATIC_INLINE void SCB_CleanDCache(void)
modtronix 1:71204b8406f2 2036 {
modtronix 1:71204b8406f2 2037 #if (__DCACHE_PRESENT == 1)
modtronix 1:71204b8406f2 2038 uint32_t ccsidr, sshift, wshift, sw;
modtronix 1:71204b8406f2 2039 uint32_t sets, ways;
modtronix 1:71204b8406f2 2040
modtronix 1:71204b8406f2 2041 ccsidr = SCB->CCSIDR;
modtronix 10:6444e6c798ce 2042 sets = CCSIDR_SETS(ccsidr);
modtronix 10:6444e6c798ce 2043 sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
modtronix 10:6444e6c798ce 2044 ways = CCSIDR_WAYS(ccsidr);
modtronix 10:6444e6c798ce 2045 wshift = __CLZ(ways) & 0x1f;
modtronix 1:71204b8406f2 2046
modtronix 1:71204b8406f2 2047 __DSB();
modtronix 1:71204b8406f2 2048
modtronix 1:71204b8406f2 2049 do { // clean D-Cache
modtronix 10:6444e6c798ce 2050 int32_t tmpways = ways;
modtronix 1:71204b8406f2 2051 do {
modtronix 1:71204b8406f2 2052 sw = ((tmpways << wshift) | (sets << sshift));
modtronix 1:71204b8406f2 2053 SCB->DCCSW = sw;
modtronix 1:71204b8406f2 2054 } while(tmpways--);
modtronix 1:71204b8406f2 2055 } while(sets--);
modtronix 1:71204b8406f2 2056
modtronix 1:71204b8406f2 2057 __DSB();
modtronix 1:71204b8406f2 2058 __ISB();
modtronix 10:6444e6c798ce 2059 #endif
modtronix 1:71204b8406f2 2060 }
modtronix 1:71204b8406f2 2061
modtronix 1:71204b8406f2 2062
modtronix 1:71204b8406f2 2063 /** \brief Clean & Invalidate D-Cache
modtronix 1:71204b8406f2 2064
modtronix 1:71204b8406f2 2065 The function cleans and Invalidates D-Cache
modtronix 1:71204b8406f2 2066 */
modtronix 10:6444e6c798ce 2067 __STATIC_INLINE void SCB_CleanInvalidateDCache(void)
modtronix 1:71204b8406f2 2068 {
modtronix 1:71204b8406f2 2069 #if (__DCACHE_PRESENT == 1)
modtronix 1:71204b8406f2 2070 uint32_t ccsidr, sshift, wshift, sw;
modtronix 1:71204b8406f2 2071 uint32_t sets, ways;
modtronix 1:71204b8406f2 2072
modtronix 1:71204b8406f2 2073 ccsidr = SCB->CCSIDR;
modtronix 10:6444e6c798ce 2074 sets = CCSIDR_SETS(ccsidr);
modtronix 10:6444e6c798ce 2075 sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
modtronix 10:6444e6c798ce 2076 ways = CCSIDR_WAYS(ccsidr);
modtronix 10:6444e6c798ce 2077 wshift = __CLZ(ways) & 0x1f;
modtronix 1:71204b8406f2 2078
modtronix 1:71204b8406f2 2079 __DSB();
modtronix 1:71204b8406f2 2080
modtronix 1:71204b8406f2 2081 do { // clean & invalidate D-Cache
modtronix 10:6444e6c798ce 2082 int32_t tmpways = ways;
modtronix 1:71204b8406f2 2083 do {
modtronix 1:71204b8406f2 2084 sw = ((tmpways << wshift) | (sets << sshift));
modtronix 1:71204b8406f2 2085 SCB->DCCISW = sw;
modtronix 1:71204b8406f2 2086 } while(tmpways--);
modtronix 1:71204b8406f2 2087 } while(sets--);
modtronix 1:71204b8406f2 2088
modtronix 1:71204b8406f2 2089 __DSB();
modtronix 1:71204b8406f2 2090 __ISB();
modtronix 10:6444e6c798ce 2091 #endif
modtronix 1:71204b8406f2 2092 }
modtronix 1:71204b8406f2 2093
modtronix 1:71204b8406f2 2094
modtronix 1:71204b8406f2 2095 /*@} end of CMSIS_Core_CacheFunctions */
modtronix 1:71204b8406f2 2096
modtronix 1:71204b8406f2 2097
modtronix 1:71204b8406f2 2098
modtronix 1:71204b8406f2 2099 /* ################################## SysTick function ############################################ */
modtronix 1:71204b8406f2 2100 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 2101 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
modtronix 1:71204b8406f2 2102 \brief Functions that configure the System.
modtronix 1:71204b8406f2 2103 @{
modtronix 1:71204b8406f2 2104 */
modtronix 1:71204b8406f2 2105
modtronix 1:71204b8406f2 2106 #if (__Vendor_SysTickConfig == 0)
modtronix 1:71204b8406f2 2107
modtronix 1:71204b8406f2 2108 /** \brief System Tick Configuration
modtronix 1:71204b8406f2 2109
modtronix 1:71204b8406f2 2110 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
modtronix 1:71204b8406f2 2111 Counter is in free running mode to generate periodic interrupts.
modtronix 1:71204b8406f2 2112
modtronix 1:71204b8406f2 2113 \param [in] ticks Number of ticks between two interrupts.
modtronix 1:71204b8406f2 2114
modtronix 1:71204b8406f2 2115 \return 0 Function succeeded.
modtronix 1:71204b8406f2 2116 \return 1 Function failed.
modtronix 1:71204b8406f2 2117
modtronix 1:71204b8406f2 2118 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
modtronix 1:71204b8406f2 2119 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
modtronix 1:71204b8406f2 2120 must contain a vendor-specific implementation of this function.
modtronix 1:71204b8406f2 2121
modtronix 1:71204b8406f2 2122 */
modtronix 1:71204b8406f2 2123 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
modtronix 1:71204b8406f2 2124 {
modtronix 10:6444e6c798ce 2125 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
modtronix 10:6444e6c798ce 2126
modtronix 10:6444e6c798ce 2127 SysTick->LOAD = ticks - 1; /* set reload register */
modtronix 10:6444e6c798ce 2128 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
modtronix 10:6444e6c798ce 2129 SysTick->VAL = 0; /* Load the SysTick Counter Value */
modtronix 1:71204b8406f2 2130 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
modtronix 1:71204b8406f2 2131 SysTick_CTRL_TICKINT_Msk |
modtronix 10:6444e6c798ce 2132 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
modtronix 10:6444e6c798ce 2133 return (0); /* Function successful */
modtronix 1:71204b8406f2 2134 }
modtronix 1:71204b8406f2 2135
modtronix 1:71204b8406f2 2136 #endif
modtronix 1:71204b8406f2 2137
modtronix 1:71204b8406f2 2138 /*@} end of CMSIS_Core_SysTickFunctions */
modtronix 1:71204b8406f2 2139
modtronix 1:71204b8406f2 2140
modtronix 1:71204b8406f2 2141
modtronix 1:71204b8406f2 2142 /* ##################################### Debug In/Output function ########################################### */
modtronix 1:71204b8406f2 2143 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 2144 \defgroup CMSIS_core_DebugFunctions ITM Functions
modtronix 1:71204b8406f2 2145 \brief Functions that access the ITM debug interface.
modtronix 1:71204b8406f2 2146 @{
modtronix 1:71204b8406f2 2147 */
modtronix 1:71204b8406f2 2148
modtronix 1:71204b8406f2 2149 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
modtronix 1:71204b8406f2 2150 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
modtronix 1:71204b8406f2 2151
modtronix 1:71204b8406f2 2152
modtronix 1:71204b8406f2 2153 /** \brief ITM Send Character
modtronix 1:71204b8406f2 2154
modtronix 1:71204b8406f2 2155 The function transmits a character via the ITM channel 0, and
modtronix 1:71204b8406f2 2156 \li Just returns when no debugger is connected that has booked the output.
modtronix 1:71204b8406f2 2157 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
modtronix 1:71204b8406f2 2158
modtronix 1:71204b8406f2 2159 \param [in] ch Character to transmit.
modtronix 1:71204b8406f2 2160
modtronix 1:71204b8406f2 2161 \returns Character to transmit.
modtronix 1:71204b8406f2 2162 */
modtronix 1:71204b8406f2 2163 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
modtronix 1:71204b8406f2 2164 {
modtronix 10:6444e6c798ce 2165 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
modtronix 10:6444e6c798ce 2166 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
modtronix 1:71204b8406f2 2167 {
modtronix 10:6444e6c798ce 2168 while (ITM->PORT[0].u32 == 0);
modtronix 10:6444e6c798ce 2169 ITM->PORT[0].u8 = (uint8_t) ch;
modtronix 1:71204b8406f2 2170 }
modtronix 1:71204b8406f2 2171 return (ch);
modtronix 1:71204b8406f2 2172 }
modtronix 1:71204b8406f2 2173
modtronix 1:71204b8406f2 2174
modtronix 1:71204b8406f2 2175 /** \brief ITM Receive Character
modtronix 1:71204b8406f2 2176
modtronix 1:71204b8406f2 2177 The function inputs a character via the external variable \ref ITM_RxBuffer.
modtronix 1:71204b8406f2 2178
modtronix 1:71204b8406f2 2179 \return Received character.
modtronix 1:71204b8406f2 2180 \return -1 No character pending.
modtronix 1:71204b8406f2 2181 */
modtronix 1:71204b8406f2 2182 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
modtronix 1:71204b8406f2 2183 int32_t ch = -1; /* no character available */
modtronix 1:71204b8406f2 2184
modtronix 1:71204b8406f2 2185 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
modtronix 1:71204b8406f2 2186 ch = ITM_RxBuffer;
modtronix 1:71204b8406f2 2187 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
modtronix 1:71204b8406f2 2188 }
modtronix 1:71204b8406f2 2189
modtronix 1:71204b8406f2 2190 return (ch);
modtronix 1:71204b8406f2 2191 }
modtronix 1:71204b8406f2 2192
modtronix 1:71204b8406f2 2193
modtronix 1:71204b8406f2 2194 /** \brief ITM Check Character
modtronix 1:71204b8406f2 2195
modtronix 1:71204b8406f2 2196 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
modtronix 1:71204b8406f2 2197
modtronix 1:71204b8406f2 2198 \return 0 No character available.
modtronix 1:71204b8406f2 2199 \return 1 Character available.
modtronix 1:71204b8406f2 2200 */
modtronix 1:71204b8406f2 2201 __STATIC_INLINE int32_t ITM_CheckChar (void) {
modtronix 1:71204b8406f2 2202
modtronix 1:71204b8406f2 2203 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
modtronix 1:71204b8406f2 2204 return (0); /* no character available */
modtronix 1:71204b8406f2 2205 } else {
modtronix 1:71204b8406f2 2206 return (1); /* character available */
modtronix 1:71204b8406f2 2207 }
modtronix 1:71204b8406f2 2208 }
modtronix 1:71204b8406f2 2209
modtronix 1:71204b8406f2 2210 /*@} end of CMSIS_core_DebugFunctions */
modtronix 1:71204b8406f2 2211
modtronix 1:71204b8406f2 2212
modtronix 1:71204b8406f2 2213
modtronix 1:71204b8406f2 2214
modtronix 1:71204b8406f2 2215 #ifdef __cplusplus
modtronix 1:71204b8406f2 2216 }
modtronix 1:71204b8406f2 2217 #endif
modtronix 1:71204b8406f2 2218
modtronix 1:71204b8406f2 2219 #endif /* __CORE_CM7_H_DEPENDANT */
modtronix 1:71204b8406f2 2220
modtronix 1:71204b8406f2 2221 #endif /* __CMSIS_GENERIC */