modtronix H / mbed_nz32sc151

mbed library for NZ32-SC151

targets/cmsis/core_cm0plus.h@17:639ed60ce759, 2016-08-19 (annotated)

Committer:
modtronix-com
Date:
Fri Aug 19 15:46:42 2016 +1000
Revision:
17:639ed60ce759
Parent:
10:6444e6c798ce 
Added tag v1.1 for changeset 076cbe3e55be

Who changed what in which revision?

UserRevisionLine numberNew contents of line
modtronix 1:71204b8406f2 1 /**************************************************************************//**
modtronix 1:71204b8406f2 2 * @file core_cm0plus.h
modtronix 1:71204b8406f2 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
modtronix 10:6444e6c798ce 4 * @version V4.00
modtronix 10:6444e6c798ce 5 * @date 22. August 2014
modtronix 1:71204b8406f2 6 *
modtronix 1:71204b8406f2 7 * @note
modtronix 1:71204b8406f2 8 *
modtronix 1:71204b8406f2 9 ******************************************************************************/
modtronix 10:6444e6c798ce 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
modtronix 1:71204b8406f2 11
modtronix 1:71204b8406f2 12 All rights reserved.
modtronix 1:71204b8406f2 13 Redistribution and use in source and binary forms, with or without
modtronix 1:71204b8406f2 14 modification, are permitted provided that the following conditions are met:
modtronix 1:71204b8406f2 15 - Redistributions of source code must retain the above copyright
modtronix 1:71204b8406f2 16 notice, this list of conditions and the following disclaimer.
modtronix 1:71204b8406f2 17 - Redistributions in binary form must reproduce the above copyright
modtronix 1:71204b8406f2 18 notice, this list of conditions and the following disclaimer in the
modtronix 1:71204b8406f2 19 documentation and/or other materials provided with the distribution.
modtronix 1:71204b8406f2 20 - Neither the name of ARM nor the names of its contributors may be used
modtronix 1:71204b8406f2 21 to endorse or promote products derived from this software without
modtronix 1:71204b8406f2 22 specific prior written permission.
modtronix 1:71204b8406f2 23 *
modtronix 1:71204b8406f2 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
modtronix 1:71204b8406f2 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
modtronix 1:71204b8406f2 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
modtronix 1:71204b8406f2 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
modtronix 1:71204b8406f2 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
modtronix 1:71204b8406f2 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
modtronix 1:71204b8406f2 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
modtronix 1:71204b8406f2 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
modtronix 1:71204b8406f2 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
modtronix 1:71204b8406f2 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
modtronix 1:71204b8406f2 34 POSSIBILITY OF SUCH DAMAGE.
modtronix 1:71204b8406f2 35 ---------------------------------------------------------------------------*/
modtronix 1:71204b8406f2 36
modtronix 1:71204b8406f2 37
modtronix 1:71204b8406f2 38 #if defined ( __ICCARM__ )
modtronix 1:71204b8406f2 39 #pragma system_include /* treat file as system include file for MISRA check */
modtronix 1:71204b8406f2 40 #endif
modtronix 1:71204b8406f2 41
modtronix 10:6444e6c798ce 42 #ifndef __CORE_CM0PLUS_H_GENERIC
modtronix 10:6444e6c798ce 43 #define __CORE_CM0PLUS_H_GENERIC
modtronix 10:6444e6c798ce 44
modtronix 1:71204b8406f2 45 #ifdef __cplusplus
modtronix 1:71204b8406f2 46 extern "C" {
modtronix 1:71204b8406f2 47 #endif
modtronix 1:71204b8406f2 48
modtronix 1:71204b8406f2 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
modtronix 1:71204b8406f2 50 CMSIS violates the following MISRA-C:2004 rules:
modtronix 1:71204b8406f2 51
modtronix 1:71204b8406f2 52 \li Required Rule 8.5, object/function definition in header file.<br>
modtronix 1:71204b8406f2 53 Function definitions in header files are used to allow 'inlining'.
modtronix 1:71204b8406f2 54
modtronix 1:71204b8406f2 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
modtronix 1:71204b8406f2 56 Unions are used for effective representation of core registers.
modtronix 1:71204b8406f2 57
modtronix 1:71204b8406f2 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
modtronix 1:71204b8406f2 59 Function-like macros are used to allow more efficient code.
modtronix 1:71204b8406f2 60 */
modtronix 1:71204b8406f2 61
modtronix 1:71204b8406f2 62
modtronix 1:71204b8406f2 63 /*******************************************************************************
modtronix 1:71204b8406f2 64 * CMSIS definitions
modtronix 1:71204b8406f2 65 ******************************************************************************/
modtronix 1:71204b8406f2 66 /** \ingroup Cortex-M0+
modtronix 1:71204b8406f2 67 @{
modtronix 1:71204b8406f2 68 */
modtronix 1:71204b8406f2 69
modtronix 1:71204b8406f2 70 /* CMSIS CM0P definitions */
modtronix 10:6444e6c798ce 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
modtronix 10:6444e6c798ce 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
modtronix 1:71204b8406f2 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
modtronix 1:71204b8406f2 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
modtronix 1:71204b8406f2 75
modtronix 1:71204b8406f2 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
modtronix 1:71204b8406f2 77
modtronix 1:71204b8406f2 78
modtronix 1:71204b8406f2 79 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
modtronix 1:71204b8406f2 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
modtronix 1:71204b8406f2 82 #define __STATIC_INLINE static __inline
modtronix 1:71204b8406f2 83
modtronix 10:6444e6c798ce 84 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
modtronix 10:6444e6c798ce 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
modtronix 10:6444e6c798ce 87 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 88
modtronix 1:71204b8406f2 89 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
modtronix 1:71204b8406f2 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
modtronix 1:71204b8406f2 92 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 93
modtronix 10:6444e6c798ce 94 #elif defined ( __TMS470__ )
modtronix 10:6444e6c798ce 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
modtronix 1:71204b8406f2 96 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 97
modtronix 1:71204b8406f2 98 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
modtronix 1:71204b8406f2 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
modtronix 1:71204b8406f2 101 #define __STATIC_INLINE static inline
modtronix 1:71204b8406f2 102
modtronix 10:6444e6c798ce 103 #elif defined ( __CSMC__ )
modtronix 10:6444e6c798ce 104 #define __packed
modtronix 10:6444e6c798ce 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
modtronix 10:6444e6c798ce 107 #define __STATIC_INLINE static inline
modtronix 10:6444e6c798ce 108
modtronix 1:71204b8406f2 109 #endif
modtronix 1:71204b8406f2 110
modtronix 10:6444e6c798ce 111 /** __FPU_USED indicates whether an FPU is used or not.
modtronix 10:6444e6c798ce 112 This core does not support an FPU at all
modtronix 1:71204b8406f2 113 */
modtronix 1:71204b8406f2 114 #define __FPU_USED 0
modtronix 1:71204b8406f2 115
modtronix 1:71204b8406f2 116 #if defined ( __CC_ARM )
modtronix 1:71204b8406f2 117 #if defined __TARGET_FPU_VFP
modtronix 1:71204b8406f2 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 119 #endif
modtronix 1:71204b8406f2 120
modtronix 10:6444e6c798ce 121 #elif defined ( __GNUC__ )
modtronix 10:6444e6c798ce 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
modtronix 10:6444e6c798ce 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 124 #endif
modtronix 10:6444e6c798ce 125
modtronix 1:71204b8406f2 126 #elif defined ( __ICCARM__ )
modtronix 1:71204b8406f2 127 #if defined __ARMVFP__
modtronix 1:71204b8406f2 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 129 #endif
modtronix 1:71204b8406f2 130
modtronix 10:6444e6c798ce 131 #elif defined ( __TMS470__ )
modtronix 10:6444e6c798ce 132 #if defined __TI__VFP_SUPPORT____
modtronix 1:71204b8406f2 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 134 #endif
modtronix 1:71204b8406f2 135
modtronix 1:71204b8406f2 136 #elif defined ( __TASKING__ )
modtronix 1:71204b8406f2 137 #if defined __FPU_VFP__
modtronix 1:71204b8406f2 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 1:71204b8406f2 139 #endif
modtronix 10:6444e6c798ce 140
modtronix 10:6444e6c798ce 141 #elif defined ( __CSMC__ ) /* Cosmic */
modtronix 10:6444e6c798ce 142 #if ( __CSMC__ & 0x400) // FPU present for parser
modtronix 10:6444e6c798ce 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
modtronix 10:6444e6c798ce 144 #endif
modtronix 1:71204b8406f2 145 #endif
modtronix 1:71204b8406f2 146
modtronix 1:71204b8406f2 147 #include <stdint.h> /* standard types definitions */
modtronix 1:71204b8406f2 148 #include <core_cmInstr.h> /* Core Instruction Access */
modtronix 1:71204b8406f2 149 #include <core_cmFunc.h> /* Core Function Access */
modtronix 1:71204b8406f2 150
modtronix 10:6444e6c798ce 151 #ifdef __cplusplus
modtronix 10:6444e6c798ce 152 }
modtronix 10:6444e6c798ce 153 #endif
modtronix 10:6444e6c798ce 154
modtronix 1:71204b8406f2 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
modtronix 1:71204b8406f2 156
modtronix 1:71204b8406f2 157 #ifndef __CMSIS_GENERIC
modtronix 1:71204b8406f2 158
modtronix 1:71204b8406f2 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
modtronix 1:71204b8406f2 160 #define __CORE_CM0PLUS_H_DEPENDANT
modtronix 1:71204b8406f2 161
modtronix 10:6444e6c798ce 162 #ifdef __cplusplus
modtronix 10:6444e6c798ce 163 extern "C" {
modtronix 10:6444e6c798ce 164 #endif
modtronix 10:6444e6c798ce 165
modtronix 1:71204b8406f2 166 /* check device defines and use defaults */
modtronix 1:71204b8406f2 167 #if defined __CHECK_DEVICE_DEFINES
modtronix 1:71204b8406f2 168 #ifndef __CM0PLUS_REV
modtronix 1:71204b8406f2 169 #define __CM0PLUS_REV 0x0000
modtronix 1:71204b8406f2 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
modtronix 1:71204b8406f2 171 #endif
modtronix 1:71204b8406f2 172
modtronix 1:71204b8406f2 173 #ifndef __MPU_PRESENT
modtronix 1:71204b8406f2 174 #define __MPU_PRESENT 0
modtronix 1:71204b8406f2 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 176 #endif
modtronix 1:71204b8406f2 177
modtronix 1:71204b8406f2 178 #ifndef __VTOR_PRESENT
modtronix 1:71204b8406f2 179 #define __VTOR_PRESENT 0
modtronix 1:71204b8406f2 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
modtronix 1:71204b8406f2 181 #endif
modtronix 1:71204b8406f2 182
modtronix 1:71204b8406f2 183 #ifndef __NVIC_PRIO_BITS
modtronix 1:71204b8406f2 184 #define __NVIC_PRIO_BITS 2
modtronix 1:71204b8406f2 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
modtronix 1:71204b8406f2 186 #endif
modtronix 1:71204b8406f2 187
modtronix 1:71204b8406f2 188 #ifndef __Vendor_SysTickConfig
modtronix 1:71204b8406f2 189 #define __Vendor_SysTickConfig 0
modtronix 1:71204b8406f2 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
modtronix 1:71204b8406f2 191 #endif
modtronix 1:71204b8406f2 192 #endif
modtronix 1:71204b8406f2 193
modtronix 1:71204b8406f2 194 /* IO definitions (access restrictions to peripheral registers) */
modtronix 1:71204b8406f2 195 /**
modtronix 1:71204b8406f2 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
modtronix 1:71204b8406f2 197
modtronix 1:71204b8406f2 198 <strong>IO Type Qualifiers</strong> are used
modtronix 1:71204b8406f2 199 \li to specify the access to peripheral variables.
modtronix 1:71204b8406f2 200 \li for automatic generation of peripheral register debug information.
modtronix 1:71204b8406f2 201 */
modtronix 1:71204b8406f2 202 #ifdef __cplusplus
modtronix 1:71204b8406f2 203 #define __I volatile /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 204 #else
modtronix 1:71204b8406f2 205 #define __I volatile const /*!< Defines 'read only' permissions */
modtronix 1:71204b8406f2 206 #endif
modtronix 1:71204b8406f2 207 #define __O volatile /*!< Defines 'write only' permissions */
modtronix 1:71204b8406f2 208 #define __IO volatile /*!< Defines 'read / write' permissions */
modtronix 1:71204b8406f2 209
modtronix 1:71204b8406f2 210 /*@} end of group Cortex-M0+ */
modtronix 1:71204b8406f2 211
modtronix 1:71204b8406f2 212
modtronix 1:71204b8406f2 213
modtronix 1:71204b8406f2 214 /*******************************************************************************
modtronix 1:71204b8406f2 215 * Register Abstraction
modtronix 1:71204b8406f2 216 Core Register contain:
modtronix 1:71204b8406f2 217 - Core Register
modtronix 1:71204b8406f2 218 - Core NVIC Register
modtronix 1:71204b8406f2 219 - Core SCB Register
modtronix 1:71204b8406f2 220 - Core SysTick Register
modtronix 1:71204b8406f2 221 - Core MPU Register
modtronix 1:71204b8406f2 222 ******************************************************************************/
modtronix 1:71204b8406f2 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
modtronix 1:71204b8406f2 224 \brief Type definitions and defines for Cortex-M processor based devices.
modtronix 1:71204b8406f2 225 */
modtronix 1:71204b8406f2 226
modtronix 1:71204b8406f2 227 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 228 \defgroup CMSIS_CORE Status and Control Registers
modtronix 1:71204b8406f2 229 \brief Core Register type definitions.
modtronix 1:71204b8406f2 230 @{
modtronix 1:71204b8406f2 231 */
modtronix 1:71204b8406f2 232
modtronix 1:71204b8406f2 233 /** \brief Union type to access the Application Program Status Register (APSR).
modtronix 1:71204b8406f2 234 */
modtronix 1:71204b8406f2 235 typedef union
modtronix 1:71204b8406f2 236 {
modtronix 1:71204b8406f2 237 struct
modtronix 1:71204b8406f2 238 {
modtronix 1:71204b8406f2 239 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 240 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
modtronix 1:71204b8406f2 241 #else
modtronix 1:71204b8406f2 242 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
modtronix 1:71204b8406f2 243 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 244 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
modtronix 1:71204b8406f2 245 #endif
modtronix 1:71204b8406f2 246 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 247 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 248 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 249 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 250 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 251 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 252 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 253 } APSR_Type;
modtronix 1:71204b8406f2 254
modtronix 1:71204b8406f2 255
modtronix 1:71204b8406f2 256 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
modtronix 1:71204b8406f2 257 */
modtronix 1:71204b8406f2 258 typedef union
modtronix 1:71204b8406f2 259 {
modtronix 1:71204b8406f2 260 struct
modtronix 1:71204b8406f2 261 {
modtronix 1:71204b8406f2 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 263 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
modtronix 1:71204b8406f2 264 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 265 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 266 } IPSR_Type;
modtronix 1:71204b8406f2 267
modtronix 1:71204b8406f2 268
modtronix 1:71204b8406f2 269 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
modtronix 1:71204b8406f2 270 */
modtronix 1:71204b8406f2 271 typedef union
modtronix 1:71204b8406f2 272 {
modtronix 1:71204b8406f2 273 struct
modtronix 1:71204b8406f2 274 {
modtronix 1:71204b8406f2 275 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
modtronix 1:71204b8406f2 276 #if (__CORTEX_M != 0x04)
modtronix 1:71204b8406f2 277 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
modtronix 1:71204b8406f2 278 #else
modtronix 1:71204b8406f2 279 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
modtronix 1:71204b8406f2 280 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
modtronix 1:71204b8406f2 281 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
modtronix 1:71204b8406f2 282 #endif
modtronix 1:71204b8406f2 283 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
modtronix 1:71204b8406f2 284 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
modtronix 1:71204b8406f2 285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
modtronix 1:71204b8406f2 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
modtronix 1:71204b8406f2 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
modtronix 1:71204b8406f2 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
modtronix 1:71204b8406f2 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
modtronix 1:71204b8406f2 290 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 291 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 292 } xPSR_Type;
modtronix 1:71204b8406f2 293
modtronix 1:71204b8406f2 294
modtronix 1:71204b8406f2 295 /** \brief Union type to access the Control Registers (CONTROL).
modtronix 1:71204b8406f2 296 */
modtronix 1:71204b8406f2 297 typedef union
modtronix 1:71204b8406f2 298 {
modtronix 1:71204b8406f2 299 struct
modtronix 1:71204b8406f2 300 {
modtronix 1:71204b8406f2 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
modtronix 1:71204b8406f2 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
modtronix 1:71204b8406f2 303 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
modtronix 1:71204b8406f2 304 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
modtronix 1:71204b8406f2 305 } b; /*!< Structure used for bit access */
modtronix 1:71204b8406f2 306 uint32_t w; /*!< Type used for word access */
modtronix 1:71204b8406f2 307 } CONTROL_Type;
modtronix 1:71204b8406f2 308
modtronix 1:71204b8406f2 309 /*@} end of group CMSIS_CORE */
modtronix 1:71204b8406f2 310
modtronix 1:71204b8406f2 311
modtronix 1:71204b8406f2 312 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 313 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
modtronix 1:71204b8406f2 314 \brief Type definitions for the NVIC Registers
modtronix 1:71204b8406f2 315 @{
modtronix 1:71204b8406f2 316 */
modtronix 1:71204b8406f2 317
modtronix 1:71204b8406f2 318 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
modtronix 1:71204b8406f2 319 */
modtronix 1:71204b8406f2 320 typedef struct
modtronix 1:71204b8406f2 321 {
modtronix 1:71204b8406f2 322 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
modtronix 1:71204b8406f2 323 uint32_t RESERVED0[31];
modtronix 1:71204b8406f2 324 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
modtronix 1:71204b8406f2 325 uint32_t RSERVED1[31];
modtronix 1:71204b8406f2 326 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
modtronix 1:71204b8406f2 327 uint32_t RESERVED2[31];
modtronix 1:71204b8406f2 328 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
modtronix 1:71204b8406f2 329 uint32_t RESERVED3[31];
modtronix 1:71204b8406f2 330 uint32_t RESERVED4[64];
modtronix 1:71204b8406f2 331 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
modtronix 1:71204b8406f2 332 } NVIC_Type;
modtronix 1:71204b8406f2 333
modtronix 1:71204b8406f2 334 /*@} end of group CMSIS_NVIC */
modtronix 1:71204b8406f2 335
modtronix 1:71204b8406f2 336
modtronix 1:71204b8406f2 337 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 338 \defgroup CMSIS_SCB System Control Block (SCB)
modtronix 1:71204b8406f2 339 \brief Type definitions for the System Control Block Registers
modtronix 1:71204b8406f2 340 @{
modtronix 1:71204b8406f2 341 */
modtronix 1:71204b8406f2 342
modtronix 1:71204b8406f2 343 /** \brief Structure type to access the System Control Block (SCB).
modtronix 1:71204b8406f2 344 */
modtronix 1:71204b8406f2 345 typedef struct
modtronix 1:71204b8406f2 346 {
modtronix 1:71204b8406f2 347 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
modtronix 1:71204b8406f2 348 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
modtronix 1:71204b8406f2 349 #if (__VTOR_PRESENT == 1)
modtronix 1:71204b8406f2 350 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
modtronix 1:71204b8406f2 351 #else
modtronix 1:71204b8406f2 352 uint32_t RESERVED0;
modtronix 1:71204b8406f2 353 #endif
modtronix 1:71204b8406f2 354 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
modtronix 1:71204b8406f2 355 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
modtronix 1:71204b8406f2 356 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
modtronix 1:71204b8406f2 357 uint32_t RESERVED1;
modtronix 1:71204b8406f2 358 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
modtronix 1:71204b8406f2 359 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
modtronix 1:71204b8406f2 360 } SCB_Type;
modtronix 1:71204b8406f2 361
modtronix 1:71204b8406f2 362 /* SCB CPUID Register Definitions */
modtronix 1:71204b8406f2 363 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
modtronix 1:71204b8406f2 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
modtronix 1:71204b8406f2 365
modtronix 1:71204b8406f2 366 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
modtronix 1:71204b8406f2 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
modtronix 1:71204b8406f2 368
modtronix 1:71204b8406f2 369 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
modtronix 1:71204b8406f2 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
modtronix 1:71204b8406f2 371
modtronix 1:71204b8406f2 372 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
modtronix 1:71204b8406f2 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
modtronix 1:71204b8406f2 374
modtronix 1:71204b8406f2 375 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
modtronix 1:71204b8406f2 376 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
modtronix 1:71204b8406f2 377
modtronix 1:71204b8406f2 378 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 379 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
modtronix 1:71204b8406f2 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
modtronix 1:71204b8406f2 381
modtronix 1:71204b8406f2 382 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
modtronix 1:71204b8406f2 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
modtronix 1:71204b8406f2 384
modtronix 1:71204b8406f2 385 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
modtronix 1:71204b8406f2 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
modtronix 1:71204b8406f2 387
modtronix 1:71204b8406f2 388 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
modtronix 1:71204b8406f2 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
modtronix 1:71204b8406f2 390
modtronix 1:71204b8406f2 391 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
modtronix 1:71204b8406f2 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
modtronix 1:71204b8406f2 393
modtronix 1:71204b8406f2 394 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
modtronix 1:71204b8406f2 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
modtronix 1:71204b8406f2 396
modtronix 1:71204b8406f2 397 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
modtronix 1:71204b8406f2 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
modtronix 1:71204b8406f2 399
modtronix 1:71204b8406f2 400 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
modtronix 1:71204b8406f2 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
modtronix 1:71204b8406f2 402
modtronix 1:71204b8406f2 403 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
modtronix 1:71204b8406f2 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
modtronix 1:71204b8406f2 405
modtronix 1:71204b8406f2 406 #if (__VTOR_PRESENT == 1)
modtronix 1:71204b8406f2 407 /* SCB Interrupt Control State Register Definitions */
modtronix 1:71204b8406f2 408 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
modtronix 1:71204b8406f2 409 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
modtronix 1:71204b8406f2 410 #endif
modtronix 1:71204b8406f2 411
modtronix 1:71204b8406f2 412 /* SCB Application Interrupt and Reset Control Register Definitions */
modtronix 1:71204b8406f2 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
modtronix 1:71204b8406f2 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
modtronix 1:71204b8406f2 415
modtronix 1:71204b8406f2 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
modtronix 1:71204b8406f2 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
modtronix 1:71204b8406f2 418
modtronix 1:71204b8406f2 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
modtronix 1:71204b8406f2 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
modtronix 1:71204b8406f2 421
modtronix 1:71204b8406f2 422 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
modtronix 1:71204b8406f2 423 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
modtronix 1:71204b8406f2 424
modtronix 1:71204b8406f2 425 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
modtronix 1:71204b8406f2 426 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
modtronix 1:71204b8406f2 427
modtronix 1:71204b8406f2 428 /* SCB System Control Register Definitions */
modtronix 1:71204b8406f2 429 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
modtronix 1:71204b8406f2 430 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
modtronix 1:71204b8406f2 431
modtronix 1:71204b8406f2 432 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
modtronix 1:71204b8406f2 433 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
modtronix 1:71204b8406f2 434
modtronix 1:71204b8406f2 435 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
modtronix 1:71204b8406f2 436 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
modtronix 1:71204b8406f2 437
modtronix 1:71204b8406f2 438 /* SCB Configuration Control Register Definitions */
modtronix 1:71204b8406f2 439 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
modtronix 1:71204b8406f2 440 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
modtronix 1:71204b8406f2 441
modtronix 1:71204b8406f2 442 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
modtronix 1:71204b8406f2 443 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
modtronix 1:71204b8406f2 444
modtronix 1:71204b8406f2 445 /* SCB System Handler Control and State Register Definitions */
modtronix 1:71204b8406f2 446 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
modtronix 1:71204b8406f2 447 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
modtronix 1:71204b8406f2 448
modtronix 1:71204b8406f2 449 /*@} end of group CMSIS_SCB */
modtronix 1:71204b8406f2 450
modtronix 1:71204b8406f2 451
modtronix 1:71204b8406f2 452 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 453 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
modtronix 1:71204b8406f2 454 \brief Type definitions for the System Timer Registers.
modtronix 1:71204b8406f2 455 @{
modtronix 1:71204b8406f2 456 */
modtronix 1:71204b8406f2 457
modtronix 1:71204b8406f2 458 /** \brief Structure type to access the System Timer (SysTick).
modtronix 1:71204b8406f2 459 */
modtronix 1:71204b8406f2 460 typedef struct
modtronix 1:71204b8406f2 461 {
modtronix 1:71204b8406f2 462 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
modtronix 1:71204b8406f2 463 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
modtronix 1:71204b8406f2 464 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
modtronix 1:71204b8406f2 465 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
modtronix 1:71204b8406f2 466 } SysTick_Type;
modtronix 1:71204b8406f2 467
modtronix 1:71204b8406f2 468 /* SysTick Control / Status Register Definitions */
modtronix 1:71204b8406f2 469 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
modtronix 1:71204b8406f2 470 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
modtronix 1:71204b8406f2 471
modtronix 1:71204b8406f2 472 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
modtronix 1:71204b8406f2 473 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
modtronix 1:71204b8406f2 474
modtronix 1:71204b8406f2 475 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
modtronix 1:71204b8406f2 476 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
modtronix 1:71204b8406f2 477
modtronix 1:71204b8406f2 478 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
modtronix 1:71204b8406f2 479 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 480
modtronix 1:71204b8406f2 481 /* SysTick Reload Register Definitions */
modtronix 1:71204b8406f2 482 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
modtronix 1:71204b8406f2 483 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
modtronix 1:71204b8406f2 484
modtronix 1:71204b8406f2 485 /* SysTick Current Register Definitions */
modtronix 1:71204b8406f2 486 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
modtronix 1:71204b8406f2 487 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
modtronix 1:71204b8406f2 488
modtronix 1:71204b8406f2 489 /* SysTick Calibration Register Definitions */
modtronix 1:71204b8406f2 490 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
modtronix 1:71204b8406f2 491 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
modtronix 1:71204b8406f2 492
modtronix 1:71204b8406f2 493 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
modtronix 1:71204b8406f2 494 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
modtronix 1:71204b8406f2 495
modtronix 1:71204b8406f2 496 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
modtronix 10:6444e6c798ce 497 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
modtronix 1:71204b8406f2 498
modtronix 1:71204b8406f2 499 /*@} end of group CMSIS_SysTick */
modtronix 1:71204b8406f2 500
modtronix 1:71204b8406f2 501 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 502 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 503 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 504 \brief Type definitions for the Memory Protection Unit (MPU)
modtronix 1:71204b8406f2 505 @{
modtronix 1:71204b8406f2 506 */
modtronix 1:71204b8406f2 507
modtronix 1:71204b8406f2 508 /** \brief Structure type to access the Memory Protection Unit (MPU).
modtronix 1:71204b8406f2 509 */
modtronix 1:71204b8406f2 510 typedef struct
modtronix 1:71204b8406f2 511 {
modtronix 1:71204b8406f2 512 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
modtronix 1:71204b8406f2 513 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
modtronix 1:71204b8406f2 514 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
modtronix 1:71204b8406f2 515 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
modtronix 1:71204b8406f2 516 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 517 } MPU_Type;
modtronix 1:71204b8406f2 518
modtronix 1:71204b8406f2 519 /* MPU Type Register */
modtronix 1:71204b8406f2 520 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
modtronix 1:71204b8406f2 521 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
modtronix 1:71204b8406f2 522
modtronix 1:71204b8406f2 523 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
modtronix 1:71204b8406f2 524 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
modtronix 1:71204b8406f2 525
modtronix 1:71204b8406f2 526 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
modtronix 1:71204b8406f2 527 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
modtronix 1:71204b8406f2 528
modtronix 1:71204b8406f2 529 /* MPU Control Register */
modtronix 1:71204b8406f2 530 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
modtronix 1:71204b8406f2 531 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
modtronix 1:71204b8406f2 532
modtronix 1:71204b8406f2 533 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
modtronix 1:71204b8406f2 534 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
modtronix 1:71204b8406f2 535
modtronix 1:71204b8406f2 536 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
modtronix 1:71204b8406f2 537 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
modtronix 1:71204b8406f2 538
modtronix 1:71204b8406f2 539 /* MPU Region Number Register */
modtronix 1:71204b8406f2 540 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
modtronix 1:71204b8406f2 541 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
modtronix 1:71204b8406f2 542
modtronix 1:71204b8406f2 543 /* MPU Region Base Address Register */
modtronix 1:71204b8406f2 544 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
modtronix 1:71204b8406f2 545 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
modtronix 1:71204b8406f2 546
modtronix 1:71204b8406f2 547 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
modtronix 1:71204b8406f2 548 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
modtronix 1:71204b8406f2 549
modtronix 1:71204b8406f2 550 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
modtronix 1:71204b8406f2 551 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
modtronix 1:71204b8406f2 552
modtronix 1:71204b8406f2 553 /* MPU Region Attribute and Size Register */
modtronix 1:71204b8406f2 554 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
modtronix 1:71204b8406f2 555 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
modtronix 1:71204b8406f2 556
modtronix 1:71204b8406f2 557 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
modtronix 1:71204b8406f2 558 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
modtronix 1:71204b8406f2 559
modtronix 1:71204b8406f2 560 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
modtronix 1:71204b8406f2 561 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
modtronix 1:71204b8406f2 562
modtronix 1:71204b8406f2 563 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
modtronix 1:71204b8406f2 564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
modtronix 1:71204b8406f2 565
modtronix 1:71204b8406f2 566 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
modtronix 1:71204b8406f2 567 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
modtronix 1:71204b8406f2 568
modtronix 1:71204b8406f2 569 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
modtronix 1:71204b8406f2 570 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
modtronix 1:71204b8406f2 571
modtronix 1:71204b8406f2 572 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
modtronix 1:71204b8406f2 573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
modtronix 1:71204b8406f2 574
modtronix 1:71204b8406f2 575 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
modtronix 1:71204b8406f2 576 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
modtronix 1:71204b8406f2 577
modtronix 1:71204b8406f2 578 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
modtronix 1:71204b8406f2 579 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
modtronix 1:71204b8406f2 580
modtronix 1:71204b8406f2 581 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
modtronix 1:71204b8406f2 582 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
modtronix 1:71204b8406f2 583
modtronix 1:71204b8406f2 584 /*@} end of group CMSIS_MPU */
modtronix 1:71204b8406f2 585 #endif
modtronix 1:71204b8406f2 586
modtronix 1:71204b8406f2 587
modtronix 1:71204b8406f2 588 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 589 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
modtronix 1:71204b8406f2 590 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
modtronix 1:71204b8406f2 591 are only accessible over DAP and not via processor. Therefore
modtronix 1:71204b8406f2 592 they are not covered by the Cortex-M0 header file.
modtronix 1:71204b8406f2 593 @{
modtronix 1:71204b8406f2 594 */
modtronix 1:71204b8406f2 595 /*@} end of group CMSIS_CoreDebug */
modtronix 1:71204b8406f2 596
modtronix 1:71204b8406f2 597
modtronix 1:71204b8406f2 598 /** \ingroup CMSIS_core_register
modtronix 1:71204b8406f2 599 \defgroup CMSIS_core_base Core Definitions
modtronix 1:71204b8406f2 600 \brief Definitions for base addresses, unions, and structures.
modtronix 1:71204b8406f2 601 @{
modtronix 1:71204b8406f2 602 */
modtronix 1:71204b8406f2 603
modtronix 1:71204b8406f2 604 /* Memory mapping of Cortex-M0+ Hardware */
modtronix 1:71204b8406f2 605 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
modtronix 1:71204b8406f2 606 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
modtronix 1:71204b8406f2 607 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
modtronix 1:71204b8406f2 608 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
modtronix 1:71204b8406f2 609
modtronix 1:71204b8406f2 610 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
modtronix 1:71204b8406f2 611 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
modtronix 1:71204b8406f2 612 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
modtronix 1:71204b8406f2 613
modtronix 1:71204b8406f2 614 #if (__MPU_PRESENT == 1)
modtronix 1:71204b8406f2 615 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 616 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
modtronix 1:71204b8406f2 617 #endif
modtronix 1:71204b8406f2 618
modtronix 1:71204b8406f2 619 /*@} */
modtronix 1:71204b8406f2 620
modtronix 1:71204b8406f2 621
modtronix 1:71204b8406f2 622
modtronix 1:71204b8406f2 623 /*******************************************************************************
modtronix 1:71204b8406f2 624 * Hardware Abstraction Layer
modtronix 1:71204b8406f2 625 Core Function Interface contains:
modtronix 1:71204b8406f2 626 - Core NVIC Functions
modtronix 1:71204b8406f2 627 - Core SysTick Functions
modtronix 1:71204b8406f2 628 - Core Register Access Functions
modtronix 1:71204b8406f2 629 ******************************************************************************/
modtronix 1:71204b8406f2 630 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
modtronix 1:71204b8406f2 631 */
modtronix 1:71204b8406f2 632
modtronix 1:71204b8406f2 633
modtronix 1:71204b8406f2 634
modtronix 1:71204b8406f2 635 /* ########################## NVIC functions #################################### */
modtronix 1:71204b8406f2 636 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 637 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
modtronix 1:71204b8406f2 638 \brief Functions that manage interrupts and exceptions via the NVIC.
modtronix 1:71204b8406f2 639 @{
modtronix 1:71204b8406f2 640 */
modtronix 1:71204b8406f2 641
modtronix 1:71204b8406f2 642 /* Interrupt Priorities are WORD accessible only under ARMv6M */
modtronix 1:71204b8406f2 643 /* The following MACROS handle generation of the register offset and byte masks */
modtronix 1:71204b8406f2 644 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
modtronix 1:71204b8406f2 645 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
modtronix 1:71204b8406f2 646 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
modtronix 1:71204b8406f2 647
modtronix 1:71204b8406f2 648
modtronix 1:71204b8406f2 649 /** \brief Enable External Interrupt
modtronix 1:71204b8406f2 650
modtronix 1:71204b8406f2 651 The function enables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 652
modtronix 1:71204b8406f2 653 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 654 */
modtronix 1:71204b8406f2 655 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 656 {
modtronix 1:71204b8406f2 657 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 658 }
modtronix 1:71204b8406f2 659
modtronix 1:71204b8406f2 660
modtronix 1:71204b8406f2 661 /** \brief Disable External Interrupt
modtronix 1:71204b8406f2 662
modtronix 1:71204b8406f2 663 The function disables a device-specific interrupt in the NVIC interrupt controller.
modtronix 1:71204b8406f2 664
modtronix 1:71204b8406f2 665 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 666 */
modtronix 1:71204b8406f2 667 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 668 {
modtronix 1:71204b8406f2 669 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 670 }
modtronix 1:71204b8406f2 671
modtronix 1:71204b8406f2 672
modtronix 1:71204b8406f2 673 /** \brief Get Pending Interrupt
modtronix 1:71204b8406f2 674
modtronix 1:71204b8406f2 675 The function reads the pending register in the NVIC and returns the pending bit
modtronix 1:71204b8406f2 676 for the specified interrupt.
modtronix 1:71204b8406f2 677
modtronix 1:71204b8406f2 678 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 679
modtronix 1:71204b8406f2 680 \return 0 Interrupt status is not pending.
modtronix 1:71204b8406f2 681 \return 1 Interrupt status is pending.
modtronix 1:71204b8406f2 682 */
modtronix 1:71204b8406f2 683 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 684 {
modtronix 1:71204b8406f2 685 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
modtronix 1:71204b8406f2 686 }
modtronix 1:71204b8406f2 687
modtronix 1:71204b8406f2 688
modtronix 1:71204b8406f2 689 /** \brief Set Pending Interrupt
modtronix 1:71204b8406f2 690
modtronix 1:71204b8406f2 691 The function sets the pending bit of an external interrupt.
modtronix 1:71204b8406f2 692
modtronix 1:71204b8406f2 693 \param [in] IRQn Interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 694 */
modtronix 1:71204b8406f2 695 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 696 {
modtronix 1:71204b8406f2 697 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
modtronix 1:71204b8406f2 698 }
modtronix 1:71204b8406f2 699
modtronix 1:71204b8406f2 700
modtronix 1:71204b8406f2 701 /** \brief Clear Pending Interrupt
modtronix 1:71204b8406f2 702
modtronix 1:71204b8406f2 703 The function clears the pending bit of an external interrupt.
modtronix 1:71204b8406f2 704
modtronix 1:71204b8406f2 705 \param [in] IRQn External interrupt number. Value cannot be negative.
modtronix 1:71204b8406f2 706 */
modtronix 1:71204b8406f2 707 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
modtronix 1:71204b8406f2 708 {
modtronix 1:71204b8406f2 709 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
modtronix 1:71204b8406f2 710 }
modtronix 1:71204b8406f2 711
modtronix 1:71204b8406f2 712
modtronix 1:71204b8406f2 713 /** \brief Set Interrupt Priority
modtronix 1:71204b8406f2 714
modtronix 1:71204b8406f2 715 The function sets the priority of an interrupt.
modtronix 1:71204b8406f2 716
modtronix 1:71204b8406f2 717 \note The priority cannot be set for every core interrupt.
modtronix 1:71204b8406f2 718
modtronix 1:71204b8406f2 719 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 720 \param [in] priority Priority to set.
modtronix 1:71204b8406f2 721 */
modtronix 1:71204b8406f2 722 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
modtronix 1:71204b8406f2 723 {
modtronix 1:71204b8406f2 724 if(IRQn < 0) {
modtronix 1:71204b8406f2 725 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 1:71204b8406f2 726 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 1:71204b8406f2 727 else {
modtronix 1:71204b8406f2 728 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
modtronix 1:71204b8406f2 729 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
modtronix 1:71204b8406f2 730 }
modtronix 1:71204b8406f2 731
modtronix 1:71204b8406f2 732
modtronix 1:71204b8406f2 733 /** \brief Get Interrupt Priority
modtronix 1:71204b8406f2 734
modtronix 1:71204b8406f2 735 The function reads the priority of an interrupt. The interrupt
modtronix 1:71204b8406f2 736 number can be positive to specify an external (device specific)
modtronix 1:71204b8406f2 737 interrupt, or negative to specify an internal (core) interrupt.
modtronix 1:71204b8406f2 738
modtronix 1:71204b8406f2 739
modtronix 1:71204b8406f2 740 \param [in] IRQn Interrupt number.
modtronix 1:71204b8406f2 741 \return Interrupt Priority. Value is aligned automatically to the implemented
modtronix 1:71204b8406f2 742 priority bits of the microcontroller.
modtronix 1:71204b8406f2 743 */
modtronix 1:71204b8406f2 744 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
modtronix 1:71204b8406f2 745 {
modtronix 1:71204b8406f2 746
modtronix 1:71204b8406f2 747 if(IRQn < 0) {
modtronix 1:71204b8406f2 748 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
modtronix 1:71204b8406f2 749 else {
modtronix 1:71204b8406f2 750 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
modtronix 1:71204b8406f2 751 }
modtronix 1:71204b8406f2 752
modtronix 1:71204b8406f2 753
modtronix 1:71204b8406f2 754 /** \brief System Reset
modtronix 1:71204b8406f2 755
modtronix 1:71204b8406f2 756 The function initiates a system reset request to reset the MCU.
modtronix 1:71204b8406f2 757 */
modtronix 1:71204b8406f2 758 __STATIC_INLINE void NVIC_SystemReset(void)
modtronix 1:71204b8406f2 759 {
modtronix 1:71204b8406f2 760 __DSB(); /* Ensure all outstanding memory accesses included
modtronix 1:71204b8406f2 761 buffered write are completed before reset */
modtronix 1:71204b8406f2 762 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
modtronix 1:71204b8406f2 763 SCB_AIRCR_SYSRESETREQ_Msk);
modtronix 1:71204b8406f2 764 __DSB(); /* Ensure completion of memory access */
modtronix 1:71204b8406f2 765 while(1); /* wait until reset */
modtronix 1:71204b8406f2 766 }
modtronix 1:71204b8406f2 767
modtronix 1:71204b8406f2 768 /*@} end of CMSIS_Core_NVICFunctions */
modtronix 1:71204b8406f2 769
modtronix 1:71204b8406f2 770
modtronix 1:71204b8406f2 771
modtronix 1:71204b8406f2 772 /* ################################## SysTick function ############################################ */
modtronix 1:71204b8406f2 773 /** \ingroup CMSIS_Core_FunctionInterface
modtronix 1:71204b8406f2 774 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
modtronix 1:71204b8406f2 775 \brief Functions that configure the System.
modtronix 1:71204b8406f2 776 @{
modtronix 1:71204b8406f2 777 */
modtronix 1:71204b8406f2 778
modtronix 1:71204b8406f2 779 #if (__Vendor_SysTickConfig == 0)
modtronix 1:71204b8406f2 780
modtronix 1:71204b8406f2 781 /** \brief System Tick Configuration
modtronix 1:71204b8406f2 782
modtronix 1:71204b8406f2 783 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
modtronix 1:71204b8406f2 784 Counter is in free running mode to generate periodic interrupts.
modtronix 1:71204b8406f2 785
modtronix 1:71204b8406f2 786 \param [in] ticks Number of ticks between two interrupts.
modtronix 1:71204b8406f2 787
modtronix 1:71204b8406f2 788 \return 0 Function succeeded.
modtronix 1:71204b8406f2 789 \return 1 Function failed.
modtronix 1:71204b8406f2 790
modtronix 1:71204b8406f2 791 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
modtronix 1:71204b8406f2 792 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
modtronix 1:71204b8406f2 793 must contain a vendor-specific implementation of this function.
modtronix 1:71204b8406f2 794
modtronix 1:71204b8406f2 795 */
modtronix 1:71204b8406f2 796 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
modtronix 1:71204b8406f2 797 {
modtronix 1:71204b8406f2 798 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
modtronix 1:71204b8406f2 799
modtronix 1:71204b8406f2 800 SysTick->LOAD = ticks - 1; /* set reload register */
modtronix 1:71204b8406f2 801 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
modtronix 1:71204b8406f2 802 SysTick->VAL = 0; /* Load the SysTick Counter Value */
modtronix 1:71204b8406f2 803 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
modtronix 1:71204b8406f2 804 SysTick_CTRL_TICKINT_Msk |
modtronix 1:71204b8406f2 805 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
modtronix 1:71204b8406f2 806 return (0); /* Function successful */
modtronix 1:71204b8406f2 807 }
modtronix 1:71204b8406f2 808
modtronix 1:71204b8406f2 809 #endif
modtronix 1:71204b8406f2 810
modtronix 1:71204b8406f2 811 /*@} end of CMSIS_Core_SysTickFunctions */
modtronix 1:71204b8406f2 812
modtronix 1:71204b8406f2 813
modtronix 1:71204b8406f2 814
modtronix 1:71204b8406f2 815
modtronix 10:6444e6c798ce 816 #ifdef __cplusplus
modtronix 10:6444e6c798ce 817 }
modtronix 10:6444e6c798ce 818 #endif
modtronix 10:6444e6c798ce 819
modtronix 1:71204b8406f2 820 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
modtronix 1:71204b8406f2 821
modtronix 1:71204b8406f2 822 #endif /* __CMSIS_GENERIC */