modtronix H / SX1276Lib_modtronix

Enabled all bandwidths, added Modtronix inAir9 module

Dependents:   SX1276PingPong_modtronix

Fork of SX1276Lib by Gregory Cristian

sx1276/sx1276.cpp@25:72381be1b0ce, 2015-07-29 (annotated)

Committer:
modtronix
Date:
Wed Jul 29 12:07:40 2015 +1000
Revision:
25:72381be1b0ce
Parent:
22:20db480143c9 
Removed DIO4 and DIO5 from code. Not available on inAir Modules.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
modtronix 20:7cf7c08f0088 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
GregCr 7:2b555111463f 44 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 45 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
modtronix 25:72381be1b0ce 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3/*, PinName dio4, PinName dio5*/)
mluis 13:618826a997e2 48 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 49 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 50 nss( nss ),
mluis 13:618826a997e2 51 reset( reset ),
modtronix 25:72381be1b0ce 52 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), /*dio4( dio4 ), dio5( dio5 ),*/
mluis 13:618826a997e2 53 isRadioActive( false )
GregCr 0:e6ceb13d2d05 54 {
mluis 13:618826a997e2 55 wait_ms( 10 );
mluis 13:618826a997e2 56 this->rxTx = 0;
mluis 13:618826a997e2 57 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 58 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 59
mluis 13:618826a997e2 60 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 61
mluis 13:618826a997e2 62 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 63 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 64 this->dioIrq[2] = &SX1276::OnDio2Irq;
modtronix 22:20db480143c9 65 //For SHD3I with BOARD_INAIR4 in imod3, on FRDM-KL25Z board. It uses A4 on FRDM-KL25Z board, which does not have interrupt
modtronix 18:cdb08d710838 66 #if( defined ( TARGET_KL25Z ) && defined(SHIELD_SHD3I_INAIR9) )
modtronix 18:cdb08d710838 67 this->dioIrq[3] = NULL;
modtronix 18:cdb08d710838 68 #else
mluis 13:618826a997e2 69 this->dioIrq[3] = &SX1276::OnDio3Irq;
modtronix 18:cdb08d710838 70 #endif
modtronix 25:72381be1b0ce 71 //this->dioIrq[4] = &SX1276::OnDio4Irq;
modtronix 25:72381be1b0ce 72 //this->dioIrq[5] = NULL;
mluis 13:618826a997e2 73
mluis 13:618826a997e2 74 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 78 {
mluis 13:618826a997e2 79 delete this->rxBuffer;
mluis 13:618826a997e2 80 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 81 }
GregCr 0:e6ceb13d2d05 82
modtronix 22:20db480143c9 83 uint8_t SX1276::GetBoardType( void )
modtronix 22:20db480143c9 84 {
modtronix 22:20db480143c9 85 return boardConnected;
modtronix 22:20db480143c9 86 }
modtronix 22:20db480143c9 87
modtronix 22:20db480143c9 88 void SX1276::SetBoardType( uint8_t boardType)
modtronix 22:20db480143c9 89 {
modtronix 22:20db480143c9 90 boardConnected = boardType;
modtronix 22:20db480143c9 91 }
modtronix 22:20db480143c9 92
GregCr 0:e6ceb13d2d05 93 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 94 {
GregCr 0:e6ceb13d2d05 95 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 96 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 97
GregCr 0:e6ceb13d2d05 98 // Save context
GregCr 0:e6ceb13d2d05 99 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 100 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 101 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 102 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 105 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 106
GregCr 0:e6ceb13d2d05 107 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 108 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 109 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 110 {
GregCr 0:e6ceb13d2d05 111 }
GregCr 0:e6ceb13d2d05 112
GregCr 0:e6ceb13d2d05 113 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 114 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 117 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 118 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 119 {
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 // Restore context
GregCr 0:e6ceb13d2d05 123 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 124 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 125 }
GregCr 0:e6ceb13d2d05 126
GregCr 0:e6ceb13d2d05 127 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 128 {
GregCr 0:e6ceb13d2d05 129 return this->settings.State;
GregCr 0:e6ceb13d2d05 130 }
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 133 {
GregCr 0:e6ceb13d2d05 134 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 135 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 136 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 137 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 138 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 139 }
GregCr 0:e6ceb13d2d05 140
GregCr 0:e6ceb13d2d05 141 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 142 {
GregCr 7:2b555111463f 143 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 SetModem( modem );
GregCr 0:e6ceb13d2d05 146
GregCr 0:e6ceb13d2d05 147 SetChannel( freq );
GregCr 0:e6ceb13d2d05 148
GregCr 0:e6ceb13d2d05 149 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 150
GregCr 4:f0ce52e94d3f 151 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 154
GregCr 0:e6ceb13d2d05 155 Sleep( );
GregCr 0:e6ceb13d2d05 156
GregCr 7:2b555111463f 157 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 158 {
GregCr 0:e6ceb13d2d05 159 return false;
GregCr 0:e6ceb13d2d05 160 }
GregCr 0:e6ceb13d2d05 161 return true;
GregCr 0:e6ceb13d2d05 162 }
GregCr 0:e6ceb13d2d05 163
GregCr 0:e6ceb13d2d05 164 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 165 {
GregCr 0:e6ceb13d2d05 166 uint8_t i;
GregCr 0:e6ceb13d2d05 167 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 168
GregCr 0:e6ceb13d2d05 169 /*
GregCr 0:e6ceb13d2d05 170 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 171 */
GregCr 0:e6ceb13d2d05 172 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 173 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 174
GregCr 0:e6ceb13d2d05 175 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 176 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 177 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 178 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 179 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 180 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 181 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 182 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 183 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 184
GregCr 0:e6ceb13d2d05 185 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 186 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 187
GregCr 0:e6ceb13d2d05 188 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 189 {
GregCr 4:f0ce52e94d3f 190 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 191 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 192 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 193 }
GregCr 0:e6ceb13d2d05 194
GregCr 0:e6ceb13d2d05 195 Sleep( );
GregCr 0:e6ceb13d2d05 196
GregCr 0:e6ceb13d2d05 197 return rnd;
GregCr 0:e6ceb13d2d05 198 }
GregCr 0:e6ceb13d2d05 199
GregCr 0:e6ceb13d2d05 200 /*!
GregCr 0:e6ceb13d2d05 201 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 202 *
GregCr 0:e6ceb13d2d05 203 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 204 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 205 */
GregCr 0:e6ceb13d2d05 206 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 207 {
GregCr 0:e6ceb13d2d05 208 uint8_t i;
GregCr 0:e6ceb13d2d05 209
GregCr 0:e6ceb13d2d05 210 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 211 {
GregCr 0:e6ceb13d2d05 212 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 213 {
GregCr 0:e6ceb13d2d05 214 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 215 }
GregCr 0:e6ceb13d2d05 216 }
GregCr 0:e6ceb13d2d05 217 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 218 while( 1 );
GregCr 0:e6ceb13d2d05 219 }
GregCr 0:e6ceb13d2d05 220
GregCr 0:e6ceb13d2d05 221 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 222 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 223 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 224 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 225 uint8_t payloadLen,
mluis 13:618826a997e2 226 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 227 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 228 {
GregCr 0:e6ceb13d2d05 229 SetModem( modem );
GregCr 0:e6ceb13d2d05 230
GregCr 0:e6ceb13d2d05 231 switch( modem )
GregCr 0:e6ceb13d2d05 232 {
GregCr 0:e6ceb13d2d05 233 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 234 {
GregCr 0:e6ceb13d2d05 235 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 236 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 239 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 240 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 241 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 242 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 243 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 246 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 247 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 248
GregCr 0:e6ceb13d2d05 249 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 250 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 251
mluis 14:8552d0b840be 252 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 253 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 254
GregCr 0:e6ceb13d2d05 255 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 256 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 257 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 258 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 259 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 260 ( crcOn << 4 ) );
mluis 13:618826a997e2 261 if( fixLen == 1 )
mluis 13:618826a997e2 262 {
mluis 13:618826a997e2 263 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 264 }
GregCr 0:e6ceb13d2d05 265 }
GregCr 0:e6ceb13d2d05 266 break;
GregCr 0:e6ceb13d2d05 267 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 268 {
modtronix 16:0927c093fd82 269 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 270 {
modtronix 16:0927c093fd82 271 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 272 while( 1 );
GregCr 0:e6ceb13d2d05 273 }
modtronix 16:0927c093fd82 274 //bandwidth += 7; //Changed bandwidth from 0-2 to 0-10
GregCr 0:e6ceb13d2d05 275 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 276 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 279 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 281 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 282 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 283 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 284 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 285
GregCr 0:e6ceb13d2d05 286 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 287 {
GregCr 0:e6ceb13d2d05 288 datarate = 12;
GregCr 0:e6ceb13d2d05 289 }
GregCr 0:e6ceb13d2d05 290 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 291 {
GregCr 0:e6ceb13d2d05 292 datarate = 6;
GregCr 0:e6ceb13d2d05 293 }
GregCr 0:e6ceb13d2d05 294
modtronix 20:7cf7c08f0088 295 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 296 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 297 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 298 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 299 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 300 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 301 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 302 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 303 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 304 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 305 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 306 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 307 )
GregCr 0:e6ceb13d2d05 308 {
GregCr 0:e6ceb13d2d05 309 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 310 }
GregCr 0:e6ceb13d2d05 311 else
GregCr 0:e6ceb13d2d05 312 {
GregCr 0:e6ceb13d2d05 313 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 314 }
GregCr 0:e6ceb13d2d05 315
GregCr 0:e6ceb13d2d05 316 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 317 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 318 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 319 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 320 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 321 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 322 fixLen );
GregCr 0:e6ceb13d2d05 323
GregCr 0:e6ceb13d2d05 324 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 325 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 326 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 327 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 328 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 329 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 330 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 331
GregCr 0:e6ceb13d2d05 332 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 333 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 334 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 335 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 336
GregCr 0:e6ceb13d2d05 337 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 338
GregCr 0:e6ceb13d2d05 339 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 340 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 341
mluis 13:618826a997e2 342 if( fixLen == 1 )
mluis 13:618826a997e2 343 {
mluis 13:618826a997e2 344 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 345 }
mluis 13:618826a997e2 346
GregCr 6:e7f02929cd3d 347 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 348 {
GregCr 6:e7f02929cd3d 349 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 350 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 351 }
GregCr 6:e7f02929cd3d 352
GregCr 0:e6ceb13d2d05 353 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 354 {
GregCr 0:e6ceb13d2d05 355 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 356 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 357 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 358 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 359 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 360 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 361 }
GregCr 0:e6ceb13d2d05 362 else
GregCr 0:e6ceb13d2d05 363 {
GregCr 0:e6ceb13d2d05 364 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 365 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 366 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 367 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 368 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 369 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 370 }
GregCr 0:e6ceb13d2d05 371 }
GregCr 0:e6ceb13d2d05 372 break;
GregCr 0:e6ceb13d2d05 373 }
GregCr 0:e6ceb13d2d05 374 }
GregCr 0:e6ceb13d2d05 375
GregCr 0:e6ceb13d2d05 376 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 377 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 378 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 379 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 380 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 381 {
GregCr 0:e6ceb13d2d05 382 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 383 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 384
GregCr 0:e6ceb13d2d05 385 SetModem( modem );
GregCr 0:e6ceb13d2d05 386
GregCr 0:e6ceb13d2d05 387 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 388 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 389
GregCr 0:e6ceb13d2d05 390 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 391 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 392
GregCr 0:e6ceb13d2d05 393 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 394 {
GregCr 0:e6ceb13d2d05 395 if( power > 17 )
GregCr 0:e6ceb13d2d05 396 {
GregCr 0:e6ceb13d2d05 397 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 398 }
GregCr 0:e6ceb13d2d05 399 else
GregCr 0:e6ceb13d2d05 400 {
GregCr 0:e6ceb13d2d05 401 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 402 }
GregCr 0:e6ceb13d2d05 403 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 404 {
GregCr 0:e6ceb13d2d05 405 if( power < 5 )
GregCr 0:e6ceb13d2d05 406 {
GregCr 0:e6ceb13d2d05 407 power = 5;
GregCr 0:e6ceb13d2d05 408 }
GregCr 0:e6ceb13d2d05 409 if( power > 20 )
GregCr 0:e6ceb13d2d05 410 {
GregCr 0:e6ceb13d2d05 411 power = 20;
GregCr 0:e6ceb13d2d05 412 }
GregCr 0:e6ceb13d2d05 413 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 414 }
GregCr 0:e6ceb13d2d05 415 else
GregCr 0:e6ceb13d2d05 416 {
GregCr 0:e6ceb13d2d05 417 if( power < 2 )
GregCr 0:e6ceb13d2d05 418 {
GregCr 0:e6ceb13d2d05 419 power = 2;
GregCr 0:e6ceb13d2d05 420 }
GregCr 0:e6ceb13d2d05 421 if( power > 17 )
GregCr 0:e6ceb13d2d05 422 {
GregCr 0:e6ceb13d2d05 423 power = 17;
GregCr 0:e6ceb13d2d05 424 }
GregCr 0:e6ceb13d2d05 425 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 426 }
GregCr 0:e6ceb13d2d05 427 }
GregCr 0:e6ceb13d2d05 428 else
GregCr 0:e6ceb13d2d05 429 {
GregCr 0:e6ceb13d2d05 430 if( power < -1 )
GregCr 0:e6ceb13d2d05 431 {
GregCr 0:e6ceb13d2d05 432 power = -1;
GregCr 0:e6ceb13d2d05 433 }
GregCr 0:e6ceb13d2d05 434 if( power > 14 )
GregCr 0:e6ceb13d2d05 435 {
GregCr 0:e6ceb13d2d05 436 power = 14;
GregCr 0:e6ceb13d2d05 437 }
GregCr 0:e6ceb13d2d05 438 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 439 }
GregCr 0:e6ceb13d2d05 440 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 441 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 442
GregCr 0:e6ceb13d2d05 443 switch( modem )
GregCr 0:e6ceb13d2d05 444 {
GregCr 0:e6ceb13d2d05 445 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 446 {
GregCr 0:e6ceb13d2d05 447 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 448 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 449 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 450 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 451 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 452 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 453 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 454 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 455 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 456
GregCr 0:e6ceb13d2d05 457 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 458 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 459 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 460
GregCr 0:e6ceb13d2d05 461 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 462 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 463 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 464
GregCr 0:e6ceb13d2d05 465 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 466 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 467
GregCr 0:e6ceb13d2d05 468 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 469 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 470 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 471 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 472 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 473 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 474 }
GregCr 0:e6ceb13d2d05 475 break;
GregCr 0:e6ceb13d2d05 476 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 477 {
GregCr 0:e6ceb13d2d05 478 this->settings.LoRa.Power = power;
modtronix 16:0927c093fd82 479 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 480 {
modtronix 16:0927c093fd82 481 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 482 while( 1 );
GregCr 0:e6ceb13d2d05 483 }
modtronix 16:0927c093fd82 484 //bandwidth += 7;
GregCr 0:e6ceb13d2d05 485 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 486 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 487 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 488 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 489 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 490 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 491 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 492 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 493 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 494 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 495
GregCr 0:e6ceb13d2d05 496 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 497 {
GregCr 0:e6ceb13d2d05 498 datarate = 12;
GregCr 0:e6ceb13d2d05 499 }
GregCr 0:e6ceb13d2d05 500 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 501 {
GregCr 0:e6ceb13d2d05 502 datarate = 6;
GregCr 0:e6ceb13d2d05 503 }
modtronix 20:7cf7c08f0088 504 //bandwidth 6=62.5, 7=125, 8=250, 9=500, datarate=SF. LowDatarateOptimize is mandatory when symbol length > 16ms
modtronix 20:7cf7c08f0088 505 //LowDatarateOptimize = 0 when (BW=500) or (BW=250 and SF=12), else it is ON (Tsym > 16ms)
modtronix 20:7cf7c08f0088 506 if( ( ( bandwidth == 8 ) && ( datarate == 12 ) ) ||
modtronix 20:7cf7c08f0088 507 ( ( bandwidth == 7 ) && ( datarate > 10 ) ) ||
modtronix 20:7cf7c08f0088 508 ( ( bandwidth == 6 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 509 ( ( bandwidth == 5 ) && ( datarate > 9 ) ) ||
modtronix 20:7cf7c08f0088 510 ( ( bandwidth == 4 ) && ( datarate > 8 ) ) || ( bandwidth < 4 )
modtronix 20:7cf7c08f0088 511 //The below is actually correct method, but assume BW = 20.8 and lower will always have SF > 8
modtronix 20:7cf7c08f0088 512 // ( ( bandwidth == 3 ) && ( datarate > 8 ) ) ||
modtronix 20:7cf7c08f0088 513 // ( ( bandwidth == 2 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 514 // ( ( bandwidth == 1 ) && ( datarate > 7 ) ) ||
modtronix 20:7cf7c08f0088 515 // ( ( bandwidth == 0 ) && ( datarate > 6 ) )
modtronix 20:7cf7c08f0088 516 )
GregCr 0:e6ceb13d2d05 517 {
GregCr 0:e6ceb13d2d05 518 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 519 }
GregCr 0:e6ceb13d2d05 520 else
GregCr 0:e6ceb13d2d05 521 {
GregCr 0:e6ceb13d2d05 522 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 523 }
GregCr 6:e7f02929cd3d 524
GregCr 6:e7f02929cd3d 525 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 526 {
GregCr 6:e7f02929cd3d 527 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 528 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 529 }
GregCr 6:e7f02929cd3d 530
GregCr 0:e6ceb13d2d05 531 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 532 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 533 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 534 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 535 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 536 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 537 fixLen );
GregCr 0:e6ceb13d2d05 538
GregCr 0:e6ceb13d2d05 539 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 540 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 541 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 542 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 543 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 544
GregCr 0:e6ceb13d2d05 545 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 546 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 547 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 548 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 549
GregCr 0:e6ceb13d2d05 550 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 551 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 552
GregCr 0:e6ceb13d2d05 553 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 554 {
GregCr 0:e6ceb13d2d05 555 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 556 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 557 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 558 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 559 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 560 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 561 }
GregCr 0:e6ceb13d2d05 562 else
GregCr 0:e6ceb13d2d05 563 {
GregCr 0:e6ceb13d2d05 564 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 565 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 566 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 567 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 568 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 569 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 570 }
GregCr 0:e6ceb13d2d05 571 }
GregCr 0:e6ceb13d2d05 572 break;
GregCr 0:e6ceb13d2d05 573 }
GregCr 0:e6ceb13d2d05 574 }
GregCr 0:e6ceb13d2d05 575
GregCr 0:e6ceb13d2d05 576 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 577 {
GregCr 0:e6ceb13d2d05 578 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 579
GregCr 0:e6ceb13d2d05 580 switch( modem )
GregCr 0:e6ceb13d2d05 581 {
GregCr 0:e6ceb13d2d05 582 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 583 {
GregCr 4:f0ce52e94d3f 584 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 585 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 586 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 587 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 588 pktLen +
GregCr 0:e6ceb13d2d05 589 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 590 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 591 }
GregCr 0:e6ceb13d2d05 592 break;
GregCr 0:e6ceb13d2d05 593 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 594 {
GregCr 0:e6ceb13d2d05 595 double bw = 0.0;
GregCr 0:e6ceb13d2d05 596 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 597 {
modtronix 16:0927c093fd82 598 case 0: // 7.8 kHz
modtronix 16:0927c093fd82 599 bw = 78e2;
modtronix 16:0927c093fd82 600 break;
modtronix 16:0927c093fd82 601 case 1: // 10.4 kHz
modtronix 16:0927c093fd82 602 bw = 104e2;
modtronix 16:0927c093fd82 603 break;
modtronix 16:0927c093fd82 604 case 2: // 15.6 kHz
modtronix 16:0927c093fd82 605 bw = 156e2;
modtronix 16:0927c093fd82 606 break;
modtronix 16:0927c093fd82 607 case 3: // 20.8 kHz
modtronix 16:0927c093fd82 608 bw = 208e2;
modtronix 16:0927c093fd82 609 break;
modtronix 16:0927c093fd82 610 case 4: // 31.2 kHz
modtronix 16:0927c093fd82 611 bw = 312e2;
modtronix 16:0927c093fd82 612 break;
modtronix 16:0927c093fd82 613 case 5: // 41.4 kHz
modtronix 16:0927c093fd82 614 bw = 414e2;
modtronix 16:0927c093fd82 615 break;
modtronix 16:0927c093fd82 616 case 6: // 62.5 kHz
modtronix 16:0927c093fd82 617 bw = 625e2;
modtronix 16:0927c093fd82 618 break;
GregCr 0:e6ceb13d2d05 619 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 620 bw = 125e3;
GregCr 0:e6ceb13d2d05 621 break;
GregCr 0:e6ceb13d2d05 622 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 623 bw = 250e3;
GregCr 0:e6ceb13d2d05 624 break;
GregCr 0:e6ceb13d2d05 625 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 626 bw = 500e3;
GregCr 0:e6ceb13d2d05 627 break;
GregCr 0:e6ceb13d2d05 628 }
GregCr 0:e6ceb13d2d05 629
GregCr 0:e6ceb13d2d05 630 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 631 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 632 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 633 // time of preamble
GregCr 0:e6ceb13d2d05 634 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 635 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 636 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 637 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 638 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 639 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 640 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 641 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 642 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 643 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 644 // Time on air
GregCr 0:e6ceb13d2d05 645 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 646 // return us secs
GregCr 0:e6ceb13d2d05 647 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 648 }
GregCr 0:e6ceb13d2d05 649 break;
GregCr 0:e6ceb13d2d05 650 }
GregCr 0:e6ceb13d2d05 651 return airTime;
GregCr 0:e6ceb13d2d05 652 }
GregCr 0:e6ceb13d2d05 653
GregCr 0:e6ceb13d2d05 654 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 655 {
GregCr 0:e6ceb13d2d05 656 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 657
GregCr 5:11ec8a6ba4f0 658 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 659
GregCr 0:e6ceb13d2d05 660 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 661 {
GregCr 0:e6ceb13d2d05 662 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 663 {
GregCr 0:e6ceb13d2d05 664 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 665 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 666
GregCr 0:e6ceb13d2d05 667 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 668 {
GregCr 0:e6ceb13d2d05 669 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 670 }
GregCr 0:e6ceb13d2d05 671 else
GregCr 0:e6ceb13d2d05 672 {
GregCr 0:e6ceb13d2d05 673 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 674 }
GregCr 0:e6ceb13d2d05 675
GregCr 0:e6ceb13d2d05 676 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 677 {
GregCr 0:e6ceb13d2d05 678 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680 else
GregCr 0:e6ceb13d2d05 681 {
GregCr 0:e6ceb13d2d05 682 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 683 }
GregCr 0:e6ceb13d2d05 684
GregCr 0:e6ceb13d2d05 685 // Write payload buffer
GregCr 0:e6ceb13d2d05 686 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 687 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 688 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 689 }
GregCr 0:e6ceb13d2d05 690 break;
GregCr 0:e6ceb13d2d05 691 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 692 {
GregCr 0:e6ceb13d2d05 693 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 694 {
GregCr 0:e6ceb13d2d05 695 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697 else
GregCr 0:e6ceb13d2d05 698 {
GregCr 0:e6ceb13d2d05 699 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 700 }
GregCr 0:e6ceb13d2d05 701
GregCr 0:e6ceb13d2d05 702 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 703
GregCr 0:e6ceb13d2d05 704 // Initializes the payload size
GregCr 0:e6ceb13d2d05 705 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 706
GregCr 0:e6ceb13d2d05 707 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 708 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 709 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 710
GregCr 0:e6ceb13d2d05 711 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 712 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 713 {
GregCr 0:e6ceb13d2d05 714 Standby( );
GregCr 4:f0ce52e94d3f 715 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 716 }
GregCr 0:e6ceb13d2d05 717 // Write payload buffer
GregCr 0:e6ceb13d2d05 718 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 719 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 720 }
GregCr 0:e6ceb13d2d05 721 break;
GregCr 0:e6ceb13d2d05 722 }
GregCr 0:e6ceb13d2d05 723
GregCr 0:e6ceb13d2d05 724 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 725 }
GregCr 0:e6ceb13d2d05 726
GregCr 0:e6ceb13d2d05 727 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 728 {
mluis 13:618826a997e2 729 // Initialize driver timeout timers
mluis 13:618826a997e2 730 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 731 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 732 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 733 }
GregCr 0:e6ceb13d2d05 734
GregCr 0:e6ceb13d2d05 735 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 736 {
GregCr 0:e6ceb13d2d05 737 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 738 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 739 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 740 }
GregCr 0:e6ceb13d2d05 741
GregCr 0:e6ceb13d2d05 742 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 743 {
GregCr 0:e6ceb13d2d05 744 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 745
GregCr 0:e6ceb13d2d05 746 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 747 {
GregCr 0:e6ceb13d2d05 748 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 749 {
GregCr 0:e6ceb13d2d05 750 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 751
GregCr 0:e6ceb13d2d05 752 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 753 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 754 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 755 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 756 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 757 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 758 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 759 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 760 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 761 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 762
GregCr 0:e6ceb13d2d05 763 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 764 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 765 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 766 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 767
GregCr 0:e6ceb13d2d05 768 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 769
GregCr 0:e6ceb13d2d05 770 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 771 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 772 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 773 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 774 }
GregCr 0:e6ceb13d2d05 775 break;
GregCr 0:e6ceb13d2d05 776 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 777 {
GregCr 0:e6ceb13d2d05 778 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 779 {
GregCr 0:e6ceb13d2d05 780 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 781 }
GregCr 0:e6ceb13d2d05 782 else
GregCr 0:e6ceb13d2d05 783 {
GregCr 0:e6ceb13d2d05 784 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 785 }
GregCr 0:e6ceb13d2d05 786
GregCr 0:e6ceb13d2d05 787 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 788
GregCr 6:e7f02929cd3d 789 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 790 {
GregCr 6:e7f02929cd3d 791 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 792 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 793 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 794 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 795 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 796 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 797 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 798 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 799
mluis 13:618826a997e2 800 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 801 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 802 }
GregCr 6:e7f02929cd3d 803 else
GregCr 6:e7f02929cd3d 804 {
GregCr 6:e7f02929cd3d 805 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 806 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 807 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 808 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 809 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 810 RFLR_IRQFLAGS_CADDONE |
GregCr 8:0fe3e0e8007b 811 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 812 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 813
GregCr 6:e7f02929cd3d 814 // DIO0=RxDone
GregCr 6:e7f02929cd3d 815 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 816 }
GregCr 0:e6ceb13d2d05 817
GregCr 0:e6ceb13d2d05 818 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 819 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 820 }
GregCr 0:e6ceb13d2d05 821 break;
GregCr 0:e6ceb13d2d05 822 }
GregCr 0:e6ceb13d2d05 823
GregCr 0:e6ceb13d2d05 824 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 825
modtronix 25:72381be1b0ce 826 this->settings.State = RX_DONE;
GregCr 0:e6ceb13d2d05 827 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 828 {
GregCr 0:e6ceb13d2d05 829 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 830 }
GregCr 0:e6ceb13d2d05 831
GregCr 0:e6ceb13d2d05 832 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 833 {
GregCr 0:e6ceb13d2d05 834 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 835
GregCr 0:e6ceb13d2d05 836 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 837 {
GregCr 0:e6ceb13d2d05 838 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 839 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 840 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 841 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 842 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 843 }
GregCr 0:e6ceb13d2d05 844 }
GregCr 0:e6ceb13d2d05 845 else
GregCr 0:e6ceb13d2d05 846 {
GregCr 0:e6ceb13d2d05 847 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 848 {
GregCr 0:e6ceb13d2d05 849 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 850 }
GregCr 0:e6ceb13d2d05 851 else
GregCr 0:e6ceb13d2d05 852 {
GregCr 0:e6ceb13d2d05 853 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 854 }
GregCr 0:e6ceb13d2d05 855 }
GregCr 0:e6ceb13d2d05 856 }
GregCr 0:e6ceb13d2d05 857
GregCr 0:e6ceb13d2d05 858 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 859 {
GregCr 0:e6ceb13d2d05 860 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 861 {
GregCr 0:e6ceb13d2d05 862 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 863 {
GregCr 0:e6ceb13d2d05 864 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 865 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 866 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 867 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 868 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 869 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 870 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 871 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 872
GregCr 0:e6ceb13d2d05 873 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 874 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 875 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 876 }
GregCr 0:e6ceb13d2d05 877 break;
GregCr 0:e6ceb13d2d05 878 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 879 {
GregCr 6:e7f02929cd3d 880
GregCr 6:e7f02929cd3d 881 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 882 {
GregCr 6:e7f02929cd3d 883 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 884 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 885 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 886 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 887 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 888 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 889 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 890 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 891
GregCr 6:e7f02929cd3d 892 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 893 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 894 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 895 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 896 }
GregCr 6:e7f02929cd3d 897 else
GregCr 6:e7f02929cd3d 898 {
GregCr 6:e7f02929cd3d 899 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 900 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 901 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 902 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 903 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 904 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 905 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 906 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 907
GregCr 6:e7f02929cd3d 908 // DIO0=TxDone
GregCr 6:e7f02929cd3d 909 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 910 }
GregCr 0:e6ceb13d2d05 911 }
GregCr 0:e6ceb13d2d05 912 break;
GregCr 0:e6ceb13d2d05 913 }
GregCr 0:e6ceb13d2d05 914
modtronix 25:72381be1b0ce 915 this->settings.State = TX_DONE;
mluis 13:618826a997e2 916 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 917 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 918 }
GregCr 0:e6ceb13d2d05 919
GregCr 7:2b555111463f 920 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 921 {
GregCr 7:2b555111463f 922 switch( this->settings.Modem )
GregCr 7:2b555111463f 923 {
GregCr 7:2b555111463f 924 case MODEM_FSK:
GregCr 7:2b555111463f 925 {
GregCr 7:2b555111463f 926
GregCr 7:2b555111463f 927 }
GregCr 7:2b555111463f 928 break;
GregCr 7:2b555111463f 929 case MODEM_LORA:
GregCr 7:2b555111463f 930 {
GregCr 7:2b555111463f 931 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 932 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 933 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 934 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 935 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 936 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 937 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 938 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 939 );
GregCr 7:2b555111463f 940
GregCr 7:2b555111463f 941 // DIO3=CADDone
GregCr 7:2b555111463f 942 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 943
GregCr 7:2b555111463f 944 this->settings.State = CAD;
GregCr 7:2b555111463f 945 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 946 }
GregCr 7:2b555111463f 947 break;
GregCr 7:2b555111463f 948 default:
GregCr 7:2b555111463f 949 break;
GregCr 7:2b555111463f 950 }
GregCr 7:2b555111463f 951 }
GregCr 7:2b555111463f 952
GregCr 7:2b555111463f 953 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 954 {
GregCr 7:2b555111463f 955 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 956
GregCr 0:e6ceb13d2d05 957 switch( modem )
GregCr 0:e6ceb13d2d05 958 {
GregCr 0:e6ceb13d2d05 959 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 960 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 961 break;
GregCr 0:e6ceb13d2d05 962 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 963 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 964 {
GregCr 0:e6ceb13d2d05 965 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 966 }
GregCr 0:e6ceb13d2d05 967 else
GregCr 0:e6ceb13d2d05 968 {
GregCr 0:e6ceb13d2d05 969 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 970 }
GregCr 0:e6ceb13d2d05 971 break;
GregCr 0:e6ceb13d2d05 972 default:
GregCr 0:e6ceb13d2d05 973 rssi = -1;
GregCr 0:e6ceb13d2d05 974 break;
GregCr 0:e6ceb13d2d05 975 }
GregCr 0:e6ceb13d2d05 976 return rssi;
GregCr 0:e6ceb13d2d05 977 }
GregCr 0:e6ceb13d2d05 978
GregCr 0:e6ceb13d2d05 979 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 980 {
GregCr 0:e6ceb13d2d05 981 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 982 {
GregCr 0:e6ceb13d2d05 983 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 984 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 985 {
GregCr 0:e6ceb13d2d05 986 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 987 }
GregCr 0:e6ceb13d2d05 988 else
GregCr 0:e6ceb13d2d05 989 {
GregCr 0:e6ceb13d2d05 990 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 991 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 992 {
GregCr 0:e6ceb13d2d05 993 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 994 }
GregCr 0:e6ceb13d2d05 995 else
GregCr 0:e6ceb13d2d05 996 {
GregCr 0:e6ceb13d2d05 997 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 998 }
GregCr 0:e6ceb13d2d05 999 }
GregCr 0:e6ceb13d2d05 1000 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1001 }
GregCr 0:e6ceb13d2d05 1002 }
GregCr 0:e6ceb13d2d05 1003
GregCr 0:e6ceb13d2d05 1004 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 1005 {
GregCr 4:f0ce52e94d3f 1006 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 1007 {
mluis 13:618826a997e2 1008 this->settings.Modem = modem;
mluis 13:618826a997e2 1009 switch( this->settings.Modem )
mluis 13:618826a997e2 1010 {
mluis 13:618826a997e2 1011 default:
mluis 13:618826a997e2 1012 case MODEM_FSK:
mluis 13:618826a997e2 1013 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1014 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 1015
mluis 13:618826a997e2 1016 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1017 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 1018 break;
mluis 13:618826a997e2 1019 case MODEM_LORA:
mluis 13:618826a997e2 1020 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 1021 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 1022 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 1023 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 1024 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 1025 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 1026 break;
mluis 13:618826a997e2 1027 }
GregCr 0:e6ceb13d2d05 1028 }
GregCr 0:e6ceb13d2d05 1029 }
GregCr 0:e6ceb13d2d05 1030
GregCr 0:e6ceb13d2d05 1031 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1032 {
GregCr 0:e6ceb13d2d05 1033 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1034 {
modtronix 25:72381be1b0ce 1035 case RX_DONE:
GregCr 0:e6ceb13d2d05 1036 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1037 {
GregCr 0:e6ceb13d2d05 1038 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1039 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1040 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1041 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1042
GregCr 0:e6ceb13d2d05 1043 // Clear Irqs
GregCr 0:e6ceb13d2d05 1044 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1045 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1046 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1047 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1048
GregCr 0:e6ceb13d2d05 1049 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1050 {
GregCr 0:e6ceb13d2d05 1051 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1052 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1053 }
GregCr 0:e6ceb13d2d05 1054 else
GregCr 0:e6ceb13d2d05 1055 {
GregCr 5:11ec8a6ba4f0 1056 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1057 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1058 }
GregCr 0:e6ceb13d2d05 1059 }
GregCr 0:e6ceb13d2d05 1060 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1061 {
GregCr 0:e6ceb13d2d05 1062 rxTimeout( );
GregCr 0:e6ceb13d2d05 1063 }
GregCr 0:e6ceb13d2d05 1064 break;
modtronix 25:72381be1b0ce 1065 case TX_DONE:
mluis 13:618826a997e2 1066 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1067 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1068 {
GregCr 0:e6ceb13d2d05 1069 txTimeout( );
GregCr 0:e6ceb13d2d05 1070 }
GregCr 0:e6ceb13d2d05 1071 break;
GregCr 0:e6ceb13d2d05 1072 default:
GregCr 0:e6ceb13d2d05 1073 break;
GregCr 0:e6ceb13d2d05 1074 }
GregCr 0:e6ceb13d2d05 1075 }
GregCr 0:e6ceb13d2d05 1076
GregCr 0:e6ceb13d2d05 1077 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1078 {
GregCr 0:e6ceb13d2d05 1079 __IO uint8_t irqFlags = 0;
modtronix 20:7cf7c08f0088 1080
GregCr 0:e6ceb13d2d05 1081 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1082 {
modtronix 25:72381be1b0ce 1083 case RX_DONE:
GregCr 0:e6ceb13d2d05 1084 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1085 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1086 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1087 {
GregCr 0:e6ceb13d2d05 1088 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1089 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1090 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1091 {
GregCr 0:e6ceb13d2d05 1092 // Clear Irqs
GregCr 0:e6ceb13d2d05 1093 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1094 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1095 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1096 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1097
GregCr 0:e6ceb13d2d05 1098 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1099 {
GregCr 0:e6ceb13d2d05 1100 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1101 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1102 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1103 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1104 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1105 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1106 }
GregCr 0:e6ceb13d2d05 1107 else
GregCr 0:e6ceb13d2d05 1108 {
GregCr 0:e6ceb13d2d05 1109 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1110 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1111 }
GregCr 0:e6ceb13d2d05 1112 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1113
GregCr 0:e6ceb13d2d05 1114 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1115 {
GregCr 0:e6ceb13d2d05 1116 rxError( );
GregCr 0:e6ceb13d2d05 1117 }
GregCr 0:e6ceb13d2d05 1118 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1119 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1120 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1121 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1122 break;
GregCr 0:e6ceb13d2d05 1123 }
GregCr 0:e6ceb13d2d05 1124
GregCr 0:e6ceb13d2d05 1125 // Read received packet size
GregCr 0:e6ceb13d2d05 1126 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1127 {
GregCr 0:e6ceb13d2d05 1128 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1129 {
GregCr 0:e6ceb13d2d05 1130 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1131 }
GregCr 0:e6ceb13d2d05 1132 else
GregCr 0:e6ceb13d2d05 1133 {
GregCr 0:e6ceb13d2d05 1134 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1135 }
GregCr 0:e6ceb13d2d05 1136 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1137 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1138 }
GregCr 0:e6ceb13d2d05 1139 else
GregCr 0:e6ceb13d2d05 1140 {
GregCr 0:e6ceb13d2d05 1141 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1142 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1143 }
GregCr 0:e6ceb13d2d05 1144
GregCr 0:e6ceb13d2d05 1145 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1146 {
GregCr 0:e6ceb13d2d05 1147 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1148 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1149 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1150 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1151 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1152 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1153 }
GregCr 0:e6ceb13d2d05 1154 else
GregCr 0:e6ceb13d2d05 1155 {
GregCr 0:e6ceb13d2d05 1156 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1157 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1158 }
GregCr 0:e6ceb13d2d05 1159 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1160
GregCr 0:e6ceb13d2d05 1161 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1162 {
GregCr 0:e6ceb13d2d05 1163 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1164 }
GregCr 0:e6ceb13d2d05 1165 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1166 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1167 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1168 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1169 break;
GregCr 0:e6ceb13d2d05 1170 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1171 {
GregCr 0:e6ceb13d2d05 1172 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1173
GregCr 0:e6ceb13d2d05 1174 // Clear Irq
GregCr 0:e6ceb13d2d05 1175 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1176
GregCr 0:e6ceb13d2d05 1177 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1178 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1179 {
GregCr 0:e6ceb13d2d05 1180 // Clear Irq
GregCr 0:e6ceb13d2d05 1181 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1182
GregCr 0:e6ceb13d2d05 1183 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1184 {
GregCr 0:e6ceb13d2d05 1185 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1186 }
GregCr 0:e6ceb13d2d05 1187 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1188
GregCr 4:f0ce52e94d3f 1189 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1190 {
GregCr 0:e6ceb13d2d05 1191 rxError( );
GregCr 0:e6ceb13d2d05 1192 }
GregCr 0:e6ceb13d2d05 1193 break;
GregCr 0:e6ceb13d2d05 1194 }
GregCr 0:e6ceb13d2d05 1195
GregCr 0:e6ceb13d2d05 1196 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1197 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1198 {
GregCr 0:e6ceb13d2d05 1199 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1200 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1201 snr = -snr;
GregCr 0:e6ceb13d2d05 1202 }
GregCr 0:e6ceb13d2d05 1203 else
GregCr 0:e6ceb13d2d05 1204 {
GregCr 0:e6ceb13d2d05 1205 // Divide by 4
GregCr 0:e6ceb13d2d05 1206 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1207 }
GregCr 0:e6ceb13d2d05 1208
GregCr 7:2b555111463f 1209 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1210 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1211 {
GregCr 0:e6ceb13d2d05 1212 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1213 {
GregCr 0:e6ceb13d2d05 1214 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1215 snr;
GregCr 0:e6ceb13d2d05 1216 }
GregCr 0:e6ceb13d2d05 1217 else
GregCr 0:e6ceb13d2d05 1218 {
GregCr 0:e6ceb13d2d05 1219 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1220 snr;
GregCr 0:e6ceb13d2d05 1221 }
GregCr 0:e6ceb13d2d05 1222 }
GregCr 0:e6ceb13d2d05 1223 else
GregCr 0:e6ceb13d2d05 1224 {
GregCr 0:e6ceb13d2d05 1225 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1226 {
GregCr 0:e6ceb13d2d05 1227 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1228 }
GregCr 0:e6ceb13d2d05 1229 else
GregCr 0:e6ceb13d2d05 1230 {
GregCr 0:e6ceb13d2d05 1231 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1232 }
GregCr 0:e6ceb13d2d05 1233 }
GregCr 0:e6ceb13d2d05 1234
GregCr 0:e6ceb13d2d05 1235 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1236 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1237
GregCr 0:e6ceb13d2d05 1238 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1239 {
GregCr 0:e6ceb13d2d05 1240 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1241 }
GregCr 0:e6ceb13d2d05 1242 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1243
GregCr 0:e6ceb13d2d05 1244 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1245 {
GregCr 0:e6ceb13d2d05 1246 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1247 }
GregCr 0:e6ceb13d2d05 1248 }
GregCr 0:e6ceb13d2d05 1249 break;
GregCr 0:e6ceb13d2d05 1250 default:
GregCr 0:e6ceb13d2d05 1251 break;
GregCr 0:e6ceb13d2d05 1252 }
GregCr 0:e6ceb13d2d05 1253 break;
modtronix 25:72381be1b0ce 1254 case TX_DONE:
GregCr 0:e6ceb13d2d05 1255 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1256 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1257 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1258 {
GregCr 0:e6ceb13d2d05 1259 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1260 // Clear Irq
GregCr 0:e6ceb13d2d05 1261 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1262 // Intentional fall through
GregCr 0:e6ceb13d2d05 1263 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1264 default:
GregCr 0:e6ceb13d2d05 1265 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1266 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1267 {
GregCr 0:e6ceb13d2d05 1268 txDone( );
GregCr 0:e6ceb13d2d05 1269 }
GregCr 0:e6ceb13d2d05 1270 break;
GregCr 0:e6ceb13d2d05 1271 }
GregCr 0:e6ceb13d2d05 1272 break;
GregCr 0:e6ceb13d2d05 1273 default:
GregCr 0:e6ceb13d2d05 1274 break;
GregCr 0:e6ceb13d2d05 1275 }
GregCr 0:e6ceb13d2d05 1276 }
GregCr 0:e6ceb13d2d05 1277
GregCr 0:e6ceb13d2d05 1278 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1279 {
GregCr 0:e6ceb13d2d05 1280 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1281 {
modtronix 25:72381be1b0ce 1282 case RX_DONE:
GregCr 0:e6ceb13d2d05 1283 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1284 {
GregCr 0:e6ceb13d2d05 1285 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1286 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1287 // Read received packet size
GregCr 0:e6ceb13d2d05 1288 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1289 {
GregCr 0:e6ceb13d2d05 1290 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1291 {
GregCr 0:e6ceb13d2d05 1292 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1293 }
GregCr 0:e6ceb13d2d05 1294 else
GregCr 0:e6ceb13d2d05 1295 {
GregCr 0:e6ceb13d2d05 1296 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1297 }
GregCr 0:e6ceb13d2d05 1298 }
GregCr 0:e6ceb13d2d05 1299
GregCr 0:e6ceb13d2d05 1300 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1301 {
GregCr 0:e6ceb13d2d05 1302 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1303 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1304 }
GregCr 0:e6ceb13d2d05 1305 else
GregCr 0:e6ceb13d2d05 1306 {
GregCr 0:e6ceb13d2d05 1307 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1308 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1309 }
GregCr 0:e6ceb13d2d05 1310 break;
GregCr 0:e6ceb13d2d05 1311 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1312 // Sync time out
GregCr 0:e6ceb13d2d05 1313 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1314 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1315 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 0:e6ceb13d2d05 1317 rxTimeout( );
GregCr 0:e6ceb13d2d05 1318 }
GregCr 0:e6ceb13d2d05 1319 break;
GregCr 0:e6ceb13d2d05 1320 default:
GregCr 0:e6ceb13d2d05 1321 break;
GregCr 0:e6ceb13d2d05 1322 }
GregCr 0:e6ceb13d2d05 1323 break;
modtronix 25:72381be1b0ce 1324 case TX_DONE:
GregCr 0:e6ceb13d2d05 1325 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1326 {
GregCr 0:e6ceb13d2d05 1327 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1328 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1329 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1330 {
GregCr 0:e6ceb13d2d05 1331 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1332 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1333 }
GregCr 0:e6ceb13d2d05 1334 else
GregCr 0:e6ceb13d2d05 1335 {
GregCr 0:e6ceb13d2d05 1336 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1337 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1338 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1339 }
GregCr 0:e6ceb13d2d05 1340 break;
GregCr 0:e6ceb13d2d05 1341 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1342 break;
GregCr 0:e6ceb13d2d05 1343 default:
GregCr 0:e6ceb13d2d05 1344 break;
GregCr 0:e6ceb13d2d05 1345 }
GregCr 0:e6ceb13d2d05 1346 break;
GregCr 0:e6ceb13d2d05 1347 default:
GregCr 0:e6ceb13d2d05 1348 break;
GregCr 0:e6ceb13d2d05 1349 }
GregCr 0:e6ceb13d2d05 1350 }
GregCr 0:e6ceb13d2d05 1351
GregCr 0:e6ceb13d2d05 1352 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1353 {
GregCr 0:e6ceb13d2d05 1354 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1355 {
modtronix 25:72381be1b0ce 1356 case RX_DONE:
GregCr 0:e6ceb13d2d05 1357 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1358 {
GregCr 0:e6ceb13d2d05 1359 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1360 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1361 {
GregCr 0:e6ceb13d2d05 1362 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1363
GregCr 0:e6ceb13d2d05 1364 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1365
GregCr 0:e6ceb13d2d05 1366 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1367
GregCr 0:e6ceb13d2d05 1368 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1369 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1370 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1371 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1372 }
GregCr 0:e6ceb13d2d05 1373 break;
GregCr 0:e6ceb13d2d05 1374 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1375 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1376 {
GregCr 6:e7f02929cd3d 1377 // Clear Irq
GregCr 6:e7f02929cd3d 1378 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1379
mluis 13:618826a997e2 1380 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1381 {
mluis 13:618826a997e2 1382 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1383 }
GregCr 6:e7f02929cd3d 1384 }
GregCr 0:e6ceb13d2d05 1385 break;
GregCr 0:e6ceb13d2d05 1386 default:
GregCr 0:e6ceb13d2d05 1387 break;
GregCr 0:e6ceb13d2d05 1388 }
GregCr 0:e6ceb13d2d05 1389 break;
modtronix 25:72381be1b0ce 1390 case TX_DONE:
GregCr 0:e6ceb13d2d05 1391 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1392 {
GregCr 0:e6ceb13d2d05 1393 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1394 break;
GregCr 0:e6ceb13d2d05 1395 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1396 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1397 {
GregCr 6:e7f02929cd3d 1398 // Clear Irq
GregCr 6:e7f02929cd3d 1399 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1400
mluis 13:618826a997e2 1401 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1402 {
mluis 13:618826a997e2 1403 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1404 }
GregCr 6:e7f02929cd3d 1405 }
GregCr 0:e6ceb13d2d05 1406 break;
GregCr 0:e6ceb13d2d05 1407 default:
GregCr 0:e6ceb13d2d05 1408 break;
GregCr 0:e6ceb13d2d05 1409 }
GregCr 0:e6ceb13d2d05 1410 break;
GregCr 0:e6ceb13d2d05 1411 default:
GregCr 0:e6ceb13d2d05 1412 break;
GregCr 0:e6ceb13d2d05 1413 }
GregCr 0:e6ceb13d2d05 1414 }
GregCr 0:e6ceb13d2d05 1415
GregCr 0:e6ceb13d2d05 1416 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1417 {
GregCr 0:e6ceb13d2d05 1418 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1419 {
GregCr 0:e6ceb13d2d05 1420 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1421 break;
GregCr 0:e6ceb13d2d05 1422 case MODEM_LORA:
mluis 13:618826a997e2 1423 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1424 {
mluis 13:618826a997e2 1425 // Clear Irq
mluis 13:618826a997e2 1426 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1427 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1428 {
mluis 13:618826a997e2 1429 cadDone( true );
mluis 13:618826a997e2 1430 }
GregCr 12:aa5b3bf7fdf4 1431 }
GregCr 12:aa5b3bf7fdf4 1432 else
mluis 13:618826a997e2 1433 {
mluis 13:618826a997e2 1434 // Clear Irq
mluis 13:618826a997e2 1435 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1436 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1437 {
mluis 13:618826a997e2 1438 cadDone( false );
mluis 13:618826a997e2 1439 }
GregCr 7:2b555111463f 1440 }
GregCr 0:e6ceb13d2d05 1441 break;
GregCr 0:e6ceb13d2d05 1442 default:
GregCr 0:e6ceb13d2d05 1443 break;
GregCr 0:e6ceb13d2d05 1444 }
GregCr 0:e6ceb13d2d05 1445 }
GregCr 0:e6ceb13d2d05 1446
modtronix 25:72381be1b0ce 1447 /*
GregCr 0:e6ceb13d2d05 1448 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1449 {
GregCr 0:e6ceb13d2d05 1450 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1451 {
GregCr 0:e6ceb13d2d05 1452 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1453 {
GregCr 0:e6ceb13d2d05 1454 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1455 {
GregCr 0:e6ceb13d2d05 1456 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1457 }
GregCr 0:e6ceb13d2d05 1458 }
GregCr 0:e6ceb13d2d05 1459 break;
GregCr 0:e6ceb13d2d05 1460 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1461 break;
GregCr 0:e6ceb13d2d05 1462 default:
GregCr 0:e6ceb13d2d05 1463 break;
GregCr 0:e6ceb13d2d05 1464 }
GregCr 0:e6ceb13d2d05 1465 }
GregCr 0:e6ceb13d2d05 1466
GregCr 0:e6ceb13d2d05 1467 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1468 {
GregCr 0:e6ceb13d2d05 1469 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1470 {
GregCr 0:e6ceb13d2d05 1471 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1472 break;
GregCr 0:e6ceb13d2d05 1473 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1474 break;
GregCr 0:e6ceb13d2d05 1475 default:
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 }
mluis 13:618826a997e2 1478 }
modtronix 25:72381be1b0ce 1479 */