Miguel Luis / SX1272Lib

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Fork of SX1272Lib by Semtech

sx1272/sx1272-hal.cpp@8:bfdcd5c6ec14, 2016-11-30 (annotated)

Committer:
mluis
Date:
Wed Nov 30 17:35:51 2016 +0000
Revision:
8:bfdcd5c6ec14
Parent:
6:69d5976b504d
Child:
9:4e1a35fd0ccd
Synchronized with https://github.com/Lora-net/LoRaMac-node develop branch git commit f1b924d9f5aaeb8e73e969a48c01c088fef7ab1f

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
mluis 8:bfdcd5c6ec14 17 #if defined ( TARGET_MOTE_L152RC )
mluis 8:bfdcd5c6ec14 18 /*
mluis 8:bfdcd5c6ec14 19 PD_2=0 PD_2=1
mluis 8:bfdcd5c6ec14 20 op PaB rfo rfo
mluis 8:bfdcd5c6ec14 21 0 4.6 18.5 27.0
mluis 8:bfdcd5c6ec14 22 1 5.6 21.1 28.1
mluis 8:bfdcd5c6ec14 23 2 6.7 23.3 29.1
mluis 8:bfdcd5c6ec14 24 3 7.7 25.3 30.1
mluis 8:bfdcd5c6ec14 25 4 8.8 26.2 30.7
mluis 8:bfdcd5c6ec14 26 5 9.8 27.3 31.2
mluis 8:bfdcd5c6ec14 27 6 10.7 28.1 31.6
mluis 8:bfdcd5c6ec14 28 7 11.7 28.6 32.2
mluis 8:bfdcd5c6ec14 29 8 12.8 29.2 32.4
mluis 8:bfdcd5c6ec14 30 9 13.7 29.9 32.9
mluis 8:bfdcd5c6ec14 31 10 14.7 30.5 33.1
mluis 8:bfdcd5c6ec14 32 11 15.6 30.8 33.4
mluis 8:bfdcd5c6ec14 33 12 16.4 30.9 33.6
mluis 8:bfdcd5c6ec14 34 13 17.1 31.0 33.7
mluis 8:bfdcd5c6ec14 35 14 17.8 31.1 33.7
mluis 8:bfdcd5c6ec14 36 15 18.4 31.1 33.7
mluis 8:bfdcd5c6ec14 37 */
mluis 8:bfdcd5c6ec14 38 // txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
mluis 8:bfdcd5c6ec14 39 static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
mluis 8:bfdcd5c6ec14 40
mluis 8:bfdcd5c6ec14 41 // txpow: 20 21 22 23 24 25 26 27 28 29 30
mluis 8:bfdcd5c6ec14 42 static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
mluis 8:bfdcd5c6ec14 43
mluis 8:bfdcd5c6ec14 44 #endif
mluis 8:bfdcd5c6ec14 45
GregCr 2:cd1093b6676f 46 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 47
GregCr 2:cd1093b6676f 48 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 49 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 50 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
mluis 0:45c4f0364ca4 51 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 52 PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 53 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 54 PinName txctl, PinName rxctl )
mluis 0:45c4f0364ca4 55 #else
mluis 0:45c4f0364ca4 56 PinName antSwitch )
mluis 0:45c4f0364ca4 57 #endif
mluis 0:45c4f0364ca4 58 : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
mluis 0:45c4f0364ca4 59 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 60 RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 61 RfSwitchCntr2( rfSwitchCntr2 ),
mluis 8:bfdcd5c6ec14 62 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 63 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 64 TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 65 RxCtl ( rxctl )
mluis 0:45c4f0364ca4 66 #else
mluis 0:45c4f0364ca4 67 AntSwitch( antSwitch ),
mluis 6:69d5976b504d 68 #if( defined ( TARGET_NUCLEO_L152RE ) ) || defined ( TARGET_NUCLEO_L476RG )
dudmuck 1:b0372ef620d0 69 Fake( D8 )
mluis 0:45c4f0364ca4 70 #else
mluis 0:45c4f0364ca4 71 Fake( A3 )
mluis 0:45c4f0364ca4 72 #endif
mluis 0:45c4f0364ca4 73 #endif
mluis 0:45c4f0364ca4 74 {
mluis 0:45c4f0364ca4 75 this->RadioEvents = events;
mluis 0:45c4f0364ca4 76
mluis 0:45c4f0364ca4 77 Reset( );
mluis 4:90bd79f1b458 78
mluis 0:45c4f0364ca4 79 IoInit( );
mluis 4:90bd79f1b458 80
mluis 0:45c4f0364ca4 81 SetOpMode( RF_OPMODE_SLEEP );
mluis 4:90bd79f1b458 82
mluis 0:45c4f0364ca4 83 IoIrqInit( dioIrq );
mluis 4:90bd79f1b458 84
mluis 0:45c4f0364ca4 85 RadioRegistersInit( );
mluis 0:45c4f0364ca4 86
mluis 0:45c4f0364ca4 87 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 88
mluis 0:45c4f0364ca4 89 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 90 }
mluis 0:45c4f0364ca4 91
mluis 4:90bd79f1b458 92 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 6:69d5976b504d 93 #if defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_NUCLEO_L476RG )
mluis 0:45c4f0364ca4 94 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 95 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 96 Fake( D8 )
mluis 0:45c4f0364ca4 97 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 98 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 99 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 100 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 101 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 102 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 103 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 104 TxCtl( LORA_TXCTL ),
mluis 4:90bd79f1b458 105 RxCtl( LORA_RXCTL )
mluis 0:45c4f0364ca4 106 #else
mluis 0:45c4f0364ca4 107 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 0:45c4f0364ca4 108 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 109 Fake( A3 )
mluis 0:45c4f0364ca4 110 #endif
mluis 0:45c4f0364ca4 111 {
mluis 0:45c4f0364ca4 112 this->RadioEvents = events;
mluis 0:45c4f0364ca4 113
mluis 0:45c4f0364ca4 114 Reset( );
mluis 4:90bd79f1b458 115
mluis 0:45c4f0364ca4 116 boardConnected = UNKNOWN;
mluis 4:90bd79f1b458 117
mluis 0:45c4f0364ca4 118 DetectBoardType( );
mluis 4:90bd79f1b458 119
mluis 0:45c4f0364ca4 120 IoInit( );
mluis 4:90bd79f1b458 121
mluis 0:45c4f0364ca4 122 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 123 IoIrqInit( dioIrq );
mluis 4:90bd79f1b458 124
mluis 0:45c4f0364ca4 125 RadioRegistersInit( );
mluis 0:45c4f0364ca4 126
mluis 0:45c4f0364ca4 127 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 128
mluis 0:45c4f0364ca4 129 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 130 }
mluis 0:45c4f0364ca4 131
mluis 0:45c4f0364ca4 132 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 133 // Board relative functions
mluis 0:45c4f0364ca4 134 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 135 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 136 {
mluis 0:45c4f0364ca4 137 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 138 {
mluis 0:45c4f0364ca4 139 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 140 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 141 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 142 boardConnected = MDOT_F411RE;
mluis 0:45c4f0364ca4 143 #else
mluis 0:45c4f0364ca4 144 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 145 wait_ms( 1 );
mluis 0:45c4f0364ca4 146 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 147 {
mluis 0:45c4f0364ca4 148 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 149 }
mluis 0:45c4f0364ca4 150 else
mluis 0:45c4f0364ca4 151 {
GregCr 2:cd1093b6676f 152 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 155 wait_ms( 1 );
mluis 0:45c4f0364ca4 156 #endif
mluis 0:45c4f0364ca4 157 }
mluis 0:45c4f0364ca4 158 return ( boardConnected );
mluis 0:45c4f0364ca4 159 }
mluis 0:45c4f0364ca4 160
GregCr 2:cd1093b6676f 161 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 162 {
mluis 0:45c4f0364ca4 163 AntSwInit( );
mluis 0:45c4f0364ca4 164 SpiInit( );
mluis 0:45c4f0364ca4 165 }
mluis 0:45c4f0364ca4 166
GregCr 2:cd1093b6676f 167 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 168 {
mluis 0:45c4f0364ca4 169 uint8_t i = 0;
mluis 0:45c4f0364ca4 170 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 171 {
mluis 0:45c4f0364ca4 172 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 173 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 174 }
mluis 0:45c4f0364ca4 175 }
mluis 0:45c4f0364ca4 176
GregCr 2:cd1093b6676f 177 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 178 {
mluis 0:45c4f0364ca4 179 nss = 1;
mluis 0:45c4f0364ca4 180 spi.format( 8,0 );
mluis 0:45c4f0364ca4 181 uint32_t frequencyToSet = 8000000;
mluis 6:69d5976b504d 182 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_NUCLEO_L476RG ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) )
mluis 0:45c4f0364ca4 183 spi.frequency( frequencyToSet );
mluis 0:45c4f0364ca4 184 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
mluis 0:45c4f0364ca4 185 spi.frequency( frequencyToSet * 2 );
mluis 0:45c4f0364ca4 186 #else
mluis 0:45c4f0364ca4 187 #warning "Check the board's SPI frequency"
mluis 0:45c4f0364ca4 188 #endif
mluis 0:45c4f0364ca4 189 wait(0.1);
mluis 0:45c4f0364ca4 190 }
mluis 0:45c4f0364ca4 191
GregCr 2:cd1093b6676f 192 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 193 {
mluis 6:69d5976b504d 194 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_NUCLEO_L476RG ) || defined ( TARGET_NUCLEO_L476RG ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 195 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 196 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 197 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 198 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 199 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 200 #endif
GregCr 2:cd1093b6676f 201 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 202 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 203 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 204 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 205 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 206 }
mluis 0:45c4f0364ca4 207
GregCr 2:cd1093b6676f 208 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 209 {
mluis 0:45c4f0364ca4 210 //nothing
mluis 0:45c4f0364ca4 211 }
mluis 0:45c4f0364ca4 212
mluis 8:bfdcd5c6ec14 213 void SX1272MB2xAS::SetRfTxPower( int8_t power )
mluis 8:bfdcd5c6ec14 214 {
mluis 8:bfdcd5c6ec14 215 #if defined ( TARGET_MOTE_L152RC )
mluis 8:bfdcd5c6ec14 216 uint8_t paConfig = 0;
mluis 8:bfdcd5c6ec14 217 uint8_t paDac = 0;
mluis 8:bfdcd5c6ec14 218
mluis 8:bfdcd5c6ec14 219 paConfig = Read( REG_PACONFIG );
mluis 8:bfdcd5c6ec14 220 paDac = Read( REG_PADAC );
mluis 8:bfdcd5c6ec14 221
mluis 8:bfdcd5c6ec14 222 if( power > 19 )
mluis 8:bfdcd5c6ec14 223 {
mluis 8:bfdcd5c6ec14 224 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
mluis 8:bfdcd5c6ec14 225 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
mluis 8:bfdcd5c6ec14 226 }
mluis 8:bfdcd5c6ec14 227 else
mluis 8:bfdcd5c6ec14 228 {
mluis 8:bfdcd5c6ec14 229 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
mluis 8:bfdcd5c6ec14 230 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
mluis 8:bfdcd5c6ec14 231 }
mluis 8:bfdcd5c6ec14 232 Write( REG_PACONFIG, paConfig );
mluis 8:bfdcd5c6ec14 233 Write( REG_PADAC, paDac );
mluis 8:bfdcd5c6ec14 234 #else
mluis 8:bfdcd5c6ec14 235 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 8:bfdcd5c6ec14 236
mluis 8:bfdcd5c6ec14 237 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 8:bfdcd5c6ec14 238 {
mluis 8:bfdcd5c6ec14 239 if( power > 17 )
mluis 8:bfdcd5c6ec14 240 {
mluis 8:bfdcd5c6ec14 241 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 8:bfdcd5c6ec14 242 }
mluis 8:bfdcd5c6ec14 243 else
mluis 8:bfdcd5c6ec14 244 {
mluis 8:bfdcd5c6ec14 245 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 8:bfdcd5c6ec14 246 }
mluis 8:bfdcd5c6ec14 247 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 8:bfdcd5c6ec14 248 {
mluis 8:bfdcd5c6ec14 249 if( power < 5 )
mluis 8:bfdcd5c6ec14 250 {
mluis 8:bfdcd5c6ec14 251 power = 5;
mluis 8:bfdcd5c6ec14 252 }
mluis 8:bfdcd5c6ec14 253 if( power > 20 )
mluis 8:bfdcd5c6ec14 254 {
mluis 8:bfdcd5c6ec14 255 power = 20;
mluis 8:bfdcd5c6ec14 256 }
mluis 8:bfdcd5c6ec14 257 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 8:bfdcd5c6ec14 258 }
mluis 8:bfdcd5c6ec14 259 else
mluis 8:bfdcd5c6ec14 260 {
mluis 8:bfdcd5c6ec14 261 if( power < 2 )
mluis 8:bfdcd5c6ec14 262 {
mluis 8:bfdcd5c6ec14 263 power = 2;
mluis 8:bfdcd5c6ec14 264 }
mluis 8:bfdcd5c6ec14 265 if( power > 17 )
mluis 8:bfdcd5c6ec14 266 {
mluis 8:bfdcd5c6ec14 267 power = 17;
mluis 8:bfdcd5c6ec14 268 }
mluis 8:bfdcd5c6ec14 269 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 8:bfdcd5c6ec14 270 }
mluis 8:bfdcd5c6ec14 271 }
mluis 8:bfdcd5c6ec14 272 else
mluis 8:bfdcd5c6ec14 273 {
mluis 8:bfdcd5c6ec14 274 if( power < -1 )
mluis 8:bfdcd5c6ec14 275 {
mluis 8:bfdcd5c6ec14 276 power = -1;
mluis 8:bfdcd5c6ec14 277 }
mluis 8:bfdcd5c6ec14 278 if( power > 14 )
mluis 8:bfdcd5c6ec14 279 {
mluis 8:bfdcd5c6ec14 280 power = 14;
mluis 8:bfdcd5c6ec14 281 }
mluis 8:bfdcd5c6ec14 282 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 8:bfdcd5c6ec14 283 }
mluis 8:bfdcd5c6ec14 284 #endif
mluis 8:bfdcd5c6ec14 285 }
mluis 8:bfdcd5c6ec14 286
GregCr 2:cd1093b6676f 287 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 288 {
dudmuck 1:b0372ef620d0 289 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE )
mluis 0:45c4f0364ca4 290 {
mluis 0:45c4f0364ca4 291 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 292 }
mluis 0:45c4f0364ca4 293 else
mluis 0:45c4f0364ca4 294 {
mluis 0:45c4f0364ca4 295 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 296 }
mluis 0:45c4f0364ca4 297 }
mluis 0:45c4f0364ca4 298
GregCr 2:cd1093b6676f 299 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 300 {
mluis 0:45c4f0364ca4 301 if( isRadioActive != status )
mluis 0:45c4f0364ca4 302 {
mluis 0:45c4f0364ca4 303 isRadioActive = status;
mluis 0:45c4f0364ca4 304
mluis 0:45c4f0364ca4 305 if( status == false )
mluis 0:45c4f0364ca4 306 {
mluis 0:45c4f0364ca4 307 AntSwInit( );
mluis 0:45c4f0364ca4 308 }
mluis 0:45c4f0364ca4 309 else
mluis 0:45c4f0364ca4 310 {
mluis 0:45c4f0364ca4 311 AntSwDeInit( );
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313 }
mluis 0:45c4f0364ca4 314 }
mluis 0:45c4f0364ca4 315
GregCr 2:cd1093b6676f 316 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 317 {
mluis 0:45c4f0364ca4 318 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 319 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 320 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 321 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 322 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 323 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 324 this->RxCtl = 0;
mluis 0:45c4f0364ca4 325 #else
mluis 0:45c4f0364ca4 326 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 327 #endif
mluis 0:45c4f0364ca4 328 }
mluis 0:45c4f0364ca4 329
GregCr 2:cd1093b6676f 330 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 331 {
mluis 0:45c4f0364ca4 332 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 333 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 334 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 335 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 336 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 337 this->TxCtl = 0;
mluis 8:bfdcd5c6ec14 338 this->RxCtl = 0;
mluis 0:45c4f0364ca4 339 #else
mluis 0:45c4f0364ca4 340 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 341 #endif
mluis 0:45c4f0364ca4 342 }
mluis 0:45c4f0364ca4 343
mluis 8:bfdcd5c6ec14 344 void SX1272MB2xAS::SetAntSw( uint8_t opMode )
mluis 0:45c4f0364ca4 345 {
mluis 8:bfdcd5c6ec14 346 switch( opMode )
mluis 0:45c4f0364ca4 347 {
mluis 0:45c4f0364ca4 348 case RFLR_OPMODE_TRANSMITTER:
mluis 8:bfdcd5c6ec14 349 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 350 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 351 {
mluis 0:45c4f0364ca4 352 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 353 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 354 }
mluis 0:45c4f0364ca4 355 else
mluis 0:45c4f0364ca4 356 {
mluis 0:45c4f0364ca4 357 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 358 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 359 }
mluis 8:bfdcd5c6ec14 360 #elif defined ( TARGET_MTS_MDOT_F411RE )
mluis 8:bfdcd5c6ec14 361 /* SKY13350 */
mluis 8:bfdcd5c6ec14 362 this->TxCtl = 1;
mluis 8:bfdcd5c6ec14 363 this->RxCtl = 0;
mluis 8:bfdcd5c6ec14 364 #else
mluis 8:bfdcd5c6ec14 365 this->AntSwitch = 1;
mluis 8:bfdcd5c6ec14 366 #endif
mluis 0:45c4f0364ca4 367 break;
mluis 0:45c4f0364ca4 368 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 369 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 370 case RFLR_OPMODE_CAD:
mluis 8:bfdcd5c6ec14 371 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 372 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 373 this->RfSwitchCntr2 = 1;
mluis 8:bfdcd5c6ec14 374 #elif defined ( TARGET_MTS_MDOT_F411RE )
mluis 8:bfdcd5c6ec14 375 /* SKY13350 */
mluis 8:bfdcd5c6ec14 376 this->TxCtl = 0;
mluis 8:bfdcd5c6ec14 377 this->RxCtl = 1;
mluis 8:bfdcd5c6ec14 378 #else
mluis 8:bfdcd5c6ec14 379 this->AntSwitch = 0;
mluis 8:bfdcd5c6ec14 380 #endif
mluis 8:bfdcd5c6ec14 381
mluis 0:45c4f0364ca4 382 break;
mluis 0:45c4f0364ca4 383 default:
mluis 8:bfdcd5c6ec14 384 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 385 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 386 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 387 this->PwrAmpCntr = 0;
mluis 8:bfdcd5c6ec14 388 #elif defined ( TARGET_MTS_MDOT_F411RE )
mluis 8:bfdcd5c6ec14 389 /* SKY13350 */
mluis 8:bfdcd5c6ec14 390 this->TxCtl = 0;
mluis 8:bfdcd5c6ec14 391 this->RxCtl = 0;
mluis 8:bfdcd5c6ec14 392 #else
mluis 8:bfdcd5c6ec14 393 this->AntSwitch = 0;
mluis 8:bfdcd5c6ec14 394 #endif
mluis 0:45c4f0364ca4 395 break;
mluis 0:45c4f0364ca4 396 }
mluis 0:45c4f0364ca4 397 }
mluis 0:45c4f0364ca4 398
GregCr 2:cd1093b6676f 399 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 400 {
mluis 0:45c4f0364ca4 401 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 402 return true;
mluis 0:45c4f0364ca4 403 }
mluis 0:45c4f0364ca4 404
mluis 0:45c4f0364ca4 405
GregCr 2:cd1093b6676f 406 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 407 {
mluis 0:45c4f0364ca4 408 reset.output();
mluis 0:45c4f0364ca4 409 reset = 0;
mluis 0:45c4f0364ca4 410 wait_ms( 1 );
mluis 0:45c4f0364ca4 411 reset.input();
mluis 0:45c4f0364ca4 412 wait_ms( 6 );
mluis 0:45c4f0364ca4 413 }
mluis 0:45c4f0364ca4 414
GregCr 2:cd1093b6676f 415 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 416 {
mluis 0:45c4f0364ca4 417 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 418 }
mluis 0:45c4f0364ca4 419
GregCr 2:cd1093b6676f 420 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 421 {
mluis 0:45c4f0364ca4 422 uint8_t data;
mluis 0:45c4f0364ca4 423 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 424 return data;
mluis 0:45c4f0364ca4 425 }
mluis 0:45c4f0364ca4 426
GregCr 2:cd1093b6676f 427 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 428 {
mluis 0:45c4f0364ca4 429 uint8_t i;
mluis 0:45c4f0364ca4 430
mluis 0:45c4f0364ca4 431 nss = 0;
mluis 0:45c4f0364ca4 432 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 433 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 434 {
mluis 0:45c4f0364ca4 435 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 436 }
mluis 0:45c4f0364ca4 437 nss = 1;
mluis 0:45c4f0364ca4 438 }
mluis 0:45c4f0364ca4 439
GregCr 2:cd1093b6676f 440 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 441 {
mluis 0:45c4f0364ca4 442 uint8_t i;
mluis 0:45c4f0364ca4 443
mluis 0:45c4f0364ca4 444 nss = 0;
mluis 0:45c4f0364ca4 445 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 446 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 447 {
mluis 0:45c4f0364ca4 448 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 449 }
mluis 0:45c4f0364ca4 450 nss = 1;
mluis 0:45c4f0364ca4 451 }
mluis 0:45c4f0364ca4 452
GregCr 2:cd1093b6676f 453 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 454 {
mluis 0:45c4f0364ca4 455 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 456 }
mluis 0:45c4f0364ca4 457
GregCr 2:cd1093b6676f 458 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 459 {
mluis 0:45c4f0364ca4 460 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 461 }