rt_HAL_CM.h

00001 /*----------------------------------------------------------------------------
00002  *      RL-ARM - RTX
00003  *----------------------------------------------------------------------------
00004  *      Name:    RT_HAL_CM.H
00005  *      Purpose: Hardware Abstraction Layer for Cortex-M definitions
00006  *      Rev.:    V4.50
00007  *----------------------------------------------------------------------------
00008  *
00009  * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
00010  * All rights reserved.
00011  * Redistribution and use in source and binary forms, with or without
00012  * modification, are permitted provided that the following conditions are met:
00013  *  - Redistributions of source code must retain the above copyright
00014  *    notice, this list of conditions and the following disclaimer.
00015  *  - Redistributions in binary form must reproduce the above copyright
00016  *    notice, this list of conditions and the following disclaimer in the
00017  *    documentation and/or other materials provided with the distribution.
00018  *  - Neither the name of ARM  nor the names of its contributors may be used 
00019  *    to endorse or promote products derived from this software without 
00020  *    specific prior written permission.
00021  *
00022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
00023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
00024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00025  * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
00028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
00029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
00030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00032  * POSSIBILITY OF SUCH DAMAGE.
00033  *---------------------------------------------------------------------------*/
00034 
00035 /* Definitions */
00036 #define INITIAL_xPSR    0x01000000
00037 #define DEMCR_TRCENA    0x01000000
00038 #define ITM_ITMENA      0x00000001
00039 #define MAGIC_WORD      0xE25A2EA5
00040 
00041 #if defined (__CC_ARM)          /* ARM Compiler */
00042 
00043 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
00044  #define __USE_EXCLUSIVE_ACCESS
00045 #else
00046  #undef  __USE_EXCLUSIVE_ACCESS
00047 #endif
00048 
00049 #elif defined (__GNUC__)        /* GNU Compiler */
00050 
00051 #undef  __USE_EXCLUSIVE_ACCESS
00052 
00053 #if defined (__CORTEX_M0)
00054 #define __TARGET_ARCH_6S_M 1
00055 #else
00056 #define __TARGET_ARCH_6S_M 0
00057 #endif
00058 
00059 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00060 #define __TARGET_FPU_VFP 1
00061 #else
00062 #define __TARGET_FPU_VFP 0
00063 #endif
00064 
00065 #define __inline inline
00066 #define __weak   __attribute__((weak))
00067 
00068 #ifndef __CMSIS_GENERIC
00069 
00070 __attribute__((always_inline)) static inline void __enable_irq(void)
00071 {
00072   __asm volatile ("cpsie i");
00073 }
00074 
00075 __attribute__((always_inline)) static inline U32 __disable_irq(void)
00076 {
00077   U32 result;
00078 
00079   __asm volatile ("mrs %0, primask" : "=r" (result));
00080   __asm volatile ("cpsid i");
00081   return(result & 1);
00082 }
00083 
00084 #endif
00085 
00086 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
00087 {
00088   U8 result;
00089   
00090   __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
00091   return(result);
00092 }
00093 
00094 #elif defined (__ICCARM__)      /* IAR Compiler */
00095 
00096 #undef  __USE_EXCLUSIVE_ACCESS
00097 
00098 #if (__CORE__ == __ARM6M__)
00099 #define __TARGET_ARCH_6S_M 1
00100 #else
00101 #define __TARGET_ARCH_6S_M 0
00102 #endif
00103 
00104 #if defined __ARMVFP__
00105 #define __TARGET_FPU_VFP 1
00106 #else
00107 #define __TARGET_FPU_VFP 0
00108 #endif
00109 
00110 #define __inline inline
00111 
00112 #ifndef __CMSIS_GENERIC
00113 
00114 static inline void __enable_irq(void)
00115 {
00116   __asm volatile ("cpsie i");
00117 }
00118 
00119 static inline U32 __disable_irq(void)
00120 {
00121   U32 result;
00122   
00123   __asm volatile ("mrs %0, primask" : "=r" (result));
00124   __asm volatile ("cpsid i");
00125   return(result & 1);
00126 }
00127 
00128 #endif
00129 
00130 static inline U8 __clz(U32 value)
00131 {
00132   U8 result;
00133   
00134   __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
00135   return(result);
00136 }
00137 
00138 #endif
00139 
00140 /* NVIC registers */
00141 #define NVIC_ST_CTRL    (*((volatile U32 *)0xE000E010))
00142 #define NVIC_ST_RELOAD  (*((volatile U32 *)0xE000E014))
00143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
00144 #define NVIC_ISER         ((volatile U32 *)0xE000E100)
00145 #define NVIC_ICER         ((volatile U32 *)0xE000E180)
00146 #define NVIC_IP           ((volatile U8  *)0xE000E400)
00147 #define NVIC_INT_CTRL   (*((volatile U32 *)0xE000ED04))
00148 #define NVIC_AIR_CTRL   (*((volatile U32 *)0xE000ED0C))
00149 #define NVIC_SYS_PRI2   (*((volatile U32 *)0xE000ED1C))
00150 #define NVIC_SYS_PRI3   (*((volatile U32 *)0xE000ED20))
00151 
00152 #define OS_PEND_IRQ()   NVIC_INT_CTRL  = (1<<28)
00153 #define OS_PENDING      ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
00154 #define OS_UNPEND(fl)   NVIC_INT_CTRL  = (*fl = OS_PENDING) << 25
00155 #define OS_PEND(fl,p)   NVIC_INT_CTRL  = (fl | p<<2) << 26
00156 #define OS_LOCK()       NVIC_ST_CTRL   =  0x0005
00157 #define OS_UNLOCK()     NVIC_ST_CTRL   =  0x0007
00158 
00159 #define OS_X_PENDING    ((NVIC_INT_CTRL >> 28) & 1)
00160 #define OS_X_UNPEND(fl) NVIC_INT_CTRL  = (*fl = OS_X_PENDING) << 27
00161 #define OS_X_PEND(fl,p) NVIC_INT_CTRL  = (fl | p) << 28
00162 #define OS_X_INIT(n)    NVIC_IP[n] = 0xFF; \
00163                         NVIC_ISER[n>>5] = 1 << (n & 0x1F)
00164 #define OS_X_LOCK(n)    NVIC_ICER[n>>5] = 1 << (n & 0x1F)
00165 #define OS_X_UNLOCK(n)  NVIC_ISER[n>>5] = 1 << (n & 0x1F)
00166 
00167 /* Core Debug registers */
00168 #define DEMCR           (*((volatile U32 *)0xE000EDFC))
00169 
00170 /* ITM registers */
00171 #define ITM_CONTROL     (*((volatile U32 *)0xE0000E80))
00172 #define ITM_ENABLE      (*((volatile U32 *)0xE0000E00))
00173 #define ITM_PORT30_U32  (*((volatile U32 *)0xE0000078))
00174 #define ITM_PORT31_U32  (*((volatile U32 *)0xE000007C))
00175 #define ITM_PORT31_U16  (*((volatile U16 *)0xE000007C))
00176 #define ITM_PORT31_U8   (*((volatile U8  *)0xE000007C))
00177 
00178 /* Variables */
00179 extern BIT dbg_msg;
00180 
00181 /* Functions */
00182 #ifdef __USE_EXCLUSIVE_ACCESS
00183  #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
00184  #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
00185 #else
00186  #define rt_inc(p)     __disable_irq();(*p)++;__enable_irq();
00187  #define rt_dec(p)     __disable_irq();(*p)--;__enable_irq();
00188 #endif
00189 
00190 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
00191   U32 cnt,c2;
00192 #ifdef __USE_EXCLUSIVE_ACCESS
00193   do {
00194     if ((cnt = __ldrex(count)) == size) {
00195       __clrex();
00196       return (cnt); }
00197   } while (__strex(cnt+1, count));
00198   do {
00199     c2 = (cnt = __ldrex(first)) + 1;
00200     if (c2 == size) c2 = 0;
00201   } while (__strex(c2, first));
00202 #else
00203   __disable_irq();
00204   if ((cnt = *count) < size) {
00205     *count = cnt+1;
00206     c2 = (cnt = *first) + 1;
00207     if (c2 == size) c2 = 0;
00208     *first = c2; 
00209   }
00210   __enable_irq ();
00211 #endif
00212   return (cnt);
00213 }
00214 
00215 __inline static void rt_systick_init (void) {
00216   NVIC_ST_RELOAD  = os_trv;
00217   NVIC_ST_CURRENT = 0;
00218   NVIC_ST_CTRL    = 0x0007;
00219   NVIC_SYS_PRI3  |= 0xFF000000;
00220 }
00221 
00222 __inline static void rt_svc_init (void) {
00223 #if !(__TARGET_ARCH_6S_M)
00224   int sh,prigroup;
00225 #endif
00226   NVIC_SYS_PRI3 |= 0x00FF0000;
00227 #if (__TARGET_ARCH_6S_M)
00228   NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
00229 #else
00230   sh       = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
00231   prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
00232   if (prigroup >= sh) {
00233     sh = prigroup + 1;
00234   }
00235   NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
00236 #endif
00237 }
00238 
00239 extern void rt_set_PSP (U32 stack);
00240 extern U32  rt_get_PSP (void);
00241 extern void os_set_env (void);
00242 extern void *_alloc_box (void *box_mem);
00243 extern int  _free_box (void *box_mem, void *box);
00244 
00245 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
00246 extern void rt_ret_val  (P_TCB p_TCB, U32 v0);
00247 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
00248 
00249 extern void dbg_init (void);
00250 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
00251 extern void dbg_task_switch (U32 task_id);
00252 
00253 #ifdef DBG_MSG
00254 #define DBG_INIT() dbg_init()
00255 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
00256 #define DBG_TASK_SWITCH(task_id)      if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
00257                                                    dbg_task_switch(task_id)
00258 #else
00259 #define DBG_INIT()
00260 #define DBG_TASK_NOTIFY(p_tcb,create)
00261 #define DBG_TASK_SWITCH(task_id)
00262 #endif
00263 
00264 /*----------------------------------------------------------------------------
00265  * end of file
00266  *---------------------------------------------------------------------------*/
00267