Michael Kersh / Mbed 2 deprecated ECE4180EthernetTest

Ethernet test for ECE 4180 and others to find your IP address and do a simple HTTP GET request over port 80.

Dependencies:   mbed Socket lwip-eth lwip-sys lwip

mbed-rtos/rtx/rt_HAL_CM.h@0:e7ca326e76ee, 2013-04-04 (annotated)

Committer:
mkersh3
Date:
Thu Apr 04 05:26:09 2013 +0000
Revision:
0:e7ca326e76ee
Ethernet Test for ECE4180 and others to find their IP Address and do a simple HTTP GET request over port 80.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mkersh3 0:e7ca326e76ee 1 /*----------------------------------------------------------------------------
mkersh3 0:e7ca326e76ee 2 * RL-ARM - RTX
mkersh3 0:e7ca326e76ee 3 *----------------------------------------------------------------------------
mkersh3 0:e7ca326e76ee 4 * Name: RT_HAL_CM.H
mkersh3 0:e7ca326e76ee 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
mkersh3 0:e7ca326e76ee 6 * Rev.: V4.50
mkersh3 0:e7ca326e76ee 7 *----------------------------------------------------------------------------
mkersh3 0:e7ca326e76ee 8 *
mkersh3 0:e7ca326e76ee 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
mkersh3 0:e7ca326e76ee 10 * All rights reserved.
mkersh3 0:e7ca326e76ee 11 * Redistribution and use in source and binary forms, with or without
mkersh3 0:e7ca326e76ee 12 * modification, are permitted provided that the following conditions are met:
mkersh3 0:e7ca326e76ee 13 * - Redistributions of source code must retain the above copyright
mkersh3 0:e7ca326e76ee 14 * notice, this list of conditions and the following disclaimer.
mkersh3 0:e7ca326e76ee 15 * - Redistributions in binary form must reproduce the above copyright
mkersh3 0:e7ca326e76ee 16 * notice, this list of conditions and the following disclaimer in the
mkersh3 0:e7ca326e76ee 17 * documentation and/or other materials provided with the distribution.
mkersh3 0:e7ca326e76ee 18 * - Neither the name of ARM nor the names of its contributors may be used
mkersh3 0:e7ca326e76ee 19 * to endorse or promote products derived from this software without
mkersh3 0:e7ca326e76ee 20 * specific prior written permission.
mkersh3 0:e7ca326e76ee 21 *
mkersh3 0:e7ca326e76ee 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mkersh3 0:e7ca326e76ee 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mkersh3 0:e7ca326e76ee 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mkersh3 0:e7ca326e76ee 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mkersh3 0:e7ca326e76ee 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mkersh3 0:e7ca326e76ee 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mkersh3 0:e7ca326e76ee 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mkersh3 0:e7ca326e76ee 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mkersh3 0:e7ca326e76ee 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mkersh3 0:e7ca326e76ee 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mkersh3 0:e7ca326e76ee 32 * POSSIBILITY OF SUCH DAMAGE.
mkersh3 0:e7ca326e76ee 33 *---------------------------------------------------------------------------*/
mkersh3 0:e7ca326e76ee 34
mkersh3 0:e7ca326e76ee 35 /* Definitions */
mkersh3 0:e7ca326e76ee 36 #define INITIAL_xPSR 0x01000000
mkersh3 0:e7ca326e76ee 37 #define DEMCR_TRCENA 0x01000000
mkersh3 0:e7ca326e76ee 38 #define ITM_ITMENA 0x00000001
mkersh3 0:e7ca326e76ee 39 #define MAGIC_WORD 0xE25A2EA5
mkersh3 0:e7ca326e76ee 40
mkersh3 0:e7ca326e76ee 41 #if defined (__CC_ARM) /* ARM Compiler */
mkersh3 0:e7ca326e76ee 42
mkersh3 0:e7ca326e76ee 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
mkersh3 0:e7ca326e76ee 44 #define __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 45 #else
mkersh3 0:e7ca326e76ee 46 #undef __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 47 #endif
mkersh3 0:e7ca326e76ee 48
mkersh3 0:e7ca326e76ee 49 #elif defined (__GNUC__) /* GNU Compiler */
mkersh3 0:e7ca326e76ee 50
mkersh3 0:e7ca326e76ee 51 #undef __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 52
mkersh3 0:e7ca326e76ee 53 #if defined (__CORTEX_M0)
mkersh3 0:e7ca326e76ee 54 #define __TARGET_ARCH_6S_M 1
mkersh3 0:e7ca326e76ee 55 #else
mkersh3 0:e7ca326e76ee 56 #define __TARGET_ARCH_6S_M 0
mkersh3 0:e7ca326e76ee 57 #endif
mkersh3 0:e7ca326e76ee 58
mkersh3 0:e7ca326e76ee 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mkersh3 0:e7ca326e76ee 60 #define __TARGET_FPU_VFP 1
mkersh3 0:e7ca326e76ee 61 #else
mkersh3 0:e7ca326e76ee 62 #define __TARGET_FPU_VFP 0
mkersh3 0:e7ca326e76ee 63 #endif
mkersh3 0:e7ca326e76ee 64
mkersh3 0:e7ca326e76ee 65 #define __inline inline
mkersh3 0:e7ca326e76ee 66 #define __weak __attribute__((weak))
mkersh3 0:e7ca326e76ee 67
mkersh3 0:e7ca326e76ee 68 #ifndef __CMSIS_GENERIC
mkersh3 0:e7ca326e76ee 69
mkersh3 0:e7ca326e76ee 70 __attribute__((always_inline)) static inline void __enable_irq(void)
mkersh3 0:e7ca326e76ee 71 {
mkersh3 0:e7ca326e76ee 72 __asm volatile ("cpsie i");
mkersh3 0:e7ca326e76ee 73 }
mkersh3 0:e7ca326e76ee 74
mkersh3 0:e7ca326e76ee 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
mkersh3 0:e7ca326e76ee 76 {
mkersh3 0:e7ca326e76ee 77 U32 result;
mkersh3 0:e7ca326e76ee 78
mkersh3 0:e7ca326e76ee 79 __asm volatile ("mrs %0, primask" : "=r" (result));
mkersh3 0:e7ca326e76ee 80 __asm volatile ("cpsid i");
mkersh3 0:e7ca326e76ee 81 return(result & 1);
mkersh3 0:e7ca326e76ee 82 }
mkersh3 0:e7ca326e76ee 83
mkersh3 0:e7ca326e76ee 84 #endif
mkersh3 0:e7ca326e76ee 85
mkersh3 0:e7ca326e76ee 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
mkersh3 0:e7ca326e76ee 87 {
mkersh3 0:e7ca326e76ee 88 U8 result;
mkersh3 0:e7ca326e76ee 89
mkersh3 0:e7ca326e76ee 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
mkersh3 0:e7ca326e76ee 91 return(result);
mkersh3 0:e7ca326e76ee 92 }
mkersh3 0:e7ca326e76ee 93
mkersh3 0:e7ca326e76ee 94 #elif defined (__ICCARM__) /* IAR Compiler */
mkersh3 0:e7ca326e76ee 95
mkersh3 0:e7ca326e76ee 96 #undef __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 97
mkersh3 0:e7ca326e76ee 98 #if (__CORE__ == __ARM6M__)
mkersh3 0:e7ca326e76ee 99 #define __TARGET_ARCH_6S_M 1
mkersh3 0:e7ca326e76ee 100 #else
mkersh3 0:e7ca326e76ee 101 #define __TARGET_ARCH_6S_M 0
mkersh3 0:e7ca326e76ee 102 #endif
mkersh3 0:e7ca326e76ee 103
mkersh3 0:e7ca326e76ee 104 #if defined __ARMVFP__
mkersh3 0:e7ca326e76ee 105 #define __TARGET_FPU_VFP 1
mkersh3 0:e7ca326e76ee 106 #else
mkersh3 0:e7ca326e76ee 107 #define __TARGET_FPU_VFP 0
mkersh3 0:e7ca326e76ee 108 #endif
mkersh3 0:e7ca326e76ee 109
mkersh3 0:e7ca326e76ee 110 #define __inline inline
mkersh3 0:e7ca326e76ee 111
mkersh3 0:e7ca326e76ee 112 #ifndef __CMSIS_GENERIC
mkersh3 0:e7ca326e76ee 113
mkersh3 0:e7ca326e76ee 114 static inline void __enable_irq(void)
mkersh3 0:e7ca326e76ee 115 {
mkersh3 0:e7ca326e76ee 116 __asm volatile ("cpsie i");
mkersh3 0:e7ca326e76ee 117 }
mkersh3 0:e7ca326e76ee 118
mkersh3 0:e7ca326e76ee 119 static inline U32 __disable_irq(void)
mkersh3 0:e7ca326e76ee 120 {
mkersh3 0:e7ca326e76ee 121 U32 result;
mkersh3 0:e7ca326e76ee 122
mkersh3 0:e7ca326e76ee 123 __asm volatile ("mrs %0, primask" : "=r" (result));
mkersh3 0:e7ca326e76ee 124 __asm volatile ("cpsid i");
mkersh3 0:e7ca326e76ee 125 return(result & 1);
mkersh3 0:e7ca326e76ee 126 }
mkersh3 0:e7ca326e76ee 127
mkersh3 0:e7ca326e76ee 128 #endif
mkersh3 0:e7ca326e76ee 129
mkersh3 0:e7ca326e76ee 130 static inline U8 __clz(U32 value)
mkersh3 0:e7ca326e76ee 131 {
mkersh3 0:e7ca326e76ee 132 U8 result;
mkersh3 0:e7ca326e76ee 133
mkersh3 0:e7ca326e76ee 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
mkersh3 0:e7ca326e76ee 135 return(result);
mkersh3 0:e7ca326e76ee 136 }
mkersh3 0:e7ca326e76ee 137
mkersh3 0:e7ca326e76ee 138 #endif
mkersh3 0:e7ca326e76ee 139
mkersh3 0:e7ca326e76ee 140 /* NVIC registers */
mkersh3 0:e7ca326e76ee 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
mkersh3 0:e7ca326e76ee 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
mkersh3 0:e7ca326e76ee 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
mkersh3 0:e7ca326e76ee 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
mkersh3 0:e7ca326e76ee 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
mkersh3 0:e7ca326e76ee 146 #define NVIC_IP ((volatile U8 *)0xE000E400)
mkersh3 0:e7ca326e76ee 147 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
mkersh3 0:e7ca326e76ee 148 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
mkersh3 0:e7ca326e76ee 149 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
mkersh3 0:e7ca326e76ee 150 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
mkersh3 0:e7ca326e76ee 151
mkersh3 0:e7ca326e76ee 152 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
mkersh3 0:e7ca326e76ee 153 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
mkersh3 0:e7ca326e76ee 154 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
mkersh3 0:e7ca326e76ee 155 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
mkersh3 0:e7ca326e76ee 156 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
mkersh3 0:e7ca326e76ee 157 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
mkersh3 0:e7ca326e76ee 158
mkersh3 0:e7ca326e76ee 159 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
mkersh3 0:e7ca326e76ee 160 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
mkersh3 0:e7ca326e76ee 161 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
mkersh3 0:e7ca326e76ee 162 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
mkersh3 0:e7ca326e76ee 163 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
mkersh3 0:e7ca326e76ee 164 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
mkersh3 0:e7ca326e76ee 165 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
mkersh3 0:e7ca326e76ee 166
mkersh3 0:e7ca326e76ee 167 /* Core Debug registers */
mkersh3 0:e7ca326e76ee 168 #define DEMCR (*((volatile U32 *)0xE000EDFC))
mkersh3 0:e7ca326e76ee 169
mkersh3 0:e7ca326e76ee 170 /* ITM registers */
mkersh3 0:e7ca326e76ee 171 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
mkersh3 0:e7ca326e76ee 172 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
mkersh3 0:e7ca326e76ee 173 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
mkersh3 0:e7ca326e76ee 174 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
mkersh3 0:e7ca326e76ee 175 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
mkersh3 0:e7ca326e76ee 176 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
mkersh3 0:e7ca326e76ee 177
mkersh3 0:e7ca326e76ee 178 /* Variables */
mkersh3 0:e7ca326e76ee 179 extern BIT dbg_msg;
mkersh3 0:e7ca326e76ee 180
mkersh3 0:e7ca326e76ee 181 /* Functions */
mkersh3 0:e7ca326e76ee 182 #ifdef __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 183 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
mkersh3 0:e7ca326e76ee 184 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
mkersh3 0:e7ca326e76ee 185 #else
mkersh3 0:e7ca326e76ee 186 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
mkersh3 0:e7ca326e76ee 187 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
mkersh3 0:e7ca326e76ee 188 #endif
mkersh3 0:e7ca326e76ee 189
mkersh3 0:e7ca326e76ee 190 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
mkersh3 0:e7ca326e76ee 191 U32 cnt,c2;
mkersh3 0:e7ca326e76ee 192 #ifdef __USE_EXCLUSIVE_ACCESS
mkersh3 0:e7ca326e76ee 193 do {
mkersh3 0:e7ca326e76ee 194 if ((cnt = __ldrex(count)) == size) {
mkersh3 0:e7ca326e76ee 195 __clrex();
mkersh3 0:e7ca326e76ee 196 return (cnt); }
mkersh3 0:e7ca326e76ee 197 } while (__strex(cnt+1, count));
mkersh3 0:e7ca326e76ee 198 do {
mkersh3 0:e7ca326e76ee 199 c2 = (cnt = __ldrex(first)) + 1;
mkersh3 0:e7ca326e76ee 200 if (c2 == size) c2 = 0;
mkersh3 0:e7ca326e76ee 201 } while (__strex(c2, first));
mkersh3 0:e7ca326e76ee 202 #else
mkersh3 0:e7ca326e76ee 203 __disable_irq();
mkersh3 0:e7ca326e76ee 204 if ((cnt = *count) < size) {
mkersh3 0:e7ca326e76ee 205 *count = cnt+1;
mkersh3 0:e7ca326e76ee 206 c2 = (cnt = *first) + 1;
mkersh3 0:e7ca326e76ee 207 if (c2 == size) c2 = 0;
mkersh3 0:e7ca326e76ee 208 *first = c2;
mkersh3 0:e7ca326e76ee 209 }
mkersh3 0:e7ca326e76ee 210 __enable_irq ();
mkersh3 0:e7ca326e76ee 211 #endif
mkersh3 0:e7ca326e76ee 212 return (cnt);
mkersh3 0:e7ca326e76ee 213 }
mkersh3 0:e7ca326e76ee 214
mkersh3 0:e7ca326e76ee 215 __inline static void rt_systick_init (void) {
mkersh3 0:e7ca326e76ee 216 NVIC_ST_RELOAD = os_trv;
mkersh3 0:e7ca326e76ee 217 NVIC_ST_CURRENT = 0;
mkersh3 0:e7ca326e76ee 218 NVIC_ST_CTRL = 0x0007;
mkersh3 0:e7ca326e76ee 219 NVIC_SYS_PRI3 |= 0xFF000000;
mkersh3 0:e7ca326e76ee 220 }
mkersh3 0:e7ca326e76ee 221
mkersh3 0:e7ca326e76ee 222 __inline static void rt_svc_init (void) {
mkersh3 0:e7ca326e76ee 223 #if !(__TARGET_ARCH_6S_M)
mkersh3 0:e7ca326e76ee 224 int sh,prigroup;
mkersh3 0:e7ca326e76ee 225 #endif
mkersh3 0:e7ca326e76ee 226 NVIC_SYS_PRI3 |= 0x00FF0000;
mkersh3 0:e7ca326e76ee 227 #if (__TARGET_ARCH_6S_M)
mkersh3 0:e7ca326e76ee 228 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
mkersh3 0:e7ca326e76ee 229 #else
mkersh3 0:e7ca326e76ee 230 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
mkersh3 0:e7ca326e76ee 231 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
mkersh3 0:e7ca326e76ee 232 if (prigroup >= sh) {
mkersh3 0:e7ca326e76ee 233 sh = prigroup + 1;
mkersh3 0:e7ca326e76ee 234 }
mkersh3 0:e7ca326e76ee 235 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
mkersh3 0:e7ca326e76ee 236 #endif
mkersh3 0:e7ca326e76ee 237 }
mkersh3 0:e7ca326e76ee 238
mkersh3 0:e7ca326e76ee 239 extern void rt_set_PSP (U32 stack);
mkersh3 0:e7ca326e76ee 240 extern U32 rt_get_PSP (void);
mkersh3 0:e7ca326e76ee 241 extern void os_set_env (void);
mkersh3 0:e7ca326e76ee 242 extern void *_alloc_box (void *box_mem);
mkersh3 0:e7ca326e76ee 243 extern int _free_box (void *box_mem, void *box);
mkersh3 0:e7ca326e76ee 244
mkersh3 0:e7ca326e76ee 245 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
mkersh3 0:e7ca326e76ee 246 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
mkersh3 0:e7ca326e76ee 247 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
mkersh3 0:e7ca326e76ee 248
mkersh3 0:e7ca326e76ee 249 extern void dbg_init (void);
mkersh3 0:e7ca326e76ee 250 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
mkersh3 0:e7ca326e76ee 251 extern void dbg_task_switch (U32 task_id);
mkersh3 0:e7ca326e76ee 252
mkersh3 0:e7ca326e76ee 253 #ifdef DBG_MSG
mkersh3 0:e7ca326e76ee 254 #define DBG_INIT() dbg_init()
mkersh3 0:e7ca326e76ee 255 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
mkersh3 0:e7ca326e76ee 256 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
mkersh3 0:e7ca326e76ee 257 dbg_task_switch(task_id)
mkersh3 0:e7ca326e76ee 258 #else
mkersh3 0:e7ca326e76ee 259 #define DBG_INIT()
mkersh3 0:e7ca326e76ee 260 #define DBG_TASK_NOTIFY(p_tcb,create)
mkersh3 0:e7ca326e76ee 261 #define DBG_TASK_SWITCH(task_id)
mkersh3 0:e7ca326e76ee 262 #endif
mkersh3 0:e7ca326e76ee 263
mkersh3 0:e7ca326e76ee 264 /*----------------------------------------------------------------------------
mkersh3 0:e7ca326e76ee 265 * end of file
mkersh3 0:e7ca326e76ee 266 *---------------------------------------------------------------------------*/
mkersh3 0:e7ca326e76ee 267