Michael Kersh / Mbed 2 deprecated ECE4180EthernetTest

Ethernet test for ECE 4180 and others to find your IP address and do a simple HTTP GET request over port 80.

Dependencies:   mbed Socket lwip-eth lwip-sys lwip

EthernetInterface/lwip-eth/arch/lpc17xx_emac.h@0:e7ca326e76ee, 2013-04-04 (annotated)

Committer:
mkersh3
Date:
Thu Apr 04 05:26:09 2013 +0000
Revision:
0:e7ca326e76ee
Ethernet Test for ECE4180 and others to find their IP Address and do a simple HTTP GET request over port 80.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mkersh3 0:e7ca326e76ee 1 /**********************************************************************
mkersh3 0:e7ca326e76ee 2 * $Id$ lpc17xx_emac.h 2010-05-21
mkersh3 0:e7ca326e76ee 3 *//**
mkersh3 0:e7ca326e76ee 4 * @file lpc17xx_emac.h
mkersh3 0:e7ca326e76ee 5 * @brief Contains all macro definitions and function prototypes
mkersh3 0:e7ca326e76ee 6 * support for Ethernet MAC firmware library on LPC17xx
mkersh3 0:e7ca326e76ee 7 * @version 2.0
mkersh3 0:e7ca326e76ee 8 * @date 21. May. 2010
mkersh3 0:e7ca326e76ee 9 * @author NXP MCU SW Application Team
mkersh3 0:e7ca326e76ee 10 *
mkersh3 0:e7ca326e76ee 11 * Copyright(C) 2010, NXP Semiconductor
mkersh3 0:e7ca326e76ee 12 * All rights reserved.
mkersh3 0:e7ca326e76ee 13 *
mkersh3 0:e7ca326e76ee 14 ***********************************************************************
mkersh3 0:e7ca326e76ee 15 * Software that is described herein is for illustrative purposes only
mkersh3 0:e7ca326e76ee 16 * which provides customers with programming information regarding the
mkersh3 0:e7ca326e76ee 17 * products. This software is supplied "AS IS" without any warranties.
mkersh3 0:e7ca326e76ee 18 * NXP Semiconductors assumes no responsibility or liability for the
mkersh3 0:e7ca326e76ee 19 * use of the software, conveys no license or title under any patent,
mkersh3 0:e7ca326e76ee 20 * copyright, or mask work right to the product. NXP Semiconductors
mkersh3 0:e7ca326e76ee 21 * reserves the right to make changes in the software without
mkersh3 0:e7ca326e76ee 22 * notification. NXP Semiconductors also make no representation or
mkersh3 0:e7ca326e76ee 23 * warranty that such application will be suitable for the specified
mkersh3 0:e7ca326e76ee 24 * use without further testing or modification.
mkersh3 0:e7ca326e76ee 25 **********************************************************************/
mkersh3 0:e7ca326e76ee 26
mkersh3 0:e7ca326e76ee 27 /* Peripheral group ----------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
mkersh3 0:e7ca326e76ee 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
mkersh3 0:e7ca326e76ee 30 * @{
mkersh3 0:e7ca326e76ee 31 */
mkersh3 0:e7ca326e76ee 32
mkersh3 0:e7ca326e76ee 33 #ifndef LPC17XX_EMAC_H_
mkersh3 0:e7ca326e76ee 34 #define LPC17XX_EMAC_H_
mkersh3 0:e7ca326e76ee 35
mkersh3 0:e7ca326e76ee 36 /* Includes ------------------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 37 #include "LPC17xx.h"
mkersh3 0:e7ca326e76ee 38
mkersh3 0:e7ca326e76ee 39 #ifdef __cplusplus
mkersh3 0:e7ca326e76ee 40 extern "C"
mkersh3 0:e7ca326e76ee 41 {
mkersh3 0:e7ca326e76ee 42 #endif
mkersh3 0:e7ca326e76ee 43
mkersh3 0:e7ca326e76ee 44 #define MCB_LPC_1768
mkersh3 0:e7ca326e76ee 45 //#define IAR_LPC_1768
mkersh3 0:e7ca326e76ee 46
mkersh3 0:e7ca326e76ee 47 /* Public Macros -------------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
mkersh3 0:e7ca326e76ee 49 * @{
mkersh3 0:e7ca326e76ee 50 */
mkersh3 0:e7ca326e76ee 51
mkersh3 0:e7ca326e76ee 52
mkersh3 0:e7ca326e76ee 53 /* EMAC PHY status type definitions */
mkersh3 0:e7ca326e76ee 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
mkersh3 0:e7ca326e76ee 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
mkersh3 0:e7ca326e76ee 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
mkersh3 0:e7ca326e76ee 57
mkersh3 0:e7ca326e76ee 58 /* EMAC PHY device Speed definitions */
mkersh3 0:e7ca326e76ee 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
mkersh3 0:e7ca326e76ee 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
mkersh3 0:e7ca326e76ee 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
mkersh3 0:e7ca326e76ee 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
mkersh3 0:e7ca326e76ee 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
mkersh3 0:e7ca326e76ee 64
mkersh3 0:e7ca326e76ee 65 /**
mkersh3 0:e7ca326e76ee 66 * @}
mkersh3 0:e7ca326e76ee 67 */
mkersh3 0:e7ca326e76ee 68 /* Private Macros ------------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
mkersh3 0:e7ca326e76ee 70 * @{
mkersh3 0:e7ca326e76ee 71 */
mkersh3 0:e7ca326e76ee 72
mkersh3 0:e7ca326e76ee 73
mkersh3 0:e7ca326e76ee 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
mkersh3 0:e7ca326e76ee 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
mkersh3 0:e7ca326e76ee 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
mkersh3 0:e7ca326e76ee 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
mkersh3 0:e7ca326e76ee 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
mkersh3 0:e7ca326e76ee 79
mkersh3 0:e7ca326e76ee 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
mkersh3 0:e7ca326e76ee 81 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 82 * Macro defines for MAC Configuration Register 1
mkersh3 0:e7ca326e76ee 83 **********************************************************************/
mkersh3 0:e7ca326e76ee 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
mkersh3 0:e7ca326e76ee 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
mkersh3 0:e7ca326e76ee 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
mkersh3 0:e7ca326e76ee 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
mkersh3 0:e7ca326e76ee 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
mkersh3 0:e7ca326e76ee 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
mkersh3 0:e7ca326e76ee 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
mkersh3 0:e7ca326e76ee 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
mkersh3 0:e7ca326e76ee 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
mkersh3 0:e7ca326e76ee 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
mkersh3 0:e7ca326e76ee 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
mkersh3 0:e7ca326e76ee 95
mkersh3 0:e7ca326e76ee 96 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 97 * Macro defines for MAC Configuration Register 2
mkersh3 0:e7ca326e76ee 98 **********************************************************************/
mkersh3 0:e7ca326e76ee 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
mkersh3 0:e7ca326e76ee 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
mkersh3 0:e7ca326e76ee 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
mkersh3 0:e7ca326e76ee 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
mkersh3 0:e7ca326e76ee 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
mkersh3 0:e7ca326e76ee 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
mkersh3 0:e7ca326e76ee 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
mkersh3 0:e7ca326e76ee 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
mkersh3 0:e7ca326e76ee 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
mkersh3 0:e7ca326e76ee 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
mkersh3 0:e7ca326e76ee 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
mkersh3 0:e7ca326e76ee 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
mkersh3 0:e7ca326e76ee 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
mkersh3 0:e7ca326e76ee 112
mkersh3 0:e7ca326e76ee 113 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
mkersh3 0:e7ca326e76ee 115 **********************************************************************/
mkersh3 0:e7ca326e76ee 116 /** Programmable field representing the nibble time offset of the minimum possible period
mkersh3 0:e7ca326e76ee 117 * between the end of any transmitted packet to the beginning of the next */
mkersh3 0:e7ca326e76ee 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
mkersh3 0:e7ca326e76ee 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
mkersh3 0:e7ca326e76ee 120 * offset of the minimum possible period between the end of any transmitted packet to the
mkersh3 0:e7ca326e76ee 121 * beginning of the next */
mkersh3 0:e7ca326e76ee 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
mkersh3 0:e7ca326e76ee 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
mkersh3 0:e7ca326e76ee 124 * offset of the minimum possible period between the end of any transmitted packet to the
mkersh3 0:e7ca326e76ee 125 * beginning of the next */
mkersh3 0:e7ca326e76ee 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
mkersh3 0:e7ca326e76ee 127
mkersh3 0:e7ca326e76ee 128 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
mkersh3 0:e7ca326e76ee 130 **********************************************************************/
mkersh3 0:e7ca326e76ee 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
mkersh3 0:e7ca326e76ee 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
mkersh3 0:e7ca326e76ee 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
mkersh3 0:e7ca326e76ee 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
mkersh3 0:e7ca326e76ee 135 /** Programmable field representing the optional carrierSense window referenced in
mkersh3 0:e7ca326e76ee 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
mkersh3 0:e7ca326e76ee 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
mkersh3 0:e7ca326e76ee 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
mkersh3 0:e7ca326e76ee 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
mkersh3 0:e7ca326e76ee 140
mkersh3 0:e7ca326e76ee 141 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 142 * Macro defines for Collision Window/Retry Register
mkersh3 0:e7ca326e76ee 143 **********************************************************************/
mkersh3 0:e7ca326e76ee 144 /** Programmable field specifying the number of retransmission attempts following a collision before
mkersh3 0:e7ca326e76ee 145 * aborting the packet due to excessive collisions */
mkersh3 0:e7ca326e76ee 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
mkersh3 0:e7ca326e76ee 147 /** Programmable field representing the slot time or collision window during which collisions occur
mkersh3 0:e7ca326e76ee 148 * in properly configured networks */
mkersh3 0:e7ca326e76ee 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
mkersh3 0:e7ca326e76ee 150 /** Default value for Collision Window / Retry register */
mkersh3 0:e7ca326e76ee 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
mkersh3 0:e7ca326e76ee 152
mkersh3 0:e7ca326e76ee 153 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 154 * Macro defines for Maximum Frame Register
mkersh3 0:e7ca326e76ee 155 **********************************************************************/
mkersh3 0:e7ca326e76ee 156 /** Represents a maximum receive frame of 1536 octets */
mkersh3 0:e7ca326e76ee 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
mkersh3 0:e7ca326e76ee 158
mkersh3 0:e7ca326e76ee 159 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 160 * Macro defines for PHY Support Register
mkersh3 0:e7ca326e76ee 161 **********************************************************************/
mkersh3 0:e7ca326e76ee 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
mkersh3 0:e7ca326e76ee 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
mkersh3 0:e7ca326e76ee 164
mkersh3 0:e7ca326e76ee 165 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 166 * Macro defines for Test Register
mkersh3 0:e7ca326e76ee 167 **********************************************************************/
mkersh3 0:e7ca326e76ee 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
mkersh3 0:e7ca326e76ee 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
mkersh3 0:e7ca326e76ee 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
mkersh3 0:e7ca326e76ee 171
mkersh3 0:e7ca326e76ee 172 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 173 * Macro defines for MII Management Configuration Register
mkersh3 0:e7ca326e76ee 174 **********************************************************************/
mkersh3 0:e7ca326e76ee 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
mkersh3 0:e7ca326e76ee 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
mkersh3 0:e7ca326e76ee 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
mkersh3 0:e7ca326e76ee 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
mkersh3 0:e7ca326e76ee 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
mkersh3 0:e7ca326e76ee 180
mkersh3 0:e7ca326e76ee 181 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 182 * Macro defines for MII Management Command Register
mkersh3 0:e7ca326e76ee 183 **********************************************************************/
mkersh3 0:e7ca326e76ee 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
mkersh3 0:e7ca326e76ee 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
mkersh3 0:e7ca326e76ee 186
mkersh3 0:e7ca326e76ee 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
mkersh3 0:e7ca326e76ee 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
mkersh3 0:e7ca326e76ee 189
mkersh3 0:e7ca326e76ee 190 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 191 * Macro defines for MII Management Address Register
mkersh3 0:e7ca326e76ee 192 **********************************************************************/
mkersh3 0:e7ca326e76ee 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
mkersh3 0:e7ca326e76ee 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
mkersh3 0:e7ca326e76ee 195
mkersh3 0:e7ca326e76ee 196 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 197 * Macro defines for MII Management Write Data Register
mkersh3 0:e7ca326e76ee 198 **********************************************************************/
mkersh3 0:e7ca326e76ee 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
mkersh3 0:e7ca326e76ee 200
mkersh3 0:e7ca326e76ee 201 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 202 * Macro defines for MII Management Read Data Register
mkersh3 0:e7ca326e76ee 203 **********************************************************************/
mkersh3 0:e7ca326e76ee 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
mkersh3 0:e7ca326e76ee 205
mkersh3 0:e7ca326e76ee 206 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 207 * Macro defines for MII Management Indicators Register
mkersh3 0:e7ca326e76ee 208 **********************************************************************/
mkersh3 0:e7ca326e76ee 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
mkersh3 0:e7ca326e76ee 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
mkersh3 0:e7ca326e76ee 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
mkersh3 0:e7ca326e76ee 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
mkersh3 0:e7ca326e76ee 213
mkersh3 0:e7ca326e76ee 214 /* Station Address 0 Register */
mkersh3 0:e7ca326e76ee 215 /* Station Address 1 Register */
mkersh3 0:e7ca326e76ee 216 /* Station Address 2 Register */
mkersh3 0:e7ca326e76ee 217
mkersh3 0:e7ca326e76ee 218
mkersh3 0:e7ca326e76ee 219 /* Control register definitions --------------------------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 220 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 221 * Macro defines for Command Register
mkersh3 0:e7ca326e76ee 222 **********************************************************************/
mkersh3 0:e7ca326e76ee 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
mkersh3 0:e7ca326e76ee 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
mkersh3 0:e7ca326e76ee 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
mkersh3 0:e7ca326e76ee 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
mkersh3 0:e7ca326e76ee 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
mkersh3 0:e7ca326e76ee 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
mkersh3 0:e7ca326e76ee 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
mkersh3 0:e7ca326e76ee 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
mkersh3 0:e7ca326e76ee 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
mkersh3 0:e7ca326e76ee 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
mkersh3 0:e7ca326e76ee 233
mkersh3 0:e7ca326e76ee 234 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 235 * Macro defines for Status Register
mkersh3 0:e7ca326e76ee 236 **********************************************************************/
mkersh3 0:e7ca326e76ee 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
mkersh3 0:e7ca326e76ee 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
mkersh3 0:e7ca326e76ee 239
mkersh3 0:e7ca326e76ee 240 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 241 * Macro defines for Transmit Status Vector 0 Register
mkersh3 0:e7ca326e76ee 242 **********************************************************************/
mkersh3 0:e7ca326e76ee 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
mkersh3 0:e7ca326e76ee 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
mkersh3 0:e7ca326e76ee 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
mkersh3 0:e7ca326e76ee 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
mkersh3 0:e7ca326e76ee 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
mkersh3 0:e7ca326e76ee 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
mkersh3 0:e7ca326e76ee 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
mkersh3 0:e7ca326e76ee 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
mkersh3 0:e7ca326e76ee 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
mkersh3 0:e7ca326e76ee 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
mkersh3 0:e7ca326e76ee 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
mkersh3 0:e7ca326e76ee 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
mkersh3 0:e7ca326e76ee 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
mkersh3 0:e7ca326e76ee 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
mkersh3 0:e7ca326e76ee 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
mkersh3 0:e7ca326e76ee 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
mkersh3 0:e7ca326e76ee 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
mkersh3 0:e7ca326e76ee 260
mkersh3 0:e7ca326e76ee 261 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 262 * Macro defines for Transmit Status Vector 1 Register
mkersh3 0:e7ca326e76ee 263 **********************************************************************/
mkersh3 0:e7ca326e76ee 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
mkersh3 0:e7ca326e76ee 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
mkersh3 0:e7ca326e76ee 266
mkersh3 0:e7ca326e76ee 267 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 268 * Macro defines for Receive Status Vector Register
mkersh3 0:e7ca326e76ee 269 **********************************************************************/
mkersh3 0:e7ca326e76ee 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
mkersh3 0:e7ca326e76ee 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
mkersh3 0:e7ca326e76ee 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
mkersh3 0:e7ca326e76ee 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
mkersh3 0:e7ca326e76ee 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
mkersh3 0:e7ca326e76ee 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
mkersh3 0:e7ca326e76ee 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
mkersh3 0:e7ca326e76ee 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
mkersh3 0:e7ca326e76ee 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
mkersh3 0:e7ca326e76ee 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
mkersh3 0:e7ca326e76ee 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
mkersh3 0:e7ca326e76ee 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
mkersh3 0:e7ca326e76ee 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
mkersh3 0:e7ca326e76ee 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
mkersh3 0:e7ca326e76ee 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
mkersh3 0:e7ca326e76ee 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
mkersh3 0:e7ca326e76ee 286
mkersh3 0:e7ca326e76ee 287 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 288 * Macro defines for Flow Control Counter Register
mkersh3 0:e7ca326e76ee 289 **********************************************************************/
mkersh3 0:e7ca326e76ee 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
mkersh3 0:e7ca326e76ee 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
mkersh3 0:e7ca326e76ee 292
mkersh3 0:e7ca326e76ee 293 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 294 * Macro defines for Flow Control Status Register
mkersh3 0:e7ca326e76ee 295 **********************************************************************/
mkersh3 0:e7ca326e76ee 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
mkersh3 0:e7ca326e76ee 297
mkersh3 0:e7ca326e76ee 298
mkersh3 0:e7ca326e76ee 299 /* Receive filter register definitions -------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 300 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 301 * Macro defines for Receive Filter Control Register
mkersh3 0:e7ca326e76ee 302 **********************************************************************/
mkersh3 0:e7ca326e76ee 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
mkersh3 0:e7ca326e76ee 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
mkersh3 0:e7ca326e76ee 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
mkersh3 0:e7ca326e76ee 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
mkersh3 0:e7ca326e76ee 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
mkersh3 0:e7ca326e76ee 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
mkersh3 0:e7ca326e76ee 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
mkersh3 0:e7ca326e76ee 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
mkersh3 0:e7ca326e76ee 311
mkersh3 0:e7ca326e76ee 312 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 313 * Macro defines for Receive Filter WoL Status/Clear Registers
mkersh3 0:e7ca326e76ee 314 **********************************************************************/
mkersh3 0:e7ca326e76ee 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
mkersh3 0:e7ca326e76ee 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
mkersh3 0:e7ca326e76ee 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
mkersh3 0:e7ca326e76ee 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
mkersh3 0:e7ca326e76ee 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
mkersh3 0:e7ca326e76ee 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
mkersh3 0:e7ca326e76ee 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
mkersh3 0:e7ca326e76ee 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
mkersh3 0:e7ca326e76ee 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
mkersh3 0:e7ca326e76ee 324
mkersh3 0:e7ca326e76ee 325
mkersh3 0:e7ca326e76ee 326 /* Module control register definitions ---------------------------------------------------- */
mkersh3 0:e7ca326e76ee 327 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
mkersh3 0:e7ca326e76ee 329 **********************************************************************/
mkersh3 0:e7ca326e76ee 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
mkersh3 0:e7ca326e76ee 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
mkersh3 0:e7ca326e76ee 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
mkersh3 0:e7ca326e76ee 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
mkersh3 0:e7ca326e76ee 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
mkersh3 0:e7ca326e76ee 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
mkersh3 0:e7ca326e76ee 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
mkersh3 0:e7ca326e76ee 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
mkersh3 0:e7ca326e76ee 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
mkersh3 0:e7ca326e76ee 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
mkersh3 0:e7ca326e76ee 340
mkersh3 0:e7ca326e76ee 341 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 342 * Macro defines for Power Down Register
mkersh3 0:e7ca326e76ee 343 **********************************************************************/
mkersh3 0:e7ca326e76ee 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
mkersh3 0:e7ca326e76ee 345
mkersh3 0:e7ca326e76ee 346 /* Descriptor and status formats ---------------------------------------------------- */
mkersh3 0:e7ca326e76ee 347 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 348 * Macro defines for RX Descriptor Control Word
mkersh3 0:e7ca326e76ee 349 **********************************************************************/
mkersh3 0:e7ca326e76ee 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
mkersh3 0:e7ca326e76ee 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
mkersh3 0:e7ca326e76ee 352
mkersh3 0:e7ca326e76ee 353 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 354 * Macro defines for RX Status Hash CRC Word
mkersh3 0:e7ca326e76ee 355 **********************************************************************/
mkersh3 0:e7ca326e76ee 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
mkersh3 0:e7ca326e76ee 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
mkersh3 0:e7ca326e76ee 358
mkersh3 0:e7ca326e76ee 359 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 360 * Macro defines for RX Status Information Word
mkersh3 0:e7ca326e76ee 361 **********************************************************************/
mkersh3 0:e7ca326e76ee 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
mkersh3 0:e7ca326e76ee 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
mkersh3 0:e7ca326e76ee 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
mkersh3 0:e7ca326e76ee 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
mkersh3 0:e7ca326e76ee 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
mkersh3 0:e7ca326e76ee 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
mkersh3 0:e7ca326e76ee 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
mkersh3 0:e7ca326e76ee 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
mkersh3 0:e7ca326e76ee 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
mkersh3 0:e7ca326e76ee 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
mkersh3 0:e7ca326e76ee 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
mkersh3 0:e7ca326e76ee 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
mkersh3 0:e7ca326e76ee 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
mkersh3 0:e7ca326e76ee 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
mkersh3 0:e7ca326e76ee 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
mkersh3 0:e7ca326e76ee 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
mkersh3 0:e7ca326e76ee 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
mkersh3 0:e7ca326e76ee 379
mkersh3 0:e7ca326e76ee 380 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 381 * Macro defines for TX Descriptor Control Word
mkersh3 0:e7ca326e76ee 382 **********************************************************************/
mkersh3 0:e7ca326e76ee 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
mkersh3 0:e7ca326e76ee 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
mkersh3 0:e7ca326e76ee 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
mkersh3 0:e7ca326e76ee 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
mkersh3 0:e7ca326e76ee 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
mkersh3 0:e7ca326e76ee 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
mkersh3 0:e7ca326e76ee 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
mkersh3 0:e7ca326e76ee 390
mkersh3 0:e7ca326e76ee 391 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 392 * Macro defines for TX Status Information Word
mkersh3 0:e7ca326e76ee 393 **********************************************************************/
mkersh3 0:e7ca326e76ee 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
mkersh3 0:e7ca326e76ee 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
mkersh3 0:e7ca326e76ee 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
mkersh3 0:e7ca326e76ee 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
mkersh3 0:e7ca326e76ee 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
mkersh3 0:e7ca326e76ee 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
mkersh3 0:e7ca326e76ee 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
mkersh3 0:e7ca326e76ee 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
mkersh3 0:e7ca326e76ee 402
mkersh3 0:e7ca326e76ee 403 #ifdef MCB_LPC_1768
mkersh3 0:e7ca326e76ee 404 /* DP83848C PHY definition ------------------------------------------------------------ */
mkersh3 0:e7ca326e76ee 405
mkersh3 0:e7ca326e76ee 406 /** PHY device reset time out definition */
mkersh3 0:e7ca326e76ee 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
mkersh3 0:e7ca326e76ee 408
mkersh3 0:e7ca326e76ee 409 /* ENET Device Revision ID */
mkersh3 0:e7ca326e76ee 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
mkersh3 0:e7ca326e76ee 411
mkersh3 0:e7ca326e76ee 412 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 413 * Macro defines for DP83848C PHY Registers
mkersh3 0:e7ca326e76ee 414 **********************************************************************/
mkersh3 0:e7ca326e76ee 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
mkersh3 0:e7ca326e76ee 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
mkersh3 0:e7ca326e76ee 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
mkersh3 0:e7ca326e76ee 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
mkersh3 0:e7ca326e76ee 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
mkersh3 0:e7ca326e76ee 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
mkersh3 0:e7ca326e76ee 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
mkersh3 0:e7ca326e76ee 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
mkersh3 0:e7ca326e76ee 423 #define EMAC_PHY_REG_LPNPA 0x08
mkersh3 0:e7ca326e76ee 424
mkersh3 0:e7ca326e76ee 425 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 426 * Macro defines for PHY Extended Registers
mkersh3 0:e7ca326e76ee 427 **********************************************************************/
mkersh3 0:e7ca326e76ee 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
mkersh3 0:e7ca326e76ee 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
mkersh3 0:e7ca326e76ee 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
mkersh3 0:e7ca326e76ee 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
mkersh3 0:e7ca326e76ee 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
mkersh3 0:e7ca326e76ee 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
mkersh3 0:e7ca326e76ee 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
mkersh3 0:e7ca326e76ee 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
mkersh3 0:e7ca326e76ee 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
mkersh3 0:e7ca326e76ee 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
mkersh3 0:e7ca326e76ee 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
mkersh3 0:e7ca326e76ee 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
mkersh3 0:e7ca326e76ee 440
mkersh3 0:e7ca326e76ee 441 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 442 * Macro defines for PHY Basic Mode Control Register
mkersh3 0:e7ca326e76ee 443 **********************************************************************/
mkersh3 0:e7ca326e76ee 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
mkersh3 0:e7ca326e76ee 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
mkersh3 0:e7ca326e76ee 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
mkersh3 0:e7ca326e76ee 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
mkersh3 0:e7ca326e76ee 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
mkersh3 0:e7ca326e76ee 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
mkersh3 0:e7ca326e76ee 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
mkersh3 0:e7ca326e76ee 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
mkersh3 0:e7ca326e76ee 452
mkersh3 0:e7ca326e76ee 453 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 454 * Macro defines for PHY Basic Mode Status Status Register
mkersh3 0:e7ca326e76ee 455 **********************************************************************/
mkersh3 0:e7ca326e76ee 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
mkersh3 0:e7ca326e76ee 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
mkersh3 0:e7ca326e76ee 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
mkersh3 0:e7ca326e76ee 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
mkersh3 0:e7ca326e76ee 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
mkersh3 0:e7ca326e76ee 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
mkersh3 0:e7ca326e76ee 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
mkersh3 0:e7ca326e76ee 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
mkersh3 0:e7ca326e76ee 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
mkersh3 0:e7ca326e76ee 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
mkersh3 0:e7ca326e76ee 466
mkersh3 0:e7ca326e76ee 467 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 468 * Macro defines for PHY Status Register
mkersh3 0:e7ca326e76ee 469 **********************************************************************/
mkersh3 0:e7ca326e76ee 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
mkersh3 0:e7ca326e76ee 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
mkersh3 0:e7ca326e76ee 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
mkersh3 0:e7ca326e76ee 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
mkersh3 0:e7ca326e76ee 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
mkersh3 0:e7ca326e76ee 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
mkersh3 0:e7ca326e76ee 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
mkersh3 0:e7ca326e76ee 477
mkersh3 0:e7ca326e76ee 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
mkersh3 0:e7ca326e76ee 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
mkersh3 0:e7ca326e76ee 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
mkersh3 0:e7ca326e76ee 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
mkersh3 0:e7ca326e76ee 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
mkersh3 0:e7ca326e76ee 483
mkersh3 0:e7ca326e76ee 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
mkersh3 0:e7ca326e76ee 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
mkersh3 0:e7ca326e76ee 486
mkersh3 0:e7ca326e76ee 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
mkersh3 0:e7ca326e76ee 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
mkersh3 0:e7ca326e76ee 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
mkersh3 0:e7ca326e76ee 490
mkersh3 0:e7ca326e76ee 491 #elif defined(IAR_LPC_1768)
mkersh3 0:e7ca326e76ee 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
mkersh3 0:e7ca326e76ee 493 /** PHY device reset time out definition */
mkersh3 0:e7ca326e76ee 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
mkersh3 0:e7ca326e76ee 495
mkersh3 0:e7ca326e76ee 496 /* ENET Device Revision ID */
mkersh3 0:e7ca326e76ee 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
mkersh3 0:e7ca326e76ee 498
mkersh3 0:e7ca326e76ee 499 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 500 * Macro defines for KSZ8721BL PHY Registers
mkersh3 0:e7ca326e76ee 501 **********************************************************************/
mkersh3 0:e7ca326e76ee 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
mkersh3 0:e7ca326e76ee 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
mkersh3 0:e7ca326e76ee 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
mkersh3 0:e7ca326e76ee 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
mkersh3 0:e7ca326e76ee 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
mkersh3 0:e7ca326e76ee 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
mkersh3 0:e7ca326e76ee 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
mkersh3 0:e7ca326e76ee 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
mkersh3 0:e7ca326e76ee 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
mkersh3 0:e7ca326e76ee 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
mkersh3 0:e7ca326e76ee 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
mkersh3 0:e7ca326e76ee 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
mkersh3 0:e7ca326e76ee 514
mkersh3 0:e7ca326e76ee 515 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 516 * Macro defines for PHY Basic Mode Control Register
mkersh3 0:e7ca326e76ee 517 **********************************************************************/
mkersh3 0:e7ca326e76ee 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
mkersh3 0:e7ca326e76ee 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
mkersh3 0:e7ca326e76ee 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
mkersh3 0:e7ca326e76ee 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
mkersh3 0:e7ca326e76ee 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
mkersh3 0:e7ca326e76ee 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
mkersh3 0:e7ca326e76ee 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
mkersh3 0:e7ca326e76ee 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
mkersh3 0:e7ca326e76ee 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
mkersh3 0:e7ca326e76ee 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
mkersh3 0:e7ca326e76ee 528
mkersh3 0:e7ca326e76ee 529 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 530 * Macro defines for PHY Basic Mode Status Register
mkersh3 0:e7ca326e76ee 531 **********************************************************************/
mkersh3 0:e7ca326e76ee 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
mkersh3 0:e7ca326e76ee 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
mkersh3 0:e7ca326e76ee 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
mkersh3 0:e7ca326e76ee 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
mkersh3 0:e7ca326e76ee 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
mkersh3 0:e7ca326e76ee 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
mkersh3 0:e7ca326e76ee 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
mkersh3 0:e7ca326e76ee 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
mkersh3 0:e7ca326e76ee 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
mkersh3 0:e7ca326e76ee 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
mkersh3 0:e7ca326e76ee 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
mkersh3 0:e7ca326e76ee 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
mkersh3 0:e7ca326e76ee 544
mkersh3 0:e7ca326e76ee 545 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 546 * Macro defines for PHY Identifier
mkersh3 0:e7ca326e76ee 547 **********************************************************************/
mkersh3 0:e7ca326e76ee 548 /* PHY Identifier 1 bitmap definitions */
mkersh3 0:e7ca326e76ee 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
mkersh3 0:e7ca326e76ee 550
mkersh3 0:e7ca326e76ee 551 /* PHY Identifier 2 bitmap definitions */
mkersh3 0:e7ca326e76ee 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
mkersh3 0:e7ca326e76ee 553
mkersh3 0:e7ca326e76ee 554 /*********************************************************************//**
mkersh3 0:e7ca326e76ee 555 * Macro defines for Auto-Negotiation Advertisement
mkersh3 0:e7ca326e76ee 556 **********************************************************************/
mkersh3 0:e7ca326e76ee 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
mkersh3 0:e7ca326e76ee 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
mkersh3 0:e7ca326e76ee 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
mkersh3 0:e7ca326e76ee 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
mkersh3 0:e7ca326e76ee 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
mkersh3 0:e7ca326e76ee 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
mkersh3 0:e7ca326e76ee 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
mkersh3 0:e7ca326e76ee 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
mkersh3 0:e7ca326e76ee 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
mkersh3 0:e7ca326e76ee 566
mkersh3 0:e7ca326e76ee 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
mkersh3 0:e7ca326e76ee 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
mkersh3 0:e7ca326e76ee 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
mkersh3 0:e7ca326e76ee 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
mkersh3 0:e7ca326e76ee 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
mkersh3 0:e7ca326e76ee 572
mkersh3 0:e7ca326e76ee 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
mkersh3 0:e7ca326e76ee 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
mkersh3 0:e7ca326e76ee 575
mkersh3 0:e7ca326e76ee 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
mkersh3 0:e7ca326e76ee 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
mkersh3 0:e7ca326e76ee 578 #endif
mkersh3 0:e7ca326e76ee 579
mkersh3 0:e7ca326e76ee 580 /**
mkersh3 0:e7ca326e76ee 581 * @}
mkersh3 0:e7ca326e76ee 582 */
mkersh3 0:e7ca326e76ee 583
mkersh3 0:e7ca326e76ee 584
mkersh3 0:e7ca326e76ee 585 /* Public Types --------------------------------------------------------------- */
mkersh3 0:e7ca326e76ee 586 /** @defgroup EMAC_Public_Types EMAC Public Types
mkersh3 0:e7ca326e76ee 587 * @{
mkersh3 0:e7ca326e76ee 588 */
mkersh3 0:e7ca326e76ee 589
mkersh3 0:e7ca326e76ee 590 /* Descriptor and status formats ---------------------------------------------- */
mkersh3 0:e7ca326e76ee 591
mkersh3 0:e7ca326e76ee 592 /**
mkersh3 0:e7ca326e76ee 593 * @brief RX Descriptor structure type definition
mkersh3 0:e7ca326e76ee 594 */
mkersh3 0:e7ca326e76ee 595 typedef struct {
mkersh3 0:e7ca326e76ee 596 uint32_t Packet; /**< Receive Packet Descriptor */
mkersh3 0:e7ca326e76ee 597 uint32_t Ctrl; /**< Receive Control Descriptor */
mkersh3 0:e7ca326e76ee 598 } RX_Desc;
mkersh3 0:e7ca326e76ee 599
mkersh3 0:e7ca326e76ee 600 /**
mkersh3 0:e7ca326e76ee 601 * @brief RX Status structure type definition
mkersh3 0:e7ca326e76ee 602 */
mkersh3 0:e7ca326e76ee 603 typedef struct {
mkersh3 0:e7ca326e76ee 604 uint32_t Info; /**< Receive Information Status */
mkersh3 0:e7ca326e76ee 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
mkersh3 0:e7ca326e76ee 606 } RX_Stat;
mkersh3 0:e7ca326e76ee 607
mkersh3 0:e7ca326e76ee 608 /**
mkersh3 0:e7ca326e76ee 609 * @brief TX Descriptor structure type definition
mkersh3 0:e7ca326e76ee 610 */
mkersh3 0:e7ca326e76ee 611 typedef struct {
mkersh3 0:e7ca326e76ee 612 uint32_t Packet; /**< Transmit Packet Descriptor */
mkersh3 0:e7ca326e76ee 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
mkersh3 0:e7ca326e76ee 614 } TX_Desc;
mkersh3 0:e7ca326e76ee 615
mkersh3 0:e7ca326e76ee 616 /**
mkersh3 0:e7ca326e76ee 617 * @brief TX Status structure type definition
mkersh3 0:e7ca326e76ee 618 */
mkersh3 0:e7ca326e76ee 619 typedef struct {
mkersh3 0:e7ca326e76ee 620 uint32_t Info; /**< Transmit Information Status */
mkersh3 0:e7ca326e76ee 621 } TX_Stat;
mkersh3 0:e7ca326e76ee 622
mkersh3 0:e7ca326e76ee 623
mkersh3 0:e7ca326e76ee 624 /**
mkersh3 0:e7ca326e76ee 625 * @brief TX Data Buffer structure definition
mkersh3 0:e7ca326e76ee 626 */
mkersh3 0:e7ca326e76ee 627 typedef struct {
mkersh3 0:e7ca326e76ee 628 uint32_t ulDataLen; /**< Data length */
mkersh3 0:e7ca326e76ee 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
mkersh3 0:e7ca326e76ee 630 } EMAC_PACKETBUF_Type;
mkersh3 0:e7ca326e76ee 631
mkersh3 0:e7ca326e76ee 632 /**
mkersh3 0:e7ca326e76ee 633 * @brief EMAC configuration structure definition
mkersh3 0:e7ca326e76ee 634 */
mkersh3 0:e7ca326e76ee 635 typedef struct {
mkersh3 0:e7ca326e76ee 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
mkersh3 0:e7ca326e76ee 637 - EMAC_MODE_AUTO
mkersh3 0:e7ca326e76ee 638 - EMAC_MODE_10M_FULL
mkersh3 0:e7ca326e76ee 639 - EMAC_MODE_10M_HALF
mkersh3 0:e7ca326e76ee 640 - EMAC_MODE_100M_FULL
mkersh3 0:e7ca326e76ee 641 - EMAC_MODE_100M_HALF
mkersh3 0:e7ca326e76ee 642 */
mkersh3 0:e7ca326e76ee 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
mkersh3 0:e7ca326e76ee 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
mkersh3 0:e7ca326e76ee 645 */
mkersh3 0:e7ca326e76ee 646 } EMAC_CFG_Type;
mkersh3 0:e7ca326e76ee 647
mkersh3 0:e7ca326e76ee 648 /** Ethernet block power/clock control bit*/
mkersh3 0:e7ca326e76ee 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
mkersh3 0:e7ca326e76ee 650
mkersh3 0:e7ca326e76ee 651 #ifdef __cplusplus
mkersh3 0:e7ca326e76ee 652 }
mkersh3 0:e7ca326e76ee 653 #endif
mkersh3 0:e7ca326e76ee 654
mkersh3 0:e7ca326e76ee 655 #endif /* LPC17XX_EMAC_H_ */
mkersh3 0:e7ca326e76ee 656
mkersh3 0:e7ca326e76ee 657 /**
mkersh3 0:e7ca326e76ee 658 * @}
mkersh3 0:e7ca326e76ee 659 */
mkersh3 0:e7ca326e76ee 660
mkersh3 0:e7ca326e76ee 661 /* --------------------------------- End Of File ------------------------------ */