Mike R
An input/output controller for virtual pinball machines, with plunger position tracking, accelerometer-based nudge sensing, button input encoding, and feedback device control.
Dependencies: USBDevice mbed FastAnalogIn FastIO FastPWM SimpleDMA
The Pinscape Controller is a special-purpose software project that I wrote for my virtual pinball machine.
New version: V2 is now available! The information below is for version 1, which will continue to be available for people who prefer the original setup.
What exactly is a virtual pinball machine? It's basically a video-game pinball emulator built to look like a real pinball machine. (The picture at right is the one I built.) You start with a standard pinball cabinet, either built from scratch or salvaged from a real machine. Inside, you install a PC motherboard to run the software, and install TVs in place of the playfield and backglass. Several Windows pinball programs can take advantage of this setup, including the open-source project Visual Pinball, which has hundreds of tables available. Building one of these makes a great DIY project, and it's a good way to add to your skills at woodworking, computers, and electronics. Check out the Cabinet Builders' Forum on vpforums.org for lots of examples and advice.
This controller project is a key piece in my setup that helps integrate the video game into the pinball cabinet. It handles several input/output tasks that are unique to virtual pinball machines. First, it lets you connect a mechanical plunger to the software, so you can launch the ball like on a real machine. Second, it sends "nudge" data to the software, based on readings from an accelerometer. This lets you interact with the game physically, which makes the playing experience more realistic and immersive. Third, the software can handle button input (for wiring flipper buttons and other cabinet buttons), and fourth, it can control output devices (for tactile feedback, button lights, flashers, and other special effects).
Documentation
The Hardware Build Guide (PDF) has detailed instructions on how to set up a Pinscape Controller for your own virtual pinball cabinet.
Update notes
December 2015 version: This version fully supports the new Expansion Board project, but it'll also run without it. The default configuration settings haven't changed, so existing setups should continue to work as before.
August 2015 version: Be sure to get the latest version of the Config Tool for windows if you're upgrading from an older version of the firmware. This update adds support for TSL1412R sensors (a version of the 1410 sensor with a slightly larger pixel array), and a config option to set the mounting orientation of the board in the firmware rather than in VP (for better support for FP and other pinball programs that don't have VP's flexibility for setting the rotation).
Feb/March 2015 software versions: If you have a CCD plunger that you've been using with the older versions, and the plunger stops working (or doesn't work as well) after you update to the latest version, you might need to increase the brightness of your light source slightly. Check the CCD exposure with the Windows config tool to see if it looks too dark. The new software reads the CCD much more quickly than the old versions did. This makes the "shutter speed" faster, which might require a little more light to get the same readings. The CCD is actually really tolerant of varying light levels, so you probably won't have to change anything for the update - I didn't. But if you do have any trouble, have a look at the exposure meter and try a slightly brighter light source if the exposure looks too dark.
Downloads
- Config tool for Windows (.exe and C# source): this is a Windows program that lets you view the raw pixel data from the CCD sensor, trigger plunger calibration mode, and configure some of the software options on the controller.
- Custom VP builds: I created modified versions of Visual Pinball 9.9 and Physmod5 that you might want to use in combination with this controller. The modified versions have special handling for plunger calibration specific to the Pinscape Controller, as well as some enhancements to the nudge physics. If you're not using the plunger, you might still want it for the nudge improvements. The modified version also works with any other input controller, so you can get the enhanced nudging effects even if you're using a different plunger/nudge kit. The big change in the modified versions is a "filter" for accelerometer input that's designed to make the response to cabinet nudges more realistic. It also makes the response more subdued than in the standard VP, so it's not to everyone's taste. The downloads include both the updated executables and the source code changes, in case you want to merge the changes into your own custom version(s).
Note! These features are now standard in the official VP 9.9.1 and VP 10 releases, so you don't need my custom builds if you're using 9.9.1 or 10 or later. I don't think there's any reason to use my 9.9 instead of the official 9.9.1, but I'm leaving it here just in case. In the official VP releases, look for the checkbox "Enable Nudge Filter" in the Keys preferences dialog. (There's no checkbox in my custom builds, though; the filter is simply always on in those.)
- Output circuit shopping list: This is a saved shopping cart at mouser.com with the parts needed for each output driver, if you want to use the LedWiz emulator feature. Note that quantities in the cart are for one output channel, so multiply everything by the number of channels you plan to use, except that you only need one of the ULN2803 transistor array chips for each eight output circuits.
- Lemming77's potentiometer mounting bracket and shooter rod connecter: Sketchup designs for 3D-printable parts for mounting a slide potentiometer as the plunger sensor. These were designed for a particular slide potentiometer that used to be available from an Aliexpress.com seller but is no longer listed. You can probably use this design as a starting point for other similar devices; just check the dimensions before committing the design to plastic.
Features
- Plunger position sensing, using a TAOS TSL 1410R CCD linear array sensor. This sensor is a 1280 x 1 pixel array at 400 dpi, which makes it about 3" long - almost exactly the travel distance of a standard pinball plunger. The idea is that you install the sensor just above (within a few mm of) the shooter rod on the inside of the cabinet, with the CCD window facing down, aligned with and centered on the long axis of the shooter rod, and positioned so that the rest position of the tip is about 1/2" from one end of the window. As you pull back the plunger, the tip will travel down the length of the window, and the maximum retraction point will put the tip just about at the far end of the window. Put a light source below, facing the sensor - I'm using two typical 20 mA blue LEDs about 8" away (near the floor of the cabinet) with good results. The principle of operation is that the shooter rod casts a shadow on the CCD, so pixels behind the rod will register lower brightness than pixels that aren't in the shadow. We scan down the length of the sensor for the edge between darker and brighter, and this tells us how far back the rod has been pulled. We can read the CCD at about 25-30 ms intervals, so we can get rapid updates. We pass the readings reports to VP via our USB joystick reports.
The hardware build guide includes schematics showing how to wire the CCD to the KL25Z. It's pretty straightforward - five wires between the two devices, no external components needed. Two GPIO ports are used as outputs to send signals to the device and one is used as an ADC in to read the pixel brightness inputs. The config tool has a feature that lets you display the raw pixel readings across the array, so you can test that the CCD is working and adjust the light source to get the right exposure level.
Alternatively, you can use a slide potentiometer as the plunger sensor. This is a cheaper and somewhat simpler option that seems to work quite nicely, as you can see in Lemming77's video of this setup in action. This option is also explained more fully in the build guide.
- Nudge sensing via the KL25Z's on-board accelerometer. Mounting the board in your cabinet makes it feel the same accelerations the cabinet experiences when you nudge it. Visual Pinball already knows how to interpret accelerometer input as nudging, so we simply feed the acceleration readings to VP via the joystick interface.
- Cabinet button wiring. Up to 24 pushbuttons and switches can be wired to the controller for input controls (for example, flipper buttons, the Start button, the tilt bob, coin slot switches, and service door buttons). These appear to Windows as joystick buttons. VP can map joystick buttons to pinball inputs via its keyboard preferences dialog. (You can raise the 24-button limit by editing the source code, but since all of the GPIO pins are allocated, you'll have to reassign pins currently used for other functions.)
- LedWiz emulation (limited). In addition to emulating a joystick, the device emulates the LedWiz USB interface, so controllers on the PC side such as DirectOutput Framework can recognize it and send it commands to control lights, solenoids, and other feedback devices. 22 GPIO ports are assigned by default as feedback device outputs. This feature has some limitations. The big one is that the KL25Z hardware only has 10 PWM channels, which isn't enough for a fully decked-out cabinet. You also need to build some external power driver circuitry to use this feature, because of the paltry 4mA output capacity of the KL25Z GPIO ports. The build guide includes instructions for a simple and robust output circuit, including part numbers for the exact components you need. It's not hard if you know your way around a soldering iron, but just be aware that it'll take a little work.
Warning: This is not replacement software for the VirtuaPin plunger kit. If you bought the VirtuaPin kit, please don't try to install this software. The VP kit happens to use the same microcontroller board, but the rest of its hardware is incompatible. The VP kit uses a different type of sensor for its plunger and has completely different button wiring, so the Pinscape software won't work properly with it.
TLC5940/TLC5940.h@40:cc0d9814522b, 2016-02-03 (annotated)
- Committer:
- mjr
- Date:
- Wed Feb 03 22:57:25 2016 +0000
- Revision:
- 40:cc0d9814522b
- Parent:
- 39:b3815a1c3802
Gamma correction option for outputs; work in progress on new config program
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mjr | 26:cb71c4af2912 | 1 | // Pinscape Controller TLC5940 interface |
| mjr | 26:cb71c4af2912 | 2 | // |
| mjr | 26:cb71c4af2912 | 3 | // Based on Spencer Davis's mbed TLC5940 library. Adapted for the |
| mjr | 26:cb71c4af2912 | 4 | // KL25Z, and simplified to just the functions needed for this |
| mjr | 26:cb71c4af2912 | 5 | // application. In particular, this version doesn't include support |
| mjr | 26:cb71c4af2912 | 6 | // for dot correction programming or status input. This version also |
| mjr | 26:cb71c4af2912 | 7 | // uses a different approach for sending the grayscale data updates, |
| mjr | 26:cb71c4af2912 | 8 | // sending updates during the blanking interval rather than overlapping |
| mjr | 26:cb71c4af2912 | 9 | // them with the PWM cycle. This results in very slightly longer |
| mjr | 26:cb71c4af2912 | 10 | // blanking intervals when updates are pending, effectively reducing |
| mjr | 26:cb71c4af2912 | 11 | // the PWM "on" duty cycle (and thus the output brightness) by about |
| mjr | 26:cb71c4af2912 | 12 | // 0.3%. This shouldn't be perceptible to users, so it's a small |
| mjr | 26:cb71c4af2912 | 13 | // trade-off for the advantage gained, which is much better signal |
| mjr | 26:cb71c4af2912 | 14 | // stability when using multiple TLC5940s daisy-chained together. |
| mjr | 26:cb71c4af2912 | 15 | // I saw a lot of instability when using the overlapped approach, |
| mjr | 26:cb71c4af2912 | 16 | // which seems to be eliminated entirely when sending updates during |
| mjr | 26:cb71c4af2912 | 17 | // the blanking interval. |
| mjr | 26:cb71c4af2912 | 18 | |
| mjr | 26:cb71c4af2912 | 19 | |
| mjr | 26:cb71c4af2912 | 20 | #ifndef TLC5940_H |
| mjr | 26:cb71c4af2912 | 21 | #define TLC5940_H |
| mjr | 26:cb71c4af2912 | 22 | |
| mjr | 38:091e511ce8a0 | 23 | // Data Transmission Mode. |
| mjr | 38:091e511ce8a0 | 24 | // |
| mjr | 38:091e511ce8a0 | 25 | // NOTE! This section contains a possible workaround to try if you're |
| mjr | 38:091e511ce8a0 | 26 | // having data signal stability problems with your TLC5940 chips. If |
| mjr | 40:cc0d9814522b | 27 | // things are working properly, you can ignore this part. |
| mjr | 33:d832bcab089e | 28 | // |
| mjr | 38:091e511ce8a0 | 29 | // The software has two options for sending data updates to the chips: |
| mjr | 38:091e511ce8a0 | 30 | // |
| mjr | 40:cc0d9814522b | 31 | // Mode 0: Send data *during* the grayscale cycle. This is the default, |
| mjr | 40:cc0d9814522b | 32 | // and it's the standard method the chips are designed for. In this mode, |
| mjr | 40:cc0d9814522b | 33 | // we start sending an update just after then blanking interval that starts |
| mjr | 40:cc0d9814522b | 34 | // a new grayscale cycle. The timing is arranged so that the update is |
| mjr | 40:cc0d9814522b | 35 | // completed well before the end of the grayscale cycle. At the next |
| mjr | 40:cc0d9814522b | 36 | // blanking interval, we latch the new data, so the new brightness levels |
| mjr | 40:cc0d9814522b | 37 | // will be shown starting on the next cycle. |
| mjr | 40:cc0d9814522b | 38 | |
| mjr | 38:091e511ce8a0 | 39 | // Mode 1: Send data *between* grayscale cycles. In this mode, we send |
| mjr | 38:091e511ce8a0 | 40 | // each complete update during a blanking period, then latch the update |
| mjr | 38:091e511ce8a0 | 41 | // and start the next grayscale cycle. This isn't the way the chips were |
| mjr | 38:091e511ce8a0 | 42 | // intended to be used, but it works. The disadvantage is that it requires |
| mjr | 40:cc0d9814522b | 43 | // the blanking interval to be extended long enough for the full data |
| mjr | 40:cc0d9814522b | 44 | // update (192 bits * the number of chips in the chain). Since the |
| mjr | 40:cc0d9814522b | 45 | // outputs are turned off throughout the blanking period, this reduces |
| mjr | 38:091e511ce8a0 | 46 | // the overall brightness/intensity of the outputs by reducing the duty |
| mjr | 38:091e511ce8a0 | 47 | // cycle. The TLC5940 chips can't achieve 100% duty cycle to begin with, |
| mjr | 40:cc0d9814522b | 48 | // since they require a brief minimum time in the blanking interval |
| mjr | 38:091e511ce8a0 | 49 | // between grayscale cycles; however, the minimum is so short that the |
| mjr | 38:091e511ce8a0 | 50 | // duty cycle is close to 100%. With the full data transmission stuffed |
| mjr | 38:091e511ce8a0 | 51 | // into the blanking interval, we reduce the duty cycle further below |
| mjr | 38:091e511ce8a0 | 52 | // 100%. With four chips in the chain, a 28 MHz data clock, and a |
| mjr | 38:091e511ce8a0 | 53 | // 500 kHz grayscale clock, the reduction is about 0.3%. |
| mjr | 33:d832bcab089e | 54 | // |
| mjr | 40:cc0d9814522b | 55 | // Mode 0 is the method documented in the manufacturer's data sheet. |
| mjr | 40:cc0d9814522b | 56 | // It works well empirically with the Pinscape expansion boards. |
| mjr | 40:cc0d9814522b | 57 | // |
| mjr | 38:091e511ce8a0 | 58 | // So what's the point of Mode 1? In early testing, with a breadboard |
| mjr | 38:091e511ce8a0 | 59 | // setup, I saw some problems with data signal stability, which manifested |
| mjr | 38:091e511ce8a0 | 60 | // as sporadic flickering in the outputs. Switching to Mode 1 improved |
| mjr | 38:091e511ce8a0 | 61 | // the signal stability considerably. I'm therefore leaving this code |
| mjr | 38:091e511ce8a0 | 62 | // available as an option in case anyone runs into similar signal problems |
| mjr | 38:091e511ce8a0 | 63 | // and wants to try the alternative mode as a workaround. |
| mjr | 38:091e511ce8a0 | 64 | // |
| mjr | 38:091e511ce8a0 | 65 | #define DATA_UPDATE_INSIDE_BLANKING 0 |
| mjr | 33:d832bcab089e | 66 | |
| mjr | 26:cb71c4af2912 | 67 | #include "mbed.h" |
| mjr | 26:cb71c4af2912 | 68 | #include "FastPWM.h" |
| mjr | 30:6e9902f06f48 | 69 | #include "SimpleDMA.h" |
| mjr | 26:cb71c4af2912 | 70 | |
| mjr | 26:cb71c4af2912 | 71 | /** |
| mjr | 26:cb71c4af2912 | 72 | * SPI speed used by the mbed to communicate with the TLC5940 |
| mjr | 26:cb71c4af2912 | 73 | * The TLC5940 supports up to 30Mhz. It's best to keep this as |
| mjr | 33:d832bcab089e | 74 | * high as possible, since a higher SPI speed yields a faster |
| mjr | 33:d832bcab089e | 75 | * grayscale data update. However, I've seen some slight |
| mjr | 33:d832bcab089e | 76 | * instability in the signal in my breadboard setup using the |
| mjr | 33:d832bcab089e | 77 | * full 30MHz, so I've reduced this slightly, which seems to |
| mjr | 33:d832bcab089e | 78 | * yield a solid signal. The limit will vary according to how |
| mjr | 33:d832bcab089e | 79 | * clean the signal path is to the chips; you can probably crank |
| mjr | 33:d832bcab089e | 80 | * this up to full speed if you have a well-designed PCB, good |
| mjr | 33:d832bcab089e | 81 | * decoupling capacitors near the 5940 VCC/GND pins, and short |
| mjr | 33:d832bcab089e | 82 | * wires between the KL25Z and the PCB. A short, clean path to |
| mjr | 33:d832bcab089e | 83 | * KL25Z ground seems especially important. |
| mjr | 26:cb71c4af2912 | 84 | * |
| mjr | 26:cb71c4af2912 | 85 | * The SPI clock must be fast enough that the data transmission |
| mjr | 26:cb71c4af2912 | 86 | * time for a full update is comfortably less than the blanking |
| mjr | 26:cb71c4af2912 | 87 | * cycle time. The grayscale refresh requires 192 bits per TLC5940 |
| mjr | 26:cb71c4af2912 | 88 | * in the daisy chain, and each bit takes one SPI clock to send. |
| mjr | 26:cb71c4af2912 | 89 | * Our reference setup in the Pinscape controller allows for up to |
| mjr | 26:cb71c4af2912 | 90 | * 4 TLC5940s, so a full refresh cycle on a fully populated system |
| mjr | 26:cb71c4af2912 | 91 | * would be 768 SPI clocks. The blanking cycle is 4096 GSCLK cycles. |
| mjr | 26:cb71c4af2912 | 92 | * |
| mjr | 26:cb71c4af2912 | 93 | * t(blank) = 4096 * 1/GSCLK_SPEED |
| mjr | 26:cb71c4af2912 | 94 | * t(refresh) = 768 * 1/SPI_SPEED |
| mjr | 26:cb71c4af2912 | 95 | * Therefore: SPI_SPEED must be > 768/4096 * GSCLK_SPEED |
| mjr | 26:cb71c4af2912 | 96 | * |
| mjr | 26:cb71c4af2912 | 97 | * Since the SPI speed can be so high, and since we want to keep |
| mjr | 26:cb71c4af2912 | 98 | * the GSCLK speed relatively low, the constraint above simply |
| mjr | 26:cb71c4af2912 | 99 | * isn't a factor. E.g., at SPI=30MHz and GSCLK=500kHz, |
| mjr | 26:cb71c4af2912 | 100 | * t(blank) is 8192us and t(refresh) is 25us. |
| mjr | 26:cb71c4af2912 | 101 | */ |
| mjr | 38:091e511ce8a0 | 102 | #define SPI_SPEED 28000000 |
| mjr | 26:cb71c4af2912 | 103 | |
| mjr | 26:cb71c4af2912 | 104 | /** |
| mjr | 26:cb71c4af2912 | 105 | * The rate at which the GSCLK pin is pulsed. This also controls |
| mjr | 26:cb71c4af2912 | 106 | * how often the reset function is called. The reset function call |
| mjr | 38:091e511ce8a0 | 107 | * interval is (1/GSCLK_SPEED) * 4096. The maximum reliable rate is |
| mjr | 26:cb71c4af2912 | 108 | * around 32Mhz. It's best to keep this rate as low as possible: |
| mjr | 26:cb71c4af2912 | 109 | * the higher the rate, the higher the refresh() call frequency, |
| mjr | 40:cc0d9814522b | 110 | * so the higher the CPU load. Higher frequencies also make it more |
| mjr | 40:cc0d9814522b | 111 | * challenging to wire the chips for clean signal transmission, so |
| mjr | 40:cc0d9814522b | 112 | * minimizing the clock speed will help with signal stability. |
| mjr | 26:cb71c4af2912 | 113 | * |
| mjr | 40:cc0d9814522b | 114 | * The lower bound depends on the application. For driving lights, |
| mjr | 40:cc0d9814522b | 115 | * the limiting factor is flicker: the lower the rate, the more |
| mjr | 40:cc0d9814522b | 116 | * noticeable the flicker. Incandescents tend to look flicker-free |
| mjr | 40:cc0d9814522b | 117 | * at about 50 Hz (205 kHz grayscale clock). LEDs need slightly |
| mjr | 40:cc0d9814522b | 118 | * faster rates. |
| mjr | 26:cb71c4af2912 | 119 | */ |
| mjr | 40:cc0d9814522b | 120 | #define GSCLK_SPEED 350000 |
| mjr | 26:cb71c4af2912 | 121 | |
| mjr | 26:cb71c4af2912 | 122 | /** |
| mjr | 26:cb71c4af2912 | 123 | * This class controls a TLC5940 PWM driver IC. |
| mjr | 26:cb71c4af2912 | 124 | * |
| mjr | 26:cb71c4af2912 | 125 | * Using the TLC5940 class to control an LED: |
| mjr | 26:cb71c4af2912 | 126 | * @code |
| mjr | 26:cb71c4af2912 | 127 | * #include "mbed.h" |
| mjr | 26:cb71c4af2912 | 128 | * #include "TLC5940.h" |
| mjr | 26:cb71c4af2912 | 129 | * |
| mjr | 26:cb71c4af2912 | 130 | * // Create the TLC5940 instance |
| mjr | 26:cb71c4af2912 | 131 | * TLC5940 tlc(p7, p5, p21, p9, p10, p11, p12, 1); |
| mjr | 26:cb71c4af2912 | 132 | * |
| mjr | 26:cb71c4af2912 | 133 | * int main() |
| mjr | 26:cb71c4af2912 | 134 | * { |
| mjr | 26:cb71c4af2912 | 135 | * // Enable the first LED |
| mjr | 26:cb71c4af2912 | 136 | * tlc.set(0, 0xfff); |
| mjr | 26:cb71c4af2912 | 137 | * |
| mjr | 26:cb71c4af2912 | 138 | * while(1) |
| mjr | 26:cb71c4af2912 | 139 | * { |
| mjr | 26:cb71c4af2912 | 140 | * } |
| mjr | 26:cb71c4af2912 | 141 | * } |
| mjr | 26:cb71c4af2912 | 142 | * @endcode |
| mjr | 26:cb71c4af2912 | 143 | */ |
| mjr | 26:cb71c4af2912 | 144 | class TLC5940 |
| mjr | 26:cb71c4af2912 | 145 | { |
| mjr | 26:cb71c4af2912 | 146 | public: |
| mjr | 26:cb71c4af2912 | 147 | /** |
| mjr | 26:cb71c4af2912 | 148 | * Set up the TLC5940 |
| mjr | 26:cb71c4af2912 | 149 | * @param SCLK - The SCK pin of the SPI bus |
| mjr | 26:cb71c4af2912 | 150 | * @param MOSI - The MOSI pin of the SPI bus |
| mjr | 26:cb71c4af2912 | 151 | * @param GSCLK - The GSCLK pin of the TLC5940(s) |
| mjr | 26:cb71c4af2912 | 152 | * @param BLANK - The BLANK pin of the TLC5940(s) |
| mjr | 26:cb71c4af2912 | 153 | * @param XLAT - The XLAT pin of the TLC5940(s) |
| mjr | 26:cb71c4af2912 | 154 | * @param nchips - The number of TLC5940s (if you are daisy chaining) |
| mjr | 26:cb71c4af2912 | 155 | */ |
| mjr | 26:cb71c4af2912 | 156 | TLC5940(PinName SCLK, PinName MOSI, PinName GSCLK, PinName BLANK, PinName XLAT, int nchips) |
| mjr | 26:cb71c4af2912 | 157 | : spi(MOSI, NC, SCLK), |
| mjr | 26:cb71c4af2912 | 158 | gsclk(GSCLK), |
| mjr | 26:cb71c4af2912 | 159 | blank(BLANK), |
| mjr | 26:cb71c4af2912 | 160 | xlat(XLAT), |
| mjr | 33:d832bcab089e | 161 | nchips(nchips) |
| mjr | 26:cb71c4af2912 | 162 | { |
| mjr | 40:cc0d9814522b | 163 | // start up initially disabled |
| mjr | 40:cc0d9814522b | 164 | enabled = false; |
| mjr | 40:cc0d9814522b | 165 | |
| mjr | 33:d832bcab089e | 166 | // set XLAT to initially off |
| mjr | 30:6e9902f06f48 | 167 | xlat = 0; |
| mjr | 33:d832bcab089e | 168 | |
| mjr | 33:d832bcab089e | 169 | // Assert BLANK while starting up, to keep the outputs turned off until |
| mjr | 33:d832bcab089e | 170 | // everything is stable. This helps prevent spurious flashes during startup. |
| mjr | 33:d832bcab089e | 171 | // (That's not particularly important for lights, but it matters more for |
| mjr | 33:d832bcab089e | 172 | // tactile devices. It's a bit alarming to fire a replay knocker on every |
| mjr | 33:d832bcab089e | 173 | // power-on, for example.) |
| mjr | 30:6e9902f06f48 | 174 | blank = 1; |
| mjr | 30:6e9902f06f48 | 175 | |
| mjr | 26:cb71c4af2912 | 176 | // Configure SPI format and speed. Note that KL25Z ONLY supports 8-bit |
| mjr | 26:cb71c4af2912 | 177 | // mode. The TLC5940 nominally requires 12-bit data blocks for the |
| mjr | 26:cb71c4af2912 | 178 | // grayscale levels, but SPI is ultimately just a bit-level serial format, |
| mjr | 26:cb71c4af2912 | 179 | // so we can reformat the 12-bit blocks into 8-bit bytes to fit the |
| mjr | 26:cb71c4af2912 | 180 | // KL25Z's limits. This should work equally well on other microcontrollers |
| mjr | 38:091e511ce8a0 | 181 | // that are more flexible. The TLC5940 requires polarity/phase format 0. |
| mjr | 26:cb71c4af2912 | 182 | spi.format(8, 0); |
| mjr | 26:cb71c4af2912 | 183 | spi.frequency(SPI_SPEED); |
| mjr | 33:d832bcab089e | 184 | |
| mjr | 33:d832bcab089e | 185 | // Send out a full data set to the chips, to clear out any random |
| mjr | 33:d832bcab089e | 186 | // startup data from the registers. Include some extra bits - there |
| mjr | 33:d832bcab089e | 187 | // are some cases (such as after sending dot correct commands) where |
| mjr | 33:d832bcab089e | 188 | // an extra bit per chip is required, and the initial state is |
| mjr | 33:d832bcab089e | 189 | // somewhat unpredictable, so send extra just to make sure we cover |
| mjr | 33:d832bcab089e | 190 | // all bases. This does no harm; extra bits just fall off the end of |
| mjr | 33:d832bcab089e | 191 | // the daisy chain, and since we want all registers set to 0, we can |
| mjr | 33:d832bcab089e | 192 | // send arbitrarily many extra 0's. |
| mjr | 33:d832bcab089e | 193 | for (int i = 0 ; i < nchips*25 ; ++i) |
| mjr | 33:d832bcab089e | 194 | spi.write(0); |
| mjr | 33:d832bcab089e | 195 | |
| mjr | 33:d832bcab089e | 196 | // do an initial XLAT to latch all of these "0" values into the |
| mjr | 33:d832bcab089e | 197 | // grayscale registers |
| mjr | 33:d832bcab089e | 198 | xlat = 1; |
| mjr | 33:d832bcab089e | 199 | xlat = 0; |
| mjr | 29:582472d0bc57 | 200 | |
| mjr | 39:b3815a1c3802 | 201 | // Allocate our DMA buffers. The transfer on each cycle is 192 bits per |
| mjr | 40:cc0d9814522b | 202 | // chip = 24 bytes per chip. Allocate two buffers, so that we have a |
| mjr | 40:cc0d9814522b | 203 | // stable buffer that we can send to the chips, and a separate working |
| mjr | 40:cc0d9814522b | 204 | // copy that we can asynchronously update. |
| mjr | 40:cc0d9814522b | 205 | dmalen = nchips*24; |
| mjr | 40:cc0d9814522b | 206 | dmabuf = new uint8_t[dmalen*2]; |
| mjr | 40:cc0d9814522b | 207 | memset(dmabuf, 0, dmalen*2); |
| mjr | 26:cb71c4af2912 | 208 | |
| mjr | 40:cc0d9814522b | 209 | zerobuf = new uint8_t[dmalen];//$$$ |
| mjr | 40:cc0d9814522b | 210 | memset(zerobuf, 0xff, dmalen);//$$$ |
| mjr | 40:cc0d9814522b | 211 | |
| mjr | 40:cc0d9814522b | 212 | // start with buffer 0 live, with no new data pending |
| mjr | 40:cc0d9814522b | 213 | livebuf = dmabuf; |
| mjr | 40:cc0d9814522b | 214 | workbuf = dmabuf + dmalen; |
| mjr | 40:cc0d9814522b | 215 | dirty = false; |
| mjr | 40:cc0d9814522b | 216 | |
| mjr | 30:6e9902f06f48 | 217 | // Set up the Simple DMA interface object. We use the DMA controller to |
| mjr | 30:6e9902f06f48 | 218 | // send grayscale data updates to the TLC5940 chips. This lets the CPU |
| mjr | 30:6e9902f06f48 | 219 | // keep running other tasks while we send gs updates, and importantly |
| mjr | 30:6e9902f06f48 | 220 | // allows our blanking interrupt handler return almost immediately. |
| mjr | 30:6e9902f06f48 | 221 | // The DMA transfer is from our internal DMA buffer to SPI0, which is |
| mjr | 30:6e9902f06f48 | 222 | // the SPI controller physically connected to the TLC5940s. |
| mjr | 40:cc0d9814522b | 223 | sdma.source(livebuf, true, 8); |
| mjr | 38:091e511ce8a0 | 224 | sdma.destination(&(SPI0->D), false, 8); |
| mjr | 30:6e9902f06f48 | 225 | sdma.trigger(Trigger_SPI0_TX); |
| mjr | 30:6e9902f06f48 | 226 | sdma.attach(this, &TLC5940::dmaDone); |
| mjr | 30:6e9902f06f48 | 227 | |
| mjr | 30:6e9902f06f48 | 228 | // Enable DMA on SPI0. SimpleDMA doesn't do this for us; we have to |
| mjr | 30:6e9902f06f48 | 229 | // do it explicitly. This is just a matter of setting bit 5 (TXDMAE) |
| mjr | 38:091e511ce8a0 | 230 | // in the SPI controller's Control Register 2 (C2). |
| mjr | 30:6e9902f06f48 | 231 | SPI0->C2 |= 0x20; // set bit 5 = 0x20 = TXDMAE in SPI0 control register 2 |
| mjr | 30:6e9902f06f48 | 232 | |
| mjr | 30:6e9902f06f48 | 233 | // Configure the GSCLK output's frequency |
| mjr | 26:cb71c4af2912 | 234 | gsclk.period(1.0/GSCLK_SPEED); |
| mjr | 33:d832bcab089e | 235 | |
| mjr | 33:d832bcab089e | 236 | // mark that we need an initial update |
| mjr | 40:cc0d9814522b | 237 | dirty = true; |
| mjr | 33:d832bcab089e | 238 | needXlat = false; |
| mjr | 40:cc0d9814522b | 239 | } |
| mjr | 40:cc0d9814522b | 240 | |
| mjr | 40:cc0d9814522b | 241 | // Global enable/disble. When disabled, we assert the blanking signal |
| mjr | 40:cc0d9814522b | 242 | // continuously to keep all outputs turned off. This can be used during |
| mjr | 40:cc0d9814522b | 243 | // startup and sleep mode to prevent spurious output signals from |
| mjr | 40:cc0d9814522b | 244 | // uninitialized grayscale registers. The chips have random values in |
| mjr | 40:cc0d9814522b | 245 | // their internal registers when power is first applied, so we have to |
| mjr | 40:cc0d9814522b | 246 | // explicitly send the initial zero levels after power cycling the chips. |
| mjr | 40:cc0d9814522b | 247 | // The chips might not have power even when the KL25Z is running, because |
| mjr | 40:cc0d9814522b | 248 | // they might be powered from a separate power supply from the KL25Z |
| mjr | 40:cc0d9814522b | 249 | // (the Pinscape Expansion Boards work this way). Global blanking helps |
| mjr | 40:cc0d9814522b | 250 | // us start up more cleanly by suppressing all outputs until we can be |
| mjr | 40:cc0d9814522b | 251 | // reasonably sure that the various chip registers are initialized. |
| mjr | 40:cc0d9814522b | 252 | void enable(bool f) |
| mjr | 40:cc0d9814522b | 253 | { |
| mjr | 40:cc0d9814522b | 254 | // note the new setting |
| mjr | 40:cc0d9814522b | 255 | enabled = f; |
| mjr | 40:cc0d9814522b | 256 | |
| mjr | 40:cc0d9814522b | 257 | // if disabled, apply blanking immediately |
| mjr | 40:cc0d9814522b | 258 | if (!f) |
| mjr | 40:cc0d9814522b | 259 | { |
| mjr | 40:cc0d9814522b | 260 | gsclk.write(0); |
| mjr | 40:cc0d9814522b | 261 | blank = 1; |
| mjr | 40:cc0d9814522b | 262 | } |
| mjr | 40:cc0d9814522b | 263 | |
| mjr | 40:cc0d9814522b | 264 | // do a full update with the new setting |
| mjr | 40:cc0d9814522b | 265 | dirty = true; |
| mjr | 40:cc0d9814522b | 266 | } |
| mjr | 29:582472d0bc57 | 267 | |
| mjr | 30:6e9902f06f48 | 268 | // Start the clock running |
| mjr | 29:582472d0bc57 | 269 | void start() |
| mjr | 29:582472d0bc57 | 270 | { |
| mjr | 26:cb71c4af2912 | 271 | // Set up the first call to the reset function, which asserts BLANK to |
| mjr | 26:cb71c4af2912 | 272 | // end the PWM cycle and handles new grayscale data output and latching. |
| mjr | 26:cb71c4af2912 | 273 | // The original version of this library uses a timer to call reset |
| mjr | 26:cb71c4af2912 | 274 | // periodically, but that approach is somewhat problematic because the |
| mjr | 26:cb71c4af2912 | 275 | // reset function itself takes a small amount of time to run, so the |
| mjr | 26:cb71c4af2912 | 276 | // *actual* cycle is slightly longer than what we get from counting |
| mjr | 26:cb71c4af2912 | 277 | // GS clocks. Running reset on a timer therefore causes the calls to |
| mjr | 26:cb71c4af2912 | 278 | // slip out of phase with the actual full cycles, which causes |
| mjr | 26:cb71c4af2912 | 279 | // premature blanking that shows up as visible flicker. To get the |
| mjr | 26:cb71c4af2912 | 280 | // reset cycle to line up exactly with a full PWM cycle, it works |
| mjr | 26:cb71c4af2912 | 281 | // better to set up a new timer on each cycle, *after* we've finished |
| mjr | 26:cb71c4af2912 | 282 | // with the somewhat unpredictable overhead of the interrupt handler. |
| mjr | 26:cb71c4af2912 | 283 | // This ensures that we'll get much closer to exact alignment of the |
| mjr | 26:cb71c4af2912 | 284 | // cycle phase, and in any case the worst that happens is that some |
| mjr | 26:cb71c4af2912 | 285 | // cycles are very slightly too long or short (due to imperfections |
| mjr | 26:cb71c4af2912 | 286 | // in the timer clock vs the PWM clock that determines the GSCLCK |
| mjr | 26:cb71c4af2912 | 287 | // output to the TLC5940), which is far less noticeable than a |
| mjr | 26:cb71c4af2912 | 288 | // constantly rotating phase misalignment. |
| mjr | 38:091e511ce8a0 | 289 | resetTimer.attach(this, &TLC5940::reset, (1.0/GSCLK_SPEED)*4096.0); |
| mjr | 26:cb71c4af2912 | 290 | } |
| mjr | 26:cb71c4af2912 | 291 | |
| mjr | 26:cb71c4af2912 | 292 | ~TLC5940() |
| mjr | 26:cb71c4af2912 | 293 | { |
| mjr | 30:6e9902f06f48 | 294 | delete [] dmabuf; |
| mjr | 26:cb71c4af2912 | 295 | } |
| mjr | 26:cb71c4af2912 | 296 | |
| mjr | 39:b3815a1c3802 | 297 | /* |
| mjr | 39:b3815a1c3802 | 298 | * Set an output |
| mjr | 26:cb71c4af2912 | 299 | */ |
| mjr | 26:cb71c4af2912 | 300 | void set(int idx, unsigned short data) |
| mjr | 26:cb71c4af2912 | 301 | { |
| mjr | 39:b3815a1c3802 | 302 | // validate the index |
| mjr | 39:b3815a1c3802 | 303 | if (idx >= 0 && idx < nchips*16) |
| mjr | 39:b3815a1c3802 | 304 | { |
| mjr | 40:cc0d9814522b | 305 | // this is a critical section, since we're updating a static buffer and |
| mjr | 40:cc0d9814522b | 306 | // can call this routine from application context or interrupt context |
| mjr | 40:cc0d9814522b | 307 | __disable_irq(); |
| mjr | 40:cc0d9814522b | 308 | |
| mjr | 40:cc0d9814522b | 309 | // If the buffer isn't dirty, it means that the previous working buffer |
| mjr | 40:cc0d9814522b | 310 | // was swapped into the live buffer on the last blanking interval. This |
| mjr | 40:cc0d9814522b | 311 | // means that the working buffer hasn't been updated to the live data yet, |
| mjr | 40:cc0d9814522b | 312 | // so we need to copy it now. |
| mjr | 40:cc0d9814522b | 313 | if (!dirty) |
| mjr | 40:cc0d9814522b | 314 | { |
| mjr | 40:cc0d9814522b | 315 | memcpy(workbuf, livebuf, dmalen); |
| mjr | 40:cc0d9814522b | 316 | dirty = true; |
| mjr | 40:cc0d9814522b | 317 | } |
| mjr | 40:cc0d9814522b | 318 | |
| mjr | 39:b3815a1c3802 | 319 | // Figure the DMA buffer location of the data. The DMA buffer has the |
| mjr | 39:b3815a1c3802 | 320 | // packed bit format that we send across the wire, with 12 bits per output, |
| mjr | 39:b3815a1c3802 | 321 | // arranged from last output to first output (N = number of outputs = nchips*16): |
| mjr | 39:b3815a1c3802 | 322 | // |
| mjr | 39:b3815a1c3802 | 323 | // byte 0 = high 8 bits of output N-1 |
| mjr | 39:b3815a1c3802 | 324 | // 1 = low 4 bits of output N-1 | high 4 bits of output N-2 |
| mjr | 39:b3815a1c3802 | 325 | // 2 = low 8 bits of N-2 |
| mjr | 39:b3815a1c3802 | 326 | // 3 = high 8 bits of N-3 |
| mjr | 39:b3815a1c3802 | 327 | // 4 = low 4 bits of N-3 | high 4 bits of N-2 |
| mjr | 39:b3815a1c3802 | 328 | // 5 = low 8bits of N-4 |
| mjr | 39:b3815a1c3802 | 329 | // ... |
| mjr | 39:b3815a1c3802 | 330 | // 24*nchips-3 = high 8 bits of output 1 |
| mjr | 39:b3815a1c3802 | 331 | // 24*nchips-2 = low 4 bits of output 1 | high 4 bits of output 0 |
| mjr | 39:b3815a1c3802 | 332 | // 24*nchips-1 = low 8 bits of output 0 |
| mjr | 39:b3815a1c3802 | 333 | // |
| mjr | 39:b3815a1c3802 | 334 | // So this update will affect two bytes. If the output number if even, we're |
| mjr | 39:b3815a1c3802 | 335 | // in the high 4 + low 8 pair; if odd, we're in the high 8 + low 4 pair. |
| mjr | 39:b3815a1c3802 | 336 | int di = nchips*24 - 3 - (3*(idx/2)); |
| mjr | 39:b3815a1c3802 | 337 | if (idx & 1) |
| mjr | 39:b3815a1c3802 | 338 | { |
| mjr | 39:b3815a1c3802 | 339 | // ODD = high 8 | low 4 |
| mjr | 40:cc0d9814522b | 340 | workbuf[di] = uint8_t((data >> 4) & 0xff); |
| mjr | 40:cc0d9814522b | 341 | workbuf[di+1] &= 0x0F; |
| mjr | 40:cc0d9814522b | 342 | workbuf[di+1] |= uint8_t((data << 4) & 0xf0); |
| mjr | 39:b3815a1c3802 | 343 | } |
| mjr | 39:b3815a1c3802 | 344 | else |
| mjr | 39:b3815a1c3802 | 345 | { |
| mjr | 39:b3815a1c3802 | 346 | // EVEN = high 4 | low 8 |
| mjr | 40:cc0d9814522b | 347 | workbuf[di+1] &= 0xF0; |
| mjr | 40:cc0d9814522b | 348 | workbuf[di+1] |= uint8_t((data >> 8) & 0x0f); |
| mjr | 40:cc0d9814522b | 349 | workbuf[di+2] = uint8_t(data & 0xff); |
| mjr | 39:b3815a1c3802 | 350 | } |
| mjr | 39:b3815a1c3802 | 351 | |
| mjr | 40:cc0d9814522b | 352 | // end the critical section |
| mjr | 40:cc0d9814522b | 353 | __enable_irq(); |
| mjr | 39:b3815a1c3802 | 354 | } |
| mjr | 26:cb71c4af2912 | 355 | } |
| mjr | 40:cc0d9814522b | 356 | |
| mjr | 40:cc0d9814522b | 357 | // Update the outputs. We automatically update the outputs on the grayscale timer |
| mjr | 40:cc0d9814522b | 358 | // when we have pending changes, so it's not necessary to call this explicitly after |
| mjr | 40:cc0d9814522b | 359 | // making a change via set(). This can be called to force an update when the chips |
| mjr | 40:cc0d9814522b | 360 | // might be out of sync with our internal state, such as after power-on. |
| mjr | 40:cc0d9814522b | 361 | void update(bool force = false) |
| mjr | 40:cc0d9814522b | 362 | { |
| mjr | 40:cc0d9814522b | 363 | if (force) |
| mjr | 40:cc0d9814522b | 364 | dirty = true; |
| mjr | 40:cc0d9814522b | 365 | } |
| mjr | 26:cb71c4af2912 | 366 | |
| mjr | 26:cb71c4af2912 | 367 | private: |
| mjr | 26:cb71c4af2912 | 368 | // current level for each output |
| mjr | 26:cb71c4af2912 | 369 | unsigned short *gs; |
| mjr | 26:cb71c4af2912 | 370 | |
| mjr | 30:6e9902f06f48 | 371 | // Simple DMA interface object |
| mjr | 30:6e9902f06f48 | 372 | SimpleDMA sdma; |
| mjr | 30:6e9902f06f48 | 373 | |
| mjr | 40:cc0d9814522b | 374 | // DMA transfer buffers - double buffer. Each time we have data to transmit to the |
| mjr | 40:cc0d9814522b | 375 | // TLC5940 chips, we format the data into the working half of this buffer exactly as |
| mjr | 40:cc0d9814522b | 376 | // it will go across the wire, then hand the buffer to the DMA controller to move |
| mjr | 40:cc0d9814522b | 377 | // through the SPI port. This memory block is actually two buffers, one live and |
| mjr | 40:cc0d9814522b | 378 | // one pending. When we're ready to send updates to the chips, we swap the working |
| mjr | 40:cc0d9814522b | 379 | // buffer into the live buffer so that we can send the latest updates. We keep a |
| mjr | 40:cc0d9814522b | 380 | // separate working copy so that our live copy is stable, so that we don't alter |
| mjr | 40:cc0d9814522b | 381 | // any data in the midst of an asynchronous DMA transmission to the chips. |
| mjr | 40:cc0d9814522b | 382 | uint8_t *dmabuf; |
| mjr | 40:cc0d9814522b | 383 | |
| mjr | 40:cc0d9814522b | 384 | uint8_t *zerobuf; // $$$ buffer for all zeroes to flush chip registers when no updates are needed |
| mjr | 40:cc0d9814522b | 385 | |
| mjr | 40:cc0d9814522b | 386 | // The working and live buffer pointers. At any give time, one buffer is live and |
| mjr | 40:cc0d9814522b | 387 | // the other is active. |
| mjr | 40:cc0d9814522b | 388 | // dmabuf1 is live and the other is the working buffer. When there's pending work, |
| mjr | 40:cc0d9814522b | 389 | // we swap them to make the pending data live. |
| mjr | 40:cc0d9814522b | 390 | uint8_t *livebuf; |
| mjr | 40:cc0d9814522b | 391 | uint8_t *workbuf; |
| mjr | 40:cc0d9814522b | 392 | |
| mjr | 40:cc0d9814522b | 393 | // length of each DMA buffer, in bytes - 12 bits = 1.5 bytes per output, 16 outputs |
| mjr | 40:cc0d9814522b | 394 | // per chip -> 24 bytes per chip |
| mjr | 40:cc0d9814522b | 395 | uint16_t dmalen; |
| mjr | 40:cc0d9814522b | 396 | |
| mjr | 40:cc0d9814522b | 397 | // Dirty: true means that the non-live buffer has new pending data. False means |
| mjr | 40:cc0d9814522b | 398 | // that the non-live buffer is empty. |
| mjr | 40:cc0d9814522b | 399 | bool dirty; |
| mjr | 40:cc0d9814522b | 400 | |
| mjr | 40:cc0d9814522b | 401 | // Enabled: this enables or disables all outputs. When this is true, we assert the |
| mjr | 40:cc0d9814522b | 402 | // BLANK signal continuously. |
| mjr | 40:cc0d9814522b | 403 | bool enabled; |
| mjr | 30:6e9902f06f48 | 404 | |
| mjr | 26:cb71c4af2912 | 405 | // SPI port - only MOSI and SCK are used |
| mjr | 26:cb71c4af2912 | 406 | SPI spi; |
| mjr | 26:cb71c4af2912 | 407 | |
| mjr | 26:cb71c4af2912 | 408 | // use a PWM out for the grayscale clock - this provides a stable |
| mjr | 26:cb71c4af2912 | 409 | // square wave signal without consuming CPU |
| mjr | 26:cb71c4af2912 | 410 | FastPWM gsclk; |
| mjr | 26:cb71c4af2912 | 411 | |
| mjr | 26:cb71c4af2912 | 412 | // Digital out pins used for the TLC5940 |
| mjr | 26:cb71c4af2912 | 413 | DigitalOut blank; |
| mjr | 26:cb71c4af2912 | 414 | DigitalOut xlat; |
| mjr | 26:cb71c4af2912 | 415 | |
| mjr | 26:cb71c4af2912 | 416 | // number of daisy-chained TLC5940s we're controlling |
| mjr | 26:cb71c4af2912 | 417 | int nchips; |
| mjr | 26:cb71c4af2912 | 418 | |
| mjr | 26:cb71c4af2912 | 419 | // Timeout to end each PWM cycle. This is a one-shot timer that we reset |
| mjr | 26:cb71c4af2912 | 420 | // on each cycle. |
| mjr | 38:091e511ce8a0 | 421 | Timeout resetTimer; |
| mjr | 26:cb71c4af2912 | 422 | |
| mjr | 33:d832bcab089e | 423 | // Do we need an XLAT signal on the next blanking interval? |
| mjr | 33:d832bcab089e | 424 | volatile bool needXlat; |
| mjr | 40:cc0d9814522b | 425 | volatile bool newGSData;//$$$ |
| mjr | 26:cb71c4af2912 | 426 | |
| mjr | 40:cc0d9814522b | 427 | // Reset the grayscale cycle and send the next data update |
| mjr | 26:cb71c4af2912 | 428 | void reset() |
| mjr | 26:cb71c4af2912 | 429 | { |
| mjr | 30:6e9902f06f48 | 430 | // start the blanking cycle |
| mjr | 30:6e9902f06f48 | 431 | startBlank(); |
| mjr | 33:d832bcab089e | 432 | |
| mjr | 40:cc0d9814522b | 433 | // if we have pending grayscale data, update the DMA data |
| mjr | 40:cc0d9814522b | 434 | /*$$$bool*/ newGSData = false; |
| mjr | 40:cc0d9814522b | 435 | if (dirty) |
| mjr | 40:cc0d9814522b | 436 | { |
| mjr | 40:cc0d9814522b | 437 | // swap live and working buffers |
| mjr | 40:cc0d9814522b | 438 | uint8_t *tmp = livebuf; |
| mjr | 40:cc0d9814522b | 439 | livebuf = workbuf; |
| mjr | 40:cc0d9814522b | 440 | workbuf = tmp; |
| mjr | 40:cc0d9814522b | 441 | |
| mjr | 40:cc0d9814522b | 442 | // set the new DMA source |
| mjr | 40:cc0d9814522b | 443 | sdma.source(livebuf, true, 8); |
| mjr | 40:cc0d9814522b | 444 | |
| mjr | 40:cc0d9814522b | 445 | // no longer dirty |
| mjr | 40:cc0d9814522b | 446 | dirty = false; |
| mjr | 40:cc0d9814522b | 447 | |
| mjr | 40:cc0d9814522b | 448 | // note the new data |
| mjr | 40:cc0d9814522b | 449 | newGSData = true; |
| mjr | 40:cc0d9814522b | 450 | } |
| mjr | 40:cc0d9814522b | 451 | else { sdma.source(zerobuf, true, 8); }//$$$ |
| mjr | 40:cc0d9814522b | 452 | |
| mjr | 33:d832bcab089e | 453 | #if DATA_UPDATE_INSIDE_BLANKING |
| mjr | 33:d832bcab089e | 454 | // We're configured to send the new GS data entirely within |
| mjr | 33:d832bcab089e | 455 | // the blanking interval. Start the DMA transfer now, and |
| mjr | 33:d832bcab089e | 456 | // return without ending the blanking interval. The DMA |
| mjr | 33:d832bcab089e | 457 | // completion interrupt handler will do that when the data |
| mjr | 33:d832bcab089e | 458 | // update has completed. |
| mjr | 33:d832bcab089e | 459 | // |
| mjr | 33:d832bcab089e | 460 | // Note that we do the data update/ unconditionally in the |
| mjr | 33:d832bcab089e | 461 | // send-during-blanking case, whether or not we have new GS |
| mjr | 33:d832bcab089e | 462 | // data. This is because the update causes a 0.3% reduction |
| mjr | 33:d832bcab089e | 463 | // in brightness because of the elongated BLANK interval. |
| mjr | 33:d832bcab089e | 464 | // That would be visible as a flicker on each update if we |
| mjr | 33:d832bcab089e | 465 | // did updates on some cycles and not others. By doing an |
| mjr | 33:d832bcab089e | 466 | // update on every cycle, we make the brightness reduction |
| mjr | 33:d832bcab089e | 467 | // uniform across time, which makes it less perceptible. |
| mjr | 40:cc0d9814522b | 468 | sdma.start(dmalen); |
| mjr | 33:d832bcab089e | 469 | |
| mjr | 33:d832bcab089e | 470 | #else // DATA_UPDATE_INSIDE_BLANKING |
| mjr | 33:d832bcab089e | 471 | |
| mjr | 33:d832bcab089e | 472 | // end the blanking interval |
| mjr | 33:d832bcab089e | 473 | endBlank(); |
| mjr | 33:d832bcab089e | 474 | |
| mjr | 40:cc0d9814522b | 475 | // send out the DMA contents if we have new data |
| mjr | 40:cc0d9814522b | 476 | //$$$ if (newGSData) |
| mjr | 40:cc0d9814522b | 477 | sdma.start(dmalen); |
| mjr | 26:cb71c4af2912 | 478 | |
| mjr | 33:d832bcab089e | 479 | #endif // DATA_UPDATE_INSIDE_BLANKING |
| mjr | 30:6e9902f06f48 | 480 | } |
| mjr | 30:6e9902f06f48 | 481 | |
| mjr | 30:6e9902f06f48 | 482 | void startBlank() |
| mjr | 30:6e9902f06f48 | 483 | { |
| mjr | 30:6e9902f06f48 | 484 | // turn off the grayscale clock, and assert BLANK to end the grayscale cycle |
| mjr | 30:6e9902f06f48 | 485 | gsclk.write(0); |
| mjr | 40:cc0d9814522b | 486 | blank = 0; // for a slight delay - chip requires 20ns GSCLK up to BLANK up |
| mjr | 30:6e9902f06f48 | 487 | blank = 1; |
| mjr | 30:6e9902f06f48 | 488 | } |
| mjr | 26:cb71c4af2912 | 489 | |
| mjr | 33:d832bcab089e | 490 | void endBlank() |
| mjr | 30:6e9902f06f48 | 491 | { |
| mjr | 33:d832bcab089e | 492 | // if we've sent new grayscale data since the last blanking |
| mjr | 33:d832bcab089e | 493 | // interval, latch it by asserting XLAT |
| mjr | 33:d832bcab089e | 494 | if (needXlat) |
| mjr | 30:6e9902f06f48 | 495 | { |
| mjr | 26:cb71c4af2912 | 496 | // latch the new data while we're still blanked |
| mjr | 26:cb71c4af2912 | 497 | xlat = 1; |
| mjr | 26:cb71c4af2912 | 498 | xlat = 0; |
| mjr | 33:d832bcab089e | 499 | needXlat = false; |
| mjr | 26:cb71c4af2912 | 500 | } |
| mjr | 26:cb71c4af2912 | 501 | |
| mjr | 40:cc0d9814522b | 502 | // End the blanking interval and restart the grayscale clock. Note |
| mjr | 40:cc0d9814522b | 503 | // that we keep the blanking on if the chips are globally disabled. |
| mjr | 40:cc0d9814522b | 504 | blank = enabled ? 0 : 1; |
| mjr | 26:cb71c4af2912 | 505 | gsclk.write(.5); |
| mjr | 26:cb71c4af2912 | 506 | |
| mjr | 26:cb71c4af2912 | 507 | // set up the next blanking interrupt |
| mjr | 38:091e511ce8a0 | 508 | resetTimer.attach(this, &TLC5940::reset, (1.0/GSCLK_SPEED)*4096.0); |
| mjr | 26:cb71c4af2912 | 509 | } |
| mjr | 26:cb71c4af2912 | 510 | |
| mjr | 30:6e9902f06f48 | 511 | // Interrupt handler for DMA completion. The DMA controller calls this |
| mjr | 30:6e9902f06f48 | 512 | // when it finishes with the transfer request we set up above. When the |
| mjr | 30:6e9902f06f48 | 513 | // transfer is done, we simply end the blanking cycle and start a new |
| mjr | 30:6e9902f06f48 | 514 | // grayscale cycle. |
| mjr | 30:6e9902f06f48 | 515 | void dmaDone() |
| mjr | 30:6e9902f06f48 | 516 | { |
| mjr | 33:d832bcab089e | 517 | // mark that we need to assert XLAT to latch the new |
| mjr | 33:d832bcab089e | 518 | // grayscale data during the next blanking interval |
| mjr | 40:cc0d9814522b | 519 | needXlat = newGSData;//$$$ true; |
| mjr | 33:d832bcab089e | 520 | |
| mjr | 33:d832bcab089e | 521 | #if DATA_UPDATE_INSIDE_BLANKING |
| mjr | 33:d832bcab089e | 522 | // we're doing the gs update within the blanking cycle, so end |
| mjr | 33:d832bcab089e | 523 | // the blanking cycle now that the transfer has completed |
| mjr | 33:d832bcab089e | 524 | endBlank(); |
| mjr | 33:d832bcab089e | 525 | #endif |
| mjr | 30:6e9902f06f48 | 526 | } |
| mjr | 30:6e9902f06f48 | 527 | |
| mjr | 26:cb71c4af2912 | 528 | }; |
| mjr | 26:cb71c4af2912 | 529 | |
| mjr | 26:cb71c4af2912 | 530 | #endif |