Mike R / FastPWM

Pinscape fork (KL25Z)

Dependents:   Pinscape_Controller_V2_arnoz Pinscape_Controller_V2

Fork of FastPWM by Erik -

Device/FastPWM_STM_TIM_PinOut.cpp@27:7f484dd7323d, 2016-02-11 (annotated)

Committer:
Sissors
Date:
Thu Feb 11 06:33:59 2016 +0000
Revision:
27:7f484dd7323d
Parent:
26:0c924507a81f
Child:
29:3c8a0d977bc3
Added extra Nucleo/Disco targets (by https://developer.mbed.org/users/mimi3/)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 13:cdefd9d75b64 1 #include "mbed.h"
Sissors 13:cdefd9d75b64 2
alpsayin 25:8b1bf34c72aa 3 #ifdef TARGET_NUCLEO_F303RE
alpsayin 25:8b1bf34c72aa 4 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
alpsayin 25:8b1bf34c72aa 5 switch (pin) {
alpsayin 25:8b1bf34c72aa 6 // Channels 1
alpsayin 25:8b1bf34c72aa 7 case PC_0: case PB_8: case PB_9: case PA_6: case PA_8: case PB_4: case PB_5: case PA_2: case PC_6: case PA_12: case PB_14: case PB_15:
alpsayin 25:8b1bf34c72aa 8 // Channels 1N
alpsayin 25:8b1bf34c72aa 9 case PA_1: case PA_5: case PB_6: case PB_3: case PA_13: case PB_7: case PC_13:
alpsayin 25:8b1bf34c72aa 10 return &pwm->CCR1;
alpsayin 25:8b1bf34c72aa 11
alpsayin 25:8b1bf34c72aa 12 // Channels 2
alpsayin 25:8b1bf34c72aa 13 case PC_1: case PA_7: case PC_7: case PA_9: case PA_3: case PA_14:
alpsayin 25:8b1bf34c72aa 14 // Channels 2N
alpsayin 25:8b1bf34c72aa 15 case PB_0:
alpsayin 25:8b1bf34c72aa 16 return &pwm->CCR2;
alpsayin 25:8b1bf34c72aa 17
alpsayin 25:8b1bf34c72aa 18 // Channels 3
alpsayin 25:8b1bf34c72aa 19 case PA_10: case PC_2: case PC_8:
alpsayin 25:8b1bf34c72aa 20 // Channels 3N
alpsayin 25:8b1bf34c72aa 21 case PB_1:
alpsayin 25:8b1bf34c72aa 22 return &pwm->CCR3;
alpsayin 25:8b1bf34c72aa 23
alpsayin 25:8b1bf34c72aa 24 // Channels 4
alpsayin 25:8b1bf34c72aa 25 case PC_3: case PC_9: case PA_11:
alpsayin 25:8b1bf34c72aa 26 // Channels 4N
alpsayin 25:8b1bf34c72aa 27
alpsayin 25:8b1bf34c72aa 28 return &pwm->CCR4;
alpsayin 25:8b1bf34c72aa 29 }
alpsayin 25:8b1bf34c72aa 30 return NULL;
alpsayin 25:8b1bf34c72aa 31 }
alpsayin 25:8b1bf34c72aa 32 #endif
alpsayin 25:8b1bf34c72aa 33
Sissors 27:7f484dd7323d 34 #if defined (TARGET_NUCLEO_F030R8) || (TARGET_DISCO_F051R8)
Sissors 13:cdefd9d75b64 35 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 13:cdefd9d75b64 36 switch (pin) {
Sissors 13:cdefd9d75b64 37 // Channels 1
Sissors 13:cdefd9d75b64 38 case PA_4: case PA_6: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6: case PB_6: case PB_7:
Sissors 13:cdefd9d75b64 39 return &pwm->CCR1;
Sissors 13:cdefd9d75b64 40
Sissors 13:cdefd9d75b64 41 // Channels 2
Sissors 13:cdefd9d75b64 42 case PA_7: case PB_5: case PC_7:
Sissors 13:cdefd9d75b64 43 return &pwm->CCR2;
Sissors 13:cdefd9d75b64 44
Sissors 13:cdefd9d75b64 45 // Channels 3
Sissors 13:cdefd9d75b64 46 case PB_0: case PC_8:
Sissors 13:cdefd9d75b64 47 return &pwm->CCR3;
Sissors 13:cdefd9d75b64 48
Sissors 13:cdefd9d75b64 49 // Channels 4
Sissors 13:cdefd9d75b64 50 case PC_9:
Sissors 13:cdefd9d75b64 51 return &pwm->CCR4;
Sissors 13:cdefd9d75b64 52 }
Sissors 13:cdefd9d75b64 53 return NULL;
Sissors 13:cdefd9d75b64 54 }
Sissors 13:cdefd9d75b64 55 #endif
Sissors 13:cdefd9d75b64 56
jocis 15:49a7eff133b3 57 #if defined TARGET_NUCLEO_F401RE || defined TARGET_NUCLEO_F411RE
Sissors 13:cdefd9d75b64 58 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 13:cdefd9d75b64 59 switch (pin) {
jocis 16:ec208b5ec0bb 60 // Channels 1 : PWMx/1
Sissors 13:cdefd9d75b64 61 case PA_0: case PA_5: case PA_6: case PA_8: case PA_15: case PB_4: case PB_6: case PC_6: case PA_7: case PB_13:
Sissors 13:cdefd9d75b64 62 return &pwm->CCR1;
Sissors 13:cdefd9d75b64 63
jocis 16:ec208b5ec0bb 64 // Channels 2 : PWMx/2
Sissors 13:cdefd9d75b64 65 case PA_1: case PA_9: case PB_3: case PB_5: case PB_7: case PC_7: case PB_0: case PB_14:
Sissors 13:cdefd9d75b64 66 return &pwm->CCR2;
Sissors 13:cdefd9d75b64 67
jocis 16:ec208b5ec0bb 68 // Channels 3 : PWMx/3
Sissors 13:cdefd9d75b64 69 case PA_2: case PA_10: case PB_8: case PB_10: case PC_8: case PB_1: case PB_15:
Sissors 13:cdefd9d75b64 70 return &pwm->CCR3;
Sissors 13:cdefd9d75b64 71
jocis 16:ec208b5ec0bb 72 // Channels 4 : PWMx/4
Sissors 13:cdefd9d75b64 73 case PA_3: case PA_11: case PB_9: case PC_9:
Sissors 13:cdefd9d75b64 74 return &pwm->CCR4;
Sissors 13:cdefd9d75b64 75 }
Sissors 13:cdefd9d75b64 76 return NULL;
Sissors 13:cdefd9d75b64 77 }
jocis 16:ec208b5ec0bb 78 #endif
jocis 16:ec208b5ec0bb 79
Sissors 27:7f484dd7323d 80 #if defined (TARGET_NUCLEO_F103RB) || (TARGET_DISCO_F100RB)
Sissors 24:1f451660d8c0 81 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
jocis 16:ec208b5ec0bb 82 switch (pin) {
jocis 16:ec208b5ec0bb 83 // Channels 1 : PWMx/1
jocis 16:ec208b5ec0bb 84 case PA_6: case PA_8: case PA_15: case PB_4: case PC_6: case PB_13:
jocis 17:8378bc456f0d 85 return &pwm->CCR1;
jocis 16:ec208b5ec0bb 86
jocis 16:ec208b5ec0bb 87 // Channels 2 : PWMx/2
jocis 16:ec208b5ec0bb 88 case PA_1: case PA_7: case PA_9: case PB_3: case PB_5: case PC_7: case PB_14:
jocis 17:8378bc456f0d 89 return &pwm->CCR2;
jocis 16:ec208b5ec0bb 90
jocis 16:ec208b5ec0bb 91 // Channels 3 : PWMx/3
jocis 16:ec208b5ec0bb 92 case PA_2: case PA_10: case PB_0: case PB_10: case PC_8: case PB_15:
jocis 17:8378bc456f0d 93 return &pwm->CCR3;
jocis 16:ec208b5ec0bb 94
jocis 16:ec208b5ec0bb 95 // Channels 4 : PWMx/4
jocis 16:ec208b5ec0bb 96 case PA_3: case PA_11: case PB_1: case PB_11: case PC_9:
jocis 17:8378bc456f0d 97 return &pwm->CCR4;
jocis 16:ec208b5ec0bb 98 }
jocis 16:ec208b5ec0bb 99 return NULL;
jocis 16:ec208b5ec0bb 100 }
Sissors 19:ba7a5bf634b3 101 #endif
Sissors 19:ba7a5bf634b3 102
Sissors 19:ba7a5bf634b3 103 #ifdef TARGET_NUCLEO_F334R8
Sissors 19:ba7a5bf634b3 104 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 19:ba7a5bf634b3 105 switch (pin) {
Sissors 19:ba7a5bf634b3 106 // Channels 1
Sissors 19:ba7a5bf634b3 107 case PA_2: case PA_6: case PA_7: case PA_8: case PA_12: case PB_4: case PB_5: case PB_8: case PB_9: case PB_14: case PC_0: case PC_6:
Sissors 19:ba7a5bf634b3 108 case PA_1: case PA_13: case PB_6: case PB_13: case PC_13:
Sissors 19:ba7a5bf634b3 109 return &pwm->CCR1;
Sissors 19:ba7a5bf634b3 110
Sissors 19:ba7a5bf634b3 111 // Channels 2
Sissors 19:ba7a5bf634b3 112 case PA_3: case PA_4: case PA_9: case PB_15: case PC_1: case PC_7:
Sissors 19:ba7a5bf634b3 113 return &pwm->CCR2;
Sissors 19:ba7a5bf634b3 114
Sissors 19:ba7a5bf634b3 115 // Channels 3
Sissors 19:ba7a5bf634b3 116 case PA_10: case PB_0: case PC_2: case PC_8:
Sissors 19:ba7a5bf634b3 117 case PF_0:
Sissors 19:ba7a5bf634b3 118 return &pwm->CCR3;
Sissors 19:ba7a5bf634b3 119
Sissors 19:ba7a5bf634b3 120 // Channels 4
Sissors 19:ba7a5bf634b3 121 case PA_11: case PB_1: case PB_7: case PC_3: case PC_9:
Sissors 19:ba7a5bf634b3 122 return &pwm->CCR4;
Sissors 19:ba7a5bf634b3 123 }
Sissors 19:ba7a5bf634b3 124 return NULL;
Sissors 19:ba7a5bf634b3 125 }
altaran 20:3c609bc4ae9c 126 #endif
altaran 20:3c609bc4ae9c 127
altaran 20:3c609bc4ae9c 128 #if defined TARGET_NUCLEO_F072RB
altaran 20:3c609bc4ae9c 129 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
altaran 20:3c609bc4ae9c 130 switch (pin) {
altaran 20:3c609bc4ae9c 131 // Channels 1 : PWMx/1
altaran 20:3c609bc4ae9c 132 case PA_2: case PA_6: case PA_4: case PA_7: case PA_8: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6:
altaran 21:aa2884be5496 133 // Channels 1N : PWMx/1N
altaran 21:aa2884be5496 134 case PA_1: case PB_6: case PB_7: case PB_13:
altaran 20:3c609bc4ae9c 135 return &pwm->CCR1;
altaran 20:3c609bc4ae9c 136
altaran 20:3c609bc4ae9c 137 // Channels 2 : PWMx/2
altaran 20:3c609bc4ae9c 138 case PA_3: case PA_9: case PB_5: case PC_7: case PB_15:
altaran 20:3c609bc4ae9c 139 return &pwm->CCR2;
altaran 20:3c609bc4ae9c 140
altaran 20:3c609bc4ae9c 141 // Channels 3 : PWMx/3
altaran 20:3c609bc4ae9c 142 case PA_10: case PB_0: case PC_8:
altaran 20:3c609bc4ae9c 143 return &pwm->CCR3;
altaran 20:3c609bc4ae9c 144
altaran 20:3c609bc4ae9c 145 // Channels 4 : PWMx/4
altaran 20:3c609bc4ae9c 146 case PA_11: case PC_9:
altaran 20:3c609bc4ae9c 147 return &pwm->CCR4;
altaran 20:3c609bc4ae9c 148 }
altaran 20:3c609bc4ae9c 149 return NULL;
altaran 20:3c609bc4ae9c 150 }
Sissors 26:0c924507a81f 151 #endif
Sissors 26:0c924507a81f 152
Sissors 26:0c924507a81f 153 #ifdef TARGET_NUCLEO_F303K8
Sissors 26:0c924507a81f 154 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 26:0c924507a81f 155 switch (pin) {
Sissors 26:0c924507a81f 156 // Channels 1
Sissors 26:0c924507a81f 157 case PA_12: case PA_8: case PB_5: case PB_4: case PA_2: case PA_7: case PA_6:
Sissors 26:0c924507a81f 158 // Channels 1N
Sissors 26:0c924507a81f 159 case PB_7: case PB_6:
Sissors 26:0c924507a81f 160 return &pwm->CCR1;
Sissors 26:0c924507a81f 161
Sissors 26:0c924507a81f 162 // Channels 2
Sissors 26:0c924507a81f 163 case PA_9: case PA_4: case PA_3:
Sissors 26:0c924507a81f 164 // Channels 2N
Sissors 26:0c924507a81f 165 case PB_0:
Sissors 26:0c924507a81f 166 return &pwm->CCR2;
Sissors 26:0c924507a81f 167
Sissors 26:0c924507a81f 168 // Channels 3
Sissors 26:0c924507a81f 169 case PA_10:
Sissors 26:0c924507a81f 170 // Channels 3N
Sissors 26:0c924507a81f 171 case PB_1: case PF_0:
Sissors 26:0c924507a81f 172 return &pwm->CCR3;
Sissors 26:0c924507a81f 173
Sissors 26:0c924507a81f 174 // Channels 4
Sissors 26:0c924507a81f 175 case PA_11:
Sissors 26:0c924507a81f 176 // Channels 4N
Sissors 26:0c924507a81f 177
Sissors 26:0c924507a81f 178 return &pwm->CCR4;
Sissors 26:0c924507a81f 179 }
Sissors 26:0c924507a81f 180 return NULL;
Sissors 26:0c924507a81f 181 }
Sissors 26:0c924507a81f 182 #endif
Sissors 26:0c924507a81f 183
Sissors 26:0c924507a81f 184
Sissors 26:0c924507a81f 185 #ifdef TARGET_NUCLEO_F446RE
Sissors 26:0c924507a81f 186 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 26:0c924507a81f 187 switch (pin) {
Sissors 26:0c924507a81f 188 // Channels 1 : PWMx/1
Sissors 26:0c924507a81f 189 case PA_0: case PA_5: case PA_6: case PB_6: case PA_8: case PB_4:
Sissors 26:0c924507a81f 190 // Channels 1N
Sissors 26:0c924507a81f 191 case PA_7:
Sissors 26:0c924507a81f 192 return &pwm->CCR1;
Sissors 26:0c924507a81f 193
Sissors 26:0c924507a81f 194 // Channels 2 : PWMx/2
Sissors 26:0c924507a81f 195 case PA_1: case PC_7: case PA_9: case PB_5: case PB_3:
Sissors 26:0c924507a81f 196 // Channels 2N
Sissors 26:0c924507a81f 197 case PB_0:
Sissors 26:0c924507a81f 198 return &pwm->CCR2;
Sissors 26:0c924507a81f 199
Sissors 26:0c924507a81f 200 // Channels 3 : PWMx/3
Sissors 26:0c924507a81f 201 case PB_8: case PB_10: case PA_10: case PA_2:
Sissors 26:0c924507a81f 202 return &pwm->CCR3;
Sissors 26:0c924507a81f 203
Sissors 26:0c924507a81f 204 // Channels 4 : PWMx/4
Sissors 26:0c924507a81f 205 case PB_9: case PA_3:
Sissors 26:0c924507a81f 206 return &pwm->CCR4;
Sissors 26:0c924507a81f 207 }
Sissors 26:0c924507a81f 208 return NULL;
Sissors 26:0c924507a81f 209 }
Sissors 27:7f484dd7323d 210 #endif
Sissors 27:7f484dd7323d 211
Sissors 27:7f484dd7323d 212 #if defined (TARGET_NUCLEO_L152RE)
Sissors 27:7f484dd7323d 213 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 27:7f484dd7323d 214 switch (pin) {
Sissors 27:7f484dd7323d 215 // Channels 1 : PWMx/1
Sissors 27:7f484dd7323d 216 case PA_6: case PB_4: case PB_12: case PB_13: case PC_6:
Sissors 27:7f484dd7323d 217 return &pwm->CCR1;
Sissors 27:7f484dd7323d 218
Sissors 27:7f484dd7323d 219 // Channels 2 : PWMx/2
Sissors 27:7f484dd7323d 220 case PA_1: case PA_7: case PB_3: case PB_5: case PB_14: case PB_7: case PC_7:
Sissors 27:7f484dd7323d 221 return &pwm->CCR2;
Sissors 27:7f484dd7323d 222
Sissors 27:7f484dd7323d 223 // Channels 3 : PWMx/3
Sissors 27:7f484dd7323d 224 case PA_2: case PB_0: case PB_8: case PB_10: case PC_8:
Sissors 27:7f484dd7323d 225 return &pwm->CCR3;
Sissors 27:7f484dd7323d 226
Sissors 27:7f484dd7323d 227 // Channels 4 : PWMx/4
Sissors 27:7f484dd7323d 228 case PA_3: case PB_1:case PB_9: case PB_11: case PC_9:
Sissors 27:7f484dd7323d 229 return &pwm->CCR4;
Sissors 27:7f484dd7323d 230 default:
Sissors 27:7f484dd7323d 231 /* NOP */
Sissors 27:7f484dd7323d 232 break;
Sissors 27:7f484dd7323d 233 }
Sissors 27:7f484dd7323d 234 return NULL;
Sissors 27:7f484dd7323d 235 }
Sissors 27:7f484dd7323d 236 #endif
Sissors 27:7f484dd7323d 237
Sissors 27:7f484dd7323d 238 #ifdef TARGET_DISCO_F303VC
Sissors 27:7f484dd7323d 239 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 27:7f484dd7323d 240 switch (pin) {
Sissors 27:7f484dd7323d 241 // Channels 1
Sissors 27:7f484dd7323d 242 case PA_1: case PA_2: case PA_6: case PA_7: case PA_8: case PA_12: case PA_13:
Sissors 27:7f484dd7323d 243 case PB_3: case PB_4: case PB_5: case PB_6: case PB_7: case PB_8: case PB_9: case PB_13: case PB_14:
Sissors 27:7f484dd7323d 244 case PC_6: case PC_10:
Sissors 27:7f484dd7323d 245 case PD_12:
Sissors 27:7f484dd7323d 246 case PE_0:case PE_1:case PE_2:case PE_8:case PE_9:
Sissors 27:7f484dd7323d 247 return &pwm->CCR1;
Sissors 27:7f484dd7323d 248
Sissors 27:7f484dd7323d 249 // Channels 2
Sissors 27:7f484dd7323d 250 case PA_3: case PA_4: case PA_9: case PA_14:
Sissors 27:7f484dd7323d 251 case PB_0:case PB_15:
Sissors 27:7f484dd7323d 252 case PC_7:
Sissors 27:7f484dd7323d 253 case PD_13:
Sissors 27:7f484dd7323d 254 case PE_3: case PE_10: case PE_11:
Sissors 27:7f484dd7323d 255 return &pwm->CCR2;
Sissors 27:7f484dd7323d 256
Sissors 27:7f484dd7323d 257 // Channels 3
Sissors 27:7f484dd7323d 258 case PA_10:
Sissors 27:7f484dd7323d 259 case PB_1:
Sissors 27:7f484dd7323d 260 case PC_8: case PC_12:
Sissors 27:7f484dd7323d 261 case PD_14:
Sissors 27:7f484dd7323d 262 case PE_4: case PE_12: case PE_13:
Sissors 27:7f484dd7323d 263 case PF_0:
Sissors 27:7f484dd7323d 264 return &pwm->CCR3;
Sissors 27:7f484dd7323d 265
Sissors 27:7f484dd7323d 266 // Channels 4
Sissors 27:7f484dd7323d 267 case PA_11:
Sissors 27:7f484dd7323d 268 case PC_9: case PC_13:
Sissors 27:7f484dd7323d 269 case PD_1: case PD_15:
Sissors 27:7f484dd7323d 270 case PE_5: case PE_14:
Sissors 27:7f484dd7323d 271 return &pwm->CCR4;
Sissors 27:7f484dd7323d 272 default:
Sissors 27:7f484dd7323d 273 /* NOP */
Sissors 27:7f484dd7323d 274 break;
Sissors 27:7f484dd7323d 275 }
Sissors 27:7f484dd7323d 276 return NULL;
Sissors 27:7f484dd7323d 277 }
Sissors 27:7f484dd7323d 278 #endif
Sissors 27:7f484dd7323d 279
Sissors 27:7f484dd7323d 280 #if defined TARGET_DISCO_F407VG
Sissors 27:7f484dd7323d 281 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 27:7f484dd7323d 282 switch (pin) {
Sissors 27:7f484dd7323d 283 // Channels 1 : PWMx/1
Sissors 27:7f484dd7323d 284 case PA_0: case PA_5: case PA_6: case PA_7: case PA_8: case PA_15:
Sissors 27:7f484dd7323d 285 case PB_4: case PB_6: case PB_13:
Sissors 27:7f484dd7323d 286 case PC_6:
Sissors 27:7f484dd7323d 287 case PD_12:
Sissors 27:7f484dd7323d 288 case PE_5: case PE_8: case PE_9:
Sissors 27:7f484dd7323d 289 case PF_6: case PF_7: case PF_8: case PF_9:
Sissors 27:7f484dd7323d 290 case PH_13:
Sissors 27:7f484dd7323d 291 case PI_5:
Sissors 27:7f484dd7323d 292 return &pwm->CCR1;
Sissors 27:7f484dd7323d 293
Sissors 27:7f484dd7323d 294 // Channels 2 : PWMx/2
Sissors 27:7f484dd7323d 295 case PA_1: case PA_9:
Sissors 27:7f484dd7323d 296 case PB_0: case PB_3: case PB_5: case PB_7: case PB_14:
Sissors 27:7f484dd7323d 297 case PC_7:
Sissors 27:7f484dd7323d 298 case PD_13:
Sissors 27:7f484dd7323d 299 case PE_6: case PE_10: case PE_11:
Sissors 27:7f484dd7323d 300 case PH_14:
Sissors 27:7f484dd7323d 301 case PI_6:
Sissors 27:7f484dd7323d 302 return &pwm->CCR2;
Sissors 27:7f484dd7323d 303
Sissors 27:7f484dd7323d 304 // Channels 3 : PWMx/3
Sissors 27:7f484dd7323d 305 case PA_2: case PA_10:
Sissors 27:7f484dd7323d 306 case PB_1: case PB_8: case PB_10: case PB_15:
Sissors 27:7f484dd7323d 307 case PC_8:
Sissors 27:7f484dd7323d 308 case PD_14:
Sissors 27:7f484dd7323d 309 case PE_12: case PE_13:
Sissors 27:7f484dd7323d 310 case PH_15:
Sissors 27:7f484dd7323d 311 case PI_7:
Sissors 27:7f484dd7323d 312 return &pwm->CCR3;
Sissors 27:7f484dd7323d 313
Sissors 27:7f484dd7323d 314 // Channels 4 : PWMx/4
Sissors 27:7f484dd7323d 315 case PA_3: case PA_11:
Sissors 27:7f484dd7323d 316 case PB_9: case PB_11:
Sissors 27:7f484dd7323d 317 case PC_9:
Sissors 27:7f484dd7323d 318 case PD_15:
Sissors 27:7f484dd7323d 319 case PE_14:
Sissors 27:7f484dd7323d 320 case PI_2:
Sissors 27:7f484dd7323d 321 return &pwm->CCR4;
Sissors 27:7f484dd7323d 322 default:
Sissors 27:7f484dd7323d 323 /* NOP */
Sissors 27:7f484dd7323d 324 break;
Sissors 27:7f484dd7323d 325 }
Sissors 27:7f484dd7323d 326 return NULL;
Sissors 27:7f484dd7323d 327 }
Sissors 27:7f484dd7323d 328 #endif