minicube.net . / mbed-src-LPC1114FN28

Fork of mbed-src file paths change. LPC1114FN28 use only.

Fork of mbed-src by mbed official

Information

この情報は2013/10/28時点での解決方法です。
現在はmbed-src、標準ライブラリで問題なくコンパイルが可能です。

・使う物
LPC1114FN28
mbed SDK

LPC1114FN28でmbed-SDKのLibraryを使うとCompile出来ない。（2013/10/28） /media/uploads/minicube/mbed_lpc1114_sdk.png

パスが通ってないだけのようなのでファイルを以下に移動する。

mbed-src\targets\cmsis\TARGET_NXP\TARGET_LPC11XX_11CXX\
mbed-src\targets\cmsis\TARGET_NXP\TARGET_LPC11XX_11CXX\TARGET_LPC11XX\

にあるファイルをすべて

mbed-src\targets\cmsis\TARGET_NXP\

へ移動

mbed-src\targets\cmsis\TARGET_NXP\TARGET_LPC11XX_11CXX\にある

TOOLCHAIN_ARM_MICRO

をフォルダごと

mbed-src\targets\cmsis\TARGET_NXP\

へ移動

mbed-src\targets\hal\TARGET_NXP\TARGET_LPC11XX_11CXX\
mbed-src\targets\hal\TARGET_NXP\TARGET_LPC11XX_11CXX\TARGET_LPC11XX\

にあるファイルをすべて

mbed-src\targets\hal\TARGET_NXP\

へ移動

移動後は以下のような構成になると思います。
※不要なファイルは削除してあります。

/media/uploads/minicube/mbed_lpc1114_sdk_tree.png


ファイルの移動が面倒なので以下に本家からフォークしたライブラリを置いておきます。

Import librarymbed-src-LPC1114FN28

Fork of mbed-src file paths change. LPC1114FN28 use only.

Last commit 27 Oct 2013 by minicube.net .


エラーが出力される場合

"TOOLCHAIN_ARM_MICRO"が無いとエラーになる。

Error: Undefined symbol _initial_sp (referred from entry2.o).
Error: Undefined symbol _heap_base (referred from malloc.o).
Error: Undefined symbol _heap_limit (referred from malloc.o).

LPC1114FN28はMicrolibを使ってCompileされるため上記のエラーになるようです。

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h@15:4892fe388435, 2013-08-07 (annotated)

Committer:
bogdanm
Date:
Wed Aug 07 16:43:59 2013 +0300
Revision:
15:4892fe388435
Parent:
13:0645d8841f51 
Added LPC4088 target and interrupt chaining code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
emilmont 10:3bc89ef62ce7 5 * based on core_cm3.h, V1.20
emilmont 10:3bc89ef62ce7 6 */
emilmont 10:3bc89ef62ce7 7
emilmont 10:3bc89ef62ce7 8 #ifndef __ARM7_CORE_H__
emilmont 10:3bc89ef62ce7 9 #define __ARM7_CORE_H__
emilmont 10:3bc89ef62ce7 10
bogdanm 15:4892fe388435 11 #include "vector_defns.h"
bogdanm 15:4892fe388435 12
emilmont 10:3bc89ef62ce7 13 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 14 extern "C" {
emilmont 10:3bc89ef62ce7 15 #endif
emilmont 10:3bc89ef62ce7 16
emilmont 10:3bc89ef62ce7 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
emilmont 10:3bc89ef62ce7 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 10:3bc89ef62ce7 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 #define __CORTEX_M (0x03) /*!< Cortex core */
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 /**
emilmont 10:3bc89ef62ce7 24 * Lint configuration \n
emilmont 10:3bc89ef62ce7 25 * ----------------------- \n
emilmont 10:3bc89ef62ce7 26 *
emilmont 10:3bc89ef62ce7 27 * The following Lint messages will be suppressed and not shown: \n
emilmont 10:3bc89ef62ce7 28 * \n
emilmont 10:3bc89ef62ce7 29 * --- Error 10: --- \n
emilmont 10:3bc89ef62ce7 30 * register uint32_t __regBasePri __asm("basepri"); \n
emilmont 10:3bc89ef62ce7 31 * Error 10: Expecting ';' \n
emilmont 10:3bc89ef62ce7 32 * \n
emilmont 10:3bc89ef62ce7 33 * --- Error 530: --- \n
emilmont 10:3bc89ef62ce7 34 * return(__regBasePri); \n
emilmont 10:3bc89ef62ce7 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
emilmont 10:3bc89ef62ce7 36 * \n
emilmont 10:3bc89ef62ce7 37 * --- Error 550: --- \n
emilmont 10:3bc89ef62ce7 38 * __regBasePri = (basePri & 0x1ff); \n
emilmont 10:3bc89ef62ce7 39 * } \n
emilmont 10:3bc89ef62ce7 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
emilmont 10:3bc89ef62ce7 41 * \n
emilmont 10:3bc89ef62ce7 42 * --- Error 754: --- \n
emilmont 10:3bc89ef62ce7 43 * uint32_t RESERVED0[24]; \n
emilmont 10:3bc89ef62ce7 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 45 * \n
emilmont 10:3bc89ef62ce7 46 * --- Error 750: --- \n
emilmont 10:3bc89ef62ce7 47 * #define __CM3_CORE_H__ \n
emilmont 10:3bc89ef62ce7 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 49 * \n
emilmont 10:3bc89ef62ce7 50 * --- Error 528: --- \n
emilmont 10:3bc89ef62ce7 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
emilmont 10:3bc89ef62ce7 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 53 * \n
emilmont 10:3bc89ef62ce7 54 * --- Error 751: --- \n
emilmont 10:3bc89ef62ce7 55 * } InterruptType_Type; \n
emilmont 10:3bc89ef62ce7 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 57 * \n
emilmont 10:3bc89ef62ce7 58 * \n
emilmont 10:3bc89ef62ce7 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
emilmont 10:3bc89ef62ce7 60 *
emilmont 10:3bc89ef62ce7 61 */
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63 /*lint -save */
emilmont 10:3bc89ef62ce7 64 /*lint -e10 */
emilmont 10:3bc89ef62ce7 65 /*lint -e530 */
emilmont 10:3bc89ef62ce7 66 /*lint -e550 */
emilmont 10:3bc89ef62ce7 67 /*lint -e754 */
emilmont 10:3bc89ef62ce7 68 /*lint -e750 */
emilmont 10:3bc89ef62ce7 69 /*lint -e528 */
emilmont 10:3bc89ef62ce7 70 /*lint -e751 */
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 #include <stdint.h> /* Include standard types */
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 75 /**
emilmont 10:3bc89ef62ce7 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
emilmont 10:3bc89ef62ce7 77 *
emilmont 10:3bc89ef62ce7 78 * @param none
emilmont 10:3bc89ef62ce7 79 * @return uint32_t Main Stack Pointer
emilmont 10:3bc89ef62ce7 80 *
emilmont 10:3bc89ef62ce7 81 * Return the current value of the MSP (main stack pointer)
emilmont 10:3bc89ef62ce7 82 * Cortex processor register
emilmont 10:3bc89ef62ce7 83 */
emilmont 10:3bc89ef62ce7 84 extern uint32_t __get_MSP(void);
emilmont 10:3bc89ef62ce7 85 #endif
emilmont 10:3bc89ef62ce7 86
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88 #if defined (__ICCARM__)
emilmont 10:3bc89ef62ce7 89 #include <intrinsics.h> /* IAR Intrinsics */
emilmont 10:3bc89ef62ce7 90 #endif
emilmont 10:3bc89ef62ce7 91
emilmont 10:3bc89ef62ce7 92
emilmont 10:3bc89ef62ce7 93 #ifndef __NVIC_PRIO_BITS
emilmont 10:3bc89ef62ce7 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
emilmont 10:3bc89ef62ce7 95 #endif
emilmont 10:3bc89ef62ce7 96
emilmont 10:3bc89ef62ce7 97 typedef struct
emilmont 10:3bc89ef62ce7 98 {
emilmont 10:3bc89ef62ce7 99 uint32_t IRQStatus;
emilmont 10:3bc89ef62ce7 100 uint32_t FIQStatus;
emilmont 10:3bc89ef62ce7 101 uint32_t RawIntr;
emilmont 10:3bc89ef62ce7 102 uint32_t IntSelect;
emilmont 10:3bc89ef62ce7 103 uint32_t IntEnable;
emilmont 10:3bc89ef62ce7 104 uint32_t IntEnClr;
emilmont 10:3bc89ef62ce7 105 uint32_t SoftInt;
emilmont 10:3bc89ef62ce7 106 uint32_t SoftIntClr;
emilmont 10:3bc89ef62ce7 107 uint32_t Protection;
emilmont 10:3bc89ef62ce7 108 uint32_t SWPriorityMask;
emilmont 10:3bc89ef62ce7 109 uint32_t RESERVED0[54];
emilmont 10:3bc89ef62ce7 110 uint32_t VectAddr[32];
emilmont 10:3bc89ef62ce7 111 uint32_t RESERVED1[32];
emilmont 10:3bc89ef62ce7 112 uint32_t VectPriority[32];
emilmont 10:3bc89ef62ce7 113 uint32_t RESERVED2[800];
emilmont 10:3bc89ef62ce7 114 uint32_t Address;
emilmont 10:3bc89ef62ce7 115 } NVIC_TypeDef;
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 #define NVIC_BASE (0xFFFFF000)
emilmont 10:3bc89ef62ce7 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 /**
emilmont 10:3bc89ef62ce7 123 * IO definitions
emilmont 10:3bc89ef62ce7 124 *
emilmont 10:3bc89ef62ce7 125 * define access restrictions to peripheral registers
emilmont 10:3bc89ef62ce7 126 */
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 129 #define __I volatile /*!< defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 130 #else
emilmont 10:3bc89ef62ce7 131 #define __I volatile const /*!< defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 132 #endif
emilmont 10:3bc89ef62ce7 133 #define __O volatile /*!< defines 'write only' permissions */
emilmont 10:3bc89ef62ce7 134 #define __IO volatile /*!< defines 'read / write' permissions */
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139
emilmont 10:3bc89ef62ce7 140 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 143
emilmont 10:3bc89ef62ce7 144 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 10:3bc89ef62ce7 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
emilmont 10:3bc89ef62ce7 147
emilmont 10:3bc89ef62ce7 148 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 155
emilmont 10:3bc89ef62ce7 156 #endif
emilmont 10:3bc89ef62ce7 157
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159 /* ################### Compiler specific Intrinsics ########################### */
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 10:3bc89ef62ce7 162 /* ARM armcc specific functions */
emilmont 10:3bc89ef62ce7 163
emilmont 10:3bc89ef62ce7 164 #define __enable_fault_irq __enable_fiq
emilmont 10:3bc89ef62ce7 165 #define __disable_fault_irq __disable_fiq
emilmont 10:3bc89ef62ce7 166
emilmont 10:3bc89ef62ce7 167 #define __NOP __nop
emilmont 10:3bc89ef62ce7 168 //#define __WFI __wfi
emilmont 10:3bc89ef62ce7 169 //#define __WFE __wfe
emilmont 10:3bc89ef62ce7 170 //#define __SEV __sev
emilmont 10:3bc89ef62ce7 171 //#define __ISB() __isb(0)
emilmont 10:3bc89ef62ce7 172 //#define __DSB() __dsb(0)
emilmont 10:3bc89ef62ce7 173 //#define __DMB() __dmb(0)
emilmont 10:3bc89ef62ce7 174 //#define __REV __rev
emilmont 10:3bc89ef62ce7 175 //#define __RBIT __rbit
emilmont 10:3bc89ef62ce7 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 179 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 180 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 181 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 182
emilmont 10:3bc89ef62ce7 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
emilmont 10:3bc89ef62ce7 184 LPC_VIC->IntEnClr = 0xffffffff
emilmont 10:3bc89ef62ce7 185
emilmont 10:3bc89ef62ce7 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
emilmont 10:3bc89ef62ce7 187
emilmont 10:3bc89ef62ce7 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
emilmont 10:3bc89ef62ce7 189
emilmont 10:3bc89ef62ce7 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
emilmont 10:3bc89ef62ce7 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
emilmont 10:3bc89ef62ce7 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
emilmont 10:3bc89ef62ce7 193
emilmont 10:3bc89ef62ce7 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 195
emilmont 10:3bc89ef62ce7 196 static __INLINE void __enable_irq() {
emilmont 10:3bc89ef62ce7 197 unsigned long temp;
emilmont 10:3bc89ef62ce7 198 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 10:3bc89ef62ce7 199 "bic %0, %0, #0x80\n"
emilmont 10:3bc89ef62ce7 200 "msr cpsr_c, %0"
emilmont 10:3bc89ef62ce7 201 : "=r" (temp)
emilmont 10:3bc89ef62ce7 202 :
emilmont 10:3bc89ef62ce7 203 : "memory");
emilmont 10:3bc89ef62ce7 204 }
emilmont 10:3bc89ef62ce7 205
emilmont 10:3bc89ef62ce7 206 static __INLINE void __disable_irq() {
emilmont 10:3bc89ef62ce7 207 unsigned long old,temp;
emilmont 10:3bc89ef62ce7 208 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 10:3bc89ef62ce7 209 "orr %1, %0, #0xc0\n"
emilmont 10:3bc89ef62ce7 210 "msr cpsr_c, %1"
emilmont 10:3bc89ef62ce7 211 : "=r" (old), "=r" (temp)
emilmont 10:3bc89ef62ce7 212 :
emilmont 10:3bc89ef62ce7 213 : "memory");
emilmont 10:3bc89ef62ce7 214 // return (old & 0x80) == 0;
emilmont 10:3bc89ef62ce7 215 }
emilmont 10:3bc89ef62ce7 216
emilmont 10:3bc89ef62ce7 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
emilmont 10:3bc89ef62ce7 218
emilmont 10:3bc89ef62ce7 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 220 /* TASKING carm specific functions */
emilmont 10:3bc89ef62ce7 221
emilmont 10:3bc89ef62ce7 222 /*
emilmont 10:3bc89ef62ce7 223 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 10:3bc89ef62ce7 224 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 10:3bc89ef62ce7 225 * Including the CMSIS ones.
emilmont 10:3bc89ef62ce7 226 */
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228 #endif
emilmont 10:3bc89ef62ce7 229
emilmont 10:3bc89ef62ce7 230
emilmont 10:3bc89ef62ce7 231 /**
emilmont 10:3bc89ef62ce7 232 * @brief Enable Interrupt in NVIC Interrupt Controller
emilmont 10:3bc89ef62ce7 233 *
emilmont 10:3bc89ef62ce7 234 * @param IRQn_Type IRQn specifies the interrupt number
emilmont 10:3bc89ef62ce7 235 * @return none
emilmont 10:3bc89ef62ce7 236 *
emilmont 10:3bc89ef62ce7 237 * Enable a device specific interupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 238 * The interrupt number cannot be a negative value.
emilmont 10:3bc89ef62ce7 239 */
emilmont 10:3bc89ef62ce7 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 241 {
emilmont 10:3bc89ef62ce7 242 NVIC->IntEnable = 1 << (uint32_t)IRQn;
emilmont 10:3bc89ef62ce7 243 }
emilmont 10:3bc89ef62ce7 244
emilmont 10:3bc89ef62ce7 245
emilmont 10:3bc89ef62ce7 246 /**
emilmont 10:3bc89ef62ce7 247 * @brief Disable the interrupt line for external interrupt specified
emilmont 10:3bc89ef62ce7 248 *
emilmont 10:3bc89ef62ce7 249 * @param IRQn_Type IRQn is the positive number of the external interrupt
emilmont 10:3bc89ef62ce7 250 * @return none
emilmont 10:3bc89ef62ce7 251 *
emilmont 10:3bc89ef62ce7 252 * Disable a device specific interupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 253 * The interrupt number cannot be a negative value.
emilmont 10:3bc89ef62ce7 254 */
emilmont 10:3bc89ef62ce7 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 256 {
emilmont 10:3bc89ef62ce7 257 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
emilmont 10:3bc89ef62ce7 258 }
emilmont 10:3bc89ef62ce7 259
bogdanm 15:4892fe388435 260 static __INLINE uint32_t __get_IPSR(void)
bogdanm 15:4892fe388435 261 {
bogdanm 15:4892fe388435 262 unsigned i;
bogdanm 15:4892fe388435 263
bogdanm 15:4892fe388435 264 for(i = 0; i < 32; i ++)
bogdanm 15:4892fe388435 265 if(NVIC->Address == NVIC->VectAddr[i])
bogdanm 15:4892fe388435 266 return i;
bogdanm 15:4892fe388435 267 return 1; // 1 is an invalid entry in the interrupt table on LPC2368
bogdanm 15:4892fe388435 268 }
emilmont 10:3bc89ef62ce7 269
emilmont 10:3bc89ef62ce7 270 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 271 }
emilmont 10:3bc89ef62ce7 272 #endif
emilmont 10:3bc89ef62ce7 273
emilmont 10:3bc89ef62ce7 274 #endif /* __ARM7_CORE_H__ */
emilmont 10:3bc89ef62ce7 275
emilmont 10:3bc89ef62ce7 276 /*lint -restore */