spi_dma_stm32f4.c

00001 #if defined(TARGET_STM32F4) || defined(TARGET_STM32L4)
00002 /* Mainly aim at 
00003     NUCLEO-F401RE 
00004     NUCLEO-F411RE 
00005     NUCLEO-F410RB 
00006     NUCLEO-F446RE 
00007 */
00008 
00009 /*
00010 
00011 This file is licensed under Apache 2.0 license.
00012 (C) 2016 dinau
00013 
00014 */
00015 #include "spi_dma.h"
00016 
00017 /* For SPI1 */
00018 #define SPI1_DMAx_CLK_ENABLE()    __DMA2_CLK_ENABLE()    
00019 #define SPI1_DMAx_TX_STREAM       DMA2_Stream3
00020 #define SPI1_DMAx_RX_STREAM       DMA2_Stream2
00021 #define SPI1_DMAx_TX_CHANNEL      DMA_CHANNEL_3
00022 #define SPI1_DMAx_RX_CHANNEL      DMA_CHANNEL_3
00023 #define SPI1_DMAx_TX_IRQn         DMA2_Stream3_IRQn    
00024 #define SPI1_DMAx_RX_IRQn         DMA2_Stream2_IRQn    
00025 #define SPI1_DMAx_TX_IRQHandler   DMA2_Stream3_IRQHandler
00026 #define SPI1_DMAx_RX_IRQHandler   DMA2_Stream2_IRQHandler
00027 /* For SPI3 */
00028 #define SPI3_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
00029 #define SPI3_DMAx_TX_STREAM        DMA1_Stream5
00030 #define SPI3_DMAx_RX_STREAM        DMA1_Stream2
00031 #define SPI3_DMAx_TX_CHANNEL       DMA_CHANNEL_0
00032 #define SPI3_DMAx_RX_CHANNEL       DMA_CHANNEL_0
00033 #define SPI3_DMAx_TX_IRQn          DMA1_Stream5_IRQn    
00034 #define SPI3_DMAx_RX_IRQn          DMA1_Stream2_IRQn    
00035 #define SPI3_DMAx_TX_IRQHandler    DMA1_Stream5_IRQHandler
00036 #define SPI3_DMAx_RX_IRQHandler    DMA1_Stream2_IRQHandler
00037 
00038 #define readReg( reg, mask)  (  (reg) & (mask)  )    
00039 
00040 void spi_dma_get_info( SPI_TypeDef *spi )
00041 {
00042     SpiHandle.Instance               = spi;
00043     SpiHandle.Init.Mode              = readReg(spi->CR1, SPI_MODE_MASTER); 
00044     SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
00045     SpiHandle.Init.Direction         = readReg(spi->CR1, SPI_CR1_BIDIMODE); 
00046     SpiHandle.Init.CLKPhase          = readReg(spi->CR1, SPI_CR1_CPHA);
00047     SpiHandle.Init.CLKPolarity       = readReg(spi->CR1, SPI_CR1_CPOL);
00048     SpiHandle.Init.CRCCalculation    = readReg(spi->CR1, SPI_CR1_CRCEN);
00049     SpiHandle.Init.CRCPolynomial     = spi->CRCPR & 0xFFFF;
00050     SpiHandle.Init.DataSize          = readReg(spi->CR1, SPI_CR1_DFF);
00051     SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
00052     SpiHandle.Init.NSS               = readReg(spi->CR1, SPI_CR1_SSM);
00053     SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
00054     SpiHandle.State                  = HAL_SPI_STATE_READY;
00055 }
00056 
00057 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
00058 {
00059     static uint8_t dma_handle_inited = 0;
00060     /* Peripheral DMA init*/
00061     /* TX: */
00062     if( !dma_handle_inited ){
00063         if( spi == SPI1 ){
00064             hdma_spi_tx.Instance             = SPI1_DMAx_TX_STREAM;
00065             hdma_spi_tx.Init.Channel         = SPI1_DMAx_TX_CHANNEL; 
00066         } else if( spi == SPI3 ) {
00067             hdma_spi_tx.Instance             = SPI3_DMAx_TX_STREAM;
00068             hdma_spi_tx.Init.Channel         = SPI3_DMAx_TX_CHANNEL; 
00069         }
00070         hdma_spi_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
00071         hdma_spi_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
00072         hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
00073         hdma_spi_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
00074         hdma_spi_tx.Init.Mode                = DMA_NORMAL;
00075         hdma_spi_tx.Init.Priority            = DMA_PRIORITY_HIGH;
00076         /**/
00077         hdma_spi_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
00078         hdma_spi_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00079         hdma_spi_tx.Init.MemBurst            = DMA_MBURST_SINGLE;
00080         hdma_spi_tx.Init.PeriphBurst         = DMA_PBURST_SINGLE;
00081         /**/
00082     }
00083     hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
00084     HAL_DMA_Init(&hdma_spi_tx);
00085     __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
00086 
00087     /* RX: */
00088     if( !dma_handle_inited ){        
00089         if( spi == SPI1 ){
00090             hdma_spi_rx.Instance             = SPI1_DMAx_RX_STREAM;
00091             hdma_spi_rx.Init.Channel         = SPI1_DMAx_RX_CHANNEL; 
00092         } else if( spi == SPI3 ) {
00093             hdma_spi_rx.Instance             = SPI3_DMAx_RX_STREAM;
00094             hdma_spi_rx.Init.Channel         = SPI3_DMAx_RX_CHANNEL; 
00095         }
00096         hdma_spi_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
00097         hdma_spi_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
00098         hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
00099         hdma_spi_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
00100         hdma_spi_rx.Init.Mode                = DMA_NORMAL;
00101         hdma_spi_rx.Init.Priority            = DMA_PRIORITY_LOW;
00102         /**/
00103         hdma_spi_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
00104         hdma_spi_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00105         hdma_spi_rx.Init.MemBurst            = DMA_MBURST_SINGLE;
00106         hdma_spi_rx.Init.PeriphBurst         = DMA_PBURST_SINGLE; 
00107         /**/
00108     }
00109     hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
00110     HAL_DMA_Init(&hdma_spi_rx);
00111     __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
00112 
00113     dma_handle_inited = 1;
00114 }
00115 
00116 void spi_dma_irq_setup( SPI_TypeDef *spi) 
00117 {
00118     /* DMA controller clock enable */
00119     if( spi == SPI1 ){
00120         SPI1_DMAx_CLK_ENABLE();
00121         /* DMA interrupt init */
00122         HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 0, 1);
00123         HAL_NVIC_EnableIRQ(  SPI1_DMAx_TX_IRQn);
00124         HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 0, 0);
00125         HAL_NVIC_EnableIRQ(  SPI1_DMAx_RX_IRQn);
00126     } else if( spi == SPI3 ){
00127         SPI3_DMAx_CLK_ENABLE();
00128         /* DMA interrupt init */
00129         HAL_NVIC_SetPriority(SPI3_DMAx_TX_IRQn, 0, 1);
00130         HAL_NVIC_EnableIRQ(  SPI3_DMAx_TX_IRQn);
00131         HAL_NVIC_SetPriority(SPI3_DMAx_RX_IRQn, 0, 0);
00132         HAL_NVIC_EnableIRQ(  SPI3_DMAx_RX_IRQn);
00133     }
00134 }
00135 
00136 /* For SPI1 */
00137 void SPI1_DMAx_TX_IRQHandler(void)
00138 {
00139   HAL_DMA_IRQHandler(&hdma_spi_tx);
00140 }
00141 
00142 void SPI1_DMAx_RX_IRQHandler(void)
00143 {
00144   HAL_DMA_IRQHandler(&hdma_spi_rx);
00145 }
00146 
00147 /* For SPI3 */
00148 void SPI3_DMAx_TX_IRQHandler(void)
00149 {
00150   HAL_DMA_IRQHandler(&hdma_spi_tx);
00151 }
00152 
00153 void SPI3_DMAx_RX_IRQHandler(void)
00154 {
00155   HAL_DMA_IRQHandler(&hdma_spi_rx);
00156 }
00157 
00158 
00159 #endif /* TARGET_STM32F4 */
00160