spi_dma_stm32f3.c

00001 #if defined(TARGET_STM32F3)
00002 
00003 /*
00004 
00005 This file is licensed under Apache 2.0 license.
00006 (C) 2016 dinau
00007 
00008 */
00009 #include "spi_dma.h"
00010 
00011 /* For SPI1 */
00012 #if defined(SPI1_BASE)
00013 #define SPI1_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
00014 #define SPI1_DMAx_TX_CHANNEL       DMA1_Channel3
00015 #define SPI1_DMAx_RX_CHANNEL       DMA1_Channel2
00016 #define SPI1_DMAx_TX_IRQn          DMA1_Channel3_IRQn    
00017 #define SPI1_DMAx_RX_IRQn          DMA1_Channel2_IRQn    
00018 #define SPI1_DMAx_TX_IRQHandler    DMA1_Channel3_IRQHandler
00019 #define SPI1_DMAx_RX_IRQHandler    DMA1_Channel2_IRQHandler
00020 #endif
00021 
00022 /* For SPI2 */
00023 #if defined(SPI2_BASE)
00024 #define SPI2_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
00025 #define SPI2_DMAx_TX_CHANNEL       DMA1_Channel5
00026 #define SPI2_DMAx_RX_CHANNEL       DMA1_Channel4
00027 #define SPI2_DMAx_TX_IRQn          DMA1_Channel5_IRQn    
00028 #define SPI2_DMAx_RX_IRQn          DMA1_Channel4_IRQn    
00029 #define SPI2_DMAx_TX_IRQHandler    DMA1_Channel5_IRQHandler
00030 #define SPI2_DMAx_RX_IRQHandler    DMA1_Channel4_IRQHandler
00031 #endif
00032 
00033 /* For SPI3 */
00034 #if defined(SPI3_BASE)
00035 #if defined(TARGET_STM32F302R8)
00036 #define SPI3_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
00037 #define SPI3_DMAx_TX_CHANNEL       DMA1_Channel3
00038 #define SPI3_DMAx_RX_CHANNEL       DMA1_Channel2
00039 #define SPI3_DMAx_TX_IRQn          DMA1_Channel3_IRQn    
00040 #define SPI3_DMAx_RX_IRQn          DMA1_Channel2_IRQn    
00041 #define SPI3_DMAx_TX_IRQHandler    DMA1_Channel3_IRQHandler
00042 #define SPI3_DMAx_RX_IRQHandler    DMA1_Channel2_IRQHandler
00043 #else
00044 #define SPI3_DMAx_CLK_ENABLE()     __DMA2_CLK_ENABLE()    
00045 #define SPI3_DMAx_TX_CHANNEL       DMA2_Channel2
00046 #define SPI3_DMAx_RX_CHANNEL       DMA2_Channel1
00047 #define SPI3_DMAx_TX_IRQn          DMA2_Channel2_IRQn    
00048 #define SPI3_DMAx_RX_IRQn          DMA2_Channel1_IRQn    
00049 #define SPI3_DMAx_TX_IRQHandler    DMA2_Channel2_IRQHandler
00050 #define SPI3_DMAx_RX_IRQHandler    DMA2_Channel1_IRQHandler
00051 #endif
00052 #endif
00053 
00054 #define readReg( reg, mask)  (  (reg) & (mask)  )    
00055 
00056 
00057 void spi_dma_get_info( SPI_TypeDef *spi )
00058 {
00059     SpiHandle.Instance               = spi;
00060     SpiHandle.Init.Mode              = readReg(spi->CR1, SPI_MODE_MASTER); 
00061     SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
00062     SpiHandle.Init.Direction         = readReg(spi->CR1, SPI_CR1_BIDIMODE); 
00063     SpiHandle.Init.CLKPhase          = readReg(spi->CR1, SPI_CR1_CPHA);
00064     SpiHandle.Init.CLKPolarity       = readReg(spi->CR1, SPI_CR1_CPOL);
00065     SpiHandle.Init.CRCCalculation    = readReg(spi->CR1, SPI_CR1_CRCEN);
00066     SpiHandle.Init.CRCPolynomial     = spi->CRCPR & 0xFFFF;
00067     SpiHandle.Init.DataSize          = readReg(spi->CR1, SPI_CR2_DS);
00068     SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
00069     SpiHandle.Init.NSS               = readReg(spi->CR1, SPI_CR1_SSM);
00070     SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
00071     SpiHandle.State                  = HAL_SPI_STATE_READY;
00072 }
00073 
00074 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
00075 {
00076     static uint8_t dma_handle_inited = 0;
00077     /* Peripheral DMA init*/
00078     /* TX: */
00079     if( !dma_handle_inited ){
00080 #if defined(SPI1_BASE)
00081         if( spi == SPI1 ){
00082             hdma_spi_tx.Instance             = SPI1_DMAx_TX_CHANNEL;
00083         } 
00084 #endif
00085 #if defined(SPI2_BASE)
00086         if( spi == SPI2 ){                           
00087             hdma_spi_tx.Instance             = SPI2_DMAx_TX_CHANNEL;
00088         } 
00089 #endif
00090 #if defined(SPI3_BASE)
00091         if( spi == SPI3 ){                           
00092             hdma_spi_tx.Instance             = SPI3_DMAx_TX_CHANNEL;
00093         }
00094 #endif
00095         hdma_spi_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
00096         hdma_spi_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
00097         hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
00098         hdma_spi_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
00099         hdma_spi_tx.Init.Mode                = DMA_NORMAL;
00100         hdma_spi_tx.Init.Priority            = DMA_PRIORITY_LOW;
00101     }
00102     hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
00103     HAL_DMA_Init(&hdma_spi_tx);
00104     __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
00105     /* RX: */
00106     if( !dma_handle_inited ){
00107 #if defined(SPI1_BASE)
00108         if( spi == SPI1 ){
00109             hdma_spi_rx.Instance             = SPI1_DMAx_RX_CHANNEL;
00110         } 
00111 #endif
00112 #if defined(SPI2_BASE)
00113         if( spi == SPI2 ){                           
00114             hdma_spi_rx.Instance             = SPI2_DMAx_RX_CHANNEL;
00115         } 
00116 #endif
00117 #if defined(SPI3_BASE)
00118         if( spi == SPI3 ){                           
00119             hdma_spi_rx.Instance             = SPI3_DMAx_RX_CHANNEL;
00120         }
00121 #endif
00122         hdma_spi_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
00123         hdma_spi_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
00124         hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
00125         hdma_spi_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
00126         hdma_spi_rx.Init.Mode                = DMA_NORMAL;
00127         hdma_spi_rx.Init.Priority            = DMA_PRIORITY_HIGH;
00128     } 
00129     hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
00130     HAL_DMA_Init(&hdma_spi_rx);
00131     __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
00132 }
00133 
00134 void spi_dma_irq_setup( SPI_TypeDef *spi) 
00135 {
00136     /* DMA controller clock enable */
00137 #if defined(SPI1_BASE)
00138     if(  spi == SPI1 ){
00139         SPI1_DMAx_CLK_ENABLE();
00140         HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 3, 0);
00141         HAL_NVIC_EnableIRQ(  SPI1_DMAx_TX_IRQn);
00142         HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 2, 0);
00143         HAL_NVIC_EnableIRQ(  SPI1_DMAx_RX_IRQn);
00144     } 
00145 #endif
00146 #if defined(SPI2_BASE)
00147     if( spi == SPI2 ){
00148         SPI2_DMAx_CLK_ENABLE();
00149         HAL_NVIC_SetPriority(SPI2_DMAx_TX_IRQn, 3, 0);
00150         HAL_NVIC_EnableIRQ(  SPI2_DMAx_TX_IRQn);
00151         HAL_NVIC_SetPriority(SPI2_DMAx_RX_IRQn, 2, 0);
00152         HAL_NVIC_EnableIRQ(  SPI2_DMAx_RX_IRQn);
00153     }
00154 #endif
00155 #if defined(SPI3_BASE)
00156     if( spi == SPI3 ){
00157         SPI3_DMAx_CLK_ENABLE();
00158         HAL_NVIC_SetPriority(SPI3_DMAx_TX_IRQn, 3, 0);
00159         HAL_NVIC_EnableIRQ(  SPI3_DMAx_TX_IRQn);
00160         HAL_NVIC_SetPriority(SPI3_DMAx_RX_IRQn, 2, 0);
00161         HAL_NVIC_EnableIRQ(  SPI3_DMAx_RX_IRQn);
00162     }
00163 #endif
00164     /* DMA interrupt init */
00165 }
00166 
00167 /* SPI1 */
00168 #if defined(SPI1_BASE)
00169 void SPI1_DMAx_TX_IRQHandler(void)
00170 {
00171   HAL_DMA_IRQHandler(&hdma_spi_tx);
00172 }
00173 void SPI1_DMAx_RX_IRQHandler(void)
00174 {
00175   HAL_DMA_IRQHandler(&hdma_spi_rx);
00176 }
00177 #endif
00178 
00179 #if defined(SPI2_BASE)
00180 /* SPI2 */
00181 void SPI2_DMAx_TX_IRQHandler(void)
00182 {
00183   HAL_DMA_IRQHandler(&hdma_spi_tx);
00184 }
00185 void SPI2_DMAx_RX_IRQHandler(void)
00186 {
00187   HAL_DMA_IRQHandler(&hdma_spi_rx);
00188 }
00189 #endif
00190 
00191 /* SPI3 */
00192 #if defined(SPI3_BASE)
00193 void SPI3_DMAx_TX_IRQHandler(void)
00194 {
00195   HAL_DMA_IRQHandler(&hdma_spi_tx);
00196 }
00197 void SPI3_DMAx_RX_IRQHandler(void)
00198 {
00199   HAL_DMA_IRQHandler(&hdma_spi_rx);
00200 }
00201 #endif
00202 
00203 #endif /* TARGET_STM32F3 */
00204