mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

Diff: spi_dma/spi_dma_stm32f3.c

Revision:
33:73237494298b
Parent:
24:92bf692d61e2
--- a/spi_dma/spi_dma_stm32f3.c	Sat Aug 27 14:03:45 2016 +0900
+++ b/spi_dma/spi_dma_stm32f3.c	Mon Aug 29 18:43:57 2016 +0900
@@ -1,6 +1,4 @@
-#if    defined(TARGET_NUCLEO_F302R8) \
-	|| defined(TARGET_NUCLEO_F303RE) \
-    || defined( TARGET_DISCO_F303VC)
+#if defined(TARGET_STM32F3)
 
 /*
 
@@ -11,6 +9,7 @@
 #include "spi_dma.h"
 
 /* For SPI1 */
+#if defined(SPI1_BASE)
 #define SPI1_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
 #define SPI1_DMAx_TX_CHANNEL       DMA1_Channel3
 #define SPI1_DMAx_RX_CHANNEL       DMA1_Channel2
@@ -18,7 +17,10 @@
 #define SPI1_DMAx_RX_IRQn          DMA1_Channel2_IRQn    
 #define SPI1_DMAx_TX_IRQHandler    DMA1_Channel3_IRQHandler
 #define SPI1_DMAx_RX_IRQHandler    DMA1_Channel2_IRQHandler
+#endif
+
 /* For SPI2 */
+#if defined(SPI2_BASE)
 #define SPI2_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
 #define SPI2_DMAx_TX_CHANNEL       DMA1_Channel5
 #define SPI2_DMAx_RX_CHANNEL       DMA1_Channel4
@@ -26,7 +28,19 @@
 #define SPI2_DMAx_RX_IRQn          DMA1_Channel4_IRQn    
 #define SPI2_DMAx_TX_IRQHandler    DMA1_Channel5_IRQHandler
 #define SPI2_DMAx_RX_IRQHandler    DMA1_Channel4_IRQHandler
+#endif
+
 /* For SPI3 */
+#if defined(SPI3_BASE)
+#if defined(TARGET_STM32F302R8)
+#define SPI3_DMAx_CLK_ENABLE()     __DMA1_CLK_ENABLE()    
+#define SPI3_DMAx_TX_CHANNEL       DMA1_Channel3
+#define SPI3_DMAx_RX_CHANNEL       DMA1_Channel2
+#define SPI3_DMAx_TX_IRQn          DMA1_Channel3_IRQn    
+#define SPI3_DMAx_RX_IRQn          DMA1_Channel2_IRQn    
+#define SPI3_DMAx_TX_IRQHandler    DMA1_Channel3_IRQHandler
+#define SPI3_DMAx_RX_IRQHandler    DMA1_Channel2_IRQHandler
+#else
 #define SPI3_DMAx_CLK_ENABLE()     __DMA2_CLK_ENABLE()    
 #define SPI3_DMAx_TX_CHANNEL       DMA2_Channel2
 #define SPI3_DMAx_RX_CHANNEL       DMA2_Channel1
@@ -34,6 +48,8 @@
 #define SPI3_DMAx_RX_IRQn          DMA2_Channel1_IRQn    
 #define SPI3_DMAx_TX_IRQHandler    DMA2_Channel2_IRQHandler
 #define SPI3_DMAx_RX_IRQHandler    DMA2_Channel1_IRQHandler
+#endif
+#endif
 
 #define readReg( reg, mask)  (  (reg) & (mask)  )    
 
@@ -61,13 +77,21 @@
     /* Peripheral DMA init*/
 	/* TX: */
     if( !dma_handle_inited ){
+#if defined(SPI1_BASE)
 		if( spi == SPI1 ){
 			hdma_spi_tx.Instance             = SPI1_DMAx_TX_CHANNEL;
-		} else if( spi == SPI2 ){                           
+		} 
+#endif
+#if defined(SPI2_BASE)
+        if( spi == SPI2 ){                           
 			hdma_spi_tx.Instance             = SPI2_DMAx_TX_CHANNEL;
-		} else if( spi == SPI3 ){                           
+		} 
+#endif
+#if defined(SPI3_BASE)
+        if( spi == SPI3 ){                           
 			hdma_spi_tx.Instance             = SPI3_DMAx_TX_CHANNEL;
 		}
+#endif
         hdma_spi_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
         hdma_spi_tx.Init.PeriphInc           = DMA_PINC_DISABLE;
         hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
@@ -80,13 +104,21 @@
 	__HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
 	/* RX: */
     if( !dma_handle_inited ){
+#if defined(SPI1_BASE)
 		if( spi == SPI1 ){
 			hdma_spi_rx.Instance             = SPI1_DMAx_RX_CHANNEL;
-		} else if( spi == SPI2 ){                           
+		} 
+#endif
+#if defined(SPI2_BASE)
+        if( spi == SPI2 ){                           
 			hdma_spi_rx.Instance             = SPI2_DMAx_RX_CHANNEL;
-		} else if( spi == SPI3 ){                           
+		} 
+#endif
+#if defined(SPI3_BASE)
+        if( spi == SPI3 ){                           
 			hdma_spi_rx.Instance             = SPI3_DMAx_RX_CHANNEL;
 		}
+#endif
         hdma_spi_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
         hdma_spi_rx.Init.PeriphInc           = DMA_PINC_DISABLE;
         hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
@@ -102,29 +134,38 @@
 void spi_dma_irq_setup( SPI_TypeDef *spi) 
 {
     /* DMA controller clock enable */
+#if defined(SPI1_BASE)
 	if(  spi == SPI1 ){
 		SPI1_DMAx_CLK_ENABLE();
 		HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 3, 0);
 		HAL_NVIC_EnableIRQ(  SPI1_DMAx_TX_IRQn);
 		HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 2, 0);
 		HAL_NVIC_EnableIRQ(  SPI1_DMAx_RX_IRQn);
-	} else if( spi == SPI2 ){
+	} 
+#endif
+#if defined(SPI2_BASE)
+    if( spi == SPI2 ){
 		SPI2_DMAx_CLK_ENABLE();
 		HAL_NVIC_SetPriority(SPI2_DMAx_TX_IRQn, 3, 0);
 		HAL_NVIC_EnableIRQ(  SPI2_DMAx_TX_IRQn);
 		HAL_NVIC_SetPriority(SPI2_DMAx_RX_IRQn, 2, 0);
 		HAL_NVIC_EnableIRQ(  SPI2_DMAx_RX_IRQn);
-	} else if( spi == SPI3 ){
+	}
+#endif
+#if defined(SPI3_BASE)
+    if( spi == SPI3 ){
 		SPI3_DMAx_CLK_ENABLE();
 		HAL_NVIC_SetPriority(SPI3_DMAx_TX_IRQn, 3, 0);
 		HAL_NVIC_EnableIRQ(  SPI3_DMAx_TX_IRQn);
 		HAL_NVIC_SetPriority(SPI3_DMAx_RX_IRQn, 2, 0);
 		HAL_NVIC_EnableIRQ(  SPI3_DMAx_RX_IRQn);
 	}
+#endif
     /* DMA interrupt init */
 }
 
 /* SPI1 */
+#if defined(SPI1_BASE)
 void SPI1_DMAx_TX_IRQHandler(void)
 {
   HAL_DMA_IRQHandler(&hdma_spi_tx);
@@ -133,6 +174,7 @@
 {
   HAL_DMA_IRQHandler(&hdma_spi_rx);
 }
+#endif
 
 #if defined(SPI2_BASE)
 /* SPI2 */